Fix "scc" call inside abc9 to consider all wires

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index a5d8231397e9f927dc3445da1e9b1c53a698eb3b..ce27f7eeadada7de41f867633d955dedb2a0eb3b 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -75,7 +75,7 @@ inline std::string remap_name(RTLIL::IdString abc_name)
 
 void handle_loops(RTLIL::Design *design)
 {
-       Pass::call(design, "scc -set_attr abc_scc_id {}");
+       Pass::call(design, "scc -set_attr abc_scc_id {} % w:*");
 
        // For every unique SCC found, (arbitrarily) find the first
        // cell in the component, and select (and mark) all its output