Fix off-by-one error on almost full condition for prefetch

This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.

diff --git a/litex/soc/cores/spi_opi.py b/litex/soc/cores/spi_opi.py
index 45f477677f142d0a5665ca7e022f6caad6c2529b..8e87518f86017bc731662c5452b15e906a996af7 100644 (file)
--- a/litex/soc/cores/spi_opi.py
+++ b/litex/soc/cores/spi_opi.py
@@ -494,7 +494,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
                 p_DATA_WIDTH              = 32,
                 p_FIRST_WORD_FALL_THROUGH = "TRUE",
                 p_ALMOST_EMPTY_OFFSET     = 6,
-                p_ALMOST_FULL_OFFSET      = (512- (8*prefetch_lines)),
+                p_ALMOST_FULL_OFFSET      = (511 - (8*prefetch_lines)),
 
                 o_ALMOSTEMPTY = rx_almostempty,
                 o_ALMOSTFULL  = rx_almostfull,