[NDS32][DOC] Describe -mcmodel= option instead of -mgp-direct in the documentation.

gcc/
	* doc/invoke.texi (NDS32 Options): Add -mcmodel= option and
	remove -mgp-direct option.

From-SVN: r219706

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e105c447ab80251604980598d7139453b17a56c3..5334bdf89368ccee16fcd7ce37a327b0aae63460 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-01-16  Chung-Ju Wu  <jasonwucj@gmail.com>
+
+       * doc/invoke.texi (NDS32 Options): Add -mcmodel= option and
+       remove -mgp-direct option.
+
 2015-01-15  Jan Hubicka  <hubicka@ucw.cz>
        
        * doc/invoke.texi (--param early-inlining-insns): Update default value.

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 12368e8e04a3bcc1b0804e0439de728568f62929..5eee2a3fe0b93711c2803bac5324571366e9c6da 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -861,10 +861,10 @@ Objective-C and Objective-C++ Dialects}.
 -mperf-ext -mno-perf-ext @gol
 -mv3push -mno-v3push @gol
 -m16bit -mno-16bit @gol
--mgp-direct -mno-gp-direct @gol
 -misr-vector-size=@var{num} @gol
 -mcache-block-size=@var{num} @gol
 -march=@var{arch} @gol
+-mcmodel=@var{code-model} @gol
 -mforce-fp-as-gp -mforbid-fp-as-gp @gol
 -mex9 -mctor-dtor -mrelax}
 
@@ -19153,14 +19153,6 @@ Generate 16-bit instructions.
 @opindex mno-16-bit
 Do not generate 16-bit instructions.
 
-@item -mgp-direct
-@opindex mgp-direct
-Generate GP base instructions directly.
-
-@item -mno-gp-direct
-@opindex mno-gp-direct
-Do no generate GP base instructions directly.
-
 @item -misr-vector-size=@var{num}
 @opindex misr-vector-size
 Specify the size of each interrupt vector, which must be 4 or 16.
@@ -19174,6 +19166,21 @@ which must be a power of 2 between 4 and 512.
 @opindex march
 Specify the name of the target architecture.
 
+@item -mcmodel=@var{code-model}
+@opindex mcmodel
+Set the code model to one of
+@table @asis
+@item @samp{small}
+All the data and read-only data segments must be within 512KB addressing space.
+The text segment must be within 16MB addressing space.
+@item @samp{medium}
+The data segment must be within 512KB while the read-only data segment can be
+within 4GB addressing space.  The text segment should be still within 16MB
+addressing space.
+@item @samp{large}
+All the text and data segments can be within 4GB addressing space.
+@end table
+
 @item -mforce-fp-as-gp
 @opindex mforce-fp-as-gp
 Prevent $fp being allocated during register allocation so that compiler