pan/midgard: Fix REGISTER_OFFSET
authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Thu, 1 Aug 2019 21:06:02 +0000 (14:06 -0700)
committerAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fri, 2 Aug 2019 21:20:03 +0000 (14:20 -0700)
r27 isn't the special one, usually.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
src/panfrost/midgard/helpers.h
src/panfrost/midgard/midgard_compile.c

index d3ae39ab1554f6034fa15c3f344959491777baac..9d04b0571260ae41b8dc4fe14476c002b90b5e5d 100644 (file)
@@ -170,8 +170,7 @@ quadword_size(int tag)
 
 #define REGISTER_UNUSED 24
 #define REGISTER_CONSTANT 26
-#define REGISTER_VARYING_BASE 26
-#define REGISTER_OFFSET 27
+#define REGISTER_LDST_BASE 26
 #define REGISTER_TEXTURE_BASE 28
 #define REGISTER_SELECT 31
 
index 7314e678c8cb15f34082dbd06356d9817b1746b0..517eabedf3258bb7efeb06fffc0d4b134eb5d8d3 100644 (file)
@@ -662,7 +662,7 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src)
                 .ssa_args = {
                         .src0 = SSA_UNUSED_1,
                         .src1 = offset,
-                        .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
+                        .dest = SSA_FIXED_REGISTER(REGISTER_LDST_BASE + 1),
                 },
                 .alu = {
                         .op = midgard_alu_op_imov,