fmpyadd and fmpysub are restricted.
FP_OR_SNAKE_FP_REGS is for reload_{in,out}di only and isn't used
- anywhere else.
-
- GENERAL_OR_FP_OR_SNAKE_FP_REGS is for reload_{in,out}si only and
- isn't used anywhereelse. */
+ anywhere else. */
enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS,
HI_SNAKE_FP_REGS, SNAKE_FP_REGS, GENERAL_OR_SNAKE_FP_REGS,
- FP_OR_SNAKE_FP_REGS, GENERAL_OR_FP_OR_SNAKE_FP_REGS, SHIFT_REGS,
- ALL_REGS, LIM_REG_CLASSES};
+ FP_OR_SNAKE_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ "NO_REGS", "R1_REGS", "GENERAL_REGS", "FP_REGS", "GENERAL_OR_FP_REGS",\
"HI_SNAKE_FP_REGS", "SNAKE_FP_REGS", "GENERAL_OR_SNAKE_FP_REGS",\
- "FP_OR_SNAKE_FP_REGS", "GENERAL_OR_FP_OR_SNAKE_FP_REGS", "SHIFT_REGS",\
- "ALL_REGS"}
+ "FP_OR_SNAKE_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
{0, 0xffff0000, ~0, 0xffff}, /* SNAKE_FP_REGS */ \
{-2, 0xffff0000, ~0, 0xffff}, /* GENERAL_OR_SNAKE_FP_REGS */\
{0, ~0, ~0, 0xffff}, /* FP_OR_SNAKE_FP_REGS */\
- {-2, ~0, ~0, 0xffff}, /* GENERAL_OR_FP_OR_SNAKE_FP_REGS */\
{0, 0, 0, 0x10000}, /* SHIFT_REGS */ \
{-2, ~0, ~0, 0x1ffff}} /* ALL_REGS */
#define FP_REG_CLASS_P(CLASS) \
(CLASS == FP_REGS || CLASS == SNAKE_FP_REGS || CLASS == HI_SNAKE_FP_REGS)
-/* Get reg_class from a letter such as appears in the machine description. */
+/* Get reg_class from a letter such as appears in the machine description.
+ Note 'Z' is not the same as 'r' since SHIFT_REGS is not part of
+ GENERAL_REGS. */
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'f' ? (!TARGET_SNAKE ? FP_REGS : NO_REGS) : \
((C) == 'q' ? SHIFT_REGS : \
((C) == 'a' ? R1_REGS : \
((C) == 'z' ? FP_OR_SNAKE_FP_REGS : \
- ((C) == 'Z' ? GENERAL_OR_FP_OR_SNAKE_FP_REGS : NO_REGS)))))))
+ ((C) == 'Z' ? ALL_REGS : NO_REGS)))))))
/* The letters I, J, K, L and M in a register constraint string
can be used to stand for particular ranges of immediate operands.