gdb/riscv: expect h/w watchpoints to trigger before the memory is written

When using QEMU as a RISCV simulator, hardware watchpoint events are
reported to GDB before the target memory gets written. GDB currently
expects the event to be reported after it is written. As a result of
this mismatch, upon receiving the event, GDB sees that the target
memory region has not changed, and therefore decides to ignore the
event. It therefore resumes the program's execution with a continue,
which is the start of an infinite loop between QEMU repeatedly
reporting the same watchpoint event over and over, and GDB repeatedly
ignoring it.

This patch fixes the issue by telling GDB to expect the watchpoint
event to be reported ahead of the memory region being modified.
Upon receiving the event, GDB then single-steps the program before
checking the watched memory value.

gdb/ChangeLog:

        * riscv-tdep.c (riscv_gdbarch_init): Set the gdbarch's
        have_nonsteppable_watchpoint attribute to 1.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index e538ac20aa61e8ff4b3e1e5efd8d18487c7b9050..88d76db13a18ac2b2591929910c94dd6fac7ccba 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-23  Joel Brobecker  <brobecker@adacore.com>
+
+       * riscv-tdep.c (riscv_gdbarch_init): Set the gdbarch's
+       have_nonsteppable_watchpoint attribute to 1.
+
 2018-10-23  Andrew Burgess  <andrew.burgess@embecosm.com>
 
        * riscv-tdep.c (riscv_gdb_reg_names): Update comment, and all

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 2fd335ac59cd3d00c8cdf6e51ea38b850df384af..48ca2accb4abf61d8fe372bf63945bc84bb7db31 100644 (file)
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -2856,6 +2856,7 @@ riscv_gdbarch_init (struct gdbarch_info info,
   set_gdbarch_return_value (gdbarch, riscv_return_value);
   set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
   set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
+  set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 
   /* Register architecture.  */
   set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);