i965: Rename the original binding table to mention that it's the WM now.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 9c89617e66da3f77d69fdd9a71dac6b2215cb088..8edd004f856da60a2c7e97a2f741beaa1f928881 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -821,12 +821,6 @@ struct brw_context
       GLuint last_bufsz;
    } curbe;
 
-   struct {
-      /** Binding table of pointers to surf_bo entries */
-      uint32_t bo_offset;
-      uint32_t surf_offset[BRW_MAX_SURFACES];
-   } bind;
-
    /** SAMPLER_STATE count and offset */
    struct {
       GLuint count;
@@ -934,6 +928,10 @@ struct brw_context
        */
       uint32_t push_const_offset;
 
+      /** Binding table of pointers to surf_bo entries */
+      uint32_t bind_bo_offset;
+      uint32_t surf_offset[BRW_MAX_SURFACES];
+
       /** @{ register allocator */
 
       struct ra_regs *regs;

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index c86755de6593cc2044ab285804f7246617f490e8..2148b2ee25221f571ed5b04c4cfbae363d419bab 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -81,7 +81,7 @@ static void upload_binding_table_pointers(struct brw_context *brw)
    OUT_BATCH(0); /* gs */
    OUT_BATCH(0); /* clip */
    OUT_BATCH(0); /* sf */
-   OUT_BATCH(brw->bind.bo_offset);
+   OUT_BATCH(brw->wm.bind_bo_offset);
    ADVANCE_BATCH();
 }
 
@@ -117,7 +117,7 @@ static void upload_gen6_binding_table_pointers(struct brw_context *brw)
             (4 - 2));
    OUT_BATCH(brw->vs.bind_bo_offset); /* vs */
    OUT_BATCH(brw->gs.bind_bo_offset); /* gs */
-   OUT_BATCH(brw->bind.bo_offset); /* wm/ps */
+   OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */
    ADVANCE_BATCH();
 }
 

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index a58b4b3c0b8373bd0083fe0ddda826d714b1ddf6..8a0e92fab0818a33e90a084a127aca104d67aade 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -70,7 +70,7 @@ extern const struct brw_tracked_state brw_wm_input_sizes;
 extern const struct brw_tracked_state brw_wm_prog;
 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
 extern const struct brw_tracked_state brw_texture_surfaces;
-extern const struct brw_tracked_state brw_binding_table;
+extern const struct brw_tracked_state brw_wm_binding_table;
 extern const struct brw_tracked_state brw_vs_binding_table;
 extern const struct brw_tracked_state brw_wm_unit;
 

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 3f5c03d8f901058d8674a6e98edf26f43c81fb94..b02e1600d629f4ab04421d1db35b22e043008258 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -71,7 +71,7 @@ static const struct brw_tracked_state *gen4_atoms[] =
    &brw_renderbuffer_surfaces,
    &brw_texture_surfaces,
    &brw_vs_binding_table,
-   &brw_binding_table,
+   &brw_wm_binding_table,
 
    &brw_samplers,
 
@@ -149,7 +149,7 @@ static const struct brw_tracked_state *gen6_atoms[] =
    &gen6_sol_surface,
    &brw_vs_binding_table,
    &gen6_gs_binding_table,
-   &brw_binding_table,
+   &brw_wm_binding_table,
 
    &brw_samplers,
    &gen6_sampler_state,
@@ -218,7 +218,7 @@ const struct brw_tracked_state *gen7_atoms[] =
    &gen6_renderbuffer_surfaces,
    &brw_texture_surfaces,
    &brw_vs_binding_table,
-   &brw_binding_table,
+   &brw_wm_binding_table,
 
    &gen7_samplers,
 

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a975b2d1c55e2c362992367475fb7b909fc4ef88..a3de2e32da08722b0167cda0859202bd5e289690 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -651,7 +651,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-                         6 * 4, 32, &brw->bind.surf_offset[surf_index]);
+                         6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 
    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
              BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
@@ -679,7 +679,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-                          brw->bind.surf_offset[surf_index] + 4,
+                          brw->wm.surf_offset[surf_index] + 4,
                           intelObj->mt->region->bo, 0,
                           I915_GEM_DOMAIN_SAMPLER, 0);
 }
@@ -843,7 +843,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
       if (brw->wm.const_bo) {
         drm_intel_bo_unreference(brw->wm.const_bo);
         brw->wm.const_bo = NULL;
-        brw->bind.surf_offset[surf_index] = 0;
+        brw->wm.surf_offset[surf_index] = 0;
         brw->state.dirty.brw |= BRW_NEW_SURFACES;
       }
       return;
@@ -864,7 +864,7 @@ brw_upload_wm_pull_constants(struct brw_context *brw)
 
    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
                                       params->NumParameters,
-                                      &brw->bind.surf_offset[surf_index]);
+                                      &brw->wm.surf_offset[surf_index]);
 
    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 }
@@ -885,7 +885,7 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
    uint32_t *surf;
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-                         6 * 4, 32, &brw->bind.surf_offset[unit]);
+                         6 * 4, 32, &brw->wm.surf_offset[unit]);
 
    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
@@ -959,7 +959,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    region = irb->mt->region;
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-                         6 * 4, 32, &brw->bind.surf_offset[unit]);
+                         6 * 4, 32, &brw->wm.surf_offset[unit]);
 
    switch (rb_format) {
    case MESA_FORMAT_SARGB8:
@@ -1027,7 +1027,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    }
 
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-                          brw->bind.surf_offset[unit] + 4,
+                          brw->wm.surf_offset[unit] + 4,
                           region->bo,
                           surf[1] - region->bo->offset,
                           I915_GEM_DOMAIN_RENDER,
@@ -1095,12 +1095,12 @@ brw_update_texture_surfaces(struct brw_context *brw)
       if (texUnit->_ReallyEnabled) {
         brw->intel.vtbl.update_texture_surface(ctx, i);
       } else {
-         brw->bind.surf_offset[surf] = 0;
+         brw->wm.surf_offset[surf] = 0;
       }
 
       /* For now, just mirror the texture setup to the VS slots. */
       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(i)] =
-        brw->bind.surf_offset[surf];
+        brw->wm.surf_offset[surf];
    }
 
    brw->state.dirty.brw |= BRW_NEW_SURFACES;
@@ -1120,7 +1120,7 @@ const struct brw_tracked_state brw_texture_surfaces = {
  * numbers to surface state objects.
  */
 static void
-brw_upload_binding_table(struct brw_context *brw)
+brw_upload_wm_binding_table(struct brw_context *brw)
 {
    uint32_t *bind;
    int i;
@@ -1130,24 +1130,24 @@ brw_upload_binding_table(struct brw_context *brw)
     */
    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
                          sizeof(uint32_t) * BRW_MAX_SURFACES,
-                         32, &brw->bind.bo_offset);
+                         32, &brw->wm.bind_bo_offset);
 
    /* BRW_NEW_SURFACES */
    for (i = 0; i < BRW_MAX_SURFACES; i++) {
-      bind[i] = brw->bind.surf_offset[i];
+      bind[i] = brw->wm.surf_offset[i];
    }
 
    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
 }
 
-const struct brw_tracked_state brw_binding_table = {
+const struct brw_tracked_state brw_wm_binding_table = {
    .dirty = {
       .mesa = 0,
       .brw = (BRW_NEW_BATCH |
              BRW_NEW_SURFACES),
       .cache = 0
    },
-   .emit = brw_upload_binding_table,
+   .emit = brw_upload_wm_binding_table,
 };
 
 void

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 8037966dd6d9cc0876da3b906e6242da9f22fab2..265ca491093c443d64dbc134deb6e7c725c61b4b 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -102,7 +102,7 @@ upload_ps_state(struct brw_context *brw)
    /* BRW_NEW_PS_BINDING_TABLE */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
-   OUT_BATCH(brw->bind.bo_offset);
+   OUT_BATCH(brw->wm.bind_bo_offset);
    ADVANCE_BATCH();
 
    /* CACHE_NEW_SAMPLER */

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 1efb82f345892d4bed7b18f02dc860eb2f7760f3..c52f6aacef783db02615a7e879592608fc260ac3 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -69,7 +69,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-                         sizeof(*surf), 32, &brw->bind.surf_offset[surf_index]);
+                         sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]);
    memset(surf, 0, sizeof(*surf));
 
    if (mt->align_h == 4)
@@ -123,7 +123,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-                          brw->bind.surf_offset[surf_index] +
+                          brw->wm.surf_offset[surf_index] +
                           offsetof(struct gen7_surface_state, ss1),
                           intelObj->mt->region->bo, 0,
                           I915_GEM_DOMAIN_SAMPLER, 0);
@@ -177,7 +177,7 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
    struct gen7_surface_state *surf;
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-                         sizeof(*surf), 32, &brw->bind.surf_offset[unit]);
+                         sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
    memset(surf, 0, sizeof(*surf));
 
    surf->ss0.surface_type = BRW_SURFACE_NULL;
@@ -203,7 +203,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    gl_format rb_format = intel_rb_format(irb);
 
    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-                         sizeof(*surf), 32, &brw->bind.surf_offset[unit]);
+                         sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
    memset(surf, 0, sizeof(*surf));
 
    if (irb->mt->align_h == 4)
@@ -250,7 +250,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    surf->ss3.pitch = (region->pitch * region->cpp) - 1;
 
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-                          brw->bind.surf_offset[unit] +
+                          brw->wm.surf_offset[unit] +
                           offsetof(struct gen7_surface_state, ss1),
                           region->bo,
                           surf->ss1.base_addr - region->bo->offset,