amdgcn: Add cond_add/sub/and/ior/xor for all vector modes

2020-03-18  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (COND_MODE): Delete.
	(COND_INT_MODE): Delete.
	(cond_op): Add "mult".
	(cond_<expander><mode>): Use VEC_ALLREG_MODE.
	(cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 114d2992bcd2ab9cda170b41569dc0ed160da4f7..dac1d41f3eae1abf304b23f8fa757cd2a928e257 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-03-18  Andrew Stubbs  <ams@codesourcery.com>
+
+       * config/gcn/gcn-valu.md (COND_MODE): Delete.
+       (COND_INT_MODE): Delete.
+       (cond_op): Add "mult".
+       (cond_<expander><mode>): Use VEC_ALLREG_MODE.
+       (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
+
 2020-03-18   Richard Biener  <rguenther@suse.de>
 
        PR middle-end/94206

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index a8034f77798194cc1289a33e1c2625cf63bff291..68d89fadc9e7189be9eb9add8e7148e7b813ca10 100644 (file)
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2903,19 +2903,15 @@
     DONE;
   })
 
-; FIXME this should be VEC_REG_MODE, but not all dependencies are implemented.
-(define_mode_iterator COND_MODE [V64SI V64DI V64SF V64DF])
-(define_mode_iterator COND_INT_MODE [V64SI V64DI])
-
-(define_code_iterator cond_op [plus minus])
+(define_code_iterator cond_op [plus minus mult])
 
 (define_expand "cond_<expander><mode>"
-  [(match_operand:COND_MODE 0 "register_operand")
+  [(match_operand:VEC_ALLREG_MODE 0 "register_operand")
    (match_operand:DI 1 "register_operand")
-   (cond_op:COND_MODE
-     (match_operand:COND_MODE 2 "gcn_alu_operand")
-     (match_operand:COND_MODE 3 "gcn_alu_operand"))
-   (match_operand:COND_MODE 4 "register_operand")]
+   (cond_op:VEC_ALLREG_MODE
+     (match_operand:VEC_ALLREG_MODE 2 "gcn_alu_operand")
+     (match_operand:VEC_ALLREG_MODE 3 "gcn_alu_operand"))
+   (match_operand:VEC_ALLREG_MODE 4 "register_operand")]
   ""
   {
     operands[1] = force_reg (DImode, operands[1]);
@@ -2927,15 +2923,16 @@
     DONE;
   })
 
+;; TODO smin umin smax umax
 (define_code_iterator cond_bitop [and ior xor])
 
 (define_expand "cond_<expander><mode>"
-  [(match_operand:COND_INT_MODE 0 "register_operand")
+  [(match_operand:VEC_ALLREG_INT_MODE 0 "register_operand")
    (match_operand:DI 1 "register_operand")
-   (cond_bitop:COND_INT_MODE
-     (match_operand:COND_INT_MODE 2 "gcn_alu_operand")
-     (match_operand:COND_INT_MODE 3 "gcn_alu_operand"))
-   (match_operand:COND_INT_MODE 4 "register_operand")]
+   (cond_bitop:VEC_ALLREG_INT_MODE
+     (match_operand:VEC_ALLREG_INT_MODE 2 "gcn_alu_operand")
+     (match_operand:VEC_ALLREG_INT_MODE 3 "gcn_alu_operand"))
+   (match_operand:VEC_ALLREG_INT_MODE 4 "register_operand")]
   ""
   {
     operands[1] = force_reg (DImode, operands[1]);