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[aarch64] Correct architecture for tsv110.
authorShaokun Zhang <zhangshaokun@hisilicon.com>
Wed, 19 Dec 2018 10:08:50 +0000 (10:08 +0000)
committerRichard Earnshaw <rearnsha@gcc.gnu.org>
Wed, 19 Dec 2018 10:08:50 +0000 (10:08 +0000)
For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but
some mandatory features are not implemented.

2018-12-19  Shaokun Zhang  <zhangshaokun@hisilicon.com>

* config/aarch64/aarch64-cores.def (tsv110): Fix architecture.  This
part is really Armv8.2 with some permitted Armv8.4 extensions.

From-SVN: r267255

gcc/ChangeLog patch | blob | history
gcc/config/aarch64/aarch64-cores.def patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cdfab54bb9fd7af30e8cfe30621ed669218478ec..524ad19285f5fa351d11e7cc7e806cb9d123f226 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-12-19  Shaokun Zhang  <zhangshaokun@hisilicon.com>
+
+       * config/aarch64/aarch64-cores.def (tsv110): Fix architecture.  This
+       part is really Armv8.2 with some permitted Armv8.4 extensions.
+
 2018-12-19  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/88541
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 74be5dbf25954560c0b78e6da62f64dc0d143486..20f4924e084d5a3dfc7dac69edb6a51ec28105a8 100644 (file)
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -96,10 +96,10 @@ AARCH64_CORE("cortex-a75",  cortexa75, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2
 AARCH64_CORE("cortex-a76",  cortexa76, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1)
 AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1)
 
-/* ARMv8.4-A Architecture Processors.  */
-
 /* HiSilicon ('H') cores. */
-AARCH64_CORE("tsv110",     tsv110,    cortexa57,    8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
+AARCH64_CORE("tsv110",  tsv110, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
+
+/* ARMv8.4-A Architecture Processors.  */
 
 /* Qualcomm ('Q') cores. */
 AARCH64_CORE("saphira",     saphira,    saphira,    8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   0x51, 0xC01, -1)