i965: clip: Move header_regs into brw_clip_compile.

This makes header_regs available for computing VUE offsets within clip code.

Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index f5ae966f8e3dd1c25d1d3bf18d8a226e71fe9d1e..f33518bee48c0346ee2212918d187bcc4fd64480 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -58,7 +58,6 @@ static void compile_clip_prog( struct brw_context *brw,
    GLuint program_size;
    GLuint delta;
    GLuint i;
-   GLuint header_regs;
 
    memset(&c, 0, sizeof(c));
 
@@ -78,11 +77,11 @@ static void compile_clip_prog( struct brw_context *brw,
     * These are currently hardcoded:
     */
    if (intel->gen == 5)
-      header_regs = 3;
+      c.header_regs = 3;
    else
-      header_regs = 1;
+      c.header_regs = 1;
 
-   delta = header_regs * REG_SIZE;
+   delta = c.header_regs * REG_SIZE;
 
    for (i = 0; i < VERT_RESULT_MAX; i++) {
       if (c.key.attrs & BITFIELD64_BIT(i)) {
@@ -99,7 +98,7 @@ static void compile_clip_prog( struct brw_context *brw,
     * length.  nr_regs determines the urb_read_length from the start
     * of the header to the end of the vertex data.
     */
-   c.nr_regs = header_regs + (c.nr_attrs + 1) / 2;
+   c.nr_regs = c.header_regs + (c.nr_attrs + 1) / 2;
 
    c.nr_bytes = c.nr_regs * REG_SIZE;
 

diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h
index abd35d235feb50c933217516454b31a1aaa6f38c..0324feac84fa9293d1bc2b9ef41363db20fe82aa 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip.h
+++ b/src/mesa/drivers/dri/i965/brw_clip.h
@@ -115,6 +115,7 @@ struct brw_clip_compile {
 
    GLboolean need_direction;
 
+   GLuint header_regs;
    /** Mapping from VERT_RESULT_* to offset within the VUE. */
    GLuint offset[VERT_RESULT_MAX];
    /** Mapping from attribute index to VERT_RESULT_* */