block_size=options.cacheline_size)
system.tol2bus = Bus()
- system.l2.cpu_side = system.tol2bus.port
- system.l2.mem_side = system.membus.port
+ system.l2.cpu_side = system.tol2bus.master
+ system.l2.mem_side = system.membus.slave
system.l2.num_cpus = options.num_cpus
for i in xrange(options.num_cpus):
self.bridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
- self.bridge.master = self.iobus.port
- self.bridge.slave = self.membus.port
- self.physmem.port = self.membus.port
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
+ self.physmem.port = self.membus.master
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
self.disk2.childImage(disk('linux-bigswap2.img'))
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.iobus)
- self.tsunami.ide.pio = self.iobus.port
- self.tsunami.ide.config = self.iobus.port
- self.tsunami.ide.dma = self.iobus.port
- self.tsunami.ethernet.pio = self.iobus.port
- self.tsunami.ethernet.config = self.iobus.port
- self.tsunami.ethernet.dma = self.iobus.port
+ self.tsunami.ide.pio = self.iobus.master
+ self.tsunami.ide.config = self.iobus.master
+ self.tsunami.ide.dma = self.iobus.slave
+ self.tsunami.ethernet.pio = self.iobus.master
+ self.tsunami.ethernet.config = self.iobus.master
+ self.tsunami.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
self.console = binary('console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
- self.system_port = self.membus.port
+ self.system_port = self.membus.slave
return self
# RubyPort currently does support functional accesses. Therefore provide
# the piobus a direct connection to physical memory
#
- self.piobus.port = physmem.port
+ self.piobus.master_port = physmem.port
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk2.childImage(disk('linux-bigswap2.img'))
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.piobus)
- self.tsunami.ide.pio = self.piobus.port
- self.tsunami.ide.config = self.piobus.port
- self.tsunami.ide.dma = self.piobus.port
- self.tsunami.ethernet.pio = self.piobus.port
- self.tsunami.ethernet.config = self.piobus.port
- self.tsunami.ethernet.dma = self.piobus.port
+ self.tsunami.ide.pio = self.piobus.master
+ self.tsunami.ide.config = self.piobus.master
+ self.tsunami.ide.dma = self.piobus.slave
+ self.tsunami.ethernet.pio = self.piobus.master
+ self.tsunami.ethernet.config = self.piobus.master
+ self.tsunami.ethernet.dma = self.piobus.slave
#
# Store the dma devices for later connection to dma ruby ports.
self.t1000.attachIO(self.iobus)
self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
- self.bridge.master = self.iobus.port
- self.bridge.slave = self.membus.port
- self.physmem.port = self.membus.port
- self.physmem2.port = self.membus.port
- self.rom.port = self.membus.port
- self.nvram.port = self.membus.port
- self.hypervisor_desc.port = self.membus.port
- self.partition_desc.port = self.membus.port
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
+ self.physmem.port = self.membus.master
+ self.physmem2.port = self.membus.master
+ self.rom.port = self.membus.master
+ self.nvram.port = self.membus.master
+ self.hypervisor_desc.port = self.membus.master
+ self.partition_desc.port = self.membus.master
self.intrctrl = IntrControl()
self.disk0 = CowMmDisk()
self.disk0.childImage(disk('disk.s10hw2'))
- self.disk0.pio = self.iobus.port
+ self.disk0.pio = self.iobus.master
# The puart0 and hvuart are placed on the IO bus, so create ranges
# for them. The remaining IO range is rather fragmented, so poke
self.hypervisor_desc_bin = binary('1up-hv.bin')
self.partition_desc_bin = binary('1up-md.bin')
- self.system_port = self.membus.port
+ self.system_port = self.membus.slave
return self
self.membus = MemBus(bus_id=1)
self.membus.badaddr_responder.warn_access = "warn"
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
- self.bridge.master = self.iobus.port
- self.bridge.slave = self.membus.port
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
self.mem_mode = mem_mode
zero = True)
self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
size = '64MB'), zero = True)
- self.nvmem.port = self.membus.port
+ self.nvmem.port = self.membus.master
self.boot_loader = binary('boot.arm')
self.boot_loader_mem = self.nvmem
self.gic_cpu_addr = self.realview.gic.cpu_addr
boot_flags += " init=/init "
self.boot_osflags = boot_flags
- self.physmem.port = self.membus.port
+ self.physmem.port = self.membus.master
self.realview.attachOnChipIO(self.membus, self.bridge)
self.realview.attachIO(self.iobus)
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
- self.system_port = self.membus.port
+ self.system_port = self.membus.slave
return self
self.membus = MemBus(bus_id=1)
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange('1GB'))
- self.bridge.master = self.iobus.port
- self.bridge.slave = self.membus.port
- self.physmem.port = self.membus.port
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
+ self.physmem.port = self.membus.master
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
self.disk2.childImage(disk('linux-bigswap2.img'))
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
- self.malta.ide.pio = self.iobus.port
- self.malta.ide.config = self.iobus.port
- self.malta.ide.dma = self.iobus.port
- self.malta.ethernet.pio = self.iobus.port
- self.malta.ethernet.config = self.iobus.port
- self.malta.ethernet.dma = self.iobus.port
+ self.malta.ide.pio = self.iobus.master
+ self.malta.ide.config = self.iobus.master
+ self.malta.ide.dma = self.iobus.slave
+ self.malta.ethernet.pio = self.iobus.master
+ self.malta.ethernet.config = self.iobus.master
+ self.malta.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
self.console = binary('mips/console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
- self.system_port = self.membus.port
+ self.system_port = self.membus.slave
return self
APIC_range_size = 1 << 12;
x86_sys.membus = MemBus(bus_id=1)
- x86_sys.physmem.port = x86_sys.membus.port
+ x86_sys.physmem.port = x86_sys.membus.master
# North Bridge
x86_sys.iobus = Bus(bus_id=0)
x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
- x86_sys.bridge.master = x86_sys.iobus.port
- x86_sys.bridge.slave = x86_sys.membus.port
+ x86_sys.bridge.master = x86_sys.iobus.slave
+ x86_sys.bridge.slave = x86_sys.membus.master
# Allow the bridge to pass through the IO APIC (two pages),
# everything in the IO address range up to the local APIC, and
# then the entire PCI address space and beyond
# Create a bridge from the IO bus to the memory bus to allow access to
# the local APIC (two pages)
x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns')
- x86_sys.apicbridge.slave = x86_sys.iobus.port
- x86_sys.apicbridge.master = x86_sys.membus.port
+ x86_sys.apicbridge.slave = x86_sys.iobus.master
+ x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
interrupts_address_space_base +
APIC_range_size - 1)]
# connect the io bus
x86_sys.pc.attachIO(x86_sys.iobus)
- x86_sys.system_port = x86_sys.membus.port
+ x86_sys.system_port = x86_sys.membus.slave
def connectX86RubySystem(x86_sys):
# North Bridge
# RubyPort currently does support functional accesses. Therefore provide
# the piobus a direct connection to physical memory
#
- x86_sys.piobus.port = x86_sys.physmem.port
+ x86_sys.piobus.master = x86_sys.physmem.port
x86_sys.pc.attachIO(x86_sys.piobus)
mem_size = SysConfig().mem()
if options.caches or options.l2cache:
test_sys.iocache = IOCache(addr_range=mem_size)
- test_sys.iocache.cpu_side = test_sys.iobus.port
- test_sys.iocache.mem_side = test_sys.membus.port
+ test_sys.iocache.cpu_side = test_sys.iobus.master
+ test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(mem_size)])
- test_sys.iobridge.slave = test_sys.iobus.port
- test_sys.iobridge.master = test_sys.membus.port
+ test_sys.iobridge.slave = test_sys.iobus.master
+ test_sys.iobridge.master = test_sys.membus.slave
for i in xrange(np):
if options.fastmem:
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
- cpu.interrupts.pio = system.piobus.port
- cpu.interrupts.int_port = system.piobus.port
+ cpu.interrupts.pio = system.piobus.master
+ cpu.interrupts.int_master = system.piobus.slave
+ cpu.interrupts.int_slave = system.piobus.master
root = Root(full_system = True, system = system)
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
else:
- system.system_port = system.membus.port
- system.physmem.port = system.membus.port
+ system.system_port = system.membus.slave
+ system.physmem.port = system.membus.master
CacheConfig.config_cache(options, system)
for i in xrange(np):
system.sys_port_proxy = sys_port_proxy
# Connect the system port for loading of binaries etc
- system.system_port = system.sys_port_proxy.port
+ system.system_port = system.sys_port_proxy.slave
#
class ArmTableWalker(MemObject):
type = 'ArmTableWalker'
cxx_class = 'ArmISA::TableWalker'
- port = Port("Port for TableWalker to do walk the translation with")
+ port = MasterPort("Port for TableWalker to do walk the translation with")
sys = Param.System(Parent.any, "system object parameter")
min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
type = 'X86LocalApic'
cxx_class = 'X86ISA::Interrupts'
pio_latency = Param.Latency('1ns', 'Programmed IO latency in simticks')
- int_port = Port("Port for sending and receiving interrupt messages")
+ int_master = MasterPort("Port for sending interrupt messages")
+ int_slave = SlavePort("Port for receiving interrupt messages")
int_latency = Param.Latency('1ns', \
"Latency for an interrupt to propagate through this device.")
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
- port = Port("Port for the hardware table walker")
+ port = MasterPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86TLB(BaseTLB):
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
+ * Andreas Hansson
*/
#ifndef __ARCH_X86_INTERRUPTS_HH__
Port *getPort(const std::string &if_name, int idx = -1)
{
- if (if_name == "int_port")
+ // a bit of an odd one since there is now two ports in the
+ // Python class we also need two ports even if they are
+ // identical
+ if (if_name == "int_master") {
return intPort;
+ } else if (if_name == "int_slave") {
+ // memory leak...but will be removed in the next patch
+ return new IntPort(name() + ".int_slave", this, this, latency);
+ }
return BasicPioDevice::getPort(if_name, idx);
}
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2005-2008 The Regents of The University of Michigan
# Copyright (c) 2011 Regents of the University of California
# All rights reserved.
#
# Authors: Nathan Binkert
# Rick Strong
+# Andreas Hansson
import sys
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
+ icache_port = MasterPort("Instruction Port")
+ dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
- _uncached_ports = []
+ _uncached_slave_ports = []
+ _uncached_master_ports = []
if buildEnv['TARGET_ISA'] == 'x86':
- _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
+ _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
+ _uncached_master_ports += ["interrupts.int_master"]
def connectCachedPorts(self, bus):
for p in self._cached_ports:
- exec('self.%s = bus.port' % p)
+ exec('self.%s = bus.slave' % p)
def connectUncachedPorts(self, bus):
- for p in self._uncached_ports:
- exec('self.%s = bus.port' % p)
+ for p in self._uncached_slave_ports:
+ exec('self.%s = bus.master' % p)
+ for p in self._uncached_master_ports:
+ exec('self.%s = bus.slave' % p)
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
self.toL2Bus = Bus()
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
- self.l2cache.cpu_side = self.toL2Bus.port
+ self.toL2Bus.master = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
- physmem_port = Port("Physical Memory Port")
+ physmem_port = MasterPort("Physical Memory Port")
class RubyDirectedTester(MemObject):
type = 'RubyDirectedTester'
- cpuPort = VectorPort("the cpu ports")
+ cpuPort = VectorMasterPort("the cpu ports")
requests_to_complete = Param.Int("checks to complete")
generator = Param.DirectedGenerator("the request generator")
"progress report interval (in accesses)")
trace_addr = Param.Addr(0, "address to trace")
- test = Port("Port to the memory system to test")
- functional = Port("Port to the functional memory used for verification")
+ test = MasterPort("Port to the memory system to test")
+ functional = MasterPort("Port to the functional memory " \
+ "used for verification")
suppress_func_warnings = Param.Bool(False,
"suppress warnings when functional accesses fail.\n")
sys = Param.System(Parent.any, "System Parameter")
traffic_type = Param.Counter(0, "Traffic type: uniform random, tornado, bit complement")
inj_rate = Param.Float(0.1, "Packet injection rate")
precision = Param.Int(3, "Number of digits of precision after decimal point")
- test = Port("Port to the memory system to test")
+ test = MasterPort("Port to the memory system to test")
system = Param.System(Parent.any, "System we belong to")
class RubyTester(MemObject):
type = 'RubyTester'
- cpuPort = VectorPort("the cpu ports")
+ cpuPort = VectorMasterPort("the cpu ports")
checks_to_complete = Param.Int(100, "checks to complete")
deadlock_threshold = Param.Int(50000, "how often to check for deadlock")
wakeup_frequency = Param.Int(10, "number of cycles between wakeups")
class PioDevice(MemObject):
type = 'PioDevice'
abstract = True
- pio = Port("Programmed I/O port")
+ pio = SlavePort("Programmed I/O port")
system = Param.System(Parent.any, "System this device is part of")
class BasicPioDevice(PioDevice):
class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
- dma = Port("DMA port")
+ dma = MasterPort("DMA port")
min_backoff_delay = Param.Latency('4ns',
"min time between a nack packet being received and the next request made by the device")
max_backoff_delay = Param.Latency('10us',
class EtherLink(EtherObject):
type = 'EtherLink'
- int0 = Port("interface 0")
- int1 = Port("interface 1")
+ int0 = SlavePort("interface 0")
+ int1 = SlavePort("interface 1")
delay = Param.Latency('0us', "packet transmit delay")
delay_var = Param.Latency('0ns', "packet transmit delay variability")
speed = Param.NetworkBandwidth('1Gbps', "link speed")
class EtherDevice(PciDevice):
type = 'EtherDevice'
abstract = True
- interface = Port("Ethernet Interface")
+ interface = MasterPort("Ethernet Interface")
class IGbE(EtherDevice):
# Base class for two IGbE adapters listed above
type = 'PciDevice'
abstract = True
platform = Param.Platform(Parent.any, "Platform this device is part of.")
- config = Port("PCI configuration space port")
+ config = SlavePort("PCI configuration space port")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
- self.cchip.pio = bus.port
- self.pchip.pio = bus.port
+ self.cchip.pio = bus.master
+ self.pchip.pio = bus.master
self.pciconfig.pio = bus.default
bus.use_default_range = True
- self.fake_sm_chip.pio = bus.port
- self.fake_uart1.pio = bus.port
- self.fake_uart2.pio = bus.port
- self.fake_uart3.pio = bus.port
- self.fake_uart4.pio = bus.port
- self.fake_ppc.pio = bus.port
- self.fake_OROM.pio = bus.port
- self.fake_pnp_addr.pio = bus.port
- self.fake_pnp_write.pio = bus.port
- self.fake_pnp_read0.pio = bus.port
- self.fake_pnp_read1.pio = bus.port
- self.fake_pnp_read2.pio = bus.port
- self.fake_pnp_read3.pio = bus.port
- self.fake_pnp_read4.pio = bus.port
- self.fake_pnp_read5.pio = bus.port
- self.fake_pnp_read6.pio = bus.port
- self.fake_pnp_read7.pio = bus.port
- self.fake_ata0.pio = bus.port
- self.fake_ata1.pio = bus.port
- self.fb.pio = bus.port
- self.io.pio = bus.port
- self.uart.pio = bus.port
- self.backdoor.pio = bus.port
+ self.fake_sm_chip.pio = bus.master
+ self.fake_uart1.pio = bus.master
+ self.fake_uart2.pio = bus.master
+ self.fake_uart3.pio = bus.master
+ self.fake_uart4.pio = bus.master
+ self.fake_ppc.pio = bus.master
+ self.fake_OROM.pio = bus.master
+ self.fake_pnp_addr.pio = bus.master
+ self.fake_pnp_write.pio = bus.master
+ self.fake_pnp_read0.pio = bus.master
+ self.fake_pnp_read1.pio = bus.master
+ self.fake_pnp_read2.pio = bus.master
+ self.fake_pnp_read3.pio = bus.master
+ self.fake_pnp_read4.pio = bus.master
+ self.fake_pnp_read5.pio = bus.master
+ self.fake_pnp_read6.pio = bus.master
+ self.fake_pnp_read7.pio = bus.master
+ self.fake_ata0.pio = bus.master
+ self.fake_ata1.pio = bus.master
+ self.fb.pio = bus.master
+ self.io.pio = bus.master
+ self.uart.pio = bus.master
+ self.backdoor.pio = bus.master
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
- self.gic.pio = bus.port
- self.l2x0_fake.pio = bus.port
- self.a9scu.pio = bus.port
- self.local_cpu_timer.pio = bus.port
+ self.gic.pio = bus.master
+ self.l2x0_fake.pio = bus.master
+ self.a9scu.pio = bus.master
+ self.local_cpu_timer.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, l2x0, a9scu, local_cpu_timer)
bridge.ranges = [AddrRange(self.realview_io.pio_addr,
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
- self.uart.pio = bus.port
- self.realview_io.pio = bus.port
- self.timer0.pio = bus.port
- self.timer1.pio = bus.port
- self.clcd.pio = bus.port
- self.clcd.dma = bus.port
- self.kmi0.pio = bus.port
- self.kmi1.pio = bus.port
- self.cf_ctrl.pio = bus.port
- self.cf_ctrl.config = bus.port
- self.cf_ctrl.dma = bus.port
- self.dmac_fake.pio = bus.port
- self.uart1_fake.pio = bus.port
- self.uart2_fake.pio = bus.port
- self.uart3_fake.pio = bus.port
- self.smc_fake.pio = bus.port
- self.sp810_fake.pio = bus.port
- self.watchdog_fake.pio = bus.port
- self.gpio0_fake.pio = bus.port
- self.gpio1_fake.pio = bus.port
- self.gpio2_fake.pio = bus.port
- self.ssp_fake.pio = bus.port
- self.sci_fake.pio = bus.port
- self.aaci_fake.pio = bus.port
- self.mmc_fake.pio = bus.port
- self.rtc_fake.pio = bus.port
- self.flash_fake.pio = bus.port
+ self.uart.pio = bus.master
+ self.realview_io.pio = bus.master
+ self.timer0.pio = bus.master
+ self.timer1.pio = bus.master
+ self.clcd.pio = bus.master
+ self.clcd.dma = bus.slave
+ self.kmi0.pio = bus.master
+ self.kmi1.pio = bus.master
+ self.cf_ctrl.pio = bus.master
+ self.cf_ctrl.config = bus.master
+ self.cf_ctrl.dma = bus.slave
+ self.dmac_fake.pio = bus.master
+ self.uart1_fake.pio = bus.master
+ self.uart2_fake.pio = bus.master
+ self.uart3_fake.pio = bus.master
+ self.smc_fake.pio = bus.master
+ self.sp810_fake.pio = bus.master
+ self.watchdog_fake.pio = bus.master
+ self.gpio0_fake.pio = bus.master
+ self.gpio1_fake.pio = bus.master
+ self.gpio2_fake.pio = bus.master
+ self.ssp_fake.pio = bus.master
+ self.sci_fake.pio = bus.master
+ self.aaci_fake.pio = bus.master
+ self.mmc_fake.pio = bus.master
+ self.rtc_fake.pio = bus.master
+ self.flash_fake.pio = bus.master
# Reference for memory map and interrupt number
# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
- self.gic.pio = bus.port
- self.l2x0_fake.pio = bus.port
+ self.gic.pio = bus.master
+ self.l2x0_fake.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, l2x0)
bridge.ranges = [AddrRange(self.realview_io.pio_addr,
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
- self.uart.pio = bus.port
- self.realview_io.pio = bus.port
- self.timer0.pio = bus.port
- self.timer1.pio = bus.port
- self.clcd.pio = bus.port
- self.clcd.dma = bus.port
- self.kmi0.pio = bus.port
- self.kmi1.pio = bus.port
- self.dmac_fake.pio = bus.port
- self.uart1_fake.pio = bus.port
- self.uart2_fake.pio = bus.port
- self.uart3_fake.pio = bus.port
- self.smc_fake.pio = bus.port
- self.sp810_fake.pio = bus.port
- self.watchdog_fake.pio = bus.port
- self.gpio0_fake.pio = bus.port
- self.gpio1_fake.pio = bus.port
- self.gpio2_fake.pio = bus.port
- self.ssp_fake.pio = bus.port
- self.sci_fake.pio = bus.port
- self.aaci_fake.pio = bus.port
- self.mmc_fake.pio = bus.port
- self.rtc_fake.pio = bus.port
- self.flash_fake.pio = bus.port
- self.smcreg_fake.pio = bus.port
+ self.uart.pio = bus.master
+ self.realview_io.pio = bus.master
+ self.timer0.pio = bus.master
+ self.timer1.pio = bus.master
+ self.clcd.pio = bus.master
+ self.clcd.dma = bus.slave
+ self.kmi0.pio = bus.master
+ self.kmi1.pio = bus.master
+ self.dmac_fake.pio = bus.master
+ self.uart1_fake.pio = bus.master
+ self.uart2_fake.pio = bus.master
+ self.uart3_fake.pio = bus.master
+ self.smc_fake.pio = bus.master
+ self.sp810_fake.pio = bus.master
+ self.watchdog_fake.pio = bus.master
+ self.gpio0_fake.pio = bus.master
+ self.gpio1_fake.pio = bus.master
+ self.gpio2_fake.pio = bus.master
+ self.ssp_fake.pio = bus.master
+ self.sci_fake.pio = bus.master
+ self.aaci_fake.pio = bus.master
+ self.mmc_fake.pio = bus.master
+ self.rtc_fake.pio = bus.master
+ self.flash_fake.pio = bus.master
+ self.smcreg_fake.pio = bus.master
class VExpress_ELT(RealView):
pci_cfg_base = 0xD0000000
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
- self.gic.pio = bus.port
- self.a9scu.pio = bus.port
- self.local_cpu_timer.pio = bus.port
+ self.gic.pio = bus.master
+ self.a9scu.pio = bus.master
+ self.local_cpu_timer.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
- self.elba_uart.pio = bus.port
- self.uart.pio = bus.port
- self.realview_io.pio = bus.port
- self.v2m_timer0.pio = bus.port
- self.v2m_timer1.pio = bus.port
- self.elba_timer0.pio = bus.port
- self.elba_timer1.pio = bus.port
- self.clcd.pio = bus.port
- self.clcd.dma = bus.port
- self.kmi0.pio = bus.port
- self.kmi1.pio = bus.port
- self.elba_kmi0.pio = bus.port
- self.elba_kmi1.pio = bus.port
- self.cf_ctrl.pio = bus.port
- self.cf_ctrl.config = bus.port
+ self.elba_uart.pio = bus.master
+ self.uart.pio = bus.master
+ self.realview_io.pio = bus.master
+ self.v2m_timer0.pio = bus.master
+ self.v2m_timer1.pio = bus.master
+ self.elba_timer0.pio = bus.master
+ self.elba_timer1.pio = bus.master
+ self.clcd.pio = bus.master
+ self.clcd.dma = bus.slave
+ self.kmi0.pio = bus.master
+ self.kmi1.pio = bus.master
+ self.elba_kmi0.pio = bus.master
+ self.elba_kmi1.pio = bus.master
+ self.cf_ctrl.pio = bus.master
+ self.cf_ctrl.config = bus.master
self.cf_ctrl.dma = bus.port
- self.ide.pio = bus.port
- self.ide.config = bus.port
- self.ide.dma = bus.port
- self.ethernet.pio = bus.port
- self.ethernet.config = bus.port
- self.ethernet.dma = bus.port
+ self.ide.pio = bus.master
+ self.ide.config = bus.master
+ self.ide.dma = bus.slave
+ self.ethernet.pio = bus.master
+ self.ethernet.config = bus.master
+ self.ethernet.dma = bus.slave
self.pciconfig.pio = bus.default
bus.use_default_range = True
- self.l2x0_fake.pio = bus.port
- self.dmac_fake.pio = bus.port
- self.uart1_fake.pio = bus.port
- self.uart2_fake.pio = bus.port
- self.uart3_fake.pio = bus.port
- self.smc_fake.pio = bus.port
- self.sp810_fake.pio = bus.port
- self.watchdog_fake.pio = bus.port
- self.aaci_fake.pio = bus.port
- self.elba_aaci_fake.pio = bus.port
- self.mmc_fake.pio = bus.port
- self.rtc_fake.pio = bus.port
- self.spsc_fake.pio = bus.port
- self.lan_fake.pio = bus.port
- self.usb_fake.pio = bus.port
+ self.l2x0_fake.pio = bus.master
+ self.dmac_fake.pio = bus.master
+ self.uart1_fake.pio = bus.master
+ self.uart2_fake.pio = bus.master
+ self.uart3_fake.pio = bus.master
+ self.smc_fake.pio = bus.master
+ self.sp810_fake.pio = bus.master
+ self.watchdog_fake.pio = bus.master
+ self.aaci_fake.pio = bus.master
+ self.elba_aaci_fake.pio = bus.master
+ self.mmc_fake.pio = bus.master
+ self.rtc_fake.pio = bus.master
+ self.spsc_fake.pio = bus.master
+ self.lan_fake.pio = bus.master
+ self.usb_fake.pio = bus.master
apic_id = Param.Int(1, 'APIC id for this IO APIC')
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
pio_addr = Param.Addr("Device address")
- int_port = Port("Port for sending and receiving interrupt messages")
+ int_master = MasterPort("Port for sending interrupt messages")
int_latency = Param.Latency('1ns', \
"Latency for an interrupt to propagate through this device.")
external_int_pic = Param.I8259(NULL, "External PIC, if any")
def attachIO(self, bus):
self.south_bridge.attachIO(bus)
- self.i_dont_exist.pio = bus.port
- self.behind_pci.pio = bus.port
- self.com_1.pio = bus.port
- self.fake_com_2.pio = bus.port
- self.fake_com_3.pio = bus.port
- self.fake_com_4.pio = bus.port
- self.fake_floppy.pio = bus.port
+ self.i_dont_exist.pio = bus.master
+ self.behind_pci.pio = bus.master
+ self.com_1.pio = bus.master
+ self.fake_com_2.pio = bus.master
+ self.fake_com_3.pio = bus.master
+ self.fake_com_4.pio = bus.master
+ self.fake_floppy.pio = bus.master
self.pciconfig.pio = bus.default
bus.use_default_range = True
self.speaker.i8254 = self.pit
self.io_apic.external_int_pic = self.pic1
# Connect to the bus
- self.cmos.pio = bus.port
- self.dma1.pio = bus.port
- self.ide.pio = bus.port
- self.ide.config = bus.port
- self.ide.dma = bus.port
- self.keyboard.pio = bus.port
- self.pic1.pio = bus.port
- self.pic2.pio = bus.port
- self.pit.pio = bus.port
- self.speaker.pio = bus.port
- self.io_apic.pio = bus.port
- self.io_apic.int_port = bus.port
+ self.cmos.pio = bus.master
+ self.dma1.pio = bus.master
+ self.ide.pio = bus.master
+ self.ide.config = bus.master
+ self.ide.dma = bus.slave
+ self.keyboard.pio = bus.master
+ self.pic1.pio = bus.master
+ self.pic2.pio = bus.master
+ self.pit.pio = bus.master
+ self.speaker.pio = bus.master
+ self.io_apic.pio = bus.master
+ self.io_apic.int_master = bus.slave
Port *getPort(const std::string &if_name, int idx = -1)
{
- if (if_name == "int_port")
+ if (if_name == "int_master")
return intPort;
return PioDevice::getPort(if_name, idx);
}
IntDev(MemObject * parent, Tick latency = 0)
{
if (parent != NULL) {
- intPort = new IntPort(parent->name() + ".int_port",
+ intPort = new IntPort(parent->name() + ".int_master",
parent, this, latency);
} else {
intPort = NULL;
class Bridge(MemObject):
type = 'Bridge'
- slave = Port('Slave port')
- master = Port('Master port')
+ slave = SlavePort('Slave port')
+ master = MasterPort('Master port')
req_size = Param.Int(16, "The number of requests to buffer")
resp_size = Param.Int(16, "The number of requests to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
class Bus(MemObject):
type = 'Bus'
- port = VectorPort("vector port for connecting devices")
+ slave = VectorSlavePort("vector port for connecting masters")
+ master = VectorMasterPort("vector port for connecting slaves")
bus_id = Param.Int(0, "blah")
clock = Param.Clock("1GHz", "bus clock speed")
header_cycles = Param.Int(1, "cycles of overhead per transaction")
width = Param.Int(64, "bus width (bytes)")
block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
- default = \
- Port("Default port for requests that aren't handled by a device.")
+ default = MasterPort("Default port for requests that aren't handled " \
+ "by a device.")
use_default_range = \
Param.Bool(False, "Query default port device for legal range.")
class PhysicalMemory(MemObject):
type = 'PhysicalMemory'
- port = VectorPort("the access port")
+ port = VectorSlavePort("the access port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
latency = Param.Latency('30ns', "latency of an access")
prefetch_on_access = Param.Bool(False,
"notify the hardware prefetcher on every access (not just misses)")
prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
- cpu_side = Port("Port on side closer to CPU")
- mem_side = Port("Port on side closer to MEM")
+ cpu_side = SlavePort("Port on side closer to CPU")
+ mem_side = MasterPort("Port on side closer to MEM")
addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
system = Param.System(Parent.any, "System we belong to")
Port *
RubyPort::getPort(const std::string &if_name, int idx)
{
- if (if_name == "port") {
- M5Port* cpuPort = new M5Port(csprintf("%s-port%d", name(), idx),
+ // used by the CPUs to connect the caches to the interconnect, and
+ // for the x86 case also the interrupt master
+ if (if_name == "slave") {
+ M5Port* cpuPort = new M5Port(csprintf("%s-slave%d", name(), idx),
this, ruby_system, access_phys_mem);
cpu_ports.push_back(cpuPort);
return cpuPort;
}
+ // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
+ // port
+ if (if_name == "master") {
+ PioPort* masterPort = new PioPort(csprintf("%s-master%d", name(), idx),
+ this);
+
+ return masterPort;
+ }
+
if (if_name == "pio_port") {
// ensure there is only one pio port
assert(pio_port == NULL);
class RubyPort(MemObject):
type = 'RubyPort'
abstract = True
- port = VectorPort("M5 port")
+ slave = VectorSlavePort("CPU slave port")
+ master = VectorMasterPort("CPU master port")
version = Param.Int(0, "")
- pio_port = Port("Ruby_pio_port")
+ pio_port = MasterPort("Ruby_pio_port")
physmem = Param.PhysicalMemory("")
- physMemPort = Port("port to physical memory")
+ physMemPort = MasterPort("port to physical memory")
using_ruby_tester = Param.Bool(False, "")
using_network_tester = Param.Bool(False, "")
access_phys_mem = Param.Bool(True,
# There are a few things we need that aren't in params.__all__ since
# normal users don't need them
from m5.params import ParamDesc, VectorParamDesc, \
- isNullPointer, SimObjectVector
+ isNullPointer, SimObjectVector, Port
from m5.proxy import *
from m5.proxy import isproxy
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2004-2006 The Regents of The University of Michigan
# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
# All rights reserved.
# Authors: Steve Reinhardt
# Nathan Binkert
# Gabe Black
+# Andreas Hansson
#####################################################################
#
# Port reference: encapsulates a reference to a particular port on a
# particular SimObject.
class PortRef(object):
- def __init__(self, simobj, name):
+ def __init__(self, simobj, name, role):
assert(isSimObject(simobj) or isSimObjectClass(simobj))
self.simobj = simobj
self.name = name
+ self.role = role
self.peer = None # not associated with another port yet
self.ccConnected = False # C++ port connection done?
self.index = -1 # always -1 for non-vector ports
def ccConnect(self):
from m5.internal.pyobject import connectPorts
+ if self.role == 'SLAVE':
+ # do nothing and let the master take care of it
+ return
+
if self.ccConnected: # already done this
return
peer = self.peer
if not self.peer: # nothing to connect to
return
+
+ # check that we connect a master to a slave
+ if self.role == peer.role:
+ raise TypeError, \
+ "cannot connect '%s' and '%s' due to identical role '%s'" \
+ % (peer, self, self.role)
+
try:
+ # self is always the master and peer the slave
connectPorts(self.simobj.getCCObject(), self.name, self.index,
peer.simobj.getCCObject(), peer.name, peer.index)
except:
# A reference to an individual element of a VectorPort... much like a
# PortRef, but has an index.
class VectorPortElementRef(PortRef):
- def __init__(self, simobj, name, index):
- PortRef.__init__(self, simobj, name)
+ def __init__(self, simobj, name, role, index):
+ PortRef.__init__(self, simobj, name, role)
self.index = index
def __str__(self):
# A reference to a complete vector-valued port (not just a single element).
# Can be indexed to retrieve individual VectorPortElementRef instances.
class VectorPortRef(object):
- def __init__(self, simobj, name):
+ def __init__(self, simobj, name, role):
assert(isSimObject(simobj) or isSimObjectClass(simobj))
self.simobj = simobj
self.name = name
+ self.role = role
self.elements = []
def __str__(self):
raise TypeError, "VectorPort index must be integer"
if key >= len(self.elements):
# need to extend list
- ext = [VectorPortElementRef(self.simobj, self.name, i)
+ ext = [VectorPortElementRef(self.simobj, self.name, self.role, i)
for i in range(len(self.elements), key+1)]
self.elements.extend(ext)
return self.elements[key]
# logical port in the SimObject class, not a particular port on a
# SimObject instance. The latter are represented by PortRef objects.
class Port(object):
- # Port("description")
- def __init__(self, *args):
- if len(args) == 1:
- self.desc = args[0]
- else:
- raise TypeError, 'wrong number of arguments'
- # self.name is set by SimObject class on assignment
- # e.g., pio_port = Port("blah") sets self.name to 'pio_port'
-
# Generate a PortRef for this port on the given SimObject with the
# given name
def makeRef(self, simobj):
- return PortRef(simobj, self.name)
+ return PortRef(simobj, self.name, self.role)
# Connect an instance of this port (on the given SimObject with
# the given name) with the port described by the supplied PortRef
def connect(self, simobj, ref):
self.makeRef(simobj).connect(ref)
+class MasterPort(Port):
+ # MasterPort("description")
+ def __init__(self, *args):
+ if len(args) == 1:
+ self.desc = args[0]
+ self.role = 'MASTER'
+ else:
+ raise TypeError, 'wrong number of arguments'
+
+class SlavePort(Port):
+ # SlavePort("description")
+ def __init__(self, *args):
+ if len(args) == 1:
+ self.desc = args[0]
+ self.role = 'SLAVE'
+ else:
+ raise TypeError, 'wrong number of arguments'
+
# VectorPort description object. Like Port, but represents a vector
# of connections (e.g., as on a Bus).
class VectorPort(Port):
def __init__(self, *args):
- Port.__init__(self, *args)
self.isVec = True
def makeRef(self, simobj):
- return VectorPortRef(simobj, self.name)
+ return VectorPortRef(simobj, self.name, self.role)
+
+class VectorMasterPort(VectorPort):
+ # VectorMasterPort("description")
+ def __init__(self, *args):
+ if len(args) == 1:
+ self.desc = args[0]
+ self.role = 'MASTER'
+ VectorPort.__init__(self, *args)
+ else:
+ raise TypeError, 'wrong number of arguments'
+
+class VectorSlavePort(VectorPort):
+ # VectorSlavePort("description")
+ def __init__(self, *args):
+ if len(args) == 1:
+ self.desc = args[0]
+ self.role = 'SLAVE'
+ VectorPort.__init__(self, *args)
+ else:
+ raise TypeError, 'wrong number of arguments'
# 'Fake' ParamDesc for Port references to assign to the _pdesc slot of
# proxy objects (via set_param_desc()) so that proxy error messages
'MaxAddr', 'MaxTick', 'AllMemory',
'Time',
'NextEthernetAddr', 'NULL',
- 'Port', 'VectorPort']
+ 'MasterPort', 'SlavePort',
+ 'VectorMasterPort', 'VectorSlavePort']
import SimObject
class System(MemObject):
type = 'System'
- system_port = Port("System port")
+ system_port = MasterPort("System port")
@classmethod
def export_method_cxx_predecls(cls, code):
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
-system.system_port = system.membus.port
-system.physmem.port = system.membus.port
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)
root = Root(full_system = False, system = system)
# Tie the cpu test and functional ports to the ruby cpu ports and
# physmem, respectively
#
- cpus[i].test = ruby_port.port
+ cpus[i].test = ruby_port.slave
cpus[i].functional = system.funcmem.port
#
# l2cache & bus
system.toL2Bus = Bus(clock="500GHz", width=16)
system.l2c = L2(size='64kB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
-system.l2c.mem_side = system.membus.port
+system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
cpu.l1c = L1(size = '32kB', assoc = 4)
cpu.l1c.cpu_side = cpu.test
- cpu.l1c.mem_side = system.toL2Bus.port
+ cpu.l1c.mem_side = system.toL2Bus.slave
system.funcmem.port = cpu.functional
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
# connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
# -----------------------
cpu.clock = '2GHz'
# connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
# Connect the system port for loading of binaries etc
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
# -----------------------
# run simulation
# l2cache & bus
system.toL2Bus = Bus()
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
-system.l2c.mem_side = system.membus.port
+system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
cpu.clock = '2GHz'
# connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
# connect system port to membus
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
# -----------------------
# run simulation
system = System(cpu = cpu,
physmem = ruby_memory,
membus = Bus())
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)
# Connect the system port for loading of binaries etc
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
root = Root(full_system = False, system = system)
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
-system.system_port = system.membus.port
-system.physmem.port = system.membus.port
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)
root = Root(full_system = False, system = system)
system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.iocache = IOCache(addr_range=mem_size)
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpu
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.iocache = IOCache(addr_range=mem_size)
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpu
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache(addr_range=mem_size)
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
#the system
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
#the system
system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
system.l2c.num_cpus = 2
#connect up the cpu and l1s
#the system
system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpu
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
#the system
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
#
# Tie the ruby tester ports to the ruby cpu ports
#
- tester.cpuPort = ruby_port.port
+ tester.cpuPort = ruby_port.slave
#
# Tell the sequencer this is the ruby tester so that it
cpu.clock = '2GHz'
# connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
# Connect the system port for loading of binaries etc
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
# -----------------------
# run simulation
# l2cache & bus
system.toL2Bus = Bus()
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
-system.l2c.mem_side = system.membus.port
+system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
cpu.clock = '2GHz'
# connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
# connect system port to membus
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
# -----------------------
# run simulation
system = System(cpu = AtomicSimpleCPU(cpu_id=0),
physmem = PhysicalMemory(),
membus = Bus())
-system.system_port = system.membus.port
-system.physmem.port = system.membus.port
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
system.cpu.connectAllPorts(system.membus)
system.cpu.clock = '2GHz'
# l2cache & bus
system.toL2Bus = Bus()
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
-system.l2c.mem_side = system.membus.port
+system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
# connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
# -----------------------
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
-system.system_port = system.membus.port
-system.physmem.port = system.membus.port
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpu
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
#the system
system = FSConfig.makeLinuxAlphaSystem('timing')
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpus
#create the l1/l2 bus
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
# from masters on the IO bus to the memory bus
test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(0, '8GB')])
-test_sys.iobridge.slave = test_sys.iobus.port
-test_sys.iobridge.master = test_sys.membus.port
+test_sys.iobridge.slave = test_sys.iobus.master
+test_sys.iobridge.master = test_sys.membus.slave
drive_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-server.rcS'))
drive_sys.cpu.connectAllPorts(drive_sys.membus)
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(0, '8GB')])
-drive_sys.iobridge.slave = drive_sys.iobus.port
-drive_sys.iobridge.master = drive_sys.membus.port
+drive_sys.iobridge.slave = drive_sys.iobus.master
+drive_sys.iobridge.master = drive_sys.membus.slave
root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
projects / gem5.git / commitdiff