[[sv/ldst]], be set to an arbitrary value. Deterministic behaviour
is *required*.
+**Apparent contradictory behaviour compared to Rc=1,VLi=0**
+
+In [[openpower/sv/normal]] mode when Rc=1 and VLi=0 the Vector of
+co-results appears to ignore VLi=0 because the last CR Field co-result
+element tested is written out regardless of the setting of VLi.
+This is because when Rc=1 the CR Fields are co-results *not* actual
+results.
+
+When looking at the *actual* number of results written (arithmetic
+results on arithmetic operations vs CR-Field results on *CR-Field*
+operations), and ignoring the Rc=1 co-results entirely,
+the totals (the behaviours) are consistent whether
+VLi=0 or VLi=1.
+
+*Programmer's Note: if necessary VL may be obtained by using the alias
+`getvl`, followed by incrementing or decrementing the GPR with the
+copy of VL, and using `setvl` with the same GPR, to adjust VL.
+Programmers should be aware that MAXVL will always limit
+VL*.
+
## Reduction and Iteration
Bearing in mind as described in the [[svp64/appendix]] SVP64 Horizontal