Implement halt request.

Also clean up some vestigial code.

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index 76bcf01d95f95068cf9a396dcab9e0642bb53996..e881776ebcd30d39c684e96f3028dbb99618d8ae 100644 (file)
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -75,26 +75,6 @@ class debug_module_t : public abstract_device_t
     bool load(reg_t addr, size_t len, uint8_t* bytes);
     bool store(reg_t addr, size_t len, const uint8_t* bytes);
 
-    void set_interrupt(uint32_t hartid) {
-      interrupt.insert(hartid);
-    }
-    void clear_interrupt(uint32_t hartid) {
-      interrupt.erase(hartid);
-    }
-    bool get_interrupt(uint32_t hartid) const {
-      return interrupt.find(hartid) != interrupt.end();
-    }
-
-    void set_halt_notification(uint32_t hartid) {
-      halt_notification.insert(hartid);
-    }
-    void clear_halt_notification(uint32_t hartid) {
-      halt_notification.erase(hartid);
-    }
-    bool get_halt_notification(uint32_t hartid) const {
-      return halt_notification.find(hartid) != halt_notification.end();
-    }
-
     // Debug Module Interface that the debugger (in our case through JTAG DTM)
     // uses to access the DM.
     // Return true for success, false for failure.
@@ -105,10 +85,6 @@ class debug_module_t : public abstract_device_t
     static const unsigned progsize = 8;
 
     sim_t *sim;
-    // Track which interrupts from module to debugger are set.
-    std::set<uint32_t> interrupt;
-    // Track which halt notifications from debugger to module are set.
-    std::set<uint32_t> halt_notification;
 
     uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE];
     uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE];

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 1e63cf02ec51b40a849b5342aa965e7d9e7e0b0b..0ac0e0ac43c729cfa08f5c6a7b3dd079b1f2177e 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -63,8 +63,7 @@ bool processor_t::slow_path()
 void processor_t::step(size_t n)
 {
   if (state.dcsr.cause == DCSR_CAUSE_NONE) {
-    // TODO: get_interrupt() isn't super fast. Does that matter?
-    if (sim->debug_module.get_interrupt(id)) {
+    if (halt_request) {
       enter_debug_mode(DCSR_CAUSE_DEBUGINT);
     } else if (state.dcsr.halt) {
       enter_debug_mode(DCSR_CAUSE_HALT);

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 13aeaa4b85759390dc8df686cfb92e2845ddbc71..58837d12fa14c87673b5515c140a9be646f989cb 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -609,19 +609,15 @@ reg_t processor_t::get_csr(int which)
       {
         uint32_t v = 0;
         v = set_field(v, DCSR_XDEBUGVER, 1);
-        v = set_field(v, DCSR_NDRESET, 0);
-        v = set_field(v, DCSR_FULLRESET, 0);
-        v = set_field(v, DCSR_PRV, state.dcsr.prv);
-        v = set_field(v, DCSR_STEP, state.dcsr.step);
-        v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
-        v = set_field(v, DCSR_STOPCYCLE, 0);
-        v = set_field(v, DCSR_STOPTIME, 0);
         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
-        v = set_field(v, DCSR_HALT, state.dcsr.halt);
+        v = set_field(v, DCSR_STOPCYCLE, 0);
+        v = set_field(v, DCSR_STOPTIME, 0);
         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
+        v = set_field(v, DCSR_STEP, state.dcsr.step);
+        v = set_field(v, DCSR_PRV, state.dcsr.prv);
         return v;
       }
     case CSR_DPC: