cpu-o3: Fix too strict assert condition in writeback()

The assert() in the LSQ writeback() only allowed ReExec faults.
However, a SplitRequest which completed the translation in
PartialFault state (i.e. any but the very first cacheline
translation failed) may end up here. The assert() condition is
extended accordingly.

The patch also removes the superfluous/unused Complete/Squashed
states from the LSQ request. (The completion of the request is
recorded in the flags still.)

Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 6f7820113f8a922f72e67aca34fedcbe00045efd..4701a8c9acc5a19d647b920390e3a3b34bb61011 100644 (file)
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -223,8 +223,6 @@ class LSQ
             NotIssued,
             Translation,
             Request,
-            Complete,
-            Squashed,
             Fault,
             PartialFault,
         };

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 27a563071e102b9ab750993de7eac0b63462b3a2..a028424b0229f2897c7605c19ae0710e56114f5f 100644 (file)
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -985,7 +985,6 @@ LSQ<Impl>::SingleDataRequest::recvTimingResp(PacketPtr pkt)
 {
     assert(_numOutstandingPackets == 1);
     auto state = dynamic_cast<LSQSenderState*>(pkt->senderState);
-    setState(State::Complete);
     flags.set(Flag::Complete);
     state->outstanding--;
     assert(pkt == _packets.front());
@@ -1005,7 +1004,6 @@ LSQ<Impl>::SplitDataRequest::recvTimingResp(PacketPtr pkt)
     numReceivedPackets++;
     state->outstanding--;
     if (numReceivedPackets == _packets.size()) {
-        setState(State::Complete);
         flags.set(Flag::Complete);
         /* Assemble packets. */
         PacketPtr resp = isLoad()

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index b71ed7f78d2ef0cf8c1174cbed323d9d0a0018e0..c2483d56742892b1c5f6909520c9508ad337a3c3 100644 (file)
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -968,8 +968,10 @@ LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt)
             // the access as this discards the current fault.
 
             // If we have an outstanding fault, the fault should only be of
-            // type ReExec.
-            assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr);
+            // type ReExec or - in case of a SplitRequest - a partial
+            // translation fault
+            assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr ||
+                   inst->savedReq->isPartialFault());
 
             DPRINTF(LSQUnit, "Not completing instruction [sn:%lli] access "
                     "due to pending fault.\n", inst->seqNum);