(define_insn "mulsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
- (match_operand:SI 2 "gpc_reg_operand" "r")))]
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
+ (clobber (match_scratch:SI 3 "=&q"))]
""
"multiply %0,%1,%2")
(subreg:SI
(mult:DI
(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))]
+ (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))
+ (clobber (match_scratch:SI 3 "=&q"))]
""
"multm %0,%1,%2")
(subreg:SI
(mult:DI
(zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))]
+ (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))
+ (clobber (match_scratch:SI 3 "=&q"))]
""
"multmu %0,%1,%2")
(define_insn "mulsidi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+ (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
+ (clobber (match_scratch:SI 3 "=&q"))]
""
"multiply %L0,%1,%2\;multm %0,%1,%2"
[(set_attr "type" "multi")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
+ (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
+ (clobber (reg:SI 180))]
"reload_completed"
- [(set (match_dup 3)
- (mult:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 4)
- (subreg:SI (mult:DI
- (sign_extend:DI (match_dup 1))
- (sign_extend:DI (match_dup 2))) 0))]
+ [(parallel [(set (match_dup 3)
+ (mult:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:SI 180))])
+ (parallel [(set (match_dup 4)
+ (subreg:SI (mult:DI
+ (sign_extend:DI (match_dup 1))
+ (sign_extend:DI (match_dup 2))) 0))
+ (clobber (reg:SI 180))])]
"
{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+ (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
+ (clobber (match_scratch:SI 3 "=&q"))]
""
"multiplu %L0,%1,%2\;multmu %0,%1,%2"
[(set_attr "type" "multi")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
- (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
+ (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
+ (clobber (reg:SI 180))]
"reload_completed"
- [(set (match_dup 3)
- (mult:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 4)
- (subreg:SI (mult:DI (zero_extend:DI (match_dup 1))
- (zero_extend:DI (match_dup 2))) 0))]
+ [(parallel [(set (match_dup 3)
+ (mult:SI (match_dup 1) (match_dup 2)))
+ (clobber (reg:SI 180))])
+ (parallel [(set (match_dup 4)
+ (subreg:SI (mult:DI (zero_extend:DI (match_dup 1))
+ (zero_extend:DI (match_dup 2))) 0))
+ (clobber (reg:SI 180))])]
"
{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")