Updating gowin

diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
index e15de6423471b362672b1450cb0d493a573fdd04..af805b254703a8641ca3b378a447126304c0c041 100644 (file)
--- a/techlibs/gowin/arith_map.v
+++ b/techlibs/gowin/arith_map.v
@@ -45,7 +45,7 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
 
    genvar              i;
    generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-      ALU #(.ALU_MODE(32'b0))
+      ALU #(.ALU_MODE(0))
       alu(.I0(AA[i]),
          .I1(BB[i]),
          .I3(1'b0),

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index ac3dbfb29f6be483e7cfcb9ea13c316cd6b75341..1fc029e3c8466dacaaeb4c57c8397bb7c85ae765 100644 (file)
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -226,7 +226,7 @@ struct SynthGowinPass : public ScriptPass
                if (check_label("vout"))
                {
                        if (!vout_file.empty() || help_mode)
-                               run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s",
+                                run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s",
                                                help_mode ? "<file-name>" : vout_file.c_str()));
                }
        }