rs6000: Remove the ancient mfcr peepholes

These peepholes replace two mfcr;mask sequences by one mfcr;mask;mask
sequence.  On modern cpus, the original mfcr's were actually mfocrf,
but the new insn is an actual heavy-weight mfcr.  This is very bad
for performance.

The comment says there is a three cycle delay between two consecutive
mfcr insns.  This may have been true on rios, and it's true on 604,
but on 603, 750, 7400 it is just a single cycle (on 7450 it is two).

This is also a define_peephole, and we should get rid of those.

So this patch just removes the peepholes; the benefit is marginal at
best, and it so very hurts in other cases.

	* config/rs6000/rs6000.md (define_peepholes for two mfcr's): Delete.

From-SVN: r237062

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 84e81cf117c851bf6040f52bb33cd6a7af83bb15..90fee17f577e86d90e843320526439609d08cd47 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2016-06-03  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/rs6000.md (define_peepholes for two mfcr's): Delete.
+
 2016-06-03  Alan Hayward  <alan.hayward@arm.com>
 
        * tree-vect-stmts.c (vectorizable_call) Remove GOMP_SIMD_LANE code.

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6628bc691f4999107393b6a3b5ee65acf93f1d6b..133eef1c14a8176827f54c7b38b5193758f89a7e 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11251,37 +11251,6 @@
                    (const_int 0)))]
   "")
 
-;; There is a 3 cycle delay between consecutive mfcr instructions
-;; so it is useful to combine 2 scc instructions to use only one mfcr.
-
-(define_peephole
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-       (match_operator:SI 1 "scc_comparison_operator"
-                          [(match_operand 2 "cc_reg_operand" "y")
-                           (const_int 0)]))
-   (set (match_operand:SI 3 "gpc_reg_operand" "=r")
-       (match_operator:SI 4 "scc_comparison_operator"
-                          [(match_operand 5 "cc_reg_operand" "y")
-                           (const_int 0)]))]
-  "REGNO (operands[2]) != REGNO (operands[5])"
-  "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
-  [(set_attr "type" "mfcr")
-   (set_attr "length" "12")])
-
-(define_peephole
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-       (match_operator:DI 1 "scc_comparison_operator"
-                          [(match_operand 2 "cc_reg_operand" "y")
-                           (const_int 0)]))
-   (set (match_operand:DI 3 "gpc_reg_operand" "=r")
-       (match_operator:DI 4 "scc_comparison_operator"
-                          [(match_operand 5 "cc_reg_operand" "y")
-                           (const_int 0)]))]
-  "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
-  "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
-  [(set_attr "type" "mfcr")
-   (set_attr "length" "12")])
-
 
 (define_mode_attr scc_eq_op2 [(SI "rKLI")
                              (DI "rKJI")])