add SVP64 LD/ST "bitrev" alternative CSV

diff --git a/openpower/isatables/svldst_minor_58.csv b/openpower/isatables/svldst_minor_58.csv
new file mode 100644 (file)
index 0000000..21837a1
--- /dev/null
+++ b/openpower/isatables/svldst_minor_58.csv
@@ -0,0 +1,4 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+0,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ld,SVDS
+1,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldu,SVDS
+2,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,1,lwa,SVDS

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index ad5b91c39aea65ea9ef8f2b0f5868d59bc56b99a..987be31094334070cba5cc6b2a18ce936e3eed6a 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -404,6 +404,7 @@ class In2Sel(Enum):
     RS = 13  # for shiftrot (M-Form)
     FRB = 14
     CONST_SSI = 15 # for SVD-Form
+    CONST_SDS = 16 # for SVDS-Form
 
 
 @unique