oppc: introduce GPRZero class

diff --git a/src/openpower/oppc/pc_ast.py b/src/openpower/oppc/pc_ast.py
index 0a51e62f72f2d737e2c8fa0606a8e2a79fe6a145..5a8d0a06e56a3557a8b78fefb418503f9c98d72b 100644 (file)
--- a/src/openpower/oppc/pc_ast.py
+++ b/src/openpower/oppc/pc_ast.py
@@ -125,7 +125,11 @@ class Literal(Token, metaclass=LiteralMeta):
         return super().__new__(cls, value)
 
 
-class GPR(Literal, choices=("RA", "RA0", "RB", "RB0", "RC", "RC0", "RS", "RSp", "RT", "RTp")):
+class GPR(Literal, choices=("RA", "RB", "RC", "RS", "RSp", "RT", "RTp")):
+    pass
+
+
+class GPRZero(GPR, choices=("RA", "RB", "RC")):
     pass
 
 

diff --git a/src/openpower/oppc/pc_parser.py b/src/openpower/oppc/pc_parser.py
index aa8cd1c73ce8854c2c4777a7021899c791fe44c4..596830ed3b950c11366e72f16ba69ce07b067ac6 100644 (file)
--- a/src/openpower/oppc/pc_parser.py
+++ b/src/openpower/oppc/pc_parser.py
@@ -377,13 +377,11 @@ class Parser:
         """
         if len(p) == 4:
             def reg0(left, op, right):
-                if (isinstance(left, (pc_ast.GPR, pc_ast.FPR)) and
+                if (isinstance(left, pc_ast.Symbol) and
                         isinstance(op, pc_ast.BitOr) and
-                        (isinstance(right, pc_ast.DecLiteral) and (str(right) == "0"))):
-                    if isinstance(left, pc_ast.GPR):
-                        return pc_ast.GPR(f"{str(left)}0")
-                    else:
-                        return pc_ast.FPR(f"{str(left)}0")
+                        (isinstance(right, pc_ast.DecLiteral) and (str(right) == "0")) and
+                        (str(left) in frozenset(pc_ast.GPRZero))):
+                    return pc_ast.GPRZero(str(left))
                 return None
 
             def repeat(left, op, right):

diff --git a/src/openpower/oppc/pc_util.py b/src/openpower/oppc/pc_util.py
index 7ab389295a997e5f67ec101abe39b687ffd03609..183f6febd8fcc888471225977ae3b39aa710d081 100644 (file)
--- a/src/openpower/oppc/pc_util.py
+++ b/src/openpower/oppc/pc_util.py
@@ -379,11 +379,11 @@ class PseudocodeVisitor(mdis.visitor.ContextVisitor):
         yield node
         self[node].emit(stmt=str(node))
 
-    @Hook(pc_ast.GPR, pc_ast.FPR)
+    @Hook(pc_ast.GPR, pc_ast.FPR, pc_ast.GPRZero)
     def Reg(self, node):
         yield node
-        if node.endswith("0"):
-            self[node].emit(stmt=f"({str(node)[:-1]}|0)")
+        if isinstance(node, pc_ast.GPRZero):
+            self[node].emit(stmt=f"({str(node)}|0)")
         else:
             self[node].emit(stmt=f"({str(node)})")