boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
eventq_index=0
init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=tests/halt.sh
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
pio=system.membus.default
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[1]
[system.simple_disk]
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
+warn: Obsolete M5 ivlb instruction encountered.
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:30:57
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 13:05:58
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 126320000
-Exiting @ tick 1903338216000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 121062000
+Exiting @ tick 1906207240000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.905651 # Number of seconds simulated
-sim_ticks 1905651402000 # Number of ticks simulated
-final_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.906207 # Number of seconds simulated
+sim_ticks 1906207240000 # Number of ticks simulated
+final_tick 1906207240000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 124387 # Simulator instruction rate (inst/s)
-host_op_rate 124387 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4179760275 # Simulator tick rate (ticks/s)
-host_mem_usage 352908 # Number of bytes of host memory used
-host_seconds 455.92 # Real time elapsed on the host
-sim_insts 56710998 # Number of instructions simulated
-sim_ops 56710998 # Number of ops (including micro ops) simulated
+host_inst_rate 147655 # Simulator instruction rate (inst/s)
+host_op_rate 147655 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5021061637 # Simulator tick rate (ticks/s)
+host_mem_usage 308576 # Number of bytes of host memory used
+host_seconds 379.64 # Real time elapsed on the host
+sim_insts 56056069 # Number of instructions simulated
+sim_ops 56056069 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28857792 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7816896 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 450903 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122139 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 450903 # Number of read requests accepted
-system.physmem.writeReqs 122139 # Number of write requests accepted
-system.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu0.inst 903488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24906304 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 74560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 378304 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28912320 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 903488 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 74560 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7848000 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7848000 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 14117 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 389161 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1165 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 5911 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 451755 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 122625 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 122625 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 473972 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 13065895 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1390019 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 39114 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 198459 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15167459 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 473972 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 39114 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 513086 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4117076 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4117076 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4117076 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 473972 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 13065895 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1390019 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 39114 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 198459 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19284535 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 451755 # Number of read requests accepted
+system.physmem.writeReqs 122625 # Number of write requests accepted
+system.physmem.readBursts 451755 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 122625 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 28904128 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7846080 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 28912320 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7848000 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 28020 # Per bank write bursts
-system.physmem.perBankRdBursts::1 28240 # Per bank write bursts
-system.physmem.perBankRdBursts::2 28746 # Per bank write bursts
-system.physmem.perBankRdBursts::3 28309 # Per bank write bursts
-system.physmem.perBankRdBursts::4 27973 # Per bank write bursts
-system.physmem.perBankRdBursts::5 28180 # Per bank write bursts
-system.physmem.perBankRdBursts::6 28116 # Per bank write bursts
-system.physmem.perBankRdBursts::7 27456 # Per bank write bursts
-system.physmem.perBankRdBursts::8 27700 # Per bank write bursts
-system.physmem.perBankRdBursts::9 28070 # Per bank write bursts
-system.physmem.perBankRdBursts::10 27744 # Per bank write bursts
-system.physmem.perBankRdBursts::11 28151 # Per bank write bursts
-system.physmem.perBankRdBursts::12 28476 # Per bank write bursts
-system.physmem.perBankRdBursts::13 28764 # Per bank write bursts
-system.physmem.perBankRdBursts::14 28477 # Per bank write bursts
-system.physmem.perBankRdBursts::15 28339 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7807 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7750 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8222 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7743 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7390 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7636 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7609 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6913 # Per bank write bursts
-system.physmem.perBankWrBursts::8 6944 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7275 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7157 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7547 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7916 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8234 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8082 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7890 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 3217 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 28097 # Per bank write bursts
+system.physmem.perBankRdBursts::1 28602 # Per bank write bursts
+system.physmem.perBankRdBursts::2 29043 # Per bank write bursts
+system.physmem.perBankRdBursts::3 27571 # Per bank write bursts
+system.physmem.perBankRdBursts::4 27384 # Per bank write bursts
+system.physmem.perBankRdBursts::5 27564 # Per bank write bursts
+system.physmem.perBankRdBursts::6 27744 # Per bank write bursts
+system.physmem.perBankRdBursts::7 27694 # Per bank write bursts
+system.physmem.perBankRdBursts::8 27865 # Per bank write bursts
+system.physmem.perBankRdBursts::9 28720 # Per bank write bursts
+system.physmem.perBankRdBursts::10 28531 # Per bank write bursts
+system.physmem.perBankRdBursts::11 28618 # Per bank write bursts
+system.physmem.perBankRdBursts::12 28938 # Per bank write bursts
+system.physmem.perBankRdBursts::13 28977 # Per bank write bursts
+system.physmem.perBankRdBursts::14 28277 # Per bank write bursts
+system.physmem.perBankRdBursts::15 28002 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7839 # Per bank write bursts
+system.physmem.perBankWrBursts::1 8045 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8418 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7040 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6886 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7040 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7326 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7097 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7158 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7908 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7739 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7821 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8331 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8401 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7959 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7587 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
-system.physmem.totGap 1905651381000 # Total gap between requests
+system.physmem.totGap 1906202745000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 450903 # Read request sizes (log2)
+system.physmem.readPktSize::6 451755 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 122139 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 122625 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 319401 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 41325 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 46009 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9272 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2017 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 4338 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 3967 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2525 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2198 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 2156 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 2109 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1642 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1631 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1933 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1904 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 2142 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1252 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 959 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 893 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1164 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1205 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3479 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4546 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5068 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5411 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5622 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5871 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6194 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 6561 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7197 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6383 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6572 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6556 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6376 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 959 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 926 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 871 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 926 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 950 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 955 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1154 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 1202 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 1166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 1281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 1449 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 1666 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 1863 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 2097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 1921 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 1890 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 1701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 1710 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 1833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 1636 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 350 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 43 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 66892 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 549.396161 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 336.305192 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 420.466175 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 14808 22.14% 22.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 11177 16.71% 38.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5157 7.71% 46.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2881 4.31% 50.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2294 3.43% 54.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1713 2.56% 56.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1492 2.23% 59.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1822 2.72% 61.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 25548 38.19% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 66892 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 7192 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 62.794355 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2475.959084 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 7189 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 7192 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 7192 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.046023 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.810949 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 3.823344 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 5742 79.84% 79.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 42 0.58% 80.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 691 9.61% 90.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 254 3.53% 93.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 102 1.42% 94.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 28 0.39% 95.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 28 0.39% 95.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 90 1.25% 97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 10 0.14% 97.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 32 0.44% 97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 22 0.31% 97.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 14 0.19% 98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 15 0.21% 98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 7 0.10% 98.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 9 0.13% 98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 23 0.32% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 11 0.15% 99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34 2 0.03% 99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35 2 0.03% 99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36 1 0.01% 99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37 3 0.04% 99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38 2 0.03% 99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39 4 0.06% 99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40 3 0.04% 99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41 4 0.06% 99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42 2 0.03% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43 1 0.01% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44 2 0.03% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45 1 0.01% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47 8 0.11% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49 1 0.01% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50 1 0.01% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51 2 0.03% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52 4 0.06% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55 2 0.03% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56 13 0.18% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57 13 0.18% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads
-system.physmem.totQLat 8930594750 # Total ticks spent queuing
-system.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 7192 # Writes before turning the bus around for reads
+system.physmem.totQLat 9007685000 # Total ticks spent queuing
+system.physmem.totMemAccLat 17475691250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2258135000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 19944.97 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 38694.97 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 15.17 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing
-system.physmem.readRowHits 407659 # Number of row buffer hits during reads
-system.physmem.writeRowHits 98604 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes
-system.physmem.avgGap 3325500.37 # Average gap between requests
-system.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states
-system.physmem.memoryStateTime::REF 63633700000 # Time in different power states
+system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing
+system.physmem.readRowHits 408104 # Number of row buffer hits during reads
+system.physmem.writeRowHits 99226 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.36 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes
+system.physmem.avgGap 3318713.65 # Average gap between requests
+system.physmem.pageHitRate 88.35 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1805036475500 # Time in different power states
+system.physmem.memoryStateTime::REF 63652420000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 37488657000 # Time in different power states
+system.physmem.memoryStateTime::ACT 37517744500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 19303809 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 296468 # Transaction distribution
-system.membus.trans_dist::ReadResp 296393 # Transaction distribution
-system.membus.trans_dist::WriteReq 13039 # Transaction distribution
-system.membus.trans_dist::WriteResp 13039 # Transaction distribution
-system.membus.trans_dist::Writeback 122139 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 9699 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4861 # Transaction distribution
-system.membus.trans_dist::ReadExReq 162690 # Transaction distribution
-system.membus.trans_dist::ReadExResp 162297 # Transaction distribution
-system.membus.trans_dist::BadAddressError 75 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 36748378 # Total data (bytes)
-system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks)
+system.membus.throughput 19340215 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 296416 # Transaction distribution
+system.membus.trans_dist::ReadResp 296338 # Transaction distribution
+system.membus.trans_dist::WriteReq 12317 # Transaction distribution
+system.membus.trans_dist::WriteResp 12317 # Transaction distribution
+system.membus.trans_dist::Writeback 122625 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1033 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 3220 # Transaction distribution
+system.membus.trans_dist::ReadExReq 163308 # Transaction distribution
+system.membus.trans_dist::ReadExResp 163210 # Transaction distribution
+system.membus.trans_dist::BadAddressError 78 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39026 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 910934 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 950116 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124653 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 124653 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1074769 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 67930 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31453376 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 31521306 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306944 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 5306944 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 36828250 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 36828250 # Total data (bytes)
+system.membus.snoop_data_through_bus 38208 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 36079499 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1585687750 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3823460772 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 376710991 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 343977 # number of replacements
-system.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use
-system.l2c.tags.total_refs 2582565 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 27108862 # Number of tag accesses
-system.l2c.tags.data_accesses 27108862 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits
-system.l2c.Writeback_hits::total 822208 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2062288 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 867616 # number of overall hits
-system.l2c.overall_hits::cpu0.data 891053 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 210128 # number of overall hits
-system.l2c.overall_hits::cpu1.data 93491 # number of overall hits
-system.l2c.overall_hits::total 2062288 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3729 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 406 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 434 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 840 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 114695 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 6342 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 121037 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 14035 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 388087 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1238 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 6794 # number of demand (read+write) misses
-system.l2c.demand_misses::total 410154 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 14035 # number of overall misses
-system.l2c.overall_misses::cpu0.data 388087 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 1238 # number of overall misses
-system.l2c.overall_misses::cpu1.data 6794 # number of overall misses
-system.l2c.overall_misses::total 410154 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 1067454245 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 17881620237 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 96862500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 35356999 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 19081293981 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 964468 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 4567794 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 5532262 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 972461 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114995 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 1087456 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 9393947733 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 639497214 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 10033444947 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 1067454245 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 27275567970 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 96862500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 674854213 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 29114738928 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 1067454245 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 27275567970 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 96862500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 674854213 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 1317 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 4159 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 455 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 458 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 913 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 269131 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 31923 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 301054 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 881651 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1279140 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 211366 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 100285 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2472442 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 881651 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1279140 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 211366 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 100285 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2472442 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015919 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.270683 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.005857 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.006612 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.133148 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940535 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.801822 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.896610 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.892308 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947598 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.920044 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.426168 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.198666 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.402044 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015919 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.303397 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.005857 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.067747 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.165890 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015919 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.303397 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.005857 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.067747 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.165890 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76056.590310 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 65406.523369 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78241.114701 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 78223.449115 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 65998.519565 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 360.818556 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4325.562500 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 1483.577903 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2395.224138 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 264.965438 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 1294.590476 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81903.724949 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100835.259224 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 82895.684353 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 70984.895742 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 70984.895742 # average overall miss latency
+system.l2c.tags.replacements 344852 # number of replacements
+system.l2c.tags.tagsinuse 65305.335131 # Cycle average of tags in use
+system.l2c.tags.total_refs 2605080 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 409986 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 6.354071 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 7095487750 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 53708.677879 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 5228.517850 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 6139.451939 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 202.418952 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 26.268512 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.819529 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.079781 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.093681 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.003089 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.000401 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.996480 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 65134 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 2578 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 5246 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 6338 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 50733 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.993866 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 27313168 # Number of tag accesses
+system.l2c.tags.data_accesses 27313168 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst 979450 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 788527 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 94097 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 31413 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1893487 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 833565 # number of Writeback hits
+system.l2c.Writeback_hits::total 833565 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 47 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 175693 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 7721 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 183414 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst 979450 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 964220 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 94097 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 39134 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2076901 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 979450 # number of overall hits
+system.l2c.overall_hits::cpu0.data 964220 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 94097 # number of overall hits
+system.l2c.overall_hits::cpu1.data 39134 # number of overall hits
+system.l2c.overall_hits::total 2076901 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 14127 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 273418 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 1173 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 340 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 289058 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 511 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2953 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 76 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 110 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 116199 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 5616 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 121815 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 14127 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 389617 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 1173 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 5956 # number of demand (read+write) misses
+system.l2c.demand_misses::total 410873 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst 14127 # number of overall misses
+system.l2c.overall_misses::cpu0.data 389617 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 1173 # number of overall misses
+system.l2c.overall_misses::cpu1.data 5956 # number of overall misses
+system.l2c.overall_misses::total 410873 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst 1071252992 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 17895085485 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 90289500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 26594999 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 19083222976 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 1079964 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 402483 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 1482447 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 116495 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 68997 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 185492 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 9654052371 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 606648221 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 10260700592 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 1071252992 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 27549137856 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 90289500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 633243220 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 29343923568 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 1071252992 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 27549137856 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 90289500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 633243220 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 29343923568 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst 993577 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 1061945 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 95270 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 31753 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2182545 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 833565 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 833565 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 2617 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 557 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 3174 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 61 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 96 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 157 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 291892 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 13337 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 305229 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst 993577 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 1353837 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 95270 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 45090 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2487774 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 993577 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 1353837 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 95270 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 45090 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2487774 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.257469 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.012312 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.010708 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.132441 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933130 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.917415 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.930372 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.557377 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.791667 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.700637 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.398089 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.421084 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.399094 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.014218 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.287787 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.012312 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.132091 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.165157 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.014218 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.287787 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.012312 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.132091 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.165157 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75830.182771 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 65449.551547 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76973.145780 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 78220.585294 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 66018.663991 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 442.245700 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 787.637965 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 502.013884 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3426.323529 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 907.855263 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 1686.290909 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83082.060698 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108021.406873 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 84231.831811 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 75830.182771 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 70708.254147 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 76973.145780 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 106320.218267 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 71418.476191 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 75830.182771 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 70708.254147 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 76973.145780 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 106320.218267 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 71418.476191 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 80619 # number of writebacks
-system.l2c.writebacks::total 80619 # number of writebacks
+system.l2c.writebacks::writebacks 81105 # number of writebacks
+system.l2c.writebacks::total 81105 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst 14026 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 273392 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 1230 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 451 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 289099 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 2673 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 1056 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 3729 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 406 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 434 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 840 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 114695 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 6342 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 121037 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 14026 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 388087 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 1230 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 6793 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 410136 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 14026 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 388087 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 1230 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 6793 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 410136 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 890067005 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14473617763 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 80840000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 29712501 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 15474237269 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26950129 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10569046 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 37519175 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4153902 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4341434 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 8495336 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7989750261 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 560973786 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 8550724047 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 890067005 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 22463368024 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 80840000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 590686287 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 24024961316 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 890067005 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 22463368024 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 80840000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 590686287 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 24024961316 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367392500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22035500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 1389428000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2022747000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 583651500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 2606398500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3390139500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 605687000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 3995826500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270683 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006597 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.133140 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940535 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.801822 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.896610 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.892308 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947598 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.920044 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.426168 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198666 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.402044 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.165883 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.165883 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52940.897184 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65881.376940 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 53525.737789 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.352787 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.566288 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.457495 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10231.285714 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.304147 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10113.495238 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69660.841894 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 88453.766320 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 70645.538530 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu0.inst 14118 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 273418 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 1165 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 339 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 289040 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 2442 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 511 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 2953 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 34 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 76 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 110 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 116199 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 5616 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 121815 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 14118 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 389617 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 1165 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 5955 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 410855 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 14118 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 389617 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 1165 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 5955 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 410855 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 892690758 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14487194015 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 75058500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 22318999 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 15477262272 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24607428 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5172008 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 29779436 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 340034 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 768576 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 1108610 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8237283129 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 537421779 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 8774704908 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 892690758 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 22724477144 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 75058500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 559740778 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 24251967180 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 892690758 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 22724477144 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 75058500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 559740778 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 24251967180 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1368893000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 20915000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 1389808000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1950614000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 503814500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 2454428500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3319507000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524729500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 3844236500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.257469 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010676 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.132433 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933130 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.917415 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.930372 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.557377 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.791667 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.700637 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.398089 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421084 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.399094 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.287787 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.132069 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.165150 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.287787 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.132069 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.165150 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52985.516736 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65837.755162 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 53547.129366 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10076.751843 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10121.346380 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10084.468676 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10112.842105 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.272727 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70889.449384 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 95694.761218 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 72033.041153 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58325.168419 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93995.092863 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59028.044395 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58325.168419 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93995.092863 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59028.044395 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 41695 # number of replacements
-system.iocache.tags.tagsinuse 0.491978 # Cycle average of tags in use
+system.iocache.tags.replacements 41700 # number of replacements
+system.iocache.tags.tagsinuse 0.491390 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 41716 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1712295759000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 0.491978 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.030749 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.030749 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1711322153000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 0.491390 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.030712 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.030712 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 375543 # Number of tag accesses
-system.iocache.tags.data_accesses 375543 # Number of data accesses
-system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
+system.iocache.tags.tag_accesses 375588 # Number of tag accesses
+system.iocache.tags.data_accesses 375588 # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide 180 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 180 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
-system.iocache.overall_misses::total 41727 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21492883 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21492883 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 12499299192 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 12499299192 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 12520792075 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 12520792075 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 12520792075 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 12520792075 # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide 41732 # number of demand (read+write) misses
+system.iocache.demand_misses::total 41732 # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide 41732 # number of overall misses
+system.iocache.overall_misses::total 41732 # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide 22063883 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 22063883 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 12446165943 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 12446165943 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 12468229826 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 12468229826 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 12468229826 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 12468229826 # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide 180 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 180 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide 41732 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 41732 # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide 41732 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41732 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122816.474286 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122816.474286 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 300811.012514 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 300811.012514 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 300064.516380 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 300064.516380 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 367481 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122577.127778 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122577.127778 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299532.295509 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 299532.295509 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 298769.045960 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 298769.045960 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 366756 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 28552 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 28394 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 12.870587 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 12.916673 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide 180 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide 41732 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 41732 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide 41732 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 41732 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12701883 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12701883 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10283217961 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 10283217961 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 10295919844 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 10295919844 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 10295919844 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 10295919844 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 12477942 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits
+system.cpu0.branchPred.lookups 13535285 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 11399113 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 368683 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 9302001 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 5741441 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 61.722644 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 871515 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 32576 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 8879185 # DTB read hits
-system.cpu0.dtb.read_misses 30734 # DTB read misses
-system.cpu0.dtb.read_acv 556 # DTB read access violations
-system.cpu0.dtb.read_accesses 627584 # DTB read accesses
-system.cpu0.dtb.write_hits 5815647 # DTB write hits
-system.cpu0.dtb.write_misses 8173 # DTB write misses
-system.cpu0.dtb.write_acv 357 # DTB write access violations
-system.cpu0.dtb.write_accesses 210225 # DTB write accesses
-system.cpu0.dtb.data_hits 14694832 # DTB hits
-system.cpu0.dtb.data_misses 38907 # DTB misses
-system.cpu0.dtb.data_acv 913 # DTB access violations
-system.cpu0.dtb.data_accesses 837809 # DTB accesses
-system.cpu0.itb.fetch_hits 998260 # ITB hits
-system.cpu0.itb.fetch_misses 27519 # ITB misses
-system.cpu0.itb.fetch_acv 894 # ITB acv
-system.cpu0.itb.fetch_accesses 1025779 # ITB accesses
+system.cpu0.dtb.read_hits 9655924 # DTB read hits
+system.cpu0.dtb.read_misses 34371 # DTB read misses
+system.cpu0.dtb.read_acv 569 # DTB read access violations
+system.cpu0.dtb.read_accesses 673777 # DTB read accesses
+system.cpu0.dtb.write_hits 6329246 # DTB write hits
+system.cpu0.dtb.write_misses 8477 # DTB write misses
+system.cpu0.dtb.write_acv 351 # DTB write access violations
+system.cpu0.dtb.write_accesses 236111 # DTB write accesses
+system.cpu0.dtb.data_hits 15985170 # DTB hits
+system.cpu0.dtb.data_misses 42848 # DTB misses
+system.cpu0.dtb.data_acv 920 # DTB access violations
+system.cpu0.dtb.data_accesses 909888 # DTB accesses
+system.cpu0.itb.fetch_hits 1092484 # ITB hits
+system.cpu0.itb.fetch_misses 31809 # ITB misses
+system.cpu0.itb.fetch_acv 996 # ITB acv
+system.cpu0.itb.fetch_accesses 1124293 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 116074371 # number of cpu cycles simulated
+system.cpu0.numCycles 120980731 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 27854466 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 69491073 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 13535285 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 6612956 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 12980522 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1985487 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 37586938 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 31052 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 209286 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 361146 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 8301805 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 269407 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 80329317 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.865077 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.209142 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 67348795 83.84% 83.84% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 826622 1.03% 84.87% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1640547 2.04% 86.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 764329 0.95% 87.86% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2736993 3.41% 91.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 565546 0.70% 91.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 615994 0.77% 92.74% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 1025224 1.28% 94.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4805267 5.98% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 80329317 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.111880 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.574398 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 28693302 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 37589637 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 12241193 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 539176 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1266008 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 554913 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 40031 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 68046301 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 123637 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1266008 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 29596220 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 13874520 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 19704370 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 11366279 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 4521918 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 64294985 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 8881 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 963704 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 49626 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 1581472 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 42969329 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 77993479 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 77835647 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 147432 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 36982529 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 5986792 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1597094 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 233553 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 9775023 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 10212119 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6719453 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1264075 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 886942 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 56810323 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 2002217 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 55156303 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 107150 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 7195907 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 4115621 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 1359252 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 80329317 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.686627 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.367653 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 56644741 70.52% 70.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10637349 13.24% 83.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4503428 5.61% 89.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3111745 3.87% 93.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2708967 3.37% 96.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1473067 1.83% 98.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 832512 1.04% 99.48% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 359476 0.45% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 58032 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 80329317 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 91428 11.87% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 367704 47.76% 59.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 310812 40.37% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 3793 0.01% 0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 37662855 68.28% 68.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 60369 0.11% 68.40% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.40% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 16864 0.03% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 10116560 18.34% 86.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 6398898 11.60% 98.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 895081 1.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued
-system.cpu0.iq.rate 0.443500 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 55156303 # Type of FU issued
+system.cpu0.iq.rate 0.455910 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 769944 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013959 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 190884663 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 65713674 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 53746277 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 634353 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 307759 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 299045 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 55590646 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 331808 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 587688 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1466473 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 4362 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13302 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 593267 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18777 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 290466 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1266008 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10034082 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 1132931 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 62323042 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 565721 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 10212119 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6719453 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1762676 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 460962 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 503945 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13302 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 186944 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 388547 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 575491 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 54610252 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9715916 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 546050 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 3229636 # number of nop insts executed
-system.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 8136394 # Number of branches executed
-system.cpu0.iew.exec_stores 5837466 # Number of stores executed
-system.cpu0.iew.exec_rate 0.440174 # Inst execution rate
-system.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 25278333 # num instructions producing a value
-system.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3510502 # number of nop insts executed
+system.cpu0.iew.exec_refs 16068148 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 8653897 # Number of branches executed
+system.cpu0.iew.exec_stores 6352232 # Number of stores executed
+system.cpu0.iew.exec_rate 0.451396 # Inst execution rate
+system.cpu0.iew.wb_sent 54145867 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 54045322 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 27468175 # num instructions producing a value
+system.cpu0.iew.wb_consumers 37895992 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.446727 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.724831 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 7798809 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 642965 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 531823 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 79063309 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.688507 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.631609 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 59272342 74.97% 74.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 8075780 10.21% 85.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4311536 5.45% 90.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2381088 3.01% 93.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1583020 2.00% 95.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 598155 0.76% 96.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 490827 0.62% 97.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 478799 0.61% 97.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1871762 2.37% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 51248256 # Number of instructions committed
-system.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 79063309 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 54435622 # Number of instructions committed
+system.cpu0.commit.committedOps 54435622 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 13810671 # Number of memory references committed
-system.cpu0.commit.loads 8171492 # Number of loads committed
-system.cpu0.commit.membars 199624 # Number of memory barriers committed
-system.cpu0.commit.branches 7741114 # Number of branches committed
-system.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 47457125 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 657479 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction
+system.cpu0.commit.refs 14871832 # Number of memory references committed
+system.cpu0.commit.loads 8745646 # Number of loads committed
+system.cpu0.commit.membars 219982 # Number of memory barriers committed
+system.cpu0.commit.branches 8204799 # Number of branches committed
+system.cpu0.commit.fp_insts 296843 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 50375539 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 712916 # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass 3148922 5.78% 5.78% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 35215746 64.69% 70.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 59292 0.11% 70.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 16864 0.03% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 8965628 16.47% 87.09% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 6132206 11.27% 98.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess 895081 1.64% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 54435622 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1871762 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 130790454 # The number of ROB reads
-system.cpu0.rob.rob_writes 116222813 # The number of ROB writes
-system.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 48300626 # Number of Instructions Simulated
-system.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 67219449 # number of integer regfile reads
-system.cpu0.int_regfile_writes 36695614 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 128632 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 130173 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 820377 # number of misc regfile writes
+system.cpu0.rob.rob_reads 139225703 # The number of ROB reads
+system.cpu0.rob.rob_writes 125735253 # The number of ROB writes
+system.cpu0.timesIdled 1168278 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 40651414 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3691427340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 51290467 # Number of Instructions Simulated
+system.cpu0.committedOps 51290467 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 2.358737 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.358737 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.423956 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.423956 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 71570668 # number of integer regfile reads
+system.cpu0.int_regfile_writes 39014056 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 147010 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 148900 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 1947197 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 897129 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 111416521 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 210926490 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks)
+system.toL2Bus.throughput 111935595 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2200566 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2200471 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 12317 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 12317 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 833565 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 4571 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 1080 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 5651 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 347592 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 306043 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1987262 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3563495 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 190571 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 127415 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5868743 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63588928 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 138451052 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 6097280 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4501998 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 212639258 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 212628634 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 743808 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 5019455896 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4476579522 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 6206391842 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 429200431 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 227242208 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 1435370 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7369 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7369 # Transaction distribution
-system.iobus.trans_dist::WriteReq 54591 # Transaction distribution
-system.iobus.trans_dist::WriteResp 54591 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
+system.iobus.throughput 1431950 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
+system.iobus.trans_dist::WriteReq 53869 # Transaction distribution
+system.iobus.trans_dist::WriteResp 53869 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10422 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 39026 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83464 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83464 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 122490 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41688 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2735314 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total 67930 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 2729594 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 2729594 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 9777000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 380161835 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 26709000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 43245009 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 881127 # number of replacements
-system.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits
-system.cpu0.icache.overall_hits::total 6795719 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses
-system.cpu0.icache.overall_misses::total 926821 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked
+system.cpu0.icache.tags.replacements 993039 # number of replacements
+system.cpu0.icache.tags.tagsinuse 509.694749 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 7257459 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 993551 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 7.304566 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 26718502250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.694749 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995498 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.995498 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 9295490 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 9295490 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 7257459 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 7257459 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 7257459 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 7257459 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 7257459 # number of overall hits
+system.cpu0.icache.overall_hits::total 7257459 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 1044346 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 1044346 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 1044346 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 1044346 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 1044346 # number of overall misses
+system.cpu0.icache.overall_misses::total 1044346 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14667970749 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 14667970749 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 14667970749 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 14667970749 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 14667970749 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 14667970749 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 8301805 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 8301805 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 8301805 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 8301805 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 8301805 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 8301805 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125797 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.125797 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125797 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.125797 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125797 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.125797 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14045.125609 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14045.125609 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 4303 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.642857 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50661 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 50661 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 50661 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 50661 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 50661 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 50661 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 993685 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 993685 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 993685 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 993685 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 993685 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 993685 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12074149969 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 12074149969 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12074149969 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 12074149969 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12074149969 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 12074149969 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119695 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.119695 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.119695 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 1281204 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements 1357625 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 506.932074 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 11305784 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1358137 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 8.324480 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 25366000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.932074 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990102 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.990102 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits
-system.cpu0.dcache.overall_hits::total 10126574 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses
-system.cpu0.dcache.overall_misses::total 3345621 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses 61088591 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 61088591 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6897589 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6897589 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 4012977 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 4012977 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181053 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 181053 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208423 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 208423 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 10910566 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 10910566 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 10910566 # number of overall hits
+system.cpu0.dcache.overall_hits::total 10910566 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 1718976 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1718976 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1889613 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1889613 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22934 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 22934 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 507 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 3608589 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 3608589 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 3608589 # number of overall misses
+system.cpu0.dcache.overall_misses::total 3608589 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42674970043 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 42674970043 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 81294445080 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 81294445080 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 374188245 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 374188245 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3007034 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 3007034 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 123969415123 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 123969415123 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 8616565 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8616565 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 5902590 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5902590 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203987 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 203987 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208930 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 208930 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 14519155 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 14519155 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 14519155 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 14519155 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199497 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.199497 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320133 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.320133 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112429 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112429 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002427 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002427 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248540 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.248540 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248540 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.248540 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5931.033531 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5931.033531 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 3433420 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 538 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 116463 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.480779 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 76.857143 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks
-system.cpu0.dcache.writebacks::total 754427 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 808609 # number of writebacks
+system.cpu0.dcache.writebacks::total 808609 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 667238 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 667238 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1594728 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1594728 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5762 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5762 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 2261966 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 2261966 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 2261966 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 2261966 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1051738 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 1051738 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 294885 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 294885 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17172 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17172 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 507 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1346623 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1346623 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1346623 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1346623 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27880739944 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27880739944 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12002536573 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12002536573 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 202887753 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 202887753 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1992966 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1992966 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39883276517 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 39883276517 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39883276517 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 39883276517 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1460997001 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1460997001 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2069284998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2069284998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3530281999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3530281999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122060 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122060 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049959 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049959 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084182 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084182 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002427 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002427 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.092748 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.092748 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3930.899408 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3930.899408 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 2485884 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 831190 # Number of BTB hits
+system.cpu1.branchPred.lookups 1483279 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 1227619 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 44770 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 650934 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 463612 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 71.222582 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 99211 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 4550 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1846757 # DTB read hits
-system.cpu1.dtb.read_misses 10485 # DTB read misses
-system.cpu1.dtb.read_acv 25 # DTB read access violations
-system.cpu1.dtb.read_accesses 320297 # DTB read accesses
-system.cpu1.dtb.write_hits 1188866 # DTB write hits
-system.cpu1.dtb.write_misses 1998 # DTB write misses
-system.cpu1.dtb.write_acv 67 # DTB write access violations
-system.cpu1.dtb.write_accesses 130212 # DTB write accesses
-system.cpu1.dtb.data_hits 3035623 # DTB hits
-system.cpu1.dtb.data_misses 12483 # DTB misses
-system.cpu1.dtb.data_acv 92 # DTB access violations
-system.cpu1.dtb.data_accesses 450509 # DTB accesses
-system.cpu1.itb.fetch_hits 420713 # ITB hits
-system.cpu1.itb.fetch_misses 6600 # ITB misses
-system.cpu1.itb.fetch_acv 223 # ITB acv
-system.cpu1.itb.fetch_accesses 427313 # ITB accesses
+system.cpu1.dtb.read_hits 1187167 # DTB read hits
+system.cpu1.dtb.read_misses 8989 # DTB read misses
+system.cpu1.dtb.read_acv 6 # DTB read access violations
+system.cpu1.dtb.read_accesses 276351 # DTB read accesses
+system.cpu1.dtb.write_hits 628916 # DTB write hits
+system.cpu1.dtb.write_misses 1890 # DTB write misses
+system.cpu1.dtb.write_acv 35 # DTB write access violations
+system.cpu1.dtb.write_accesses 104365 # DTB write accesses
+system.cpu1.dtb.data_hits 1816083 # DTB hits
+system.cpu1.dtb.data_misses 10879 # DTB misses
+system.cpu1.dtb.data_acv 41 # DTB access violations
+system.cpu1.dtb.data_accesses 380716 # DTB accesses
+system.cpu1.itb.fetch_hits 316911 # ITB hits
+system.cpu1.itb.fetch_misses 5517 # ITB misses
+system.cpu1.itb.fetch_acv 125 # ITB acv
+system.cpu1.itb.fetch_accesses 322428 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 14964653 # number of cpu cycles simulated
+system.cpu1.numCycles 8637240 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 2818807 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 7093634 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 1483279 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 562823 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 1271731 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 278690 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 3719491 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 23500 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 54196 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 48363 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 894062 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 29430 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 8117811 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.873836 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.252237 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 6846080 84.33% 84.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 64163 0.79% 85.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 148479 1.83% 86.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 110798 1.36% 88.32% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 183312 2.26% 90.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 76211 0.94% 91.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 83539 1.03% 92.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 57250 0.71% 93.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 547979 6.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 8117811 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.171731 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.821285 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 2872853 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 3821739 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 1206360 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 38891 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 177967 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 63499 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 3800 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 6911640 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 11536 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 177967 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 2981399 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 177384 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 3223332 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 1138018 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 419709 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 6319378 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 203 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 45248 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 5428 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 135690 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 4267087 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 7667393 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 7641550 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 21648 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 3453234 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 813853 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 270338 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 17002 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 1051064 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 1262745 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 687524 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 118324 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 74010 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 5585108 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 271421 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 5341703 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 20645 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1049804 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 612834 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 207573 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 8117811 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.658023 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.347544 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 5813637 71.62% 71.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 1034901 12.75% 84.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 447279 5.51% 89.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 322285 3.97% 93.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 244246 3.01% 96.85% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 126246 1.56% 98.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 72876 0.90% 99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 50809 0.63% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 5532 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 8117811 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 4295 3.26% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 3.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 76591 58.14% 61.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 50850 38.60% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3518 0.07% 0.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 3268625 61.19% 61.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 9680 0.18% 61.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 8881 0.17% 61.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 1232456 23.07% 84.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 646098 12.10% 96.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 170686 3.20% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued
-system.cpu1.iq.rate 0.609525 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 5341703 # Type of FU issued
+system.cpu1.iq.rate 0.618450 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 131736 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 18885884 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 6873502 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 5132762 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 67714 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 33978 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 32480 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 5434957 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 34964 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 63957 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 266370 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 353 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 1238 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 98626 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 72939 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 177967 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 80772 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 78093 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 6077668 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 83087 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 1262745 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 687524 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 253926 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 4593 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 73335 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 1238 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 19913 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 60148 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 80061 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 5287979 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 1198929 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 53724 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 483081 # number of nop insts executed
-system.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 1345265 # Number of branches executed
-system.cpu1.iew.exec_stores 1196645 # Number of stores executed
-system.cpu1.iew.exec_rate 0.603549 # Inst execution rate
-system.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 4203498 # num instructions producing a value
-system.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value
+system.cpu1.iew.exec_nop 221139 # number of nop insts executed
+system.cpu1.iew.exec_refs 1832774 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 762873 # Number of branches executed
+system.cpu1.iew.exec_stores 633845 # Number of stores executed
+system.cpu1.iew.exec_rate 0.612230 # Inst execution rate
+system.cpu1.iew.wb_sent 5189273 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 5165242 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 2532511 # num instructions producing a value
+system.cpu1.iew.wb_consumers 3587094 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.598020 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.706006 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1065222 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 63848 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 75650 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 7939844 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.623951 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.560784 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 6043541 76.12% 76.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 925286 11.65% 87.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 320402 4.04% 91.81% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 190890 2.40% 94.21% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 129096 1.63% 95.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 57238 0.72% 96.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 65164 0.82% 97.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 44060 0.55% 97.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 164167 2.07% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 8834118 # Number of instructions committed
-system.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 7939844 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 4954074 # Number of instructions committed
+system.cpu1.commit.committedOps 4954074 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 2811640 # Number of memory references committed
-system.cpu1.commit.loads 1676136 # Number of loads committed
-system.cpu1.commit.membars 41495 # Number of memory barriers committed
-system.cpu1.commit.branches 1262292 # Number of branches committed
-system.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 8189363 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 139415 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction
+system.cpu1.commit.refs 1585273 # Number of memory references committed
+system.cpu1.commit.loads 996375 # Number of loads committed
+system.cpu1.commit.membars 16576 # Number of memory barriers committed
+system.cpu1.commit.branches 700739 # Number of branches committed
+system.cpu1.commit.fp_insts 31280 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 4632533 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 77324 # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass 191990 3.88% 3.88% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 2969211 59.93% 63.81% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 9565 0.19% 64.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 8881 0.18% 64.18% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.18% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.18% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.18% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 1759 0.04% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 1012951 20.45% 84.66% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 589031 11.89% 96.55% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess 170686 3.45% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 4954074 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 164167 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 23736453 # The number of ROB reads
-system.cpu1.rob.rob_writes 20710450 # The number of ROB writes
-system.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 8410372 # Number of Instructions Simulated
-system.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 11653751 # number of integer regfile reads
-system.cpu1.int_regfile_writes 6367365 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 51509 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 51143 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 926936 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 206554 # number of misc regfile writes
-system.cpu1.icache.tags.replacements 210820 # number of replacements
-system.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy
+system.cpu1.rob.rob_reads 13715407 # The number of ROB reads
+system.cpu1.rob.rob_writes 12215098 # The number of ROB writes
+system.cpu1.timesIdled 57372 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 519429 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 3803095502 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 4765602 # Number of Instructions Simulated
+system.cpu1.committedOps 4765602 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 1.812413 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.812413 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.551751 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.551751 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 6848640 # number of integer regfile reads
+system.cpu1.int_regfile_writes 3746417 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 21244 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 19994 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 693471 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 115172 # number of misc regfile writes
+system.cpu1.icache.tags.replacements 94727 # number of replacements
+system.cpu1.icache.tags.tagsinuse 453.369242 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 794363 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 95239 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 8.340732 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 1880860642000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.369242 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885487 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.885487 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits
-system.cpu1.icache.overall_hits::total 1201520 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses
-system.cpu1.icache.overall_misses::total 219211 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.154295 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154295 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.154295 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13453.418898 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13453.418898 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses 989361 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 989361 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 794363 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 794363 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 794363 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 794363 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 794363 # number of overall hits
+system.cpu1.icache.overall_hits::total 794363 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 99697 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 99697 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 99697 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 99697 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 99697 # number of overall misses
+system.cpu1.icache.overall_misses::total 99697 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1381976879 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 1381976879 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 1381976879 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 1381976879 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 1381976879 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 1381976879 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 894060 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 894060 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 894060 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 894060 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 894060 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 894060 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111510 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.111510 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111510 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.111510 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111510 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.111510 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13861.769953 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13861.769953 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13861.769953 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13861.769953 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.217391 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7818 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 7818 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 7818 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 7818 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 7818 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 7818 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211393 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 211393 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 211393 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 211393 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 211393 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 211393 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 4396 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 4396 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 4396 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 4396 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 4396 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 4396 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 95301 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 95301 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 95301 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 95301 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 95301 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 95301 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1139734069 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 1139734069 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1139734069 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 1139734069 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1139734069 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 1139734069 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106594 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.106594 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.106594 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 102235 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 1521331 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 890954 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 890954 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30283 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 30283 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29173 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 29173 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 2412285 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 2412285 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 2412285 # number of overall hits
-system.cpu1.dcache.overall_hits::total 2412285 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 196472 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 196472 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 206616 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 206616 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5011 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 5011 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2898 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 2898 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 403088 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 403088 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 403088 # number of overall misses
-system.cpu1.dcache.overall_misses::total 403088 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2745758970 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2745758970 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6806020354 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 6806020354 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50048997 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 50048997 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21170434 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 21170434 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 9551779324 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 9551779324 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 9551779324 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 9551779324 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 1717803 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 1717803 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 1097570 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 1097570 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 35294 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 35294 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32071 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 32071 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 2815373 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 2815373 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 2815373 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 2815373 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114374 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.114374 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188249 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.188249 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.141979 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.141979 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090362 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090362 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143174 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.143174 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143174 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.143174 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9987.826182 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9987.826182 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7305.187716 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7305.187716 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23696.511243 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23696.511243 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 206242 # number of cycles access was blocked
+system.cpu1.dcache.tags.replacements 45361 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 428.999436 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 1451630 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 45680 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 31.778240 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 1880566804000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.999436 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837890 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.837890 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 6609919 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 6609919 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 960992 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 960992 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 477143 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 477143 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 12504 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 12504 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 10799 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 10799 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 1438135 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 1438135 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 1438135 # number of overall hits
+system.cpu1.dcache.overall_hits::total 1438135 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 81302 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 81302 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 95545 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 95545 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1156 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 1156 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 573 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 573 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 176847 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 176847 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 176847 # number of overall misses
+system.cpu1.dcache.overall_misses::total 176847 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1110177095 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 1110177095 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5046033431 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 5046033431 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13905498 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 13905498 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4132075 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 4132075 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 6156210526 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 6156210526 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 6156210526 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 6156210526 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 1042294 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 1042294 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 572688 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 572688 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 13660 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 13660 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11372 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 11372 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 1614982 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 1614982 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 1614982 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 1614982 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078003 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.078003 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166836 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.166836 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084627 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084627 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050387 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050387 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.109504 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.109504 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.109504 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.109504 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7211.300175 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7211.300175 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 236601 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 6165 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 38.378102 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks
-system.cpu1.dcache.writebacks::total 67781 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 24956 # number of writebacks
+system.cpu1.dcache.writebacks::total 24956 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 46173 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 46173 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 80581 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 80581 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 235 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 235 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 126754 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 126754 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 126754 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 126754 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35129 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 35129 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 14964 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 14964 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 921 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 921 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 573 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 573 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 50093 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 50093 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 50093 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 50093 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 398615352 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 398615352 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 730663501 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 730663501 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8358752 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8358752 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2984925 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2984925 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1129278853 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 1129278853 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1129278853 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 1129278853 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22397000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22397000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 533147000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 533147000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555544000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555544000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033704 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033704 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026129 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067423 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067423 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050387 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050387 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.031018 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.031018 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9075.735071 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9075.735071 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5209.293194 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5209.293194 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6410 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 202830 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 72673 40.72% 40.72% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.07% 40.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1926 1.08% 41.87% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 6 0.00% 41.88% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 103726 58.12% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 178462 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 71304 49.29% 49.29% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.09% 49.38% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1926 1.33% 50.71% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 6 0.00% 50.72% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 71298 49.28% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 144665 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1863558813000 97.76% 97.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 63845500 0.00% 97.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 565237000 0.03% 97.80% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 3385500 0.00% 97.80% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 42015112000 2.20% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1906206393000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.981162 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed
-system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed
-system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed
-system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed
-system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed
-system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed
-system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed
-system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed
-system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed
-system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed
-system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed
-system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed
-system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed
-system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed
-system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed
-system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed
-system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 211 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.687369 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.810621 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
+system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
+system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
+system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
+system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
+system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
+system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
+system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
+system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
+system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
+system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
+system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
+system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
+system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
+system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
+system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
+system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
+system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
+system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
+system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
+system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
+system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
+system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
+system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
+system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 234 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed
-system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed
-system.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed
-system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 169959 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 95 0.05% 0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3930 2.10% 2.15% # number of callpals executed
+system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 171605 91.48% 93.66% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6547 3.49% 97.15% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 4 0.00% 97.15% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed
+system.cpu0.kern.callpal::rti 4793 2.56% 99.72% # number of callpals executed
+system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed
+system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 187581 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 7378 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1286
-system.cpu0.kern.mode_good::user 1287
+system.cpu0.kern.mode_good::kernel 1369
+system.cpu0.kern.mode_good::user 1370
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.185552 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.313100 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1904135221500 99.89% 99.89% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2071163500 0.11% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3530 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3931 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2254 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 34590 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 8916 31.91% 31.91% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1925 6.89% 38.80% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 95 0.34% 39.14% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 17006 60.86% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 27942 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 8908 45.12% 45.12% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1925 9.75% 54.88% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 95 0.48% 55.36% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 8813 44.64% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 19741 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1876395415500 98.45% 98.45% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 531818000 0.03% 98.48% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 44293500 0.00% 98.48% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 28895956000 1.52% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1905867483000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.999103 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed
-system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed
-system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed
-system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed
-system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed
-system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed
-system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed
-system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed
-system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed
-system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed
-system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed
-system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed
-system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed
-system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed
-system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed
-system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 115 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.518229 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.706499 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
+system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
+system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
+system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
+system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
+system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
+system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
+system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 92 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed
-system.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed
-system.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed
-system.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed
-system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 298 1.04% 1.07% # number of callpals executed
+system.cpu1.kern.callpal::tbi 3 0.01% 1.08% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.02% 1.11% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 23527 82.20% 83.30% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2214 7.74% 91.04% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 91.04% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 3 0.01% 91.05% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.01% 91.06% # number of callpals executed
+system.cpu1.kern.callpal::rti 2394 8.36% 99.43% # number of callpals executed
+system.cpu1.kern.callpal::callsys 121 0.42% 99.85% # number of callpals executed
+system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 48076 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 460 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 662
-system.cpu1.kern.mode_good::user 460
-system.cpu1.kern.mode_good::idle 202
-system.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 28623 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 659 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2036 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 386
+system.cpu1.kern.mode_good::user 367
+system.cpu1.kern.mode_good::idle 19
+system.cpu1.kern.mode_switch_good::kernel 0.585736 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1068 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.009332 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.252123 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 1444110500 0.08% 0.08% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 692193000 0.04% 0.11% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1903401131500 99.89% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 299 # number of times the context was actually changed
---------- End Simulation Statistics ----------
\rmemcluster 1, usage 0, start 392, end 16384
\rfreeing pages 1069:16384
\rreserving pages 1069:1070
-\r4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles
+\r4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
\rSMP: 2 CPUs probed -- cpu_present_mask = 3
\rBuilt 1 zonelists
\rKernel command line: root=/dev/hda1 console=ttyS0
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
eventq_index=0
init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=tests/halt.sh
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
pio=system.membus.default
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[1]
[system.simple_disk]
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:25:00
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 13:05:52
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1860197780500 because m5_exit instruction encountered
+Exiting @ tick 1860172195000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.860188 # Number of seconds simulated
-sim_ticks 1860187818000 # Number of ticks simulated
-final_tick 1860187818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.860172 # Number of seconds simulated
+sim_ticks 1860172195000 # Number of ticks simulated
+final_tick 1860172195000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 129673 # Simulator instruction rate (inst/s)
-host_op_rate 129673 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4553007725 # Simulator tick rate (ticks/s)
-host_mem_usage 348812 # Number of bytes of host memory used
-host_seconds 408.56 # Real time elapsed on the host
-sim_insts 52979638 # Number of instructions simulated
-sim_ops 52979638 # Number of ops (including micro ops) simulated
+host_inst_rate 152063 # Simulator instruction rate (inst/s)
+host_op_rate 152063 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5340733222 # Simulator tick rate (ticks/s)
+host_mem_usage 304984 # Number of bytes of host memory used
+host_seconds 348.30 # Real time elapsed on the host
+sim_insts 52963419 # Number of instructions simulated
+sim_ops 52963419 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 963200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24881344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 965120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28496832 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 963200 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 963200 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7516608 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7516608 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15050 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388771 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28496512 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 965120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 965120 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7515712 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7515712 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15080 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 445263 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117447 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117447 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 517797 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13375716 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1425817 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15319331 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 517797 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 517797 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4040779 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4040779 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4040779 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 517797 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13375716 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1425817 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19360110 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 445263 # Number of read requests accepted
-system.physmem.writeReqs 117447 # Number of write requests accepted
-system.physmem.readBursts 445263 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 117447 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 28490624 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7515520 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 28496832 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7516608 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total 445258 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 117433 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 117433 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 518834 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13374624 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1425829 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15319287 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 518834 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 518834 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4040331 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4040331 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4040331 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 518834 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13374624 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1425829 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19359618 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 445258 # Number of read requests accepted
+system.physmem.writeReqs 117433 # Number of write requests accepted
+system.physmem.readBursts 445258 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 117433 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 28490432 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7513664 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 28496512 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7515712 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 171 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 28211 # Per bank write bursts
-system.physmem.perBankRdBursts::1 27992 # Per bank write bursts
-system.physmem.perBankRdBursts::2 28433 # Per bank write bursts
-system.physmem.perBankRdBursts::3 27987 # Per bank write bursts
-system.physmem.perBankRdBursts::4 27796 # Per bank write bursts
-system.physmem.perBankRdBursts::5 27217 # Per bank write bursts
-system.physmem.perBankRdBursts::6 27269 # Per bank write bursts
-system.physmem.perBankRdBursts::7 27319 # Per bank write bursts
-system.physmem.perBankRdBursts::8 27690 # Per bank write bursts
-system.physmem.perBankRdBursts::9 27272 # Per bank write bursts
-system.physmem.perBankRdBursts::10 28021 # Per bank write bursts
-system.physmem.perBankRdBursts::11 27509 # Per bank write bursts
-system.physmem.perBankRdBursts::12 27548 # Per bank write bursts
-system.physmem.perBankRdBursts::13 28237 # Per bank write bursts
-system.physmem.perBankRdBursts::14 28335 # Per bank write bursts
-system.physmem.perBankRdBursts::15 28330 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7921 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7511 # Per bank write bursts
-system.physmem.perBankWrBursts::2 7946 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7492 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7346 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6678 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6778 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6711 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7130 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6681 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7414 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6966 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7109 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7879 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8056 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7812 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 176 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 28223 # Per bank write bursts
+system.physmem.perBankRdBursts::1 27968 # Per bank write bursts
+system.physmem.perBankRdBursts::2 28292 # Per bank write bursts
+system.physmem.perBankRdBursts::3 27927 # Per bank write bursts
+system.physmem.perBankRdBursts::4 27805 # Per bank write bursts
+system.physmem.perBankRdBursts::5 27242 # Per bank write bursts
+system.physmem.perBankRdBursts::6 27352 # Per bank write bursts
+system.physmem.perBankRdBursts::7 27274 # Per bank write bursts
+system.physmem.perBankRdBursts::8 27691 # Per bank write bursts
+system.physmem.perBankRdBursts::9 27508 # Per bank write bursts
+system.physmem.perBankRdBursts::10 27933 # Per bank write bursts
+system.physmem.perBankRdBursts::11 27527 # Per bank write bursts
+system.physmem.perBankRdBursts::12 27552 # Per bank write bursts
+system.physmem.perBankRdBursts::13 28225 # Per bank write bursts
+system.physmem.perBankRdBursts::14 28330 # Per bank write bursts
+system.physmem.perBankRdBursts::15 28314 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7932 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7496 # Per bank write bursts
+system.physmem.perBankWrBursts::2 7821 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7427 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7353 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6703 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6854 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6665 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7118 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6889 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7323 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6981 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7116 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7874 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8055 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7794 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
-system.physmem.totGap 1860182401000 # Total gap between requests
+system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
+system.physmem.totGap 1860166839000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 445263 # Read request sizes (log2)
+system.physmem.readPktSize::6 445258 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 117447 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 316668 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 59729 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 27667 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 5430 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2043 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 4389 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 3993 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 3992 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2540 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2192 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 117433 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 317162 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 38754 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 44609 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9021 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2051 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 3954 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2513 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2195 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 2086 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1617 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1588 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1906 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1882 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2139 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1226 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 986 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 905 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 2106 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1630 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1618 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1898 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1857 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 2113 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1232 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 984 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 899 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1100 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1131 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2272 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3501 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4229 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4755 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4765 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4891 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5082 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5274 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5526 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5836 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 6245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6071 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6268 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5967 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 924 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 916 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 938 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 867 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 935 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 954 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 998 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1187 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 1182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 1234 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 1359 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 1592 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 1859 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 2023 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 1831 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 1802 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 1695 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 1731 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 1643 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 821 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 206 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 137 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 63749 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 564.805095 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 351.189585 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 419.649920 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 13350 20.94% 20.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 10335 16.21% 37.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4789 7.51% 44.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2797 4.39% 49.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2437 3.82% 52.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1576 2.47% 55.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1469 2.30% 57.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1613 2.53% 60.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 25383 39.82% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 63749 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6887 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 64.637723 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 16.523346 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2544.314640 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191 6884 99.96% 99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1114 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2248 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3162 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4215 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4772 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4937 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5276 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5563 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5819 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 6253 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6876 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6083 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6291 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6234 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6019 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 966 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 924 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 969 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 901 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 988 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1058 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 973 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 1179 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 1174 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 1276 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 1414 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 1656 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 1874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 1977 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 1860 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 1800 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 1689 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 1697 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 1803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 1633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 837 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 395 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 63680 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 565.384925 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 351.672479 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 419.574374 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 13299 20.88% 20.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 10397 16.33% 37.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4628 7.27% 44.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2746 4.31% 48.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2553 4.01% 52.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1655 2.60% 55.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1376 2.16% 57.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1696 2.66% 60.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 25330 39.78% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 63680 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6888 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 64.625581 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 16.554610 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2544.325145 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 6885 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6887 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6887 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.050966 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.814496 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 3.834643 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 5493 79.76% 79.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 28 0.41% 80.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 690 10.02% 90.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 216 3.14% 93.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 116 1.68% 95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 20 0.29% 95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 25 0.36% 95.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 93 1.35% 97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 19 0.28% 97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 44 0.64% 97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 11 0.16% 98.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 7 0.10% 98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 8 0.12% 98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 16 0.23% 98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 2 0.03% 98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 14 0.20% 98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 9 0.13% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33 1 0.01% 98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34 1 0.01% 98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35 3 0.04% 98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36 2 0.03% 99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37 1 0.01% 99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38 1 0.01% 99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39 2 0.03% 99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40 7 0.10% 99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41 4 0.06% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42 2 0.03% 99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43 3 0.04% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44 1 0.01% 99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45 4 0.06% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46 3 0.04% 99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47 3 0.04% 99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48 7 0.10% 99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50 4 0.06% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51 1 0.01% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53 1 0.01% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54 1 0.01% 99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56 7 0.10% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57 17 0.25% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6887 # Writes before turning the bus around for reads
-system.physmem.totQLat 8647566500 # Total ticks spent queuing
-system.physmem.totMemAccLat 16994429000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2225830000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 19425.49 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6888 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6888 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.044280 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.812634 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 3.762583 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 5511 80.01% 80.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 31 0.45% 80.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 662 9.61% 90.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 220 3.19% 93.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 110 1.60% 94.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 25 0.36% 95.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 25 0.36% 95.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 91 1.32% 96.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 31 0.45% 97.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 12 0.17% 97.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 22 0.32% 98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 6 0.09% 98.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 14 0.20% 98.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 3 0.04% 98.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 16 0.23% 98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 12 0.17% 98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34 7 0.10% 99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35 1 0.01% 99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36 1 0.01% 99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37 3 0.04% 99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38 4 0.06% 99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39 4 0.06% 99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40 4 0.06% 99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41 6 0.09% 99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43 3 0.04% 99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46 3 0.04% 99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48 2 0.03% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50 2 0.03% 99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51 2 0.03% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52 1 0.01% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53 1 0.01% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55 1 0.01% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56 8 0.12% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57 12 0.17% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6888 # Writes before turning the bus around for reads
+system.physmem.totQLat 8740437500 # Total ticks spent queuing
+system.physmem.totMemAccLat 17087243750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2225815000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 19634.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 38175.49 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 38384.24 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.02 # Average write queue length when enqueuing
-system.physmem.readRowHits 403062 # Number of row buffer hits during reads
-system.physmem.writeRowHits 95784 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.54 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 81.56 # Row buffer hit rate for writes
-system.physmem.avgGap 3305756.79 # Average gap between requests
-system.physmem.pageHitRate 88.67 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1761433244000 # Time in different power states
-system.physmem.memoryStateTime::REF 62115560000 # Time in different power states
+system.physmem.avgRdQLen 1.65 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.75 # Average write queue length when enqueuing
+system.physmem.readRowHits 403028 # Number of row buffer hits during reads
+system.physmem.writeRowHits 95855 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.53 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 81.63 # Row buffer hit rate for writes
+system.physmem.avgGap 3305840.75 # Average gap between requests
+system.physmem.pageHitRate 88.68 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1761575145500 # Time in different power states
+system.physmem.memoryStateTime::REF 62115040000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 36633312250 # Time in different power states
+system.physmem.memoryStateTime::ACT 36476358250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 19402968 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 295944 # Transaction distribution
-system.membus.trans_dist::ReadResp 295866 # Transaction distribution
+system.membus.throughput 19402477 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 295985 # Transaction distribution
+system.membus.trans_dist::ReadResp 295900 # Transaction distribution
system.membus.trans_dist::WriteReq 9597 # Transaction distribution
system.membus.trans_dist::WriteResp 9597 # Transaction distribution
-system.membus.trans_dist::Writeback 117447 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 174 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 174 # Transaction distribution
-system.membus.trans_dist::ReadExReq 156883 # Transaction distribution
-system.membus.trans_dist::ReadExResp 156883 # Transaction distribution
-system.membus.trans_dist::BadAddressError 78 # Transaction distribution
+system.membus.trans_dist::Writeback 117433 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 178 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 179 # Transaction distribution
+system.membus.trans_dist::ReadExReq 156844 # Transaction distribution
+system.membus.trans_dist::ReadExResp 156844 # Transaction distribution
+system.membus.trans_dist::BadAddressError 85 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884195 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884181 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748524 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30703168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30747308 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 36057580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 36057580 # Total data (bytes)
+system.membus.tot_pkt_size::total 36056364 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 36056364 # Total data (bytes)
system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 29864500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 29838500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1548275500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1526200750 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 98000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 104500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3770327047 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3755175800 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 376611244 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 376659242 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.261115 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.260971 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1710335896000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.261115 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1710335831000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.260971 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.078811 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.078811 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21272883 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21272883 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 12456693929 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 12456693929 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 12477966812 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 12477966812 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 12477966812 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 12477966812 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 12441682213 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 12441682213 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 12462816596 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 12462816596 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 12462816596 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 12462816596 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122964.641618 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 299785.664445 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 299052.529946 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 299052.529946 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 365915 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299424.389031 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 299424.389031 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 298689.433098 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 298689.433098 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 366119 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 28370 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 28395 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 12.897956 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 12.893784 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12274883 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 12274883 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10293819441 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 10293819441 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 10306094324 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 10306094324 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 10306094324 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 10306094324 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10278710729 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 10278710729 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 10290848112 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 10290848112 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 10290848112 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 10290848112 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247369.819239 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 247369.819239 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 13846630 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11622667 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 398238 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9513264 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5817388 # Number of BTB hits
+system.cpu.branchPred.lookups 13973676 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11739131 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 397652 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9590938 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5932533 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 61.150284 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 900921 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 39034 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.855608 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 905503 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 38808 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9912884 # DTB read hits
-system.cpu.dtb.read_misses 41215 # DTB read misses
-system.cpu.dtb.read_acv 553 # DTB read access violations
-system.cpu.dtb.read_accesses 941108 # DTB read accesses
-system.cpu.dtb.write_hits 6599017 # DTB write hits
-system.cpu.dtb.write_misses 10339 # DTB write misses
-system.cpu.dtb.write_acv 401 # DTB write access violations
-system.cpu.dtb.write_accesses 338138 # DTB write accesses
-system.cpu.dtb.data_hits 16511901 # DTB hits
-system.cpu.dtb.data_misses 51554 # DTB misses
-system.cpu.dtb.data_acv 954 # DTB access violations
-system.cpu.dtb.data_accesses 1279246 # DTB accesses
-system.cpu.itb.fetch_hits 1308304 # ITB hits
-system.cpu.itb.fetch_misses 36786 # ITB misses
-system.cpu.itb.fetch_acv 1079 # ITB acv
-system.cpu.itb.fetch_accesses 1345090 # ITB accesses
+system.cpu.dtb.read_hits 10112222 # DTB read hits
+system.cpu.dtb.read_misses 41745 # DTB read misses
+system.cpu.dtb.read_acv 542 # DTB read access violations
+system.cpu.dtb.read_accesses 945441 # DTB read accesses
+system.cpu.dtb.write_hits 6611008 # DTB write hits
+system.cpu.dtb.write_misses 10791 # DTB write misses
+system.cpu.dtb.write_acv 413 # DTB write access violations
+system.cpu.dtb.write_accesses 339727 # DTB write accesses
+system.cpu.dtb.data_hits 16723230 # DTB hits
+system.cpu.dtb.data_misses 52536 # DTB misses
+system.cpu.dtb.data_acv 955 # DTB access violations
+system.cpu.dtb.data_accesses 1285168 # DTB accesses
+system.cpu.itb.fetch_hits 1309723 # ITB hits
+system.cpu.itb.fetch_misses 39683 # ITB misses
+system.cpu.itb.fetch_acv 1073 # ITB acv
+system.cpu.itb.fetch_accesses 1349406 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 121969353 # number of cpu cycles simulated
+system.cpu.numCycles 121578156 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 28022459 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 70674133 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13846630 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6718309 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 13243332 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1983249 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37995640 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 254581 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 364654 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8542175 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 264688 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 81194854 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.870426 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.213908 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28154197 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 72069959 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13973676 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6838036 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 13462286 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2111809 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 36504135 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 258219 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 367287 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8654218 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 283642 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 80169891 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.898965 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.245398 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67951522 83.69% 83.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 854853 1.05% 84.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1698258 2.09% 86.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 823227 1.01% 87.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2753963 3.39% 91.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 558188 0.69% 91.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 642929 0.79% 92.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1006595 1.24% 93.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4905319 6.04% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 66707605 83.21% 83.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 850391 1.06% 84.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1701562 2.12% 86.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 829510 1.03% 87.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2814732 3.51% 90.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 566680 0.71% 91.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 649069 0.81% 92.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1061564 1.32% 93.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4988778 6.22% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 81194854 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.113525 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.579442 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29206421 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37679452 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 12104138 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 965352 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1239490 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 585042 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 69357398 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 129450 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1239490 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 30354385 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 13996332 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19984766 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 11324382 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4295497 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 65588313 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 7118 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 505148 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1530678 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 43795306 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 79617271 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79438234 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38180209 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5615089 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1682372 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 239607 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12205686 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10422971 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6895231 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1319326 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 854507 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58152614 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2049745 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 56795087 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 97937 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6861282 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3503589 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1388801 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 81194854 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.699491 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.361721 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 80169891 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.114936 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.592787 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 28969141 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 36597720 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 12749238 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 505228 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1348563 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 587502 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 42619 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 70583559 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 129875 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1348563 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 29902418 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 12633582 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 20046715 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 11807818 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4430793 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 66640171 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 8986 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 787429 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 47943 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1601274 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 44565634 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 80920867 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 80741427 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 166989 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38166970 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 6398656 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1681821 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 238696 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 9832739 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10696003 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 7004082 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1336985 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 877203 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58981840 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2047452 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 57223975 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 117650 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 7712570 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4365148 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1386476 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 80169891 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.713784 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.404933 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56519522 69.61% 69.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10856431 13.37% 82.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5145956 6.34% 89.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3402319 4.19% 93.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2626681 3.24% 96.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1459376 1.80% 98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 753323 0.93% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 333723 0.41% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 97523 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56166624 70.06% 70.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10391261 12.96% 83.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 4679899 5.84% 88.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3142763 3.92% 92.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2796032 3.49% 96.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1647190 2.05% 98.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 895238 1.12% 99.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 353951 0.44% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 96933 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 81194854 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 80169891 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 92642 11.69% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 372744 47.05% 58.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 326922 41.26% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 98738 11.92% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 400158 48.30% 60.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 329520 39.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 38726894 68.19% 68.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61723 0.11% 68.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10344006 18.21% 86.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6676923 11.76% 98.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 38901419 67.98% 67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61759 0.11% 68.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10584317 18.50% 86.65% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6690891 11.69% 98.34% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 949060 1.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 56795087 # Type of FU issued
-system.cpu.iq.rate 0.465650 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 792308 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013950 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 194982001 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 66741051 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55566428 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 693271 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 336387 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 327889 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 57217918 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 362191 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 598643 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 57223975 # Type of FU issued
+system.cpu.iq.rate 0.470676 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 828416 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014477 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 194870458 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 68419457 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55733530 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 693448 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 335810 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 328249 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 57682446 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 362659 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 614531 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1330641 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3245 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 517313 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1606237 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3745 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 13777 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 627539 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17932 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 166827 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 18239 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 375591 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1239490 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 10213175 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 697716 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 63724678 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 681593 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10422971 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6895231 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1805950 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 512370 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 16905 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 202448 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 409860 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 612308 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 56329043 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 9982328 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 466043 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1348563 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 9312966 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 978337 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 64604997 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 590069 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10696003 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 7004082 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1802911 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 468863 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 377382 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 13777 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 204854 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 411482 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 616336 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 56685901 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 10182131 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 538073 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3522319 # number of nop insts executed
-system.cpu.iew.exec_refs 16606918 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8922931 # Number of branches executed
-system.cpu.iew.exec_stores 6624590 # Number of stores executed
-system.cpu.iew.exec_rate 0.461829 # Inst execution rate
-system.cpu.iew.wb_sent 56008659 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 55894317 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 27713107 # num instructions producing a value
-system.cpu.iew.wb_consumers 37520284 # num instructions consuming a value
+system.cpu.iew.exec_nop 3575705 # number of nop insts executed
+system.cpu.iew.exec_refs 16819167 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8947461 # Number of branches executed
+system.cpu.iew.exec_stores 6637036 # Number of stores executed
+system.cpu.iew.exec_rate 0.466251 # Inst execution rate
+system.cpu.iew.wb_sent 56177988 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 56061779 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 28606216 # num instructions producing a value
+system.cpu.iew.wb_consumers 39617780 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.458265 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.738617 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.461117 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.722055 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7436889 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 660944 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 566942 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 79955364 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.702522 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.631936 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 8325898 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 566478 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 78821328 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.712415 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.665597 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 59166975 74.00% 74.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8627079 10.79% 84.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4603678 5.76% 90.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2536989 3.17% 93.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1507337 1.89% 95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 611638 0.76% 96.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 523619 0.65% 97.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 528614 0.66% 97.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1849435 2.31% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 58682621 74.45% 74.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8193641 10.40% 84.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4257107 5.40% 90.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2319840 2.94% 93.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1767395 2.24% 95.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 615421 0.78% 96.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 496583 0.63% 96.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 549859 0.70% 97.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1938861 2.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 79955364 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56170432 # Number of instructions committed
-system.cpu.commit.committedOps 56170432 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 78821328 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 56153459 # Number of instructions committed
+system.cpu.commit.committedOps 56153459 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 15470248 # Number of memory references committed
-system.cpu.commit.loads 9092330 # Number of loads committed
-system.cpu.commit.membars 226348 # Number of memory barriers committed
-system.cpu.commit.branches 8439871 # Number of branches committed
+system.cpu.commit.refs 15466309 # Number of memory references committed
+system.cpu.commit.loads 9089766 # Number of loads committed
+system.cpu.commit.membars 226357 # Number of memory barriers committed
+system.cpu.commit.branches 8438044 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 52020070 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740568 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 3198067 5.69% 5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 36230888 64.50% 70.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.30% # Class of committed instruction
+system.cpu.commit.int_insts 52003822 # Number of committed integer instructions.
+system.cpu.commit.function_calls 740374 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 3197313 5.69% 5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 36218566 64.50% 70.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 60658 0.11% 70.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 9318678 16.59% 86.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 6383871 11.37% 98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 949012 1.69% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 9316123 16.59% 86.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 6382496 11.37% 98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 949060 1.69% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 56170432 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1849435 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 56153459 # Class of committed instruction
+system.cpu.commit.bw_lim_events 1938861 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 141463709 # The number of ROB reads
-system.cpu.rob.rob_writes 128455843 # The number of ROB writes
-system.cpu.timesIdled 1197783 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 40774499 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3598399845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52979638 # Number of Instructions Simulated
-system.cpu.committedOps 52979638 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.302193 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.302193 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.434368 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.434368 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 73867254 # number of integer regfile reads
-system.cpu.int_regfile_writes 40307997 # number of integer regfile writes
-system.cpu.fp_regfile_reads 166020 # number of floating regfile reads
-system.cpu.fp_regfile_writes 167441 # number of floating regfile writes
-system.cpu.misc_regfile_reads 2027897 # number of misc regfile reads
-system.cpu.misc_regfile_writes 938938 # number of misc regfile writes
+system.cpu.rob.rob_reads 141112277 # The number of ROB reads
+system.cpu.rob.rob_writes 130308588 # The number of ROB writes
+system.cpu.timesIdled 1194216 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 41408265 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 3598759795 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52963419 # Number of Instructions Simulated
+system.cpu.committedOps 52963419 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.295512 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.295512 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.435633 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.435633 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 74250743 # number of integer regfile reads
+system.cpu.int_regfile_writes 40442410 # number of integer regfile writes
+system.cpu.fp_regfile_reads 166399 # number of floating regfile reads
+system.cpu.fp_regfile_writes 167429 # number of floating regfile writes
+system.cpu.misc_regfile_reads 2028427 # number of misc regfile reads
+system.cpu.misc_regfile_writes 938976 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.iobus.throughput 1454556 # Throughput (bytes/s)
+system.iobus.throughput 1454569 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51149 # Transaction distribution
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 380172568 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 380163354 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 43172756 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 43205758 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.throughput 111944057 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2118154 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2118059 # Transaction distribution
+system.cpu.toL2Bus.throughput 111909594 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2117185 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2117083 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 840946 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 840753 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 64 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 342489 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 300938 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020220 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677927 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5698147 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64643392 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586284 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 208229676 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 208219628 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 17344 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2480508998 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 342629 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 301078 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2018148 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678150 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5696298 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64577024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586668 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 208163692 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 208153644 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 17472 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 2479804999 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1518532368 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1516964420 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2189805164 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2185370157 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.icache.tags.replacements 1009436 # number of replacements
-system.cpu.icache.tags.tagsinuse 509.668112 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 7476172 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1009944 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 7.402561 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 26651967250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 509.668112 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.995446 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.995446 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 1008400 # number of replacements
+system.cpu.icache.tags.tagsinuse 509.648597 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 7589401 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1008908 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 7.522392 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 26586363250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 509.648597 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.995407 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.995407 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 9552342 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 9552342 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 7476173 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7476173 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7476173 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7476173 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7476173 # number of overall hits
-system.cpu.icache.overall_hits::total 7476173 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1066002 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1066002 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1066002 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1066002 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1066002 # number of overall misses
-system.cpu.icache.overall_misses::total 1066002 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14786308436 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14786308436 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14786308436 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14786308436 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14786308436 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14786308436 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 8542175 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8542175 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 8542175 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8542175 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 8542175 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8542175 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124793 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.124793 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.124793 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.124793 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.124793 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.124793 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13870.807406 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13870.807406 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13870.807406 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13870.807406 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 4221 # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses 9663349 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 9663349 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 7589402 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7589402 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 7589402 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 7589402 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 7589402 # number of overall hits
+system.cpu.icache.overall_hits::total 7589402 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1064815 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1064815 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1064815 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1064815 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1064815 # number of overall misses
+system.cpu.icache.overall_misses::total 1064815 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14788071318 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14788071318 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14788071318 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14788071318 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14788071318 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14788071318 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 8654217 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 8654217 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 8654217 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 8654217 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 8654217 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 8654217 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123040 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.123040 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.123040 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.123040 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.123040 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.123040 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13887.925431 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13887.925431 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13887.925431 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13887.925431 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 4640 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 182 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 23.065574 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 25.494505 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55835 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 55835 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 55835 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 55835 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 55835 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 55835 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010167 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1010167 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1010167 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1010167 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1010167 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1010167 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12133097628 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12133097628 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12133097628 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12133097628 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12133097628 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12133097628 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118256 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.118256 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.118256 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12010.981974 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12010.981974 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55683 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 55683 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 55683 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 55683 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 55683 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 55683 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009132 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1009132 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1009132 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1009132 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1009132 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1009132 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12130132326 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 12130132326 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12130132326 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 12130132326 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12130132326 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 12130132326 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116606 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.116606 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.116606 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12020.362377 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12020.362377 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 338321 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 65341.789916 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2546336 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 403490 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 6.310778 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 5544203750 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53907.448463 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 5292.784095 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 6141.557358 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.822562 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080761 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.093713 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.997037 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3494 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3325 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55443 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 26727783 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 26727783 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 995001 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 827094 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1822095 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 840946 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 840946 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 27 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 27 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 185467 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 185467 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 995001 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1012561 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2007562 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 995001 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1012561 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2007562 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 15052 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 273790 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 288842 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 115470 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 115470 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 15052 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 389260 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 404312 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 15052 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 389260 # number of overall misses
-system.cpu.l2cache.overall_misses::total 404312 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1147195743 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17910681229 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 19057876972 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262998 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 262998 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9445420357 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 9445420357 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 1147195743 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 27356101586 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 28503297329 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 1147195743 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 27356101586 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 28503297329 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010053 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1100884 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2110937 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 840946 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 840946 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.tags.replacements 338319 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 65340.875442 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 2545143 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 6.307884 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 5540956750 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 53842.334774 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 5321.183862 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 6177.356806 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.821569 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081195 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.094259 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.997023 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3496 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3313 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2397 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55469 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 26719739 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 26719739 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 993934 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 827149 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1821083 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 840753 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 840753 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 185645 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 185645 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 993934 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1012794 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2006728 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 993934 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1012794 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2006728 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 15082 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 273801 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 288883 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 115432 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 115432 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 15082 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 389233 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 404315 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 15082 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 389233 # number of overall misses
+system.cpu.l2cache.overall_misses::total 404315 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1156562743 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17908390235 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 19064952978 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 285997 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 285997 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9622114357 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 9622114357 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 1156562743 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 27530504592 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 28687067335 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 1156562743 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 27530504592 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 28687067335 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009016 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1100950 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2109966 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 840753 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 840753 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 300937 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 300937 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1010053 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1401821 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2411874 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1010053 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1401821 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2411874 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014902 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248700 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.136831 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.564516 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.564516 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383702 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.383702 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014902 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.277682 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.167634 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014902 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.277682 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.167634 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76215.502458 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65417.587308 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65980.283241 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7514.228571 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7514.228571 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81799.777925 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81799.777925 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76215.502458 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70277.196696 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70498.271951 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76215.502458 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70277.196696 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70498.271951 # average overall miss latency
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 301077 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 301077 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 1009016 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1402027 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2411043 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1009016 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1402027 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2411043 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014947 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248695 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.136914 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383397 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.383397 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014947 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.277622 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.167693 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014947 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.277622 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.167693 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76684.971688 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65406.591777 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65995.413292 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7526.236842 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7526.236842 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83357.425645 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83357.425645 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76684.971688 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70730.140024 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70952.270717 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76684.971688 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70730.140024 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70952.270717 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 75935 # number of writebacks
-system.cpu.l2cache.writebacks::total 75935 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 75921 # number of writebacks
+system.cpu.l2cache.writebacks::total 75921 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15051 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273790 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 288841 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115470 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 115470 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 15051 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 389260 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 404311 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 15051 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 389260 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 404311 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 957328507 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14497719271 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15455047778 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 500032 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 500032 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8018115143 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8018115143 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 957328507 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22515834414 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 23473162921 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 957328507 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22515834414 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 23473162921 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333977500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333977500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882390000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882390000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216367500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216367500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248700 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136831 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.564516 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.564516 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383702 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383702 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277682 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.167634 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277682 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.167634 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63605.641286 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52951.967826 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53507.112141 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14286.628571 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14286.628571 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69438.946419 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69438.946419 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63605.641286 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57842.661496 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58057.195874 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63605.641286 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57842.661496 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58057.195874 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15081 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273801 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 288882 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115432 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 115432 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 15081 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 389233 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 404314 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 15081 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 389233 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 404314 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 966321757 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14496174265 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15462496022 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 531034 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 531034 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8215113143 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8215113143 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 966321757 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22711287408 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23677609165 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 966321757 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22711287408 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23677609165 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333995500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333995500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882363500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882363500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216359000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216359000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248695 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136913 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383397 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383397 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.167693 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.167693 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64075.443074 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52944.197665 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53525.301064 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71168.420741 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71168.420741 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64075.443074 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58348.822962 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58562.427136 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64075.443074 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58348.822962 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58562.427136 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1401230 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.994514 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 11803041 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1401742 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 8.420266 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 25812000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.994514 # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements 1401429 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.994598 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 11820645 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1401941 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 8.431628 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 25377000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.994598 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 417 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 63715251 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 63715251 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 7198260 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7198260 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4203038 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4203038 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 186010 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 186010 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 215511 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 215511 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 11401298 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 11401298 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 11401298 # number of overall hits
-system.cpu.dcache.overall_hits::total 11401298 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1808147 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1808147 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1944666 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1944666 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses 63732446 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 63732446 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 7221951 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7221951 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4197394 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4197394 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 185535 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 185535 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 215521 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 215521 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 11419345 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 11419345 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 11419345 # number of overall hits
+system.cpu.dcache.overall_hits::total 11419345 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1789877 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1789877 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1948925 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1948925 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 23421 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 23421 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3752813 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3752813 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3752813 # number of overall misses
-system.cpu.dcache.overall_misses::total 3752813 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 40323855155 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 40323855155 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 76523868035 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 76523868035 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322545000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 322545000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 116847723190 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 116847723190 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 116847723190 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 116847723190 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 9006407 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9006407 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6147704 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6147704 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208753 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 208753 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 215513 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 215513 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15154111 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15154111 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15154111 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15154111 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200762 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.200762 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316324 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.316324 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108947 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108947 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data 3738802 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3738802 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3738802 # number of overall misses
+system.cpu.dcache.overall_misses::total 3738802 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 40163370133 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 40163370133 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 77928512640 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 77928512640 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358310999 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 358310999 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38001 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 38001 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 118091882773 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 118091882773 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 118091882773 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 118091882773 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 9011828 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9011828 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6146319 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6146319 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208956 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 208956 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 215523 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 215523 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 15158147 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15158147 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15158147 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15158147 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198614 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.198614 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.317088 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.317088 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.112086 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.112086 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.247643 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.247643 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.247643 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.247643 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31136.036672 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31136.036672 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 3013190 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 80012 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.659226 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 118.428571 # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.246653 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.246653 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.246653 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.246653 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22439.178856 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22439.178856 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39985.383039 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39985.383039 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15298.706247 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15298.706247 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000.500000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31585.487216 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31585.487216 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 3437281 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 992 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 114395 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.047476 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 124 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 840946 # number of writebacks
-system.cpu.dcache.writebacks::total 840946 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 724204 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 724204 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5146 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 5146 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2368528 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2368528 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2368528 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2368528 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083943 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1083943 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300342 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 300342 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17597 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17597 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 840753 # number of writebacks
+system.cpu.dcache.writebacks::total 840753 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705849 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 705849 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1648446 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1648446 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5839 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5839 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2354295 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2354295 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2354295 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2354295 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084028 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1084028 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300479 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 300479 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17582 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17582 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1384285 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1384285 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1384285 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1384285 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275514507 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275514507 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11674414609 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11674414609 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201282500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201282500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38949929116 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 38949929116 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38949929116 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 38949929116 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424067500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424067500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997567998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997567998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421635498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421635498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120352 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120352 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084296 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084296 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1384507 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1384507 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1384507 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1384507 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275332511 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275332511 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11834545572 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11834545572 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200445001 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200445001 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33999 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39109878083 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 39109878083 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39109878083 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 39109878083 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424085500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424085500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997539998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997539998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048888 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048888 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084142 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084142 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091347 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091347 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25161.095941 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25161.095941 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39385.599566 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39385.599566 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11400.580196 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11400.580196 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16999.500000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 211015 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74666 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31 105570 57.93% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182246 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73299 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1817873983000 97.73% 97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 64184500 0.00% 97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 553817500 0.03% 97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 41694992500 2.24% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1860186977500 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31 73299 49.32% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1817910535000 97.73% 97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 64222000 0.00% 97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 554846000 0.03% 97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 41641763000 2.24% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1860171366000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.815425 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175119 91.23% 93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175131 91.23% 93.44% # number of callpals executed
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 191963 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches
+system.cpu.kern.callpal::total 191975 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1910
system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 29561208000 1.59% 1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2704677000 0.15% 1.73% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1827921084500 98.27% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel 29515260500 1.59% 1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2703792500 0.15% 1.73% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1827952305000 98.27% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
\rmemcluster 1, usage 0, start 392, end 16384
\rfreeing pages 1069:16384
\rreserving pages 1069:1070
-\r4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles
+\r4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
\rSMP: 1 CPUs probed -- cpu_present_mask = 1
\rBuilt 1 zonelists
\rKernel command line: root=/dev/hda1 console=ttyS0
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
eventq_index=0
init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
+load_offset=0
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=tests/halt.sh
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
+socket_id=0
switched_out=false
system=system
tracer=system.cpu0.tracer
[system.cpu1]
type=TimingSimpleCPU
children=dtb isa itb tracer
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
profile=0
progress_interval=0
simpoint_start_insts=
+socket_id=0
switched_out=true
system=system
tracer=system.cpu1.tracer
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=true
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
pio=system.membus.default
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[1]
[system.simple_disk]
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:37:21
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 13:11:51
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
---------- Begin Simulation Statistics ----------
-sim_seconds 1.843672 # Number of seconds simulated
-sim_ticks 1843672389000 # Number of ticks simulated
-final_tick 1843672389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.842688 # Number of seconds simulated
+sim_ticks 1842688380000 # Number of ticks simulated
+final_tick 1842688380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 195444 # Simulator instruction rate (inst/s)
-host_op_rate 195444 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4916161077 # Simulator tick rate (ticks/s)
-host_mem_usage 347768 # Number of bytes of host memory used
-host_seconds 375.02 # Real time elapsed on the host
-sim_insts 73296119 # Number of instructions simulated
-sim_ops 73296119 # Number of ops (including micro ops) simulated
+host_inst_rate 219315 # Simulator instruction rate (inst/s)
+host_op_rate 219315 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5608158508 # Simulator tick rate (ticks/s)
+host_mem_usage 303992 # Number of bytes of host memory used
+host_seconds 328.57 # Real time elapsed on the host
+sim_insts 72060922 # Number of instructions simulated
+sim_ops 72060922 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 488384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 20120896 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 480512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 20113024 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 147840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2228608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 281856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2520448 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28440384 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 488384 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 147840 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 281856 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 918080 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7465920 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7465920 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 7631 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 314389 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 147456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2236096 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 291264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2520128 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 480512 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 147456 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 291264 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7466176 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7466176 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 7508 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 314266 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2310 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 34822 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 4404 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 39382 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 444381 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 116655 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 116655 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 264897 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 10913488 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1438624 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 80188 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1208787 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 152877 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 1367080 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15425942 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 264897 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 80188 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 152877 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 497963 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4049483 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4049483 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4049483 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 264897 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 10913488 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1438624 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 80188 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1208787 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 152877 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1367080 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19475425 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 98065 # Number of read requests accepted
-system.physmem.writeReqs 44647 # Number of write requests accepted
-system.physmem.readBursts 98065 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 44647 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 6274880 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 1280 # Total number of bytes read from write queue
-system.physmem.bytesWritten 2856000 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 6276160 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 2857408 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 20 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu1.inst 2304 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 34939 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 4551 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 39377 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 116659 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 116659 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 260767 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 10915044 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1439393 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 80022 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1213497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 158065 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 1367637 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15434423 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 260767 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 80022 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 158065 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 498854 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4051784 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4051784 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4051784 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 260767 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 10915044 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1439393 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 80022 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1213497 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 158065 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1367637 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19486207 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 98062 # Number of read requests accepted
+system.physmem.writeReqs 44473 # Number of write requests accepted
+system.physmem.readBursts 98062 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 44473 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 6274816 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue
+system.physmem.bytesWritten 2845184 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 6275968 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 2846272 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 43 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 6107 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5922 # Per bank write bursts
-system.physmem.perBankRdBursts::2 6220 # Per bank write bursts
-system.physmem.perBankRdBursts::3 6321 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5635 # Per bank write bursts
-system.physmem.perBankRdBursts::5 6235 # Per bank write bursts
-system.physmem.perBankRdBursts::6 5931 # Per bank write bursts
-system.physmem.perBankRdBursts::7 6044 # Per bank write bursts
-system.physmem.perBankRdBursts::8 6533 # Per bank write bursts
-system.physmem.perBankRdBursts::9 6108 # Per bank write bursts
-system.physmem.perBankRdBursts::10 6507 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5966 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5866 # Per bank write bursts
-system.physmem.perBankRdBursts::13 6273 # Per bank write bursts
-system.physmem.perBankRdBursts::14 6336 # Per bank write bursts
-system.physmem.perBankRdBursts::15 6041 # Per bank write bursts
-system.physmem.perBankWrBursts::0 2748 # Per bank write bursts
-system.physmem.perBankWrBursts::1 2555 # Per bank write bursts
-system.physmem.perBankWrBursts::2 2839 # Per bank write bursts
-system.physmem.perBankWrBursts::3 3065 # Per bank write bursts
-system.physmem.perBankWrBursts::4 2620 # Per bank write bursts
-system.physmem.perBankWrBursts::5 2963 # Per bank write bursts
-system.physmem.perBankWrBursts::6 2854 # Per bank write bursts
-system.physmem.perBankWrBursts::7 2670 # Per bank write bursts
-system.physmem.perBankWrBursts::8 3259 # Per bank write bursts
-system.physmem.perBankWrBursts::9 2627 # Per bank write bursts
-system.physmem.perBankWrBursts::10 3029 # Per bank write bursts
-system.physmem.perBankWrBursts::11 2539 # Per bank write bursts
-system.physmem.perBankWrBursts::12 2431 # Per bank write bursts
-system.physmem.perBankWrBursts::13 2744 # Per bank write bursts
-system.physmem.perBankWrBursts::14 2948 # Per bank write bursts
-system.physmem.perBankWrBursts::15 2734 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 6096 # Per bank write bursts
+system.physmem.perBankRdBursts::1 5927 # Per bank write bursts
+system.physmem.perBankRdBursts::2 6222 # Per bank write bursts
+system.physmem.perBankRdBursts::3 6258 # Per bank write bursts
+system.physmem.perBankRdBursts::4 5693 # Per bank write bursts
+system.physmem.perBankRdBursts::5 6247 # Per bank write bursts
+system.physmem.perBankRdBursts::6 5971 # Per bank write bursts
+system.physmem.perBankRdBursts::7 5980 # Per bank write bursts
+system.physmem.perBankRdBursts::8 6426 # Per bank write bursts
+system.physmem.perBankRdBursts::9 5994 # Per bank write bursts
+system.physmem.perBankRdBursts::10 6527 # Per bank write bursts
+system.physmem.perBankRdBursts::11 6117 # Per bank write bursts
+system.physmem.perBankRdBursts::12 5881 # Per bank write bursts
+system.physmem.perBankRdBursts::13 6322 # Per bank write bursts
+system.physmem.perBankRdBursts::14 6340 # Per bank write bursts
+system.physmem.perBankRdBursts::15 6043 # Per bank write bursts
+system.physmem.perBankWrBursts::0 2729 # Per bank write bursts
+system.physmem.perBankWrBursts::1 2556 # Per bank write bursts
+system.physmem.perBankWrBursts::2 2841 # Per bank write bursts
+system.physmem.perBankWrBursts::3 3001 # Per bank write bursts
+system.physmem.perBankWrBursts::4 2678 # Per bank write bursts
+system.physmem.perBankWrBursts::5 2962 # Per bank write bursts
+system.physmem.perBankWrBursts::6 2867 # Per bank write bursts
+system.physmem.perBankWrBursts::7 2601 # Per bank write bursts
+system.physmem.perBankWrBursts::8 3150 # Per bank write bursts
+system.physmem.perBankWrBursts::9 2533 # Per bank write bursts
+system.physmem.perBankWrBursts::10 3049 # Per bank write bursts
+system.physmem.perBankWrBursts::11 2640 # Per bank write bursts
+system.physmem.perBankWrBursts::12 2384 # Per bank write bursts
+system.physmem.perBankWrBursts::13 2771 # Per bank write bursts
+system.physmem.perBankWrBursts::14 2950 # Per bank write bursts
+system.physmem.perBankWrBursts::15 2744 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
-system.physmem.totGap 1842660063500 # Total gap between requests
+system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
+system.physmem.totGap 1841676054500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 98065 # Read request sizes (log2)
+system.physmem.readPktSize::6 98062 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 44647 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 65397 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 7824 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 8078 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2035 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 831 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1795 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1629 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1651 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1059 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 913 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 873 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 850 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 660 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 661 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 817 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 795 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 896 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 513 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 393 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 373 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 44473 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 65686 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 7740 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 8102 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2064 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 855 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1814 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1613 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1627 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1004 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 871 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 858 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 847 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 653 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 645 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 779 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 766 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 872 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 494 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 391 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 362 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 569 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 590 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 1239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 1447 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 1573 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 1674 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 1688 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 1720 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1786 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1841 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 1914 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 2036 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 2069 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 2187 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 2080 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 2119 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 2107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 2073 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 350 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 302 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 350 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 363 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 393 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 474 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 505 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 461 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 518 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 587 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 667 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 827 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 929 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 857 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 863 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 793 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 769 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 814 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 721 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 371 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 21868 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 417.545272 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 236.447646 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 397.078129 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 6878 31.45% 31.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 4663 21.32% 52.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 1715 7.84% 60.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 976 4.46% 65.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 897 4.10% 69.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 495 2.26% 71.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 365 1.67% 73.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 382 1.75% 74.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5497 25.14% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 21868 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 2618 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 37.446906 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 907.093650 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 2616 99.92% 99.92% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 612 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 1247 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 1386 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 1579 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 1688 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 1686 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 1737 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1810 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1870 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 1937 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 2004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 2070 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 2198 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 2105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 2188 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 2144 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 2115 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 355 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 362 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 456 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 479 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 463 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 497 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 562 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 666 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 784 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 700 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 689 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 741 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 691 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 362 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 21822 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 417.926863 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 236.963090 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 396.574874 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 6839 31.34% 31.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 4667 21.39% 52.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 1650 7.56% 60.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1022 4.68% 64.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 930 4.26% 69.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 496 2.27% 71.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 383 1.76% 73.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 375 1.72% 74.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5460 25.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 21822 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 2614 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 37.504973 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 907.786867 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 2612 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 2618 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 2618 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.045455 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.392541 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 4.534822 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-1 25 0.95% 0.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2-3 9 0.34% 1.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-5 2 0.08% 1.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6-7 3 0.11% 1.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-9 2 0.08% 1.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10-11 1 0.04% 1.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14-15 1 0.04% 1.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 1908 72.88% 74.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 472 18.03% 92.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 41 1.57% 94.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 56 2.14% 96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 26 0.99% 97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 16 0.61% 97.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 10 0.38% 98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 14 0.53% 98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 7 0.27% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37 1 0.04% 99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39 1 0.04% 99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41 3 0.11% 99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45 4 0.15% 99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53 1 0.04% 99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55 1 0.04% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57 11 0.42% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59 1 0.04% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61 1 0.04% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65 1 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 2618 # Writes before turning the bus around for reads
-system.physmem.totQLat 2942753000 # Total ticks spent queuing
-system.physmem.totMemAccLat 4781096750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 490225000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 30014.31 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 2614 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 2614 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.006886 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.398766 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 4.165807 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1 24 0.92% 0.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2 7 0.27% 1.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3 2 0.08% 1.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4 1 0.04% 1.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5 1 0.04% 1.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7 3 0.11% 1.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8 2 0.08% 1.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10 1 0.04% 1.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13 1 0.04% 1.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15 1 0.04% 1.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 1860 71.16% 72.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 26 0.99% 73.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 431 16.49% 90.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 74 2.83% 93.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 23 0.88% 93.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 9 0.34% 94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 11 0.42% 94.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 40 1.53% 96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 8 0.31% 96.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 18 0.69% 97.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 8 0.31% 97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 7 0.27% 97.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 3 0.11% 97.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 5 0.19% 98.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 6 0.23% 98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 9 0.34% 98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 5 0.19% 98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33 1 0.04% 98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34 1 0.04% 99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35 1 0.04% 99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36 1 0.04% 99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37 1 0.04% 99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39 4 0.15% 99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41 3 0.11% 99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42 2 0.08% 99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43 1 0.04% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47 1 0.04% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48 4 0.15% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51 1 0.04% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53 1 0.04% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56 3 0.11% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57 2 0.08% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58 1 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 2614 # Writes before turning the bus around for reads
+system.physmem.totQLat 2880597750 # Total ticks spent queuing
+system.physmem.totMemAccLat 4718922750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 490220000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29380.66 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 48764.31 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 48130.66 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.41 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.41 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 4.22 # Average write queue length when enqueuing
-system.physmem.readRowHits 85384 # Number of row buffer hits during reads
-system.physmem.writeRowHits 35418 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing
+system.physmem.readRowHits 85382 # Number of row buffer hits during reads
+system.physmem.writeRowHits 35296 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 79.33 # Row buffer hit rate for writes
-system.physmem.avgGap 12911738.77 # Average gap between requests
-system.physmem.pageHitRate 84.66 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 1768578867000 # Time in different power states
-system.physmem.memoryStateTime::REF 61564100000 # Time in different power states
+system.physmem.writeRowHitRate 79.37 # Row buffer hit rate for writes
+system.physmem.avgGap 12920868.94 # Average gap between requests
+system.physmem.pageHitRate 84.68 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 1767714784750 # Time in different power states
+system.physmem.memoryStateTime::REF 61531340000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 13524513000 # Time in different power states
+system.physmem.memoryStateTime::ACT 13440274000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 19519346 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 44419 # Transaction distribution
-system.membus.trans_dist::ReadResp 44389 # Transaction distribution
-system.membus.trans_dist::WriteReq 3765 # Transaction distribution
-system.membus.trans_dist::WriteResp 3765 # Transaction distribution
-system.membus.trans_dist::Writeback 44647 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 46 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 46 # Transaction distribution
-system.membus.trans_dist::ReadExReq 56746 # Transaction distribution
-system.membus.trans_dist::ReadExResp 56746 # Transaction distribution
-system.membus.trans_dist::BadAddressError 30 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13356 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189542 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 202958 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51481 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 51481 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 254439 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15715 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6940992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 6956707 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2192576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 2192576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 9149283 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 35977232 # Total data (bytes)
-system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 12506000 # Layer occupancy (ticks)
+system.membus.throughput 19530148 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 44582 # Transaction distribution
+system.membus.trans_dist::ReadResp 44547 # Transaction distribution
+system.membus.trans_dist::WriteReq 3734 # Transaction distribution
+system.membus.trans_dist::WriteResp 3734 # Transaction distribution
+system.membus.trans_dist::Writeback 44473 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 43 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 43 # Transaction distribution
+system.membus.trans_dist::ReadExReq 56556 # Transaction distribution
+system.membus.trans_dist::ReadExResp 56556 # Transaction distribution
+system.membus.trans_dist::BadAddressError 35 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13238 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 190124 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 70 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 203432 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 254144 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15652 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6962432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 6978084 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 9137892 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 35977992 # Total data (bytes)
+system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 12394500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 516947250 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 511002500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 37500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 45000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 762242703 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 763523207 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 155440000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 153153250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 337456 # number of replacements
-system.l2c.tags.tagsinuse 65422.465864 # Cycle average of tags in use
-system.l2c.tags.total_refs 2473240 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 402619 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.142879 # Average number of references to valid blocks.
+system.l2c.tags.replacements 337462 # number of replacements
+system.l2c.tags.tagsinuse 65424.483078 # Cycle average of tags in use
+system.l2c.tags.total_refs 2473806 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 402625 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 6.144194 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 54816.531838 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 2443.286445 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2722.487240 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 580.950396 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 624.587700 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 2109.099829 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 2125.522416 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.836434 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.037282 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.041542 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.008865 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.009530 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.032182 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.032433 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.998268 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks 54864.362424 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 2329.333896 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 2645.609154 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 576.513665 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 589.890909 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 2235.608932 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 2183.164099 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.837164 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.035543 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.040369 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.008797 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.009001 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.034113 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.033312 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.998298 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 1026 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 5608 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 55383 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 1028 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 26151122 # Number of tag accesses
-system.l2c.tags.data_accesses 26151122 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst 519486 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 493287 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 124779 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 84464 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 292648 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 239510 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1754174 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 836240 # number of Writeback hits
-system.l2c.Writeback_hits::total 836240 # number of Writeback hits
+system.l2c.tags.tag_accesses 26155869 # Number of tag accesses
+system.l2c.tags.data_accesses 26155869 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst 519275 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 492761 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 124644 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 83355 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 294324 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 240703 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1755062 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 835893 # number of Writeback hits
+system.l2c.Writeback_hits::total 835893 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 92910 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 26171 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 67815 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 186896 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 519486 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 586197 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 124779 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 110635 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 292648 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 307325 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1941070 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 519486 # number of overall hits
-system.l2c.overall_hits::cpu0.data 586197 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 124779 # number of overall hits
-system.l2c.overall_hits::cpu1.data 110635 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 292648 # number of overall hits
-system.l2c.overall_hits::cpu2.data 307325 # number of overall hits
-system.l2c.overall_hits::total 1941070 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst 7631 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 238513 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 2310 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 16826 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 4404 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 17896 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 287580 # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu0.data 92934 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 26300 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 67701 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 186935 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst 519275 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 585695 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 124644 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 109655 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 294324 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 308404 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1941997 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst 519275 # number of overall hits
+system.l2c.overall_hits::cpu0.data 585695 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 124644 # number of overall hits
+system.l2c.overall_hits::cpu1.data 109655 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 294324 # number of overall hits
+system.l2c.overall_hits::cpu2.data 308404 # number of overall hits
+system.l2c.overall_hits::total 1941997 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst 7508 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 238474 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 2304 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 16794 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 4551 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 17979 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 287610 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 12 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 20 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 9 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 17 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 76151 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 18045 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 21583 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 115779 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst 7631 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 314664 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 2310 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 34871 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 4404 # number of demand (read+write) misses
+system.l2c.ReadExReq_misses::cpu0.data 76068 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 18194 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 21500 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 115762 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst 7508 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 314542 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 2304 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 34988 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 4551 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 39479 # number of demand (read+write) misses
-system.l2c.demand_misses::total 403359 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 7631 # number of overall misses
-system.l2c.overall_misses::cpu0.data 314664 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 2310 # number of overall misses
-system.l2c.overall_misses::cpu1.data 34871 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 4404 # number of overall misses
+system.l2c.demand_misses::total 403372 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst 7508 # number of overall misses
+system.l2c.overall_misses::cpu0.data 314542 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 2304 # number of overall misses
+system.l2c.overall_misses::cpu1.data 34988 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 4551 # number of overall misses
system.l2c.overall_misses::cpu2.data 39479 # number of overall misses
-system.l2c.overall_misses::total 403359 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst 168327497 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 1121769250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 335079500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 1193124499 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 2818300746 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 318496 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 318496 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 1237365240 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 1750671726 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 2988036966 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 168327497 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 2359134490 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 335079500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 2943796225 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 5806337712 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 168327497 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 2359134490 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 335079500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 2943796225 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 5806337712 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst 527117 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 731800 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 127089 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 101290 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 297052 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 257406 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2041754 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 836240 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 836240 # number of Writeback accesses(hits+misses)
+system.l2c.overall_misses::total 403372 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst 169555248 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 1119867750 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 344601500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 1200068749 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 2834093247 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data 263498 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 263498 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 1245576490 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 1752401476 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 2997977966 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 169555248 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 2365444240 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 344601500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 2952470225 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 5832071213 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 169555248 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 2365444240 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 344601500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 2952470225 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 5832071213 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst 526783 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 731235 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 126948 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 100149 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 298875 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 258682 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2042672 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 835893 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 835893 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 12 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 169061 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 44216 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 89398 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 302675 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 527117 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 900861 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 127089 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 145506 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 297052 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 346804 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2344429 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 527117 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 900861 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 127089 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 145506 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 297052 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 346804 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2344429 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.014477 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.325926 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.018176 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.166117 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.014826 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.069524 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.140849 # miss rate for ReadReq accesses
+system.l2c.ReadExReq_accesses::cpu0.data 169002 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 44494 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 89201 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 302697 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst 526783 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 900237 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 126948 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 144643 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 298875 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 347883 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2345369 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 526783 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 900237 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 126948 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 144643 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 298875 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 347883 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2345369 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.014253 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.326125 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.018149 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.167690 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.015227 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.069502 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.140801 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.800000 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.740741 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.750000 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.708333 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.450435 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.408110 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.241426 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.382519 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.014477 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.349293 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.018176 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.239653 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.014826 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.113837 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.172050 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.014477 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.349293 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.018176 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.239653 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.014826 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.113837 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.172050 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72869.046320 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 66668.801260 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76085.263397 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 66669.898245 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 9800.058231 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26541.333333 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 15924.800000 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68571.085619 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81113.456239 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 25808.108258 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72869.046320 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 67653.192911 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 76085.263397 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 74566.129461 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 14394.962582 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72869.046320 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 67653.192911 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 76085.263397 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 74566.129461 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 14394.962582 # average overall miss latency
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.450101 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.408909 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.241029 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.382435 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.014253 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.349399 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.018149 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.241892 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.015227 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.113484 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.171987 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.014253 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.349399 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.018149 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.241892 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.015227 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.113484 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.171987 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73591.687500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 66682.609861 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75719.951659 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 66748.359141 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 9853.945437 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29277.555556 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 15499.882353 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68460.838188 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81507.045395 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 25897.772723 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 73591.687500 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 67607.300789 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 75719.951659 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 74785.841207 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 14458.294609 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 73591.687500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 67607.300789 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 75719.951659 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 74785.841207 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 14458.294609 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 75143 # number of writebacks
-system.l2c.writebacks::total 75143 # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu1.inst 2310 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 16826 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 4404 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 17896 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 41436 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 12 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 18045 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 21583 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 39628 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 2310 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 34871 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 4404 # number of demand (read+write) MSHR misses
+system.l2c.writebacks::writebacks 75147 # number of writebacks
+system.l2c.writebacks::total 75147 # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.inst 2304 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 16794 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst 4551 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data 17979 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 41628 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 9 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 18194 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 21500 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 39694 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 2304 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 34988 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 4551 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 39479 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 81064 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 2310 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 34871 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 4404 # number of overall MSHR misses
+system.l2c.demand_mshr_misses::total 81322 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 2304 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 34988 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 4551 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 39479 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 81064 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 138909503 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 911100250 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 279632500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 972656001 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 2302298254 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 279009 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 279009 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1010621760 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1486000274 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 2496622034 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 138909503 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 1921722010 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 279632500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 2458656275 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 4798920288 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 138909503 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 1921722010 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 279632500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 2458656275 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 4798920288 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277729500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 292749000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 570478500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 344555500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 403769000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 748324500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 622285000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 696518000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 1318803000 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018176 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.166117 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014826 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.069524 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.020294 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408110 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241426 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.130926 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018176 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014826 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.113837 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.034577 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018176 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014826 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.113837 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.034577 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60133.983983 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54148.356710 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63495.118074 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54350.469435 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 55562.753499 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23250.750000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23250.750000 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56005.639235 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68850.496873 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63001.464470 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60133.983983 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55109.460870 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63495.118074 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62277.572254 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59199.154841 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60133.983983 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55109.460870 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63495.118074 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62277.572254 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59199.154841 # average overall mshr miss latency
+system.l2c.overall_mshr_misses::total 81322 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 140206252 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 909595750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 287277500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 979239251 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 2316318753 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 241006 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 241006 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1016974010 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1489833024 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 2506807034 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 140206252 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 1926569760 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 287277500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 2469072275 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 4823125787 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 140206252 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 1926569760 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 287277500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 2469072275 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 4823125787 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 272308500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 292895500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 565204000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 339653500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 403064000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 742717500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 611962000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 695959500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 1307921500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167690 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.069502 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.020379 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750000 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408909 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241029 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.131134 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.241892 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.113484 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.034673 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.241892 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.113484 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.034673 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54161.947719 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54465.723956 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 55643.287042 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26778.444444 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26778.444444 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55896.120149 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69294.559256 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63153.298584 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55063.729279 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62541.408724 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59308.991257 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55063.729279 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62541.408724 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59308.991257 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.262765 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.254888 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1694865594000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.262765 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.078923 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.078923 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1694865618000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.254888 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 9418062 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 9418062 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 5145673458 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 5145673458 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 5155091520 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 5155091520 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 5155091520 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 5155091520 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 5047462530 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 5047462530 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 5056765993 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 5056765993 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 5056765993 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 5056765993 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54439.664740 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 54439.664740 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 123836.962312 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 123836.962312 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 123549.227561 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123549.227561 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 123549.227561 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123549.227561 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 151978 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 121473.395504 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 121473.395504 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 121192.714032 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 121192.714032 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 149207 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 11614 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 11483 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 13.085759 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 12.993730 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::tsunami.ide 17152 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 17152 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide 17222 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 17222 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide 17222 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 17222 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5777062 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 5777062 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4252886458 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 4252886458 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 4258663520 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 4258663520 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 4258663520 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 4258663520 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.412784 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 0.412784 # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.412750 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.412750 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82529.457143 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 82529.457143 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247952.801889 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 247952.801889 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4167935030 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 4167935030 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 4173649493 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 4173649493 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 4173649493 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 4173649493 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246681.760772 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 246681.760772 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 4916751 # DTB read hits
-system.cpu0.dtb.read_misses 6099 # DTB read misses
+system.cpu0.dtb.read_hits 4913708 # DTB read hits
+system.cpu0.dtb.read_misses 6100 # DTB read misses
system.cpu0.dtb.read_acv 126 # DTB read access violations
-system.cpu0.dtb.read_accesses 428233 # DTB read accesses
-system.cpu0.dtb.write_hits 3511411 # DTB write hits
-system.cpu0.dtb.write_misses 670 # DTB write misses
+system.cpu0.dtb.read_accesses 428235 # DTB read accesses
+system.cpu0.dtb.write_hits 3510172 # DTB write hits
+system.cpu0.dtb.write_misses 671 # DTB write misses
system.cpu0.dtb.write_acv 84 # DTB write access violations
-system.cpu0.dtb.write_accesses 163777 # DTB write accesses
-system.cpu0.dtb.data_hits 8428162 # DTB hits
-system.cpu0.dtb.data_misses 6769 # DTB misses
+system.cpu0.dtb.write_accesses 163990 # DTB write accesses
+system.cpu0.dtb.data_hits 8423880 # DTB hits
+system.cpu0.dtb.data_misses 6771 # DTB misses
system.cpu0.dtb.data_acv 210 # DTB access violations
-system.cpu0.dtb.data_accesses 592010 # DTB accesses
-system.cpu0.itb.fetch_hits 2761691 # ITB hits
+system.cpu0.dtb.data_accesses 592225 # DTB accesses
+system.cpu0.itb.fetch_hits 2758823 # ITB hits
system.cpu0.itb.fetch_misses 3034 # ITB misses
system.cpu0.itb.fetch_acv 104 # ITB acv
-system.cpu0.itb.fetch_accesses 2764725 # ITB accesses
+system.cpu0.itb.fetch_accesses 2761857 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 928579533 # number of cpu cycles simulated
+system.cpu0.numCycles 928196841 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 33817210 # Number of instructions committed
-system.cpu0.committedOps 33817210 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 31677975 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 169596 # Number of float alu accesses
-system.cpu0.num_func_calls 812570 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4683135 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 31677975 # number of integer instructions
-system.cpu0.num_fp_insts 169596 # number of float instructions
-system.cpu0.num_int_register_reads 44495639 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 23114141 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 87595 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 89102 # number of times the floating registers were written
-system.cpu0.num_mem_refs 8458293 # number of memory refs
-system.cpu0.num_load_insts 4938120 # Number of load instructions
-system.cpu0.num_store_insts 3520173 # Number of store instructions
-system.cpu0.num_idle_cycles 904460149.841647 # Number of idle cycles
-system.cpu0.num_busy_cycles 24119383.158353 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.025974 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.974026 # Percentage of idle cycles
-system.cpu0.Branches 5759211 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 1618304 4.78% 4.78% # Class of executed instruction
-system.cpu0.op_class::IntAlu 23033604 68.10% 72.88% # Class of executed instruction
-system.cpu0.op_class::IntMult 32432 0.10% 72.98% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 72.98% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 12174 0.04% 73.01% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 73.01% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 73.01% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 73.01% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 1606 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 73.02% # Class of executed instruction
-system.cpu0.op_class::MemRead 5072252 15.00% 88.02% # Class of executed instruction
-system.cpu0.op_class::MemWrite 3523323 10.42% 98.43% # Class of executed instruction
-system.cpu0.op_class::IprAccess 530494 1.57% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 33463552 # Number of instructions committed
+system.cpu0.committedOps 33463552 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 31328637 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 169756 # Number of float alu accesses
+system.cpu0.num_func_calls 812549 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4574772 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 31328637 # number of integer instructions
+system.cpu0.num_fp_insts 169756 # number of float instructions
+system.cpu0.num_int_register_reads 43916482 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 22873823 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 87693 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 89172 # number of times the floating registers were written
+system.cpu0.num_mem_refs 8454037 # number of memory refs
+system.cpu0.num_load_insts 4935095 # Number of load instructions
+system.cpu0.num_store_insts 3518942 # Number of store instructions
+system.cpu0.num_idle_cycles 904607153.884767 # Number of idle cycles
+system.cpu0.num_busy_cycles 23589687.115233 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.025415 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.974585 # Percentage of idle cycles
+system.cpu0.Branches 5650356 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1614853 4.82% 4.82% # Class of executed instruction
+system.cpu0.op_class::IntAlu 22689020 67.79% 72.61% # Class of executed instruction
+system.cpu0.op_class::IntMult 32419 0.10% 72.71% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 72.71% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 12179 0.04% 72.75% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 1606 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.75% # Class of executed instruction
+system.cpu0.op_class::MemRead 5069147 15.15% 87.90% # Class of executed instruction
+system.cpu0.op_class::MemWrite 3522084 10.52% 98.42% # Class of executed instruction
+system.cpu0.op_class::IprAccess 529225 1.58% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 33824189 # Class of executed instruction
+system.cpu0.op_class::total 33470533 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6417 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 211389 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1820445327500 98.74% 98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 38826000 0.00% 98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 365496000 0.02% 98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 22821970000 1.24% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1843671619500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1819515986000 98.74% 98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 38828500 0.00% 98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 364353500 0.02% 98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 22768442500 1.24% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1842687610500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.694807 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.815839 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed
+system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 192243 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches
-system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1908
-system.cpu0.kern.mode_good::user 1739
-system.cpu0.kern.mode_good::idle 169
-system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches
+system.cpu0.kern.callpal::total 192241 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches
+system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches
+system.cpu0.kern.mode_good::kernel 1907
+system.cpu0.kern.mode_good::user 1737
+system.cpu0.kern.mode_good::idle 170
+system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 29786667000 1.62% 1.62% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2578002500 0.14% 1.76% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle 1811306945500 98.24% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
+system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 29751992000 1.61% 1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2580511000 0.14% 1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle 1810355103000 98.25% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 4177 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 110441912 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 785832 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 785787 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 3765 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 3765 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 372222 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
+system.toL2Bus.throughput 110521342 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 787621 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 787571 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 3734 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 3734 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 372342 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 150766 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 133614 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 848294 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370287 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 2218581 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27145024 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55347363 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 82492387 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 203607824 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 10880 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 2138460500 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 150591 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 133695 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 35 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 851659 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370714 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 2222373 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252672 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55368420 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 82621092 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 203645448 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 10944 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 2139903500 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1910550337 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1918103434 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2233740752 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 2234598905 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.iobus.throughput 1468369 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 2983 # Transaction distribution
-system.iobus.trans_dist::ReadResp 2983 # Transaction distribution
-system.iobus.trans_dist::WriteReq 20917 # Transaction distribution
-system.iobus.trans_dist::WriteResp 20917 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes)
+system.iobus.throughput 1469149 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 2954 # Transaction distribution
+system.iobus.trans_dist::ReadResp 2954 # Transaction distribution
+system.iobus.trans_dist::WriteReq 20630 # Transaction distribution
+system.iobus.trans_dist::WriteResp 20630 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2332 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8382 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2408 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 13356 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34444 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total 34444 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 47800 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8304 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2378 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 22 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 13238 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 47168 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9328 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4191 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 15715 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1099184 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1099184 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 1114899 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 2707192 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1550 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 17 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 15652 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 1098444 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 2707184 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6246000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6188000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 1819000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 1792000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy 13000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 156921520 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 154562743 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 9591000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 9504000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 17887000 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 17636750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 950608 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.189792 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 43374256 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 951119 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 45.603396 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 10403794250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.164377 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 98.345392 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 161.680023 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490555 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.192081 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.315781 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.998418 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 951958 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.193866 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 42822968 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 952469 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 44.959960 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 10341081250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 254.383910 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.394710 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.415245 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.496844 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180458 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321124 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.998426 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 45292775 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 45292775 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 33297051 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 7835821 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 2241384 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 43374256 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 33297051 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 7835821 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 2241384 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 43374256 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 33297051 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 7835821 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 2241384 # number of overall hits
-system.cpu0.icache.overall_hits::total 43374256 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 527138 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 127089 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 313001 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 967228 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 527138 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 127089 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 313001 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 967228 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 527138 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 127089 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 313001 # number of overall misses
-system.cpu0.icache.overall_misses::total 967228 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1805503003 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4394679722 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 6200182725 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 1805503003 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 4394679722 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 6200182725 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 1805503003 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 4394679722 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 6200182725 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 33824189 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 7962910 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 2554385 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 44341484 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 33824189 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 7962910 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 2554385 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 44341484 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 33824189 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 7962910 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 2554385 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 44341484 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015585 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015960 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122535 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.021813 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015585 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015960 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122535 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.021813 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015585 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015960 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122535 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.021813 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14206.603270 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14040.465436 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 6410.259758 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14206.603270 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14040.465436 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 6410.259758 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14206.603270 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14040.465436 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 6410.259758 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2211 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 139 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.906475 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses 44744661 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 44744661 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 32943729 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 7613321 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 2265918 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 42822968 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 32943729 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 7613321 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 2265918 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 42822968 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 32943729 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 7613321 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 2265918 # number of overall hits
+system.cpu0.icache.overall_hits::total 42822968 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 526804 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 126948 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 315301 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 969053 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 526804 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 126948 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 315301 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 969053 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 526804 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 126948 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 315301 # number of overall misses
+system.cpu0.icache.overall_misses::total 969053 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1804971752 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4436657422 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 6241629174 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 1804971752 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 4436657422 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 6241629174 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 1804971752 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 4436657422 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 6241629174 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 33470533 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 7740269 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 2581219 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 43792021 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 33470533 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 7740269 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 2581219 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 43792021 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 33470533 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 7740269 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 2581219 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 43792021 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015739 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016401 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122152 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.022129 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015739 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016401 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122152 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.022129 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015739 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016401 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122152 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.022129 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14218.197624 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14071.180941 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 6440.957485 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14218.197624 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14071.180941 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 6440.957485 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14218.197624 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14071.180941 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 6440.957485 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 2807 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 180 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 158 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.765823 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets 180 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 15937 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 15937 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 15937 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 15937 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 15937 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 15937 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 127089 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297064 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 424153 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 127089 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 297064 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 424153 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 127089 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 297064 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 424153 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550405997 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3623912160 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 5174318157 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1550405997 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3623912160 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 5174318157 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1550405997 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3623912160 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 5174318157 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015960 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116296 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009566 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015960 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116296 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.009566 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015960 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116296 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.009566 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12199.372070 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.178497 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12199.372070 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.178497 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12199.372070 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.178497 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16413 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 16413 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst 16413 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 16413 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst 16413 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 16413 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126948 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 298888 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 425836 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 126948 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 298888 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 425836 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 126948 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 298888 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 425836 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550155248 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3653520809 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 5203676057 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1550155248 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3653520809 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 5203676057 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1550155248 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3653520809 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 5203676057 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009724 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.009724 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.009724 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12219.906389 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 1392627 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 13291421 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1393139 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 9.540628 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 1392214 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 13295925 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1392726 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 9.546691 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 251.446594 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 129.524111 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.027107 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.491107 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.252977 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255912 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.443226 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.415700 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.138886 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.496959 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246906 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data 0.256131 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 63293161 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 63293161 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 4078776 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 1086651 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 2400445 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7565872 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3215108 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 831895 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 1295006 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5342009 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117088 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19357 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47741 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 184186 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126296 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21393 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51592 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 7293884 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 1918546 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 3695451 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12907881 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 7293884 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 1918546 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 3695451 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12907881 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 722029 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 99123 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 533441 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1354593 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 169072 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 44217 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 597048 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 810337 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9771 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2167 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6787 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 18725 # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses 63306620 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 63306620 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 4076279 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 1084544 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 2409625 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7570448 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3214036 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 832568 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 1295168 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 5341772 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117096 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19328 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47935 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 184359 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126165 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21357 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51769 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 199291 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 7290315 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 1917112 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 3704793 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 12912220 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 7290315 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 1917112 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 3704793 # number of overall hits
+system.cpu0.dcache.overall_hits::total 12912220 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 721601 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 97990 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 534145 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1353736 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 169013 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 44495 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 596516 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 810024 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9634 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2159 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7048 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 18841 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 891101 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 143340 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 1130489 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2164930 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 891101 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 143340 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 1130489 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2164930 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2252505500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9329560863 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 11582066363 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1640569260 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17995165012 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 19635734272 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28565250 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 103170749 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 131735999 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data 890614 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 142485 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 1130661 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 2163760 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 890614 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 142485 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 1130661 # number of overall misses
+system.cpu0.dcache.overall_misses::total 2163760 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2236149750 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9408423500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 11644573250 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1650986010 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18036124563 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 19687110573 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28476000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 115371499 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 143847499 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 3893074760 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 27324725875 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 31217800635 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 3893074760 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 27324725875 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 31217800635 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 4800805 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 1185774 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 2933886 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8920465 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 3384180 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 876112 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 1892054 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 6152346 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126859 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21524 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54528 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 202911 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126297 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21393 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51593 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 199283 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 8184985 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 2061886 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 4825940 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 15072811 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 8184985 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 2061886 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 4825940 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 15072811 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150397 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083594 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181821 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.151852 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049960 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050470 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315555 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.131712 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077023 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100678 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124468 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092282 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu1.data 3887135760 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 27444548063 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 31331683823 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 3887135760 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 27444548063 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 31331683823 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 4797880 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 1182534 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 2943770 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8924184 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383049 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 877063 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 1891684 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 6151796 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126730 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21487 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54983 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 203200 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126166 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21357 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51770 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 199293 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 8180929 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 2059597 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 4835454 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 15075980 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 8180929 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 2059597 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 4835454 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 15075980 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150400 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082864 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181449 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.151693 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049959 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050732 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315336 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.131673 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076020 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100479 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.128185 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092721 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108870 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069519 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234253 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.143631 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108870 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069519 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234253 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.143631 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22724.347528 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17489.395946 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 8550.218673 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37102.681322 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30140.231626 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 24231.565721 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.933549 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15201.230146 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7035.300347 # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108865 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069181 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233827 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.143524 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108865 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069181 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233827 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.143524 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22820.183182 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17613.987775 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 8601.805116 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37104.978312 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30235.776682 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 24304.354652 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13189.439555 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16369.395431 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7634.812324 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6500 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27159.723455 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24170.713625 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14419.773681 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27159.723455 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24170.713625 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14419.773681 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 573016 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 707 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 17657 # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14480.202898 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14480.202898 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 642685 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 913 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 30067 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 32.452625 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 101 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.375096 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 130.428571 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 836240 # number of writebacks
-system.cpu0.dcache.writebacks::total 836240 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 281234 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 281234 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507881 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 507881 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1344 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 789115 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 789115 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 789115 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 789115 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 99123 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252207 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 351330 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44217 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89167 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 133384 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2167 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5443 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7610 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks 835893 # number of writebacks
+system.cpu0.dcache.writebacks::total 835893 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280644 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 280644 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507552 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 507552 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1619 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1619 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 788196 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 788196 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 788196 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 788196 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97990 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 253501 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 351491 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44495 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88964 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 133459 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2159 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5429 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7588 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 143340 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 341374 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 484714 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 143340 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 341374 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 484714 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2046709500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4236520898 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6283230398 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1543938740 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2600534498 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4144473238 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24229750 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66769000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90998750 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 142485 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 342465 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 484950 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 142485 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 342465 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 484950 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2032617250 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4252838742 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285455992 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553735990 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2601199489 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4154935479 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24156000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66182251 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90338251 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3590648240 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6837055396 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 10427703636 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3590648240 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6837055396 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 10427703636 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296463000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311893000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 608356000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 365040500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 428466000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 793506500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 661503500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 740359000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1401862500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083594 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085963 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039385 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050470 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047127 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021680 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100678 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099820 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037504 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3586353240 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6854038231 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 10440391471 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3586353240 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6854038231 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10440391471 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 290678000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312039500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 602717500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 359850500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427676500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 787527000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 650528500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 739716000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1390244500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082864 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086114 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039386 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050732 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047029 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021694 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100479 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098740 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037343 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.032158 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.032158 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20648.179535 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16797.792678 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17884.127168 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34917.310989 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29164.763848 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31071.742023 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11181.241347 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12266.948374 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.785808 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.032167 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.032167 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20743.108991 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16776.418010 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17882.267233 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34919.339027 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29238.787476 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31132.673548 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11188.513201 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12190.504881 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.409989 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1205243 # DTB read hits
+system.cpu1.dtb.read_hits 1201953 # DTB read hits
system.cpu1.dtb.read_misses 1367 # DTB read misses
system.cpu1.dtb.read_acv 34 # DTB read access violations
system.cpu1.dtb.read_accesses 142945 # DTB read accesses
-system.cpu1.dtb.write_hits 897974 # DTB write hits
+system.cpu1.dtb.write_hits 898873 # DTB write hits
system.cpu1.dtb.write_misses 185 # DTB write misses
system.cpu1.dtb.write_acv 23 # DTB write access violations
-system.cpu1.dtb.write_accesses 58533 # DTB write accesses
-system.cpu1.dtb.data_hits 2103217 # DTB hits
+system.cpu1.dtb.write_accesses 58321 # DTB write accesses
+system.cpu1.dtb.data_hits 2100826 # DTB hits
system.cpu1.dtb.data_misses 1552 # DTB misses
system.cpu1.dtb.data_acv 57 # DTB access violations
-system.cpu1.dtb.data_accesses 201478 # DTB accesses
-system.cpu1.itb.fetch_hits 859888 # ITB hits
+system.cpu1.dtb.data_accesses 201266 # DTB accesses
+system.cpu1.itb.fetch_hits 861128 # ITB hits
system.cpu1.itb.fetch_misses 693 # ITB misses
system.cpu1.itb.fetch_acv 30 # ITB acv
-system.cpu1.itb.fetch_accesses 860581 # ITB accesses
+system.cpu1.itb.fetch_accesses 861821 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 953622390 # number of cpu cycles simulated
+system.cpu1.numCycles 953604102 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7961300 # Number of instructions committed
-system.cpu1.committedOps 7961300 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 7416956 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 45099 # Number of float alu accesses
-system.cpu1.num_func_calls 213358 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1019863 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 7416956 # number of integer instructions
-system.cpu1.num_fp_insts 45099 # number of float instructions
-system.cpu1.num_int_register_reads 10395465 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5394572 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 24307 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 24707 # number of times the floating registers were written
-system.cpu1.num_mem_refs 2110464 # number of memory refs
-system.cpu1.num_load_insts 1210140 # Number of load instructions
-system.cpu1.num_store_insts 900324 # Number of store instructions
-system.cpu1.num_idle_cycles 923192460.103175 # Number of idle cycles
-system.cpu1.num_busy_cycles 30429929.896825 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.031910 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.968090 # Percentage of idle cycles
-system.cpu1.Branches 1300058 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 413905 5.20% 5.20% # Class of executed instruction
-system.cpu1.op_class::IntAlu 5261386 66.07% 71.27% # Class of executed instruction
-system.cpu1.op_class::IntMult 8416 0.11% 71.38% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 71.38% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 5003 0.06% 71.44% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction
-system.cpu1.op_class::MemRead 1239389 15.56% 87.01% # Class of executed instruction
-system.cpu1.op_class::MemWrite 901545 11.32% 98.34% # Class of executed instruction
-system.cpu1.op_class::IprAccess 132455 1.66% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 7738659 # Number of instructions committed
+system.cpu1.committedOps 7738659 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 7195320 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 44971 # Number of float alu accesses
+system.cpu1.num_func_calls 212104 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 948894 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 7195320 # number of integer instructions
+system.cpu1.num_fp_insts 44971 # number of float instructions
+system.cpu1.num_int_register_reads 10028277 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5244710 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 24303 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 24579 # number of times the floating registers were written
+system.cpu1.num_mem_refs 2108049 # number of memory refs
+system.cpu1.num_load_insts 1206835 # Number of load instructions
+system.cpu1.num_store_insts 901214 # Number of store instructions
+system.cpu1.num_idle_cycles 922268722.786044 # Number of idle cycles
+system.cpu1.num_busy_cycles 31335379.213956 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.032860 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.967140 # Percentage of idle cycles
+system.cpu1.Branches 1227675 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 413043 5.34% 5.34% # Class of executed instruction
+system.cpu1.op_class::IntAlu 5041451 65.13% 70.47% # Class of executed instruction
+system.cpu1.op_class::IntMult 8548 0.11% 70.58% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 70.58% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 4999 0.06% 70.64% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 70.64% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 70.64% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 70.64% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 810 0.01% 70.65% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.65% # Class of executed instruction
+system.cpu1.op_class::MemRead 1235944 15.97% 86.62% # Class of executed instruction
+system.cpu1.op_class::MemWrite 902434 11.66% 98.28% # Class of executed instruction
+system.cpu1.op_class::IprAccess 133039 1.72% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 7962909 # Class of executed instruction
+system.cpu1.op_class::total 7740268 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
-system.cpu2.branchPred.lookups 9178120 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 8499449 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 123200 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 7695654 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 6571533 # Number of BTB hits
+system.cpu2.branchPred.lookups 8997141 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 8310458 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 125233 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 7551874 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 6369180 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 85.392781 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 282084 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 12342 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 84.339066 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 284910 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 13175 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 3191151 # DTB read hits
-system.cpu2.dtb.read_misses 11650 # DTB read misses
-system.cpu2.dtb.read_acv 122 # DTB read access violations
-system.cpu2.dtb.read_accesses 216295 # DTB read accesses
-system.cpu2.dtb.write_hits 2013879 # DTB write hits
-system.cpu2.dtb.write_misses 2626 # DTB write misses
-system.cpu2.dtb.write_acv 104 # DTB write access violations
-system.cpu2.dtb.write_accesses 81955 # DTB write accesses
-system.cpu2.dtb.data_hits 5205030 # DTB hits
-system.cpu2.dtb.data_misses 14276 # DTB misses
+system.cpu2.dtb.read_hits 3232647 # DTB read hits
+system.cpu2.dtb.read_misses 11674 # DTB read misses
+system.cpu2.dtb.read_acv 117 # DTB read access violations
+system.cpu2.dtb.read_accesses 217551 # DTB read accesses
+system.cpu2.dtb.write_hits 2020818 # DTB write hits
+system.cpu2.dtb.write_misses 2669 # DTB write misses
+system.cpu2.dtb.write_acv 109 # DTB write access violations
+system.cpu2.dtb.write_accesses 82591 # DTB write accesses
+system.cpu2.dtb.data_hits 5253465 # DTB hits
+system.cpu2.dtb.data_misses 14343 # DTB misses
system.cpu2.dtb.data_acv 226 # DTB access violations
-system.cpu2.dtb.data_accesses 298250 # DTB accesses
-system.cpu2.itb.fetch_hits 370022 # ITB hits
-system.cpu2.itb.fetch_misses 5569 # ITB misses
-system.cpu2.itb.fetch_acv 246 # ITB acv
-system.cpu2.itb.fetch_accesses 375591 # ITB accesses
+system.cpu2.dtb.data_accesses 300142 # DTB accesses
+system.cpu2.itb.fetch_hits 371576 # ITB hits
+system.cpu2.itb.fetch_misses 5695 # ITB misses
+system.cpu2.itb.fetch_acv 235 # ITB acv
+system.cpu2.itb.fetch_accesses 377271 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.numCycles 31335688 # number of cpu cycles simulated
+system.cpu2.numCycles 31002313 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 8331242 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 37157937 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 9178120 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 6853617 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 8899845 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 601293 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 9656250 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 10264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 62491 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 87858 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 258 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2554389 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 85437 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 27441825 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.354062 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.292990 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 8393929 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 36824229 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 8997141 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 6654090 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 8723757 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 635832 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 9323842 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 10747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 1941 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 64126 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 88179 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 2581223 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 87099 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 27026118 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.362542 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.315525 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 18541980 67.57% 67.57% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 269924 0.98% 68.55% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 430608 1.57% 70.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 5041958 18.37% 88.49% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 762355 2.78% 91.27% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 165901 0.60% 91.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 191104 0.70% 92.57% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 428586 1.56% 94.14% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1609409 5.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 18302361 67.72% 67.72% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 270640 1.00% 68.72% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 435105 1.61% 70.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 4809867 17.80% 88.13% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 769933 2.85% 90.98% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 167503 0.62% 91.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 192346 0.71% 92.31% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 444449 1.64% 93.95% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1633914 6.05% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 27441825 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.292897 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.185802 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8480872 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 9736053 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 8290323 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 308881 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 379812 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 165178 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 12521 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 36770346 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 39237 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 379812 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 8839767 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 2783657 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 5759458 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 8162466 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1270789 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 35635356 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2433 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 230404 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 445807 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 23881418 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 44614948 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 44558512 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 52675 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 22098169 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 1783249 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 500707 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 58904 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3714662 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 3352351 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 2102718 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 368829 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 261079 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 33144056 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 620028 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 32694445 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 35243 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2135274 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 1079120 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 437376 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 27441825 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.191409 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.576872 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 27026118 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.290209 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.187790 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 8441173 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 9512814 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 8253964 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 165145 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 407122 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 167309 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 12818 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 36409694 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 40311 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 407122 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 8734574 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 2556870 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 5774789 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 8067686 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1239186 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 35224318 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 3572 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 388506 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 20310 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 316059 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 23620864 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 44017646 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 43961139 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 52746 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 21667069 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 1953795 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 502665 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 59694 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 2961257 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 3405802 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 2124807 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 397929 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 274147 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 32669106 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 622861 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 32140552 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 36002 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 2321360 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 1217953 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 439629 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 27026118 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.189240 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.607686 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 15111094 55.07% 55.07% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3067205 11.18% 66.24% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 1556680 5.67% 71.92% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 5872597 21.40% 93.32% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 904620 3.30% 96.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 481374 1.75% 98.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 286422 1.04% 99.41% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 142457 0.52% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 19376 0.07% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 15119064 55.94% 55.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 2962463 10.96% 66.90% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 1396485 5.17% 72.07% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 5591038 20.69% 92.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 885243 3.28% 96.03% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 550698 2.04% 98.07% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 348435 1.29% 99.36% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 154603 0.57% 99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 18089 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 27441825 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 27026118 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 33866 13.68% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 112679 45.53% 59.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 100956 40.79% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 38019 14.73% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.73% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 117677 45.59% 60.31% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 102444 39.69% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 27019317 82.64% 82.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 20282 0.06% 82.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 8426 0.03% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 3318398 10.15% 92.89% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 2035966 6.23% 99.12% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 288396 0.88% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 26413495 82.18% 82.19% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 20160 0.06% 82.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 8429 0.03% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 3362943 10.46% 92.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 2042777 6.36% 99.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 289088 0.90% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 32694445 # Type of FU issued
-system.cpu2.iq.rate 1.043361 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 247501 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.007570 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 92879210 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 35788610 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 32300559 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 234249 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 114557 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 110717 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 32817438 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 122068 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 187489 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 32140552 # Type of FU issued
+system.cpu2.iq.rate 1.036715 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 258140 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.008032 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 91366801 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 35502508 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 31706710 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 234563 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 114868 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 110893 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 32274032 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 122220 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 191624 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 409544 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 984 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 3929 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 155635 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 457264 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1199 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4154 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 177923 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 4136 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 26287 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 4195 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 54966 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 379812 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 2011431 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 204809 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 35034427 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 220433 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 3352351 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 2102718 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 550753 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 142349 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2108 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 3929 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 63003 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 127121 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 190124 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 32537756 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 3211080 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 156689 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 407122 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 1875775 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 219548 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 34577439 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 209711 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 3405802 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 2124807 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 553318 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 48768 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 120434 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4154 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 65270 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 127814 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 193084 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 31975437 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 3252613 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 165115 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 1270343 # number of nop insts executed
-system.cpu2.iew.exec_refs 5232018 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 7610407 # Number of branches executed
-system.cpu2.iew.exec_stores 2020938 # Number of stores executed
-system.cpu2.iew.exec_rate 1.038361 # Inst execution rate
-system.cpu2.iew.wb_sent 32444193 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 32411276 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 18891849 # num instructions producing a value
-system.cpu2.iew.wb_consumers 22089477 # num instructions consuming a value
+system.cpu2.iew.exec_nop 1285472 # number of nop insts executed
+system.cpu2.iew.exec_refs 5280547 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 7393667 # Number of branches executed
+system.cpu2.iew.exec_stores 2027934 # Number of stores executed
+system.cpu2.iew.exec_rate 1.031389 # Inst execution rate
+system.cpu2.iew.wb_sent 31851458 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 31817603 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 18729651 # num instructions producing a value
+system.cpu2.iew.wb_consumers 22311181 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.034325 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.855242 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.026298 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.839474 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 2305077 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 182652 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 175963 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 27062013 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.207707 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.849174 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 2502130 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 183232 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 177866 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 26618996 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.203206 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.875540 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 16121128 59.57% 59.57% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 2330838 8.61% 68.18% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1224813 4.53% 72.71% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 5615394 20.75% 93.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 503174 1.86% 95.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 185895 0.69% 96.01% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 176248 0.65% 96.66% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 179513 0.66% 97.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 725010 2.68% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 16042703 60.27% 60.27% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 2256116 8.48% 68.74% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1167560 4.39% 73.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 5327635 20.01% 93.14% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 518833 1.95% 95.09% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 187130 0.70% 95.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 168998 0.63% 96.43% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 171142 0.64% 97.07% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 778879 2.93% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 27062013 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 32682976 # Number of instructions committed
-system.cpu2.commit.committedOps 32682976 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 26618996 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 32028137 # Number of instructions committed
+system.cpu2.commit.committedOps 32028137 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 4889890 # Number of memory references committed
-system.cpu2.commit.loads 2942807 # Number of loads committed
-system.cpu2.commit.membars 63964 # Number of memory barriers committed
-system.cpu2.commit.branches 7465437 # Number of branches committed
-system.cpu2.commit.fp_insts 109562 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 31237309 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 229028 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 1167807 3.57% 3.57% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 26241804 80.29% 83.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 19886 0.06% 83.93% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.93% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 8426 0.03% 83.95% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.95% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.95% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.95% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 3006771 9.20% 93.16% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 1948666 5.96% 99.12% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess 288396 0.88% 100.00% # Class of committed instruction
+system.cpu2.commit.refs 4895422 # Number of memory references committed
+system.cpu2.commit.loads 2948538 # Number of loads committed
+system.cpu2.commit.membars 64184 # Number of memory barriers committed
+system.cpu2.commit.branches 7237241 # Number of branches committed
+system.cpu2.commit.fp_insts 109664 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 30577389 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 229570 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 1171866 3.66% 3.66% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 25576585 79.86% 83.52% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 19753 0.06% 83.58% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.58% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 8429 0.03% 83.60% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.60% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.60% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.60% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 3012722 9.41% 93.01% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 1948474 6.08% 99.10% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess 289088 0.90% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 32682976 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 725010 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 32028137 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 778879 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 61251181 # The number of ROB reads
-system.cpu2.rob.rob_writes 70355425 # The number of ROB writes
-system.cpu2.timesIdled 245354 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 3893863 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 1748379581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 31517609 # Number of Instructions Simulated
-system.cpu2.committedOps 31517609 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 0.994228 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.994228 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.005806 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.005806 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 42812311 # number of integer regfile reads
-system.cpu2.int_regfile_writes 22772429 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 67678 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 67966 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 5406368 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 257490 # number of misc regfile writes
+system.cpu2.rob.rob_reads 60296509 # The number of ROB reads
+system.cpu2.rob.rob_writes 69467378 # The number of ROB writes
+system.cpu2.timesIdled 246541 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 3976195 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 1746763449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 30858711 # Number of Instructions Simulated
+system.cpu2.committedOps 30858711 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.004654 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.004654 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.995368 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.995368 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 42053824 # number of integer regfile reads
+system.cpu2.int_regfile_writes 22390255 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 67731 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 68085 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 5172203 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 258202 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=256
-boot_loader=/dist/binaries/boot.arm
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-arm-ael.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
read_only=true
[system.clk_domain]
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
profile=0
progress_interval=0
simpoint_start_insts=
+socket_id=0
switched_out=false
system=system
tracer=system.cpu.checker.tracer
pio=system.membus.default
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[6]
[system.realview]
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
-warn: 6176053500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 6184767500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 6220839500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 6236327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6779610500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: 6127336500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 6135886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 6171724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 6187045500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6729690500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported
-warn: 51874115000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
-warn: 2476169247000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2490093200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2491309014500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2512521404000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2513043156000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2517323856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10
-warn: 2518814467000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2519896624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2519897721500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
-warn: 2520452967000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
+warn: 51815926000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 2464496392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
+warn: 2490035144500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2491240940500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
+warn: 2491596722500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
+warn: 2505538162500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
+warn: 2507237495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
+warn: 2512436106000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2512950831500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2518637805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2519704735000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2519705958000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:47:40
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:27:42
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu.checker.isa: ISA system set to: 0x645a800 0x645a800
- 0: system.cpu.isa: ISA system set to: 0x645a800 0x645a800
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
+ 0: system.cpu.checker.isa: ISA system set to: 0x639d990 0x639d990
+ 0: system.cpu.isa: ISA system set to: 0x639d990 0x639d990
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2526146947500 because m5_exit instruction encountered
+Exiting @ tick 2525888859000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.526192 # Number of seconds simulated
-sim_ticks 2526192217500 # Number of ticks simulated
-final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.525889 # Number of seconds simulated
+sim_ticks 2525888859000 # Number of ticks simulated
+final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 45758 # Simulator instruction rate (inst/s)
-host_op_rate 58877 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1916680323 # Simulator tick rate (ticks/s)
-host_mem_usage 469072 # Number of bytes of host memory used
-host_seconds 1318.00 # Real time elapsed on the host
-sim_insts 60309034 # Number of instructions simulated
-sim_ops 77600502 # Number of ops (including micro ops) simulated
+host_inst_rate 55568 # Simulator instruction rate (inst/s)
+host_op_rate 71500 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2327295647 # Simulator tick rate (ticks/s)
+host_mem_usage 420424 # Number of bytes of host memory used
+host_seconds 1085.33 # Real time elapsed on the host
+sim_insts 60309513 # Number of instructions simulated
+sim_ops 77601128 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096864 # Number of read requests accepted
-system.physmem.writeReqs 813148 # Number of write requests accepted
-system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 943480 # Per bank write bursts
-system.physmem.perBankRdBursts::1 937980 # Per bank write bursts
-system.physmem.perBankRdBursts::2 937559 # Per bank write bursts
-system.physmem.perBankRdBursts::3 937528 # Per bank write bursts
-system.physmem.perBankRdBursts::4 943087 # Per bank write bursts
-system.physmem.perBankRdBursts::5 937982 # Per bank write bursts
-system.physmem.perBankRdBursts::6 937070 # Per bank write bursts
-system.physmem.perBankRdBursts::7 936990 # Per bank write bursts
-system.physmem.perBankRdBursts::8 943982 # Per bank write bursts
-system.physmem.perBankRdBursts::9 938303 # Per bank write bursts
-system.physmem.perBankRdBursts::10 937119 # Per bank write bursts
-system.physmem.perBankRdBursts::11 936407 # Per bank write bursts
-system.physmem.perBankRdBursts::12 943924 # Per bank write bursts
-system.physmem.perBankRdBursts::13 938214 # Per bank write bursts
-system.physmem.perBankRdBursts::14 937241 # Per bank write bursts
-system.physmem.perBankRdBursts::15 937211 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6601 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6388 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6528 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6554 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6464 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6726 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6713 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6652 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7031 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6803 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6461 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6104 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7064 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6684 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6965 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6836 # Per bank write bursts
+system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096846 # Number of read requests accepted
+system.physmem.writeReqs 813159 # Number of write requests accepted
+system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 943526 # Per bank write bursts
+system.physmem.perBankRdBursts::1 937990 # Per bank write bursts
+system.physmem.perBankRdBursts::2 937469 # Per bank write bursts
+system.physmem.perBankRdBursts::3 937431 # Per bank write bursts
+system.physmem.perBankRdBursts::4 943079 # Per bank write bursts
+system.physmem.perBankRdBursts::5 938170 # Per bank write bursts
+system.physmem.perBankRdBursts::6 937203 # Per bank write bursts
+system.physmem.perBankRdBursts::7 936910 # Per bank write bursts
+system.physmem.perBankRdBursts::8 943866 # Per bank write bursts
+system.physmem.perBankRdBursts::9 938107 # Per bank write bursts
+system.physmem.perBankRdBursts::10 936563 # Per bank write bursts
+system.physmem.perBankRdBursts::11 936045 # Per bank write bursts
+system.physmem.perBankRdBursts::12 943886 # Per bank write bursts
+system.physmem.perBankRdBursts::13 937531 # Per bank write bursts
+system.physmem.perBankRdBursts::14 937186 # Per bank write bursts
+system.physmem.perBankRdBursts::15 937024 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6617 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6376 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6529 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6558 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6459 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6705 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6711 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6649 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7036 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6794 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6454 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6111 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7073 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6679 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6963 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6824 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2526191083500 # Total gap between requests
+system.physmem.totGap 2525887732500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 38 # Read request sizes (log2)
system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 154618 # Read request sizes (log2)
+system.physmem.readPktSize::6 154600 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 59130 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59141 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads
-system.physmem.totQLat 389908010000 # Total ticks spent queuing
-system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads
+system.physmem.totQLat 389024977250 # Total ticks spent queuing
+system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 2.99 # Data bus utilization in percentage
system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing
-system.physmem.readRowHits 14044000 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91096 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing
+system.physmem.readRowHits 14042089 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91063 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes
-system.physmem.avgGap 158779.96 # Average gap between requests
+system.physmem.avgGap 158760.96 # Average gap between requests
system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states
-system.physmem.memoryStateTime::REF 84354920000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states
+system.physmem.memoryStateTime::REF 84344780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states
+system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54877773 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16149486 # Transaction distribution
-system.membus.trans_dist::ReadResp 16149486 # Transaction distribution
+system.membus.throughput 54884184 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16149487 # Transaction distribution
+system.membus.trans_dist::ReadResp 16149487 # Transaction distribution
system.membus.trans_dist::WriteReq 763349 # Transaction distribution
system.membus.trans_dist::WriteResp 763349 # Transaction distribution
-system.membus.trans_dist::Writeback 59130 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution
+system.membus.trans_dist::Writeback 59141 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131451 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131451 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131431 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131431 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 138631802 # Total data (bytes)
+system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138631350 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 48265574 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution
+system.iobus.throughput 48271369 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution
system.iobus.trans_dist::WriteReq 8174 # Transaction distribution
system.iobus.trans_dist::WriteResp 8174 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 121928118 # Total data (bytes)
+system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121928114 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 14753661 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits
+system.cpu.branchPred.lookups 14910337 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions.
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 14987453 # DTB read hits
-system.cpu.checker.dtb.read_misses 7308 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227597 # DTB write hits
+system.cpu.checker.dtb.read_hits 14987595 # DTB read hits
+system.cpu.checker.dtb.read_misses 7306 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227720 # DTB write hits
system.cpu.checker.dtb.write_misses 2191 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 14994761 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229788 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994901 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229911 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26215050 # DTB hits
-system.cpu.checker.dtb.misses 9499 # DTB misses
-system.cpu.checker.dtb.accesses 26224549 # DTB accesses
+system.cpu.checker.dtb.hits 26215315 # DTB hits
+system.cpu.checker.dtb.misses 9497 # DTB misses
+system.cpu.checker.dtb.accesses 26224812 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.itb.inst_hits 61483008 # ITB inst hits
+system.cpu.checker.itb.inst_hits 61483491 # ITB inst hits
system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61487481 # ITB inst accesses
-system.cpu.checker.itb.hits 61483008 # DTB hits
+system.cpu.checker.itb.inst_accesses 61487964 # ITB inst accesses
+system.cpu.checker.itb.hits 61483491 # DTB hits
system.cpu.checker.itb.misses 4473 # DTB misses
-system.cpu.checker.itb.accesses 61487481 # DTB accesses
-system.cpu.checker.numCycles 77886295 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61487964 # DTB accesses
+system.cpu.checker.numCycles 77886925 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51183231 # DTB read hits
-system.cpu.dtb.read_misses 65223 # DTB read misses
-system.cpu.dtb.write_hits 11700953 # DTB write hits
-system.cpu.dtb.write_misses 15725 # DTB write misses
+system.cpu.dtb.read_hits 51097792 # DTB read hits
+system.cpu.dtb.read_misses 64987 # DTB read misses
+system.cpu.dtb.write_hits 11709971 # DTB write hits
+system.cpu.dtb.write_misses 15921 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51248454 # DTB read accesses
-system.cpu.dtb.write_accesses 11716678 # DTB write accesses
+system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51162779 # DTB read accesses
+system.cpu.dtb.write_accesses 11725892 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 62884184 # DTB hits
-system.cpu.dtb.misses 80948 # DTB misses
-system.cpu.dtb.accesses 62965132 # DTB accesses
+system.cpu.dtb.hits 62807763 # DTB hits
+system.cpu.dtb.misses 80908 # DTB misses
+system.cpu.dtb.accesses 62888671 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 11525561 # ITB inst hits
-system.cpu.itb.inst_misses 11159 # ITB inst misses
+system.cpu.itb.inst_hits 11575507 # ITB inst hits
+system.cpu.itb.inst_misses 11335 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11536720 # ITB inst accesses
-system.cpu.itb.hits 11525561 # DTB hits
-system.cpu.itb.misses 11159 # DTB misses
-system.cpu.itb.accesses 11536720 # DTB accesses
-system.cpu.numCycles 477128882 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11586842 # ITB inst accesses
+system.cpu.itb.hits 11575507 # DTB hits
+system.cpu.itb.misses 11335 # DTB misses
+system.cpu.itb.accesses 11586842 # DTB accesses
+system.cpu.numCycles 476238509 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued
-system.cpu.iq.rate 0.257622 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued
+system.cpu.iq.rate 0.258180 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 222849 # number of nop insts executed
-system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11822089 # Number of branches executed
-system.cpu.iew.exec_stores 12212847 # Number of stores executed
-system.cpu.iew.exec_rate 0.253272 # Inst execution rate
-system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47017508 # num instructions producing a value
-system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value
+system.cpu.iew.exec_nop 226309 # number of nop insts executed
+system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11843747 # Number of branches executed
+system.cpu.iew.exec_stores 12222179 # Number of stores executed
+system.cpu.iew.exec_rate 0.253798 # Inst execution rate
+system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47892202 # num instructions producing a value
+system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60459415 # Number of instructions committed
-system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60459894 # Number of instructions committed
+system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386618 # Number of memory references committed
-system.cpu.commit.loads 15654647 # Number of loads committed
-system.cpu.commit.membars 403571 # Number of memory barriers committed
-system.cpu.commit.branches 10306311 # Number of branches committed
+system.cpu.commit.refs 27386881 # Number of memory references committed
+system.cpu.commit.loads 15654781 # Number of loads committed
+system.cpu.commit.membars 403574 # Number of memory barriers committed
+system.cpu.commit.branches 10306383 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69190973 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991245 # Number of function calls committed.
+system.cpu.commit.int_insts 69191543 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991261 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction
-system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction
+system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 243007370 # The number of ROB reads
-system.cpu.rob.rob_writes 195993770 # The number of ROB writes
-system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60309034 # Number of Instructions Simulated
-system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 548643018 # number of integer regfile reads
-system.cpu.int_regfile_writes 87545925 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8332 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2902 # number of floating regfile writes
-system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution
+system.cpu.rob.rob_reads 239318561 # The number of ROB reads
+system.cpu.rob.rob_writes 197472000 # The number of ROB writes
+system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60309513 # Number of Instructions Simulated
+system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 548833946 # number of integer regfile reads
+system.cpu.int_regfile_writes 87707846 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8328 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
+system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 981488 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 980898 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits
-system.cpu.icache.overall_hits::total 10460581 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses
-system.cpu.icache.overall_misses::total 1061360 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits
+system.cpu.icache.overall_hits::total 10510158 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1061739 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1061739 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1061739 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1061739 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1061739 # number of overall misses
+system.cpu.icache.overall_misses::total 1061739 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14266290615 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14266290615 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14266290615 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14266290615 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14266290615 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14266290615 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11571897 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11571897 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11571897 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11571897 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11571897 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11571897 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091752 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.091752 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.091752 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.091752 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 21.883582 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 116 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982041 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 982041 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 982041 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 982041 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 982041 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 982041 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583712225 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11583712225 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583712225 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11583712225 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583712225 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11583712225 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8965500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8965500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8965500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 8965500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 80293 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 80293 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 80293 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 80293 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 80293 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981446 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 981446 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 981446 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 981446 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 981446 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 981446 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11573178578 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11573178578 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11573178578 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11573178578 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11573178578 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11573178578 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8964000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8964000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8964000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total 8964000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084813 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.084813 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.084813 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 64387 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1888247 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 129781 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 14.549487 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 2490875317000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 37.347999 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.789418 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 6233.237161 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.563624 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000570 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements 64369 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 51363.817213 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1888922 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 129761 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 14.556932 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 2490733870000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 33.862464 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000252 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 8170.435646 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 6222.182012 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.563619 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000517 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124753 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.095112 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.784059 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124671 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.094943 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.783750 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 65369 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3046 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6928 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54999 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 18797143 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 18797143 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53905 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10470 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 968525 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 386928 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1419828 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 607456 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 607456 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112956 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112956 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 53905 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 10470 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 968525 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 499884 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1532784 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 53905 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 10470 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 968525 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 499884 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1532784 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 12346 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 10726 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3050 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54961 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997452 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 18802940 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 18802940 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54086 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10683 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 967938 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 387449 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1420156 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607940 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607940 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112904 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112904 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 54086 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10683 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 967938 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 500353 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1533060 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 54086 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10683 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 967938 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 500353 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1533060 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10729 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23125 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133222 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133222 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 12346 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143948 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 156349 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 53 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 12346 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143948 # number of overall misses
-system.cpu.l2cache.overall_misses::total 156349 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4489500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 430000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 894766750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 805694000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1705380250 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465480 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9848665479 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 9848665479 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4489500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 894766750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10654359479 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 11554045729 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4489500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 430000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 894766750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10654359479 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 11554045729 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53958 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10472 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 980871 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 397654 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1442955 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 607456 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 607456 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133201 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133201 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143930 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156326 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 12347 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143930 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156326 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3943500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 83000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 890764250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 800380499 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1695171249 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 583475 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 583475 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9778985980 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 9778985980 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3943500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 83000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 890764250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10579366479 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 11474157229 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3943500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 83000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 890764250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10579366479 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 11474157229 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54134 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10684 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 980285 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 398178 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1443281 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607940 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607940 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 246178 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 246178 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53958 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 10472 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 980871 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 643832 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1689133 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53958 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 10472 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 980871 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 643832 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1689133 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012587 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026973 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.016028 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984828 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984828 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541161 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.541161 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012587 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.223580 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.092562 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012587 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.223580 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.092562 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84707.547170 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 215000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72474.222420 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.979862 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73739.795477 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.356385 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.356385 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73926.719904 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73926.719904 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73899.070215 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73899.070215 # average overall miss latency
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54134 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10684 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 980285 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 644283 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1689386 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54134 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10684 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 980285 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 644283 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1689386 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000887 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000094 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012595 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026945 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.016023 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985502 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985502 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.272727 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541236 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541236 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000887 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000094 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012595 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223396 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.092534 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000887 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000094 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012595 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223396 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.092534 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82156.250000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72144.184822 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74599.729611 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73304.702659 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 199.615121 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 199.615121 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73415.259495 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73415.259495 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73398.905038 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73398.905038 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 59130 # number of writebacks
-system.cpu.l2cache.writebacks::total 59130 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12332 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10659 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks 59141 # number of writebacks
+system.cpu.l2cache.writebacks::total 59141 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12336 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10663 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133222 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133222 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12332 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143881 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 156268 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12332 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143881 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3834000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 405500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 738779500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668273250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1411292250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29213921 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29213921 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133201 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133201 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12336 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143864 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156249 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12336 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143864 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156249 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3351000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 71000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 734971750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 663368999 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1401762749 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29236922 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29236922 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8190370021 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8190370021 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3834000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 405500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 738779500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8858643271 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 9601662271 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3834000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 405500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 738779500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8858643271 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 9601662271 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6434999 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17456853479 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17456853479 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6434999 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8137112520 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8137112520 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3351000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 71000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 734971750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8800481519 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 9538875269 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3351000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 71000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 734971750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8800481519 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 9538875269 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6435500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942048250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948483750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17498078150 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17498078150 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6435500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184440126400 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184446561900 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026779 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015969 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541236 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541236 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.092489 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.092489 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62212.229110 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60819.279287 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.368115 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.368115 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61088.974707 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61088.974707 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 643320 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.993245 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 21508532 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements 643771 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.993313 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 21491250 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 644283 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.993313 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits
-system.cpu.dcache.overall_hits::total 21015072 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses
-system.cpu.dcache.overall_misses::total 3699212 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses 101573451 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 101573451 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 13743815 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13743815 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7253892 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7253892 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 242816 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 242816 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 20997707 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 20997707 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 20997707 # number of overall hits
+system.cpu.dcache.overall_hits::total 20997707 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 762201 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 762201 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2968429 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2968429 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13530 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13530 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3730630 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3730630 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3730630 # number of overall misses
+system.cpu.dcache.overall_misses::total 3730630 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 10170757825 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 10170757825 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 136412874713 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 136412874713 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184826749 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 184826749 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 180503 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 180503 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 146583632538 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 146583632538 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 146583632538 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 146583632538 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14506016 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14506016 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10222321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10222321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256346 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 256346 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247609 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247609 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24728337 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24728337 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24728337 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24728337 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052544 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.052544 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290387 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.290387 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052780 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052780 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.150865 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.150865 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.150865 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.150865 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks
-system.cpu.dcache.writebacks::total 607456 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks
+system.cpu.dcache.writebacks::total 607940 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249004 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 635064 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 635064 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=256
-boot_loader=/dist/binaries/boot.arm
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-arm-ael.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
read_only=true
[system.clk_domain]
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
pio=system.membus.default
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[6]
[system.realview]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:56:34
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:27:42
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu0.isa: ISA system set to: 0x6856800 0x6856800
- 0: system.cpu1.isa: ISA system set to: 0x6856800 0x6856800
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
+ 0: system.cpu0.isa: ISA system set to: 0x628e100 0x628e100
+ 0: system.cpu1.isa: ISA system set to: 0x628e100 0x628e100
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2605645191500 because m5_exit instruction encountered
+Exiting @ tick 2605245500000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.605644 # Number of seconds simulated
-sim_ticks 2605643988500 # Number of ticks simulated
-final_tick 2605643988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.605246 # Number of seconds simulated
+sim_ticks 2605245500000 # Number of ticks simulated
+final_tick 2605245500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56388 # Simulator instruction rate (inst/s)
-host_op_rate 72604 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2339801960 # Simulator tick rate (ticks/s)
-host_mem_usage 475216 # Number of bytes of host memory used
-host_seconds 1113.62 # Real time elapsed on the host
-sim_insts 62794806 # Number of instructions simulated
-sim_ops 80853196 # Number of ops (including micro ops) simulated
+host_inst_rate 66179 # Simulator instruction rate (inst/s)
+host_op_rate 85203 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2745863070 # Simulator tick rate (ticks/s)
+host_mem_usage 426204 # Number of bytes of host memory used
+host_seconds 948.79 # Real time elapsed on the host
+sim_insts 62790043 # Number of instructions simulated
+sim_ops 80839298 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 394240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4377212 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 429184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5246712 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131559796 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 394240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 429184 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 823424 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4275584 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4351548 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 427968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5241528 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131526900 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 427968 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 821504 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4250944 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7304720 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7280080 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6160 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68468 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6706 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 82008 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15302188 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66806 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68067 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6687 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 81927 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15301674 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66421 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 824090 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46480075 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 151302 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1679896 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 164713 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2013595 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50490319 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 151302 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 164713 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316016 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1640893 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2803422 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1640893 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46480075 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 151302 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1686421 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 164713 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3169600 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53293741 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15302188 # Number of read requests accepted
-system.physmem.writeReqs 824090 # Number of write requests accepted
-system.physmem.readBursts 15302188 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 824090 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 974626176 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 4713856 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7328128 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 131559796 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7304720 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 73654 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 709569 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 14159 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 956238 # Per bank write bursts
-system.physmem.perBankRdBursts::1 951013 # Per bank write bursts
-system.physmem.perBankRdBursts::2 950196 # Per bank write bursts
-system.physmem.perBankRdBursts::3 950464 # Per bank write bursts
-system.physmem.perBankRdBursts::4 956634 # Per bank write bursts
-system.physmem.perBankRdBursts::5 950822 # Per bank write bursts
-system.physmem.perBankRdBursts::6 949869 # Per bank write bursts
-system.physmem.perBankRdBursts::7 949811 # Per bank write bursts
-system.physmem.perBankRdBursts::8 956681 # Per bank write bursts
-system.physmem.perBankRdBursts::9 951277 # Per bank write bursts
-system.physmem.perBankRdBursts::10 949961 # Per bank write bursts
-system.physmem.perBankRdBursts::11 949024 # Per bank write bursts
-system.physmem.perBankRdBursts::12 956331 # Per bank write bursts
-system.physmem.perBankRdBursts::13 950586 # Per bank write bursts
-system.physmem.perBankRdBursts::14 950041 # Per bank write bursts
-system.physmem.perBankRdBursts::15 949586 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7062 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6963 # Per bank write bursts
-system.physmem.perBankWrBursts::2 7126 # Per bank write bursts
-system.physmem.perBankWrBursts::3 7116 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7811 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7409 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7013 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7004 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7458 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7561 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6914 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6583 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7179 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7101 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7219 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6983 # Per bank write bursts
+system.physmem.num_writes::total 823705 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46487184 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 151055 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1670302 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 319 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 164272 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2011913 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50485415 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 151055 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 164272 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315327 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1631687 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6525 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 1156181 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2794393 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1631687 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46487184 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 151055 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1676828 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 164272 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 3168095 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53279808 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15301674 # Number of read requests accepted
+system.physmem.writeReqs 823705 # Number of write requests accepted
+system.physmem.readBursts 15301674 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 823705 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 974584832 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 4722304 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7299840 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 131526900 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7280080 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 73786 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 709619 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 14174 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 956301 # Per bank write bursts
+system.physmem.perBankRdBursts::1 950868 # Per bank write bursts
+system.physmem.perBankRdBursts::2 950386 # Per bank write bursts
+system.physmem.perBankRdBursts::3 950557 # Per bank write bursts
+system.physmem.perBankRdBursts::4 956616 # Per bank write bursts
+system.physmem.perBankRdBursts::5 950990 # Per bank write bursts
+system.physmem.perBankRdBursts::6 949776 # Per bank write bursts
+system.physmem.perBankRdBursts::7 949548 # Per bank write bursts
+system.physmem.perBankRdBursts::8 956645 # Per bank write bursts
+system.physmem.perBankRdBursts::9 951285 # Per bank write bursts
+system.physmem.perBankRdBursts::10 949982 # Per bank write bursts
+system.physmem.perBankRdBursts::11 948991 # Per bank write bursts
+system.physmem.perBankRdBursts::12 956228 # Per bank write bursts
+system.physmem.perBankRdBursts::13 950424 # Per bank write bursts
+system.physmem.perBankRdBursts::14 949846 # Per bank write bursts
+system.physmem.perBankRdBursts::15 949445 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7049 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6917 # Per bank write bursts
+system.physmem.perBankWrBursts::2 7321 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7203 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7749 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7300 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7008 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6995 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7363 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7456 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6910 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6580 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7092 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7012 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7131 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6974 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2605642823000 # Total gap between requests
+system.physmem.totGap 2605244301000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 109 # Read request sizes (log2)
system.physmem.readPktSize::3 15138816 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 163263 # Read request sizes (log2)
+system.physmem.readPktSize::6 162749 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 757284 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 66806 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1074226 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1009957 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 967065 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1078396 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 970167 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1034458 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2664402 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2566961 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3342237 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 136100 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 116220 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 107345 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 103465 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 19833 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 18840 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 18525 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 66421 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1076672 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1007796 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 966781 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1073648 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 970528 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1031139 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2669789 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2577083 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3357471 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 128637 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 102015 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 98116 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 19856 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 18946 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 18627 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2784 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3035 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4735 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6745 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6909 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6865 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 6920 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6907 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 6964 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4505 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6717 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6884 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6834 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6859 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7222 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 6902 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 6949 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6984 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6828 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6810 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6824 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6992 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 96 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7238 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6837 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6807 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6705 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1012463 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 969.866853 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 900.909804 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 207.662919 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 24967 2.47% 2.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 21104 2.08% 4.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8681 0.86% 5.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2506 0.25% 5.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2720 0.27% 5.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2029 0.20% 6.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8638 0.85% 6.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1014 0.10% 7.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 940804 92.92% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1012463 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6706 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2270.880853 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 84552.226363 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143 6700 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6706 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6706 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.074560 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.020748 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.396636 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3829 57.10% 57.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 48 0.72% 57.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1779 26.53% 84.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 878 13.09% 97.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 53 0.79% 98.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 31 0.46% 98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 34 0.51% 99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 40 0.60% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 12 0.18% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6706 # Writes before turning the bus around for reads
-system.physmem.totQLat 395588666000 # Total ticks spent queuing
-system.physmem.totMemAccLat 681123678500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76142670000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25976.81 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1012037 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 970.206299 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 901.657757 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 207.022901 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 24841 2.45% 2.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 20798 2.06% 4.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8822 0.87% 5.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2548 0.25% 5.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2540 0.25% 5.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1879 0.19% 6.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8798 0.87% 6.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1115 0.11% 7.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 940696 92.95% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1012037 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2278.257181 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 111148.889106 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 6680 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.064632 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.010880 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.396865 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3849 57.59% 57.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 42 0.63% 58.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1749 26.17% 84.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 863 12.91% 97.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 73 1.09% 98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 28 0.42% 98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 31 0.46% 99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 31 0.46% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 14 0.21% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads
+system.physmem.totQLat 394529621500 # Total ticks spent queuing
+system.physmem.totMemAccLat 680052521500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 76139440000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25908.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44726.81 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 374.04 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44658.36 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 374.09 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.94 # Data bus utilization in percentage
system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing
-system.physmem.readRowHits 14234195 # Number of row buffer hits during reads
-system.physmem.writeRowHits 96378 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
+system.physmem.readRowHits 14233868 # Number of row buffer hits during reads
+system.physmem.writeRowHits 96043 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 84.16 # Row buffer hit rate for writes
-system.physmem.avgGap 161577.45 # Average gap between requests
+system.physmem.writeRowHitRate 84.18 # Row buffer hit rate for writes
+system.physmem.avgGap 161561.74 # Average gap between requests
system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2260536385250 # Time in different power states
-system.physmem.memoryStateTime::REF 87007960000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2261037204000 # Time in different power states
+system.physmem.memoryStateTime::REF 86994700000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 258093332250 # Time in different power states
+system.physmem.memoryStateTime::ACT 257208674750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54224369 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16352672 # Transaction distribution
-system.membus.trans_dist::ReadResp 16352672 # Transaction distribution
+system.membus.throughput 54210578 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16352619 # Transaction distribution
+system.membus.trans_dist::ReadResp 16352619 # Transaction distribution
system.membus.trans_dist::WriteReq 769183 # Transaction distribution
system.membus.trans_dist::WriteResp 769183 # Transaction distribution
-system.membus.trans_dist::Writeback 66806 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 35949 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 18292 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 14159 # Transaction distribution
-system.membus.trans_dist::ReadExReq 138125 # Transaction distribution
-system.membus.trans_dist::ReadExResp 137746 # Transaction distribution
+system.membus.trans_dist::Writeback 66421 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 35773 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 18321 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 14174 # Transaction distribution
+system.membus.trans_dist::ReadExReq 137666 # Transaction distribution
+system.membus.trans_dist::ReadExResp 137285 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976897 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4377155 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975354 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4375612 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34654787 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34653244 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17753988 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 20178873 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17696452 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 20121337 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 141289401 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 141289401 # Total data (bytes)
+system.membus.tot_pkt_size::total 141231865 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 141231865 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1487962500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1487709500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11808000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 11701000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1796000 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1799000 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17659548997 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17608394498 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4847870095 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4825319244 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37379122644 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 37398632151 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 72974 # number of replacements
-system.l2c.tags.tagsinuse 53023.948009 # Cycle average of tags in use
-system.l2c.tags.total_refs 1873330 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 138152 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 13.559920 # Average number of references to valid blocks.
+system.l2c.tags.replacements 72458 # number of replacements
+system.l2c.tags.tagsinuse 53011.924457 # Cycle average of tags in use
+system.l2c.tags.total_refs 1875821 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 137631 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 13.629349 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 37706.296895 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.412172 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000364 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4169.126027 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2962.597547 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.621110 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 4061.748879 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 4107.145016 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.575352 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks 37713.505334 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.216539 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 4181.052971 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 2965.825646 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.076579 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 4028.442908 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 4106.804235 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.575462 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000080 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.063616 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.045206 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000177 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.061977 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.062670 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.809081 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3154 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 9081 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 52631 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 18850449 # Number of tag accesses
-system.l2c.tags.data_accesses 18850449 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 22712 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 4441 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 393676 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 165723 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 33196 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 5802 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 607870 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 201576 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1434996 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 583128 # number of Writeback hits
-system.l2c.Writeback_hits::total 583128 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 1123 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1850 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 207 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 158 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 47567 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 59393 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 22712 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 4441 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 393676 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 213290 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 33196 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 5802 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 607870 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 260969 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1541956 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 22712 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 4441 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 393676 # number of overall hits
-system.l2c.overall_hits::cpu0.data 213290 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 33196 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 5802 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 607870 # number of overall hits
-system.l2c.overall_hits::cpu1.data 260969 # number of overall hits
-system.l2c.overall_hits::total 1541956 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 6041 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6321 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 6670 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 6363 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 25425 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 5691 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 4436 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 10127 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 767 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1356 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 63545 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 76877 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140422 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 6041 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 69866 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 6670 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 83240 # number of demand (read+write) misses
-system.l2c.demand_misses::total 165847 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 6041 # number of overall misses
-system.l2c.overall_misses::cpu0.data 69866 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 6670 # number of overall misses
-system.l2c.overall_misses::cpu1.data 83240 # number of overall misses
-system.l2c.overall_misses::total 165847 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1149750 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker 368000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 435967250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 468270999 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1231000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 485141500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 483349999 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1875478498 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 9144593 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 12320478 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 21465071 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 441981 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3192363 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 3634344 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 4462150559 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 6003353008 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 10465503567 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 1149750 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker 368000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 435967250 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 4930421558 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 1231000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 485141500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 6486703007 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 12340982065 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 1149750 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker 368000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 435967250 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 4930421558 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 1231000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 485141500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 6486703007 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 12340982065 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 22724 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 4443 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 399717 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 172044 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 33212 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 5802 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 614540 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 207939 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1460421 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 583128 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 583128 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 6814 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 5163 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 11977 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 974 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 747 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1721 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 111112 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 136270 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 247382 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 22724 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 4443 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 399717 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 283156 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 33212 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 5802 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 614540 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 344209 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1707803 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 22724 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 4443 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 399717 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 283156 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 33212 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 5802 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 614540 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 344209 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1707803 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000450 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015113 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.036741 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.010854 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.030600 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.017409 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.835192 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.859190 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.845537 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787474 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.788487 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.787914 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.571900 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.564152 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.567632 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000450 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015113 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.246740 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.010854 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.241830 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.097111 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000450 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015113 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.246740 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.010854 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.241830 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.097111 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95812.500000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 184000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72168.059924 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 74081.790698 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76937.500000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72734.857571 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 75962.596102 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 73765.132665 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1606.851696 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2777.384581 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 2119.588328 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 576.246415 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5419.971138 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 2680.194690 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70220.325108 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78090.365233 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74528.945372 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95812.500000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 184000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 72168.059924 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 70569.684224 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76937.500000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72734.857571 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 77927.715125 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 74411.849868 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95812.500000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 184000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 72168.059924 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70569.684224 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76937.500000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72734.857571 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 77927.715125 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 74411.849868 # average overall miss latency
+system.l2c.tags.occ_percent::cpu0.inst 0.063798 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.045255 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.061469 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.062665 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.808898 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 3104 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 8671 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 53043 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 18870937 # Number of tag accesses
+system.l2c.tags.data_accesses 18870937 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 23602 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 4624 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 393472 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 166101 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 33133 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 5623 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 609766 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 201485 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1437806 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 583097 # number of Writeback hits
+system.l2c.Writeback_hits::total 583097 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 1009 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 849 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 1858 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 170 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 380 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 48094 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 59208 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 107302 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 23602 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 4624 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 393472 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 214195 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 33133 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 5623 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 609766 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 260693 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1545108 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 23602 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 4624 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 393472 # number of overall hits
+system.l2c.overall_hits::cpu0.data 214195 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 33133 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 5623 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 609766 # number of overall hits
+system.l2c.overall_hits::cpu1.data 260693 # number of overall hits
+system.l2c.overall_hits::total 1545108 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 6027 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6315 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 13 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 6652 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 6349 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 25371 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 5736 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 4455 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 10191 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 772 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 591 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1363 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 63106 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 76799 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 139905 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 6027 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 69421 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 6652 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 83148 # number of demand (read+write) misses
+system.l2c.demand_misses::total 165276 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 6027 # number of overall misses
+system.l2c.overall_misses::cpu0.data 69421 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 13 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 6652 # number of overall misses
+system.l2c.overall_misses::cpu1.data 83148 # number of overall misses
+system.l2c.overall_misses::total 165276 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1286000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker 293000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 437446500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 469525749 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1020750 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 484881000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 483780000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1878232999 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 9370079 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 12322478 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 21692557 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 533977 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3118865 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 3652842 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 4338208852 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 5958244026 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 10296452878 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 1286000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 437446500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 4807734601 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 1020750 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 484881000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 6442024026 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 12174685877 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 1286000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker 293000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 437446500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 4807734601 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 1020750 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 484881000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 6442024026 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 12174685877 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 23616 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 4625 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 399499 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 172416 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 33146 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 5623 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 616418 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 207834 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1463177 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 583097 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 583097 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 6745 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 5304 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 12049 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 982 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 761 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1743 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 111200 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 136007 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 23616 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 4625 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 399499 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 283616 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 33146 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 5623 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 616418 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 343841 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1710384 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 23616 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 4625 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 399499 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 283616 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 33146 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 5623 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 616418 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 343841 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1710384 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000216 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015086 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.036627 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.010791 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.030548 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.017340 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.850408 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.839932 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.845796 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.786151 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776610 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.781985 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.567500 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.564669 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.565943 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000216 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015086 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.244771 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.010791 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.241821 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.096631 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000216 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015086 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.244771 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.010791 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.241821 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.096631 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 91857.142857 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 293000 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72581.134893 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 74350.870784 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78519.230769 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72892.513530 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76197.826429 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 74030.704308 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1633.556311 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2765.988328 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 2128.599450 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 691.680052 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5277.267343 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 2680.001467 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68744.792128 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77582.312608 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 73596.032150 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91857.142857 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 293000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 72581.134893 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 69254.758661 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78519.230769 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 72892.513530 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 77476.596262 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 73662.757309 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91857.142857 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 293000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 72581.134893 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 69254.758661 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78519.230769 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72892.513530 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 77476.596262 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 73662.757309 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 66806 # number of writebacks
-system.l2c.writebacks::total 66806 # number of writebacks
+system.l2c.writebacks::writebacks 66421 # number of writebacks
+system.l2c.writebacks::total 66421 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 26 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 12 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 6036 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 6284 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 6663 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 6337 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 25350 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 5691 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 4436 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 10127 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 767 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 1356 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 63545 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 76877 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 140422 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 12 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 6036 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 69829 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 6663 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 83214 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 165772 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 12 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 6036 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 69829 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 6663 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 83214 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 165772 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1001750 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 343500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 359682000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 387178249 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1034000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 400959000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 402487249 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1552685748 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57050142 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44722851 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 101772993 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7680764 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5892086 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 13572850 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3668395937 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5048276480 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 8716672417 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1001750 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 343500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 359682000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 4055574186 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1034000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 400959000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 5450763729 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 10269358165 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1001750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 343500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 359682000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 4055574186 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1034000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 400959000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 5450763729 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 10269358165 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6890749 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12335372988 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2843750 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154881314980 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167226422467 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1073382998 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16528122341 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 17601505339 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6890749 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13408755986 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2843750 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171409437321 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184827927806 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036526 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030475 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.017358 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.835192 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.859190 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.845537 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787474 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.788487 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.787914 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.571900 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564152 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.567632 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.246610 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.241754 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.097067 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.246610 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.241754 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.097067 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61613.343253 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63513.847089 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61249.930888 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.625198 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.796889 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.668510 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10014.033898 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.541596 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10009.476401 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57729.104367 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65666.928730 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 62074.834549 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency
+system.l2c.overall_mshr_hits::total 77 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 6022 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 6277 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 13 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 6644 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 6323 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 25294 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 5736 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 4455 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 10191 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 772 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 591 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 1363 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 63106 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 76799 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 139905 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 6022 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 69383 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 13 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 6644 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 83122 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 165199 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 6022 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 69383 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 13 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 6644 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 83122 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 165199 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1113000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 281000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 361272500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 388267999 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 860750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 400921250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 403426250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1556142749 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57546650 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44906373 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 102453023 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7730770 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5917089 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 13647859 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3559268136 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5010952970 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 8570221106 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1113000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 281000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 361272500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 3947536135 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 860750 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 400921250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 5414379220 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 10126363855 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1113000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 281000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 361272500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 3947536135 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 860750 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 400921250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 5414379220 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 10126363855 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7054750 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12335372985 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3127500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154881187230 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167226742465 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1073385998 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16534155943 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 17607541941 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7054750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13408758983 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3127500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171415343173 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184834284406 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036406 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030423 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.017287 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.850408 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.839932 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.845796 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.786151 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776610 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.781985 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567500 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564669 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.565943 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.244637 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.241745 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.096586 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.244637 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.241745 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.096586 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61855.663374 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63802.981180 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61522.208785 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10032.540098 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10079.993939 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10053.284565 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.950777 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.994924 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.102715 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56401.421988 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65247.633042 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61257.432586 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61297.973081 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61297.973081 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 58718575 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2740966 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2740965 # Transaction distribution
+system.toL2Bus.throughput 58770672 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2743232 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2743231 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 583128 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 35123 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 53780 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 259272 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 259272 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800244 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073141 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13760 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56807 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1229764 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820581 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15635 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75586 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8085518 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25589824 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34686241 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17772 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90896 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39333696 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48239320 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23208 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132848 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 148113805 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 148113805 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 4885896 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4921313376 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::Writeback 583097 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 35011 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 18701 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 53712 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 259154 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 259154 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799809 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073837 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14034 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57985 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1233533 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820063 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15283 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75701 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 8090245 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25576064 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34728353 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18500 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94464 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39453888 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48201112 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22492 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132584 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 148227457 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 148227457 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 4884572 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4922251450 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1803473389 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1802620121 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1514355955 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1515652575 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 9338456 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 9436941 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 34226949 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 34537141 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 2770248418 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 2778792830 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 3257977460 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 3257203486 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy 9851958 # Layer occupancy (ticks)
+system.toL2Bus.respLayer8.occupancy 9681453 # Layer occupancy (ticks)
system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy 42643941 # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.occupancy 42845398 # Layer occupancy (ticks)
system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 47398342 # Throughput (bytes/s)
+system.iobus.throughput 47405592 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution
system.iobus.trans_dist::WriteReq 8083 # Transaction distribution
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38174483356 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38152801849 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 6117114 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4670626 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 296157 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3842728 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2949969 # Number of BTB hits
+system.cpu0.branchPred.lookups 6193187 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4738042 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 296192 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3876930 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2986045 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 76.767572 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 683314 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 28361 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 77.020864 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 687525 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28310 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8969403 # DTB read hits
-system.cpu0.dtb.read_misses 29343 # DTB read misses
-system.cpu0.dtb.write_hits 5210557 # DTB write hits
-system.cpu0.dtb.write_misses 5731 # DTB write misses
+system.cpu0.dtb.read_hits 8977307 # DTB read hits
+system.cpu0.dtb.read_misses 29619 # DTB read misses
+system.cpu0.dtb.write_hits 5215302 # DTB write hits
+system.cpu0.dtb.write_misses 5680 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1050 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1732 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 993 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8998746 # DTB read accesses
-system.cpu0.dtb.write_accesses 5216288 # DTB write accesses
+system.cpu0.dtb.perms_faults 620 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 9006926 # DTB read accesses
+system.cpu0.dtb.write_accesses 5220982 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14179960 # DTB hits
-system.cpu0.dtb.misses 35074 # DTB misses
-system.cpu0.dtb.accesses 14215034 # DTB accesses
+system.cpu0.dtb.hits 14192609 # DTB hits
+system.cpu0.dtb.misses 35299 # DTB misses
+system.cpu0.dtb.accesses 14227908 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 4277605 # ITB inst hits
-system.cpu0.itb.inst_misses 5145 # ITB inst misses
+system.cpu0.itb.inst_hits 4299863 # ITB inst hits
+system.cpu0.itb.inst_misses 5195 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1219 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1426 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1331 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4282750 # ITB inst accesses
-system.cpu0.itb.hits 4277605 # DTB hits
-system.cpu0.itb.misses 5145 # DTB misses
-system.cpu0.itb.accesses 4282750 # DTB accesses
-system.cpu0.numCycles 70248238 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4305058 # ITB inst accesses
+system.cpu0.itb.hits 4299863 # DTB hits
+system.cpu0.itb.misses 5195 # DTB misses
+system.cpu0.itb.accesses 4305058 # DTB accesses
+system.cpu0.numCycles 69478980 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 11931842 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 32451975 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6117114 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3633283 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7612739 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1460869 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 60951 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 20309232 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 6063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 46682 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1377400 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 299 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4276074 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 156796 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2089 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 42393450 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.988978 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.370199 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 11944453 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32774113 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6193187 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3673570 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7678957 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1502530 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 63317 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 19508655 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 6049 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 47760 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1413705 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 248 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4298413 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 159366 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2185 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 41753011 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.013655 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.394447 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 34788183 82.06% 82.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 572054 1.35% 83.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 825907 1.95% 85.36% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 686377 1.62% 86.98% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 779180 1.84% 88.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 565083 1.33% 90.15% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 677221 1.60% 91.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 357838 0.84% 92.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3141607 7.41% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 34081524 81.63% 81.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 576095 1.38% 83.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 828597 1.98% 84.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 688423 1.65% 86.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 783359 1.88% 88.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 570610 1.37% 89.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 698382 1.67% 91.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 360373 0.86% 92.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3165648 7.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 42393450 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.087079 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.461961 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12487890 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 21493629 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6874468 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 552722 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 984741 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 950951 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64626 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 40558878 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 212020 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 984741 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 13064503 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5883311 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13498743 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6804692 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2157460 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 39446559 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 311 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 442642 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1180293 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 145 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 39856275 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 180582545 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 163877057 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 4135 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 31488132 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8368142 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 460013 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 416638 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5509006 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7758217 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5771757 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1123661 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1193308 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 37348678 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 906063 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37718806 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 82800 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6312476 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13233696 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 257258 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 42393450 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.889732 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.506737 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 41753011 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.089138 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.471713 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12274082 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 20961054 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 7066192 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 425731 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1025952 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 955706 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 65065 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40945366 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 213036 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1025952 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12760478 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 3004976 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13648632 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 7041602 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 4271371 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 39802599 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1199 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 1526731 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 1438820 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 1837389 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 522 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 40279465 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 182145305 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 165318292 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 4116 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 31479900 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8799564 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 460456 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 417031 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 4293085 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7837564 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5796369 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1159621 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1213862 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 37649045 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 906994 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37770468 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 93887 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6620221 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 14342287 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 258409 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 41753011 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.904617 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.539726 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 27027469 63.75% 63.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5904750 13.93% 77.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3167008 7.47% 85.15% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2470651 5.83% 90.98% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2117188 4.99% 95.97% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 941206 2.22% 98.20% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 520081 1.23% 99.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 187957 0.44% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 57140 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 26686839 63.92% 63.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5690671 13.63% 77.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3035101 7.27% 84.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2408430 5.77% 90.58% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2094356 5.02% 95.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 953036 2.28% 97.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 611124 1.46% 99.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 212675 0.51% 99.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 60779 0.15% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 42393450 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 41753011 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 26875 2.51% 2.51% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 458 0.04% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 836202 77.98% 80.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 208765 19.47% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 29050 2.58% 2.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 460 0.04% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 862862 76.64% 79.26% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 233562 20.74% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22694630 60.17% 60.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 47979 0.13% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 14549 0.04% 0.04% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22728130 60.17% 60.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 48220 0.13% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9430195 25.00% 85.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5530734 14.66% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9442602 25.00% 85.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5536256 14.66% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37718806 # Type of FU issued
-system.cpu0.iq.rate 0.536936 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1072300 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028429 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 119012569 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 44575137 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 34852276 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8350 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38772197 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4358 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 316382 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37770468 # Type of FU issued
+system.cpu0.iq.rate 0.543624 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1125934 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.029810 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 118540397 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 45184408 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 34905571 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8382 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38877516 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4337 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 330330 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1375838 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2694 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13105 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 538991 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1458060 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2363 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13414 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 565962 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2149907 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5937 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2141820 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5981 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 984741 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4273547 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 99764 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 38372810 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 83727 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7758217 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5771757 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 578717 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 40350 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3282 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13105 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 151036 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 117828 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 268864 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 37337135 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9286340 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 381671 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1025952 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 2385802 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 275075 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 38676599 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 76106 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7837564 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5796369 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 579111 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 58653 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 199282 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13414 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 149919 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 118426 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 268345 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 37387044 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9294285 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 383424 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 118069 # number of nop insts executed
-system.cpu0.iew.exec_refs 14769450 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4962843 # Number of branches executed
-system.cpu0.iew.exec_stores 5483110 # Number of stores executed
-system.cpu0.iew.exec_rate 0.531503 # Inst execution rate
-system.cpu0.iew.wb_sent 37142523 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 34856145 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18592748 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35683758 # num instructions consuming a value
+system.cpu0.iew.exec_nop 120560 # number of nop insts executed
+system.cpu0.iew.exec_refs 14782259 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4971290 # Number of branches executed
+system.cpu0.iew.exec_stores 5487974 # Number of stores executed
+system.cpu0.iew.exec_rate 0.538106 # Inst execution rate
+system.cpu0.iew.wb_sent 37190474 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34909443 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18996365 # num instructions producing a value
+system.cpu0.iew.wb_consumers 36943291 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.496185 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.521042 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.502446 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.514203 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6125993 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 648805 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 232656 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 41408709 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.767702 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.726975 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6443412 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 648585 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 232277 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 40727059 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.780301 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.748318 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 29445863 71.11% 71.11% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5939620 14.34% 85.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1940870 4.69% 90.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1013361 2.45% 92.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 759448 1.83% 94.42% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 515426 1.24% 95.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 408347 0.99% 96.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 223076 0.54% 97.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1162698 2.81% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 28935599 71.05% 71.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5796697 14.23% 85.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1842943 4.53% 89.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1067095 2.62% 92.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 737891 1.81% 94.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 511993 1.26% 95.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 448684 1.10% 96.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 197374 0.48% 97.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1188783 2.92% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 41408709 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 24071577 # Number of instructions committed
-system.cpu0.commit.committedOps 31789563 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 40727059 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 24067678 # Number of instructions committed
+system.cpu0.commit.committedOps 31779383 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11615145 # Number of memory references committed
-system.cpu0.commit.loads 6382379 # Number of loads committed
-system.cpu0.commit.membars 231812 # Number of memory barriers committed
-system.cpu0.commit.branches 4351457 # Number of branches committed
+system.cpu0.commit.refs 11609911 # Number of memory references committed
+system.cpu0.commit.loads 6379504 # Number of loads committed
+system.cpu0.commit.membars 231786 # Number of memory barriers committed
+system.cpu0.commit.branches 4350837 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 28135168 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 498959 # Number of function calls committed.
+system.cpu0.commit.int_insts 28125415 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 498912 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 20133954 63.34% 63.34% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 39784 0.13% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 6382379 20.08% 83.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 5232766 16.46% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 20129006 63.34% 63.34% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 39786 0.13% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 6379504 20.07% 83.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 5230407 16.46% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 31789563 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1162698 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 31779383 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1188783 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 77292791 # The number of ROB reads
-system.cpu0.rob.rob_writes 76817595 # The number of ROB writes
-system.cpu0.timesIdled 365665 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 27854788 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5140997105 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 23990835 # Number of Instructions Simulated
-system.cpu0.committedOps 31708821 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 2.928128 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.928128 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.341515 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.341515 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 174285855 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34604955 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3294 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 912 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 79299010 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 500883 # number of misc regfile writes
-system.cpu0.icache.tags.replacements 399739 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.543627 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 3844274 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 400251 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 9.604658 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 7097393250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.543627 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999109 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999109 # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads 76892389 # The number of ROB reads
+system.cpu0.rob.rob_writes 77473478 # The number of ROB writes
+system.cpu0.timesIdled 368167 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 27725969 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5140969387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 23986936 # Number of Instructions Simulated
+system.cpu0.committedOps 31698641 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 2.896534 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.896534 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.345240 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.345240 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 174527841 # number of integer regfile reads
+system.cpu0.int_regfile_writes 34672219 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 3319 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 920 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 78617689 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 500675 # number of misc regfile writes
+system.cpu0.icache.tags.replacements 399525 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.581560 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 3866760 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 400037 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 9.666006 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6951542250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.581560 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999183 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999183 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 4676219 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 4676219 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3844274 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3844274 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3844274 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3844274 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3844274 # number of overall hits
-system.cpu0.icache.overall_hits::total 3844274 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 431668 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 431668 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 431668 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 431668 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 431668 # number of overall misses
-system.cpu0.icache.overall_misses::total 431668 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5966691765 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5966691765 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5966691765 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5966691765 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5966691765 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5966691765 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 4275942 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 4275942 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 4275942 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 4275942 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 4275942 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 4275942 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100953 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.100953 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100953 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.100953 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100953 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.100953 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13822.409271 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13822.409271 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13822.409271 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13822.409271 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 4149 # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses 4698333 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 4698333 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 3866760 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 3866760 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 3866760 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 3866760 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 3866760 # number of overall hits
+system.cpu0.icache.overall_hits::total 3866760 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 431519 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 431519 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 431519 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 431519 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 431519 # number of overall misses
+system.cpu0.icache.overall_misses::total 431519 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5963742706 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5963742706 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5963742706 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5963742706 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5963742706 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5963742706 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 4298279 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 4298279 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 4298279 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 4298279 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 4298279 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 4298279 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100393 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.100393 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100393 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.100393 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100393 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.100393 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.347901 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13820.347901 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13820.347901 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13820.347901 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 4778 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.122093 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.493827 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31390 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 31390 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 31390 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 31390 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 31390 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 31390 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400278 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 400278 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 400278 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 400278 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 400278 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 400278 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859637603 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4859637603 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859637603 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4859637603 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859637603 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4859637603 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9490000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9490000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9490000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 9490000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093612 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.093612 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.093612 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12140.656251 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31464 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 31464 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 31464 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 31464 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 31464 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 31464 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400055 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 400055 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 400055 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 400055 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 400055 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 400055 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4860147872 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4860147872 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4860147872 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4860147872 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4860147872 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4860147872 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9713500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9713500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9713500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 9713500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093073 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.093073 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.093073 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12148.699234 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 275002 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 479.873805 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 9429051 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 275514 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 34.223491 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 43985250 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.873805 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937254 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.937254 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements 275167 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 480.361699 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 9408418 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 275679 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 34.128164 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 42907250 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.361699 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938206 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.938206 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 45805638 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 45805638 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 5875796 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 5875796 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3229179 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3229179 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139566 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 139566 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137212 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 137212 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 9104975 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 9104975 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 9104975 # number of overall hits
-system.cpu0.dcache.overall_hits::total 9104975 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 392540 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 392540 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1582550 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1582550 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8878 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 8878 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7747 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7747 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1975090 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1975090 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1975090 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1975090 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5503316358 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5503316358 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80403947306 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 80403947306 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91149731 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 91149731 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49845761 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 49845761 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 85907263664 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 85907263664 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 85907263664 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 85907263664 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 6268336 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 6268336 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 4811729 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 4811729 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148444 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 148444 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144959 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 144959 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 11080065 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 11080065 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 11080065 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 11080065 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062623 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.062623 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328894 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.328894 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059807 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059807 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053443 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053443 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178256 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.178256 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178256 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.178256 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14019.759408 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14019.759408 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50806.576289 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 50806.576289 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10266.921717 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10266.921717 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6434.201756 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6434.201756 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 43495.366623 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 43495.366623 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 9513 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 7748 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 587 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.206133 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 56.970588 # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses 45804428 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 45804428 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 5867272 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 5867272 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3220606 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3220606 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139465 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 139465 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137168 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 137168 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 9087878 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 9087878 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 9087878 # number of overall hits
+system.cpu0.dcache.overall_hits::total 9087878 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 403110 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 403110 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1588797 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1588797 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8920 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 8920 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7758 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7758 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1991907 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1991907 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 1991907 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1991907 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5653636758 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 5653636758 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74855868606 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 74855868606 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91362982 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 91362982 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50049767 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 50049767 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 80509505364 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 80509505364 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 80509505364 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 80509505364 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 6270382 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 6270382 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4809403 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4809403 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148385 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 148385 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144926 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 144926 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 11079785 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 11079785 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 11079785 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 11079785 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064288 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.064288 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330352 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.330352 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060114 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060114 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053531 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053531 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179778 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.179778 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179778 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.179778 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14025.047153 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14025.047153 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47114.809888 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 47114.809888 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10242.486771 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10242.486771 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6451.374968 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6451.374968 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 40418.305355 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 40418.305355 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 9294 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 6492 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 635 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 113 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.636220 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 57.451327 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 255347 # number of writebacks
-system.cpu0.dcache.writebacks::total 255347 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203411 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 203411 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451593 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1451593 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655004 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1655004 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655004 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1655004 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189129 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 189129 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130957 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 130957 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8410 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8410 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7747 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7747 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 320086 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 320086 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 320086 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 320086 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2397985131 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2397985131 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338215866 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338215866 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69513767 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69513767 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34349239 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34349239 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7736200997 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 7736200997 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7736200997 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 7736200997 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434640527 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434640527 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206086382 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206086382 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640726909 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640726909 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030172 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030172 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027216 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027216 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056654 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056654 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053443 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053443 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.028888 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.028888 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8265.608442 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8265.608442 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4433.876210 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4433.876210 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 255545 # number of writebacks
+system.cpu0.dcache.writebacks::total 255545 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 213826 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 213826 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457949 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1457949 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 469 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1671775 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1671775 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1671775 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1671775 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189284 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 189284 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130848 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 130848 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 320132 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 320132 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 320132 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 320132 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2416725188 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2416725188 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5154000431 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5154000431 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69605516 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69605516 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34529233 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34529233 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7570725619 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 7570725619 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7570725619 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 7570725619 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434660545 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434660545 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206058380 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206058380 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640718925 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640718925 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030187 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030187 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027207 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027207 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056953 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056953 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053531 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053531 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.028893 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.028893 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12767.720399 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12767.720399 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39389.218261 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39389.218261 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8236.364454 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8236.364454 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4450.790539 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4450.790539 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9293378 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 7631598 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 415998 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 5889507 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 5046361 # Number of BTB hits
+system.cpu1.branchPred.lookups 9402679 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7728805 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 418099 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 6037829 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 5108046 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 85.683929 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 797302 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 43622 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 84.600707 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 802186 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 44176 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 42971422 # DTB read hits
-system.cpu1.dtb.read_misses 37905 # DTB read misses
-system.cpu1.dtb.write_hits 6976449 # DTB write hits
-system.cpu1.dtb.write_misses 10883 # DTB write misses
+system.cpu1.dtb.read_hits 42878527 # DTB read hits
+system.cpu1.dtb.read_misses 38253 # DTB read misses
+system.cpu1.dtb.write_hits 6985734 # DTB write hits
+system.cpu1.dtb.write_misses 10793 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2893 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 296 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2963 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 43009327 # DTB read accesses
-system.cpu1.dtb.write_accesses 6987332 # DTB write accesses
+system.cpu1.dtb.perms_faults 687 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 42916780 # DTB read accesses
+system.cpu1.dtb.write_accesses 6996527 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 49947871 # DTB hits
-system.cpu1.dtb.misses 48788 # DTB misses
-system.cpu1.dtb.accesses 49996659 # DTB accesses
+system.cpu1.dtb.hits 49864261 # DTB hits
+system.cpu1.dtb.misses 49046 # DTB misses
+system.cpu1.dtb.accesses 49913307 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 7719787 # ITB inst hits
-system.cpu1.itb.inst_misses 5634 # ITB inst misses
+system.cpu1.itb.inst_hits 7755980 # ITB inst hits
+system.cpu1.itb.inst_misses 5491 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1362 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1538 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1507 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7725421 # ITB inst accesses
-system.cpu1.itb.hits 7719787 # DTB hits
-system.cpu1.itb.misses 5634 # DTB misses
-system.cpu1.itb.accesses 7725421 # DTB accesses
-system.cpu1.numCycles 413693823 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7761471 # ITB inst accesses
+system.cpu1.itb.hits 7755980 # DTB hits
+system.cpu1.itb.misses 5491 # DTB misses
+system.cpu1.itb.accesses 7761471 # DTB accesses
+system.cpu1.numCycles 413132210 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 19372544 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 61318271 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9293378 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 5843663 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 13362487 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3346253 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 69736 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 80999073 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles 19420388 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 61788688 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9402679 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5910232 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 13466568 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3411318 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 67616 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 77041165 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 42062 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 1494344 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 7717920 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 551887 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2996 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 117635394 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.638004 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.959630 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.PendingTrapStallCycles 42813 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 1523639 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 7754163 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 555305 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2851 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 113918823 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.663934 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.994464 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 104280280 88.65% 88.65% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 814710 0.69% 89.34% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 961160 0.82% 90.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1713171 1.46% 91.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1415249 1.20% 92.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 586962 0.50% 93.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1954597 1.66% 94.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 422243 0.36% 95.34% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5487022 4.66% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 100459727 88.19% 88.19% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 820479 0.72% 88.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 969052 0.85% 89.76% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1718827 1.51% 91.27% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1427854 1.25% 92.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 590556 0.52% 93.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1988498 1.75% 94.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 426289 0.37% 95.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5517541 4.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 117635394 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022464 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.148221 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 20963679 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 81759193 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 11913295 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 809519 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2189708 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1137363 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 100954 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 71089276 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 336011 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2189708 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22156707 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 33902507 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 43325786 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11473545 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4587141 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 67137864 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 137 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 682095 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3075433 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 1010 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 70763032 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 313108743 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 286757803 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 6623 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 50416422 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 20346610 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 765987 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 705836 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8420477 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 12843204 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8115826 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1055497 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1512633 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 61850161 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1179252 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 88896986 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 93979 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 13548762 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 36246660 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 279849 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 117635394 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.755699 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.498688 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 113918823 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022759 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.149562 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 20573629 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 78271180 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 12141436 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 681674 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2250904 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1146333 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 101070 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 71648546 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 337709 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2250904 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 21753755 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 11785871 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 44839476 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11758144 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 21530673 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 67615561 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 613 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 15671923 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 18336953 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 1545811 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 1295 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 71310682 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 315205355 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 288681323 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 6622 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 50413608 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 20897074 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 766814 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 706637 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 7207016 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 12951593 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8155935 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1106689 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1533453 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 62295252 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1184366 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 88905891 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 106644 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 13983630 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 37714490 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 285025 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 113918823 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.780432 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.530885 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 86772303 73.76% 73.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 9298113 7.90% 81.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4175598 3.55% 85.22% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3594840 3.06% 88.27% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10374006 8.82% 97.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1994938 1.70% 98.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1065613 0.91% 99.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 281099 0.24% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 78884 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 83813472 73.57% 73.57% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8528665 7.49% 81.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3988574 3.50% 84.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3433815 3.01% 87.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10704573 9.40% 96.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1891022 1.66% 98.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1169449 1.03% 99.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 305487 0.27% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 83766 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 117635394 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 113918823 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 32152 0.41% 0.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 986 0.01% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7573471 95.70% 96.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 306947 3.88% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 34951 0.44% 0.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 989 0.01% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.45% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7593663 95.44% 95.90% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 326577 4.10% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 14268 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37614404 42.31% 42.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43858329 49.34% 91.74% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7347048 8.26% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 14267 0.02% 0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 37698483 42.40% 42.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 61348 0.07% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 43772925 49.24% 91.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7357130 8.28% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 88896986 # Type of FU issued
-system.cpu1.iq.rate 0.214886 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7913556 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.089019 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 303469985 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 76586992 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 54255274 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 15534 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8108 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6874 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96788024 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 8250 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 355713 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 88905891 # Type of FU issued
+system.cpu1.iq.rate 0.215200 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7956180 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.089490 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 299826864 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 77472999 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 54370047 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 15424 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8128 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6867 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 96839621 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 8183 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 371805 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2862172 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 4122 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17485 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1111950 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2971595 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3826 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 18443 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1153168 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31965671 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 675853 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31846626 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 675699 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2189708 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 26386476 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 363440 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 63133555 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 115239 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 12843204 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8115826 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 883054 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 66097 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 4286 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17485 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 204520 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 158639 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 363159 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 87164207 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43354058 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1732779 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2250904 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 9489416 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 1235015 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 63585663 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 104803 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 12951593 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8155935 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 886916 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 232294 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 885959 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 18443 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 206591 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 158855 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 365446 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 87166570 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43262018 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1739321 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 104142 # number of nop insts executed
-system.cpu1.iew.exec_refs 50636612 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 7376811 # Number of branches executed
-system.cpu1.iew.exec_stores 7282554 # Number of stores executed
-system.cpu1.iew.exec_rate 0.210697 # Inst execution rate
-system.cpu1.iew.wb_sent 86400335 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 54262148 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 30287291 # num instructions producing a value
-system.cpu1.iew.wb_consumers 53873069 # num instructions consuming a value
+system.cpu1.iew.exec_nop 106045 # number of nop insts executed
+system.cpu1.iew.exec_refs 50553896 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 7398817 # Number of branches executed
+system.cpu1.iew.exec_stores 7291878 # Number of stores executed
+system.cpu1.iew.exec_rate 0.210990 # Inst execution rate
+system.cpu1.iew.wb_sent 86399299 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 54376914 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 30829889 # num instructions producing a value
+system.cpu1.iew.wb_consumers 55266228 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.131165 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.562197 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.131621 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.557843 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 13443206 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 899403 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 316783 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 115445686 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.426296 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.378874 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 13879712 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 899341 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 318567 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 111667919 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.440684 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.404622 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 97421932 84.39% 84.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 9594899 8.31% 92.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2172227 1.88% 94.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1301741 1.13% 95.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 988993 0.86% 96.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 587152 0.51% 97.07% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1008803 0.87% 97.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 534624 0.46% 98.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1835315 1.59% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 93786179 83.99% 83.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 9487781 8.50% 92.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2098555 1.88% 94.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1338170 1.20% 95.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 960614 0.86% 96.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 571645 0.51% 96.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1030883 0.92% 97.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 527820 0.47% 98.33% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1866272 1.67% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 115445686 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38873610 # Number of instructions committed
-system.cpu1.commit.committedOps 49214014 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 111667919 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38872746 # Number of instructions committed
+system.cpu1.commit.committedOps 49210296 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16984908 # Number of memory references committed
-system.cpu1.commit.loads 9981032 # Number of loads committed
-system.cpu1.commit.membars 195536 # Number of memory barriers committed
-system.cpu1.commit.branches 6424997 # Number of branches committed
+system.cpu1.commit.refs 16982765 # Number of memory references committed
+system.cpu1.commit.loads 9979998 # Number of loads committed
+system.cpu1.commit.membars 195533 # Number of memory barriers committed
+system.cpu1.commit.branches 6424967 # Number of branches committed
system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 43926362 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 553376 # Number of function calls committed.
+system.cpu1.commit.int_insts 43922606 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 553368 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 32169137 65.37% 65.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 58263 0.12% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 32167564 65.37% 65.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 58261 0.12% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 9981032 20.28% 85.77% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 7003876 14.23% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 9979998 20.28% 85.77% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 7002767 14.23% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 49214014 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1835315 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 49210296 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1866272 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 175201017 # The number of ROB reads
-system.cpu1.rob.rob_writes 127586843 # The number of ROB writes
-system.cpu1.timesIdled 1428644 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 296058429 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4796946974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 38803971 # Number of Instructions Simulated
-system.cpu1.committedOps 49144375 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 10.661121 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.661121 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.093799 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.093799 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 391634066 # number of integer regfile reads
-system.cpu1.int_regfile_writes 56368159 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 5144 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 202762353 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 723009 # number of misc regfile writes
-system.cpu1.icache.tags.replacements 614589 # number of replacements
-system.cpu1.icache.tags.tagsinuse 498.738252 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 7056364 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 615101 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 11.471879 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 74953244500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.738252 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974098 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.974098 # Average percentage of cache occupancy
+system.cpu1.rob.rob_reads 171825162 # The number of ROB reads
+system.cpu1.rob.rob_writes 128514038 # The number of ROB writes
+system.cpu1.timesIdled 1427088 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 299213387 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 4796716848 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 38803107 # Number of Instructions Simulated
+system.cpu1.committedOps 49140657 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 10.646885 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 10.646885 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.093924 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.093924 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 391718305 # number of integer regfile reads
+system.cpu1.int_regfile_writes 56505033 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 5108 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 199117817 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 722972 # number of misc regfile writes
+system.cpu1.icache.tags.replacements 616464 # number of replacements
+system.cpu1.icache.tags.tagsinuse 498.721065 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 7090163 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 616976 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 11.491797 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 74744507500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.721065 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974065 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.974065 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 8332995 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 8332995 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 7056364 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 7056364 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 7056364 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 7056364 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 7056364 # number of overall hits
-system.cpu1.icache.overall_hits::total 7056364 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 661505 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 661505 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 661505 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 661505 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 661505 # number of overall misses
-system.cpu1.icache.overall_misses::total 661505 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8964922762 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 8964922762 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 8964922762 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 8964922762 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 8964922762 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 8964922762 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 7717869 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 7717869 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 7717869 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 7717869 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 7717869 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 7717869 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085711 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.085711 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085711 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.085711 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085711 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.085711 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13552.312926 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13552.312926 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 3582 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 212 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.896226 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses 8371129 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 8371129 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 7090163 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 7090163 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 7090163 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 7090163 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 7090163 # number of overall hits
+system.cpu1.icache.overall_hits::total 7090163 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 663949 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 663949 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 663949 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 663949 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 663949 # number of overall misses
+system.cpu1.icache.overall_misses::total 663949 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9003300184 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 9003300184 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 9003300184 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 9003300184 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 9003300184 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 9003300184 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 7754112 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 7754112 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 7754112 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 7754112 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 7754112 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 7754112 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085625 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.085625 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085625 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.085625 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085625 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.085625 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13560.228548 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13560.228548 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13560.228548 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13560.228548 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 3101 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 648 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 217 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.290323 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets 648 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46379 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 46379 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 46379 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 46379 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 46379 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 46379 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615126 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 615126 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 615126 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 615126 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 615126 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 615126 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7320744820 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 7320744820 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7320744820 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 7320744820 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7320744820 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 7320744820 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3847250 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3847250 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3847250 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 3847250 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079702 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.079702 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.079702 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11901.211817 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46932 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 46932 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 46932 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 46932 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 46932 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 46932 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 617017 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 617017 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 617017 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 617017 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 617017 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 617017 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343865656 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343865656 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343865656 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 7343865656 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343865656 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 7343865656 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4135000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4135000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4135000 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 4135000 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079573 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.079573 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.079573 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11902.209592 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 363297 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 486.117445 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 13019165 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 363645 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 35.801853 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 71011321250 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.117445 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949448 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.949448 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 60291027 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 60291027 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 8513196 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 8513196 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4271027 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4271027 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99804 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 99804 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97081 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 97081 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 12784223 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 12784223 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 12784223 # number of overall hits
-system.cpu1.dcache.overall_hits::total 12784223 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 403038 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 403038 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1566274 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1566274 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14187 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 14187 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10911 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 10911 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 1969312 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 1969312 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 1969312 # number of overall misses
-system.cpu1.dcache.overall_misses::total 1969312 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6108097691 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 6108097691 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 77891341203 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 77891341203 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131130743 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 131130743 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58206088 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 58206088 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 83999438894 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 83999438894 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 83999438894 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 83999438894 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 8916234 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 8916234 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837301 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 5837301 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113991 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 113991 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107992 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 107992 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 14753535 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 14753535 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 14753535 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 14753535 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045203 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.045203 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268322 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.268322 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124457 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124457 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101035 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101035 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133481 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.133481 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133481 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.133481 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15155.140932 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15155.140932 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 49730.341692 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9243.021287 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9243.021287 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.624507 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.624507 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 42654.205577 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 42654.205577 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 29593 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 18156 # number of cycles access was blocked
+system.cpu1.dcache.tags.replacements 363234 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 485.053035 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 13011922 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 363603 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 35.786069 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 70837218250 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.053035 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947369 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.947369 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 60324528 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 60324528 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 8516413 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 8516413 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 4259216 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 4259216 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99616 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 99616 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97058 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 97058 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 12775629 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 12775629 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 12775629 # number of overall hits
+system.cpu1.dcache.overall_hits::total 12775629 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 409488 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 409488 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1576995 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1576995 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14210 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 14210 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10944 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10944 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 1986483 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 1986483 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 1986483 # number of overall misses
+system.cpu1.dcache.overall_misses::total 1986483 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6227092173 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 6227092173 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 74233295889 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 74233295889 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131030244 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 131030244 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58441088 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 58441088 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 80460388062 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 80460388062 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 80460388062 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 80460388062 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 8925901 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 8925901 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 5836211 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 5836211 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113826 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 113826 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108002 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 108002 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 14762112 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 14762112 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 14762112 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 14762112 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045876 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.045876 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.270209 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.270209 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124840 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124840 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101331 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101331 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134566 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.134566 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134566 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.134566 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15207.019920 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15207.019920 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47072.626032 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 47072.626032 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9220.988318 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9220.988318 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5340.011696 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5340.011696 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 40503.939909 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 40503.939909 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 30714 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 17665 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.003042 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 103.748571 # average number of cycles each access was blocked
+system.cpu1.dcache.blocked::no_targets 190 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.344083 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 92.973684 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 327781 # number of writebacks
-system.cpu1.dcache.writebacks::total 327781 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171674 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 171674 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1403027 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 1403027 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1467 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1467 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574701 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1574701 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574701 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1574701 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231364 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 231364 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163247 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 163247 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10911 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10911 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 394611 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 394611 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 394611 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 394611 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2878773157 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2878773157 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7001686259 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7001686259 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89753005 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89753005 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36382912 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36382912 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9880459416 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 9880459416 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9880459416 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 9880459416 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25869959988 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25869959988 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025949 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025949 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027966 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027966 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111588 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111588 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101035 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101035 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026747 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026747 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7056.053852 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7056.053852 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3334.516726 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3334.516726 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 327552 # number of writebacks
+system.cpu1.dcache.writebacks::total 327552 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178171 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 178171 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1413840 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1413840 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1592011 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1592011 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1592011 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1592011 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231317 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 231317 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163155 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 163155 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12755 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12755 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10944 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10944 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 394472 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 394472 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 394472 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 394472 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2894401946 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2894401946 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6921941032 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6921941032 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89586755 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89586755 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36550912 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36550912 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9816342978 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 9816342978 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9816342978 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 9816342978 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231628259 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231628259 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25874415734 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25874415734 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195106043993 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195106043993 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025915 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025915 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027956 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027956 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112057 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112057 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101331 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101331 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026722 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026722 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.707436 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.707436 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42425.552585 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42425.552585 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7023.657781 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7023.657781 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3339.812865 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3339.812865 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1735350782356 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1734300149849 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1734300149849 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 42636 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 42635 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 50408 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 50404 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=256
-boot_loader=/dist/binaries/boot.arm
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-arm-ael.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
read_only=true
[system.clk_domain]
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
pio=system.membus.default
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[6]
[system.realview]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:42:01
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:27:42
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
- 0: system.cpu.isa: ISA system set to: 0x6dd8800 0x6dd8800
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
+ 0: system.cpu.isa: ISA system set to: 0x4e2f380 0x4e2f380
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2526146947500 because m5_exit instruction encountered
+Exiting @ tick 2525888859000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.526192 # Number of seconds simulated
-sim_ticks 2526192217500 # Number of ticks simulated
-final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.525889 # Number of seconds simulated
+sim_ticks 2525888859000 # Number of ticks simulated
+final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56578 # Simulator instruction rate (inst/s)
-host_op_rate 72800 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2369913329 # Simulator tick rate (ticks/s)
-host_mem_usage 467016 # Number of bytes of host memory used
-host_seconds 1065.94 # Real time elapsed on the host
-sim_insts 60309034 # Number of instructions simulated
-sim_ops 77600502 # Number of ops (including micro ops) simulated
+host_inst_rate 66506 # Simulator instruction rate (inst/s)
+host_op_rate 85575 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2785423099 # Simulator tick rate (ticks/s)
+host_mem_usage 419792 # Number of bytes of host memory used
+host_seconds 906.82 # Real time elapsed on the host
+sim_insts 60309513 # Number of instructions simulated
+sim_ops 77601128 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096864 # Number of read requests accepted
-system.physmem.writeReqs 813148 # Number of write requests accepted
-system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 943480 # Per bank write bursts
-system.physmem.perBankRdBursts::1 937980 # Per bank write bursts
-system.physmem.perBankRdBursts::2 937559 # Per bank write bursts
-system.physmem.perBankRdBursts::3 937528 # Per bank write bursts
-system.physmem.perBankRdBursts::4 943087 # Per bank write bursts
-system.physmem.perBankRdBursts::5 937982 # Per bank write bursts
-system.physmem.perBankRdBursts::6 937070 # Per bank write bursts
-system.physmem.perBankRdBursts::7 936990 # Per bank write bursts
-system.physmem.perBankRdBursts::8 943982 # Per bank write bursts
-system.physmem.perBankRdBursts::9 938303 # Per bank write bursts
-system.physmem.perBankRdBursts::10 937119 # Per bank write bursts
-system.physmem.perBankRdBursts::11 936407 # Per bank write bursts
-system.physmem.perBankRdBursts::12 943924 # Per bank write bursts
-system.physmem.perBankRdBursts::13 938214 # Per bank write bursts
-system.physmem.perBankRdBursts::14 937241 # Per bank write bursts
-system.physmem.perBankRdBursts::15 937211 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6601 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6388 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6528 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6554 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6464 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6726 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6713 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6652 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7031 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6803 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6461 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6104 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7064 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6684 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6965 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6836 # Per bank write bursts
+system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096846 # Number of read requests accepted
+system.physmem.writeReqs 813159 # Number of write requests accepted
+system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 943526 # Per bank write bursts
+system.physmem.perBankRdBursts::1 937990 # Per bank write bursts
+system.physmem.perBankRdBursts::2 937469 # Per bank write bursts
+system.physmem.perBankRdBursts::3 937431 # Per bank write bursts
+system.physmem.perBankRdBursts::4 943079 # Per bank write bursts
+system.physmem.perBankRdBursts::5 938170 # Per bank write bursts
+system.physmem.perBankRdBursts::6 937203 # Per bank write bursts
+system.physmem.perBankRdBursts::7 936910 # Per bank write bursts
+system.physmem.perBankRdBursts::8 943866 # Per bank write bursts
+system.physmem.perBankRdBursts::9 938107 # Per bank write bursts
+system.physmem.perBankRdBursts::10 936563 # Per bank write bursts
+system.physmem.perBankRdBursts::11 936045 # Per bank write bursts
+system.physmem.perBankRdBursts::12 943886 # Per bank write bursts
+system.physmem.perBankRdBursts::13 937531 # Per bank write bursts
+system.physmem.perBankRdBursts::14 937186 # Per bank write bursts
+system.physmem.perBankRdBursts::15 937024 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6617 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6376 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6529 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6558 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6459 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6705 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6711 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6649 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7036 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6794 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6454 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6111 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7073 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6679 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6963 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6824 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2526191083500 # Total gap between requests
+system.physmem.totGap 2525887732500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 38 # Read request sizes (log2)
system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 154618 # Read request sizes (log2)
+system.physmem.readPktSize::6 154600 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 59130 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59141 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads
-system.physmem.totQLat 389908010000 # Total ticks spent queuing
-system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads
+system.physmem.totQLat 389024977250 # Total ticks spent queuing
+system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 2.99 # Data bus utilization in percentage
system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing
-system.physmem.readRowHits 14044000 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91096 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing
+system.physmem.readRowHits 14042089 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91063 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes
-system.physmem.avgGap 158779.96 # Average gap between requests
+system.physmem.avgGap 158760.96 # Average gap between requests
system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states
-system.physmem.memoryStateTime::REF 84354920000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states
+system.physmem.memoryStateTime::REF 84344780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states
+system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54877773 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16149486 # Transaction distribution
-system.membus.trans_dist::ReadResp 16149486 # Transaction distribution
+system.membus.throughput 54884184 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16149487 # Transaction distribution
+system.membus.trans_dist::ReadResp 16149487 # Transaction distribution
system.membus.trans_dist::WriteReq 763349 # Transaction distribution
system.membus.trans_dist::WriteResp 763349 # Transaction distribution
-system.membus.trans_dist::Writeback 59130 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution
+system.membus.trans_dist::Writeback 59141 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131451 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131451 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131431 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131431 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 138631802 # Total data (bytes)
+system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138631350 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 48265574 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution
+system.iobus.throughput 48271369 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution
system.iobus.trans_dist::WriteReq 8174 # Transaction distribution
system.iobus.trans_dist::WriteResp 8174 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 121928118 # Total data (bytes)
+system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121928114 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 14753661 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits
+system.cpu.branchPred.lookups 14910337 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51183231 # DTB read hits
-system.cpu.dtb.read_misses 65223 # DTB read misses
-system.cpu.dtb.write_hits 11700953 # DTB write hits
-system.cpu.dtb.write_misses 15725 # DTB write misses
+system.cpu.dtb.read_hits 51097792 # DTB read hits
+system.cpu.dtb.read_misses 64987 # DTB read misses
+system.cpu.dtb.write_hits 11709971 # DTB write hits
+system.cpu.dtb.write_misses 15921 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51248454 # DTB read accesses
-system.cpu.dtb.write_accesses 11716678 # DTB write accesses
+system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51162779 # DTB read accesses
+system.cpu.dtb.write_accesses 11725892 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 62884184 # DTB hits
-system.cpu.dtb.misses 80948 # DTB misses
-system.cpu.dtb.accesses 62965132 # DTB accesses
+system.cpu.dtb.hits 62807763 # DTB hits
+system.cpu.dtb.misses 80908 # DTB misses
+system.cpu.dtb.accesses 62888671 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 11525561 # ITB inst hits
-system.cpu.itb.inst_misses 11159 # ITB inst misses
+system.cpu.itb.inst_hits 11575507 # ITB inst hits
+system.cpu.itb.inst_misses 11335 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11536720 # ITB inst accesses
-system.cpu.itb.hits 11525561 # DTB hits
-system.cpu.itb.misses 11159 # DTB misses
-system.cpu.itb.accesses 11536720 # DTB accesses
-system.cpu.numCycles 477128882 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11586842 # ITB inst accesses
+system.cpu.itb.hits 11575507 # DTB hits
+system.cpu.itb.misses 11335 # DTB misses
+system.cpu.itb.accesses 11586842 # DTB accesses
+system.cpu.numCycles 476238509 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued
-system.cpu.iq.rate 0.257622 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued
+system.cpu.iq.rate 0.258180 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 222849 # number of nop insts executed
-system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11822089 # Number of branches executed
-system.cpu.iew.exec_stores 12212847 # Number of stores executed
-system.cpu.iew.exec_rate 0.253272 # Inst execution rate
-system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47017508 # num instructions producing a value
-system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value
+system.cpu.iew.exec_nop 226309 # number of nop insts executed
+system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11843747 # Number of branches executed
+system.cpu.iew.exec_stores 12222179 # Number of stores executed
+system.cpu.iew.exec_rate 0.253798 # Inst execution rate
+system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47892202 # num instructions producing a value
+system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60459415 # Number of instructions committed
-system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60459894 # Number of instructions committed
+system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386618 # Number of memory references committed
-system.cpu.commit.loads 15654647 # Number of loads committed
-system.cpu.commit.membars 403571 # Number of memory barriers committed
-system.cpu.commit.branches 10306311 # Number of branches committed
+system.cpu.commit.refs 27386881 # Number of memory references committed
+system.cpu.commit.loads 15654781 # Number of loads committed
+system.cpu.commit.membars 403574 # Number of memory barriers committed
+system.cpu.commit.branches 10306383 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69190973 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991245 # Number of function calls committed.
+system.cpu.commit.int_insts 69191543 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991261 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction
-system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction
+system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 243007370 # The number of ROB reads
-system.cpu.rob.rob_writes 195993770 # The number of ROB writes
-system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60309034 # Number of Instructions Simulated
-system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 548643015 # number of integer regfile reads
-system.cpu.int_regfile_writes 87545924 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8332 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2902 # number of floating regfile writes
-system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution
+system.cpu.rob.rob_reads 239318561 # The number of ROB reads
+system.cpu.rob.rob_writes 197472000 # The number of ROB writes
+system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60309513 # Number of Instructions Simulated
+system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 548833940 # number of integer regfile reads
+system.cpu.int_regfile_writes 87707844 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8328 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
+system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 981488 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 980898 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits
-system.cpu.icache.overall_hits::total 10460581 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses
-system.cpu.icache.overall_misses::total 1061360 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits
+system.cpu.icache.overall_hits::total 10510158 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1061739 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1061739 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1061739 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1061739 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1061739 # number of overall misses
+system.cpu.icache.overall_misses::total 1061739 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14266290615 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14266290615 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14266290615 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14266290615 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14266290615 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14266290615 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11571897 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11571897 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11571897 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11571897 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11571897 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11571897 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091752 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.091752 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.091752 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.091752 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 21.883582 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 116 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982041 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 982041 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 982041 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 982041 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 982041 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 982041 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583712225 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11583712225 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583712225 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11583712225 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583712225 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11583712225 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8965500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8965500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8965500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 8965500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 80293 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 80293 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 80293 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 80293 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 80293 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981446 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 981446 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 981446 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 981446 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 981446 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 981446 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11573178578 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11573178578 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11573178578 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11573178578 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11573178578 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11573178578 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8964000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8964000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8964000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total 8964000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084813 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.084813 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.084813 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 64387 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1888247 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 129781 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 14.549487 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 2490875317000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 37.347999 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.789418 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 6233.237161 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.563624 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000570 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements 64369 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 51363.817213 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1888922 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 129761 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 14.556932 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 2490733870000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 33.862464 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000252 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 8170.435646 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 6222.182012 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.563619 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000517 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124753 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.095112 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.784059 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124671 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.094943 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.783750 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 65369 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3046 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6928 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54999 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 18797143 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 18797143 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53905 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10470 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 968525 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 386928 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1419828 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 607456 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 607456 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112956 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112956 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 53905 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 10470 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 968525 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 499884 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1532784 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 53905 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 10470 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 968525 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 499884 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1532784 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 12346 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 10726 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3050 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54961 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997452 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 18802940 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 18802940 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54086 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10683 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 967938 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 387449 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1420156 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607940 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607940 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112904 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112904 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 54086 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10683 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 967938 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 500353 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1533060 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 54086 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10683 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 967938 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 500353 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1533060 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10729 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23125 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133222 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133222 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 12346 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143948 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 156349 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 53 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 12346 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143948 # number of overall misses
-system.cpu.l2cache.overall_misses::total 156349 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4489500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 430000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 894766750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 805694000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1705380250 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465480 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9848665479 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 9848665479 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4489500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 894766750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10654359479 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 11554045729 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4489500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 430000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 894766750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10654359479 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 11554045729 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53958 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10472 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 980871 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 397654 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1442955 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 607456 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 607456 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133201 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133201 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143930 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156326 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 12347 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143930 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156326 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3943500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 83000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 890764250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 800380499 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1695171249 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 583475 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 583475 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9778985980 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 9778985980 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3943500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 83000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 890764250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10579366479 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 11474157229 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3943500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 83000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 890764250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10579366479 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 11474157229 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54134 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10684 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 980285 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 398178 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1443281 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607940 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607940 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 246178 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 246178 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53958 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 10472 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 980871 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 643832 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1689133 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53958 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 10472 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 980871 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 643832 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1689133 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012587 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026973 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.016028 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984828 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984828 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541161 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.541161 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012587 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.223580 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.092562 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012587 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.223580 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.092562 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84707.547170 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 215000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72474.222420 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.979862 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73739.795477 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.356385 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.356385 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73926.719904 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73926.719904 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73899.070215 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73899.070215 # average overall miss latency
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54134 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10684 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 980285 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 644283 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1689386 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54134 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10684 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 980285 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 644283 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1689386 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000887 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000094 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012595 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026945 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.016023 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985502 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985502 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.272727 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541236 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541236 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000887 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000094 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012595 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223396 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.092534 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000887 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000094 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012595 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223396 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.092534 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82156.250000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72144.184822 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74599.729611 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73304.702659 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 199.615121 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 199.615121 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73415.259495 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73415.259495 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73398.905038 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73398.905038 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 59130 # number of writebacks
-system.cpu.l2cache.writebacks::total 59130 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12332 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10659 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks 59141 # number of writebacks
+system.cpu.l2cache.writebacks::total 59141 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12336 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10663 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133222 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133222 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12332 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143881 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 156268 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12332 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143881 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3834000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 405500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 738779500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668273250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1411292250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29213921 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29213921 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133201 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133201 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12336 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143864 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156249 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12336 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143864 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156249 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3351000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 71000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 734971750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 663368999 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1401762749 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29236922 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29236922 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8190370021 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8190370021 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3834000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 405500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 738779500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8858643271 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 9601662271 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3834000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 405500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 738779500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8858643271 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 9601662271 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6434999 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17456853479 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17456853479 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6434999 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8137112520 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8137112520 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3351000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 71000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 734971750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8800481519 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 9538875269 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3351000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 71000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 734971750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8800481519 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 9538875269 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6435500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942048250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948483750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17498078150 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17498078150 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6435500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184440126400 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184446561900 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026779 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015969 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541236 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541236 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.092489 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.092489 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62212.229110 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60819.279287 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.368115 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.368115 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61088.974707 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61088.974707 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 643320 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.993245 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 21508532 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements 643771 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.993313 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 21491250 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 644283 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.993313 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits
-system.cpu.dcache.overall_hits::total 21015072 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses
-system.cpu.dcache.overall_misses::total 3699212 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses 101573451 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 101573451 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 13743815 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13743815 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7253892 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7253892 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 242816 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 242816 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 20997707 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 20997707 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 20997707 # number of overall hits
+system.cpu.dcache.overall_hits::total 20997707 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 762201 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 762201 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2968429 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2968429 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13530 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13530 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3730630 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3730630 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3730630 # number of overall misses
+system.cpu.dcache.overall_misses::total 3730630 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 10170757825 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 10170757825 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 136412874713 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 136412874713 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184826749 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 184826749 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 180503 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 180503 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 146583632538 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 146583632538 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 146583632538 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 146583632538 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14506016 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14506016 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10222321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10222321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256346 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 256346 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247609 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247609 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24728337 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24728337 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24728337 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24728337 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052544 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.052544 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290387 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.290387 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052780 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052780 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.150865 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.150865 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.150865 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.150865 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks
-system.cpu.dcache.writebacks::total 607456 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks
+system.cpu.dcache.writebacks::total 607940 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249004 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 635064 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 635064 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=256
-boot_loader=/dist/binaries/boot.arm
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-arm-ael.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
read_only=true
[system.clk_domain]
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
+socket_id=0
switched_out=false
system=system
tracer=system.cpu0.tracer
[system.cpu1]
type=TimingSimpleCPU
children=dstage2_mmu dtb isa istage2_mmu itb tracer
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
profile=0
progress_interval=0
simpoint_start_insts=
+socket_id=0
switched_out=true
system=system
tracer=system.cpu1.tracer
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=true
pio=system.membus.default
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[6]
[system.realview]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 19:05:28
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:27:42
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x5606400 0x5606400
- 0: system.cpu1.isa: ISA system set to: 0x5606400 0x5606400
- 0: system.cpu2.isa: ISA system set to: 0x5606400 0x5606400
+ 0: system.cpu0.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
+ 0: system.cpu1.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
+ 0: system.cpu2.isa: ISA system set to: 0x61c8fe0 0x61c8fe0
---------- Begin Simulation Statistics ----------
-sim_seconds 2.403852 # Number of seconds simulated
-sim_ticks 2403852457500 # Number of ticks simulated
-final_tick 2403852457500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.403860 # Number of seconds simulated
+sim_ticks 2403859810000 # Number of ticks simulated
+final_tick 2403859810000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 165592 # Simulator instruction rate (inst/s)
-host_op_rate 212680 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6597855857 # Simulator tick rate (ticks/s)
-host_mem_usage 469068 # Number of bytes of host memory used
-host_seconds 364.34 # Real time elapsed on the host
-sim_insts 60331653 # Number of instructions simulated
-sim_ops 77487544 # Number of ops (including micro ops) simulated
+host_inst_rate 189252 # Simulator instruction rate (inst/s)
+host_op_rate 243065 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7540617560 # Simulator tick rate (ticks/s)
+host_mem_usage 419508 # Number of bytes of host memory used
+host_seconds 318.79 # Real time elapsed on the host
+sim_insts 60331162 # Number of instructions simulated
+sim_ops 77486236 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 7048216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 510792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 7044824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 63936 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 680960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 186944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1348288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 124660704 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 63936 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 186944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3743808 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1298564 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 159248 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data 1558004 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6759624 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 65024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 679232 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 188416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1352768 # Number of bytes read from this memory
+system.physmem.bytes_read::total 124661152 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 510792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 65024 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 188416 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 764232 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3745216 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1298452 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data 1558108 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6761032 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 110164 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 14193 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 110111 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 999 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10640 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 9 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2921 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 21067 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 14512407 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58497 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 324641 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 39812 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data 389501 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812451 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47764609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 1016 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10613 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 12 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 2944 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 21137 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 14512414 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 58519 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 324613 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data 389527 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 812473 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47764463 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 213181 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2932050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 212488 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2930630 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 26597 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 283279 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 240 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 77769 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 560886 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51858717 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 213181 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 26597 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 77769 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 317547 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1557420 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 540201 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 66247 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data 648128 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2811996 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1557420 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47764609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 27050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 282559 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 319 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 78381 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 562748 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51858745 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 212488 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 27050 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 78381 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 317919 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1558001 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 540153 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data 648169 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2812573 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1558001 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47764463 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 213181 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3472251 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 212488 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3470783 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 26597 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 349526 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 240 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 77769 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1209014 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54670713 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 13446501 # Number of read requests accepted
-system.physmem.writeReqs 446412 # Number of write requests accepted
-system.physmem.readBursts 13446501 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 446412 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 860576000 # Total number of bytes read from DRAM
+system.physmem.bw_total::cpu1.inst 27050 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 348809 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 78381 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1210918 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54671318 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 13444811 # Number of read requests accepted
+system.physmem.writeReqs 446538 # Number of write requests accepted
+system.physmem.readBursts 13444811 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 446538 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 860467840 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue
-system.physmem.bytesWritten 2816640 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 109567680 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 2811588 # Total written bytes from the system interface side
+system.physmem.bytesWritten 2823232 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 109558976 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 2817972 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 402376 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 2365 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 835689 # Per bank write bursts
-system.physmem.perBankRdBursts::1 835334 # Per bank write bursts
-system.physmem.perBankRdBursts::2 835514 # Per bank write bursts
-system.physmem.perBankRdBursts::3 835992 # Per bank write bursts
-system.physmem.perBankRdBursts::4 837083 # Per bank write bursts
-system.physmem.perBankRdBursts::5 837766 # Per bank write bursts
-system.physmem.perBankRdBursts::6 837910 # Per bank write bursts
-system.physmem.perBankRdBursts::7 839140 # Per bank write bursts
-system.physmem.perBankRdBursts::8 840643 # Per bank write bursts
-system.physmem.perBankRdBursts::9 843328 # Per bank write bursts
-system.physmem.perBankRdBursts::10 843395 # Per bank write bursts
-system.physmem.perBankRdBursts::11 843892 # Per bank write bursts
-system.physmem.perBankRdBursts::12 845429 # Per bank write bursts
-system.physmem.perBankRdBursts::13 846004 # Per bank write bursts
-system.physmem.perBankRdBursts::14 844795 # Per bank write bursts
-system.physmem.perBankRdBursts::15 844586 # Per bank write bursts
-system.physmem.perBankWrBursts::0 2674 # Per bank write bursts
-system.physmem.perBankWrBursts::1 2534 # Per bank write bursts
-system.physmem.perBankWrBursts::2 2538 # Per bank write bursts
-system.physmem.perBankWrBursts::3 3024 # Per bank write bursts
-system.physmem.perBankWrBursts::4 3410 # Per bank write bursts
-system.physmem.perBankWrBursts::5 3131 # Per bank write bursts
-system.physmem.perBankWrBursts::6 2493 # Per bank write bursts
-system.physmem.perBankWrBursts::7 2267 # Per bank write bursts
-system.physmem.perBankWrBursts::8 2164 # Per bank write bursts
+system.physmem.mergedWrBursts 402393 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 2368 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 835670 # Per bank write bursts
+system.physmem.perBankRdBursts::1 835346 # Per bank write bursts
+system.physmem.perBankRdBursts::2 835517 # Per bank write bursts
+system.physmem.perBankRdBursts::3 836010 # Per bank write bursts
+system.physmem.perBankRdBursts::4 837094 # Per bank write bursts
+system.physmem.perBankRdBursts::5 837780 # Per bank write bursts
+system.physmem.perBankRdBursts::6 837922 # Per bank write bursts
+system.physmem.perBankRdBursts::7 839142 # Per bank write bursts
+system.physmem.perBankRdBursts::8 840618 # Per bank write bursts
+system.physmem.perBankRdBursts::9 843327 # Per bank write bursts
+system.physmem.perBankRdBursts::10 843373 # Per bank write bursts
+system.physmem.perBankRdBursts::11 843894 # Per bank write bursts
+system.physmem.perBankRdBursts::12 845193 # Per bank write bursts
+system.physmem.perBankRdBursts::13 844981 # Per bank write bursts
+system.physmem.perBankRdBursts::14 844356 # Per bank write bursts
+system.physmem.perBankRdBursts::15 844587 # Per bank write bursts
+system.physmem.perBankWrBursts::0 2683 # Per bank write bursts
+system.physmem.perBankWrBursts::1 2536 # Per bank write bursts
+system.physmem.perBankWrBursts::2 2524 # Per bank write bursts
+system.physmem.perBankWrBursts::3 3040 # Per bank write bursts
+system.physmem.perBankWrBursts::4 3434 # Per bank write bursts
+system.physmem.perBankWrBursts::5 3138 # Per bank write bursts
+system.physmem.perBankWrBursts::6 2510 # Per bank write bursts
+system.physmem.perBankWrBursts::7 2271 # Per bank write bursts
+system.physmem.perBankWrBursts::8 2160 # Per bank write bursts
system.physmem.perBankWrBursts::9 2378 # Per bank write bursts
-system.physmem.perBankWrBursts::10 2328 # Per bank write bursts
+system.physmem.perBankWrBursts::10 2319 # Per bank write bursts
system.physmem.perBankWrBursts::11 2803 # Per bank write bursts
-system.physmem.perBankWrBursts::12 3718 # Per bank write bursts
-system.physmem.perBankWrBursts::13 3446 # Per bank write bursts
-system.physmem.perBankWrBursts::14 2595 # Per bank write bursts
-system.physmem.perBankWrBursts::15 2507 # Per bank write bursts
+system.physmem.perBankWrBursts::12 3771 # Per bank write bursts
+system.physmem.perBankWrBursts::13 3447 # Per bank write bursts
+system.physmem.perBankWrBursts::14 2601 # Per bank write bursts
+system.physmem.perBankWrBursts::15 2498 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2402816386500 # Total gap between requests
+system.physmem.totGap 2402823771000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 13410864 # Read request sizes (log2)
+system.physmem.readPktSize::3 13409088 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 35637 # Read request sizes (log2)
+system.physmem.readPktSize::6 35723 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 429313 # Write request sizes (log2)
+system.physmem.writePktSize::2 429341 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 17099 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 877452 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 853858 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 853065 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 937219 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 861122 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 912169 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2402802 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2330624 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3052022 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 86874 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 80661 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 76244 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 73288 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 16615 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 16291 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 16173 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 21 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 17197 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 877930 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 852855 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 852810 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 941410 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 861042 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 915654 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2398641 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2321801 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3038639 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 92226 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 84687 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 80541 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 77647 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 16577 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 16214 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 16108 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1916 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2309 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 2421 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 2538 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 2461 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 2402 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 2681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2411 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 2396 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 2417 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 2368 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 2356 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 2413 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 2343 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 2346 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 2344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 2313 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2300 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 2423 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 2579 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 2455 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 2431 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 2665 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2414 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 2438 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 2433 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 2373 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 2390 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 2400 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 2348 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 2337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 2336 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 2315 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 866032 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 996.952353 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 964.296727 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 145.584191 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 8288 0.96% 0.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8846 1.02% 1.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6189 0.71% 2.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 800 0.09% 2.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 916 0.11% 2.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 687 0.08% 2.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7828 0.90% 3.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 865990 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 996.883419 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 964.040735 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 145.863432 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 8417 0.97% 0.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 8847 1.02% 1.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6111 0.71% 2.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 842 0.10% 2.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 894 0.10% 2.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 743 0.09% 2.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 7672 0.89% 3.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 832235 96.10% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 866032 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 2414 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 5570.207125 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 258157.496677 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-524287 2413 99.96% 99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::1024-1151 832221 96.10% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 865990 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 2416 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 5564.893626 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 258050.737776 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 2415 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 2414 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 2414 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18.231152 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.108696 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.979905 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2 1 0.04% 0.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3 2 0.08% 0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4 1 0.04% 0.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5 1 0.04% 0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7 2 0.08% 0.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9 1 0.04% 0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12 1 0.04% 0.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14 1 0.04% 0.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15 7 0.29% 0.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 485 20.09% 20.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 15 0.62% 21.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 872 36.12% 57.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 845 35.00% 92.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 52 2.15% 94.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 24 0.99% 95.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 26 1.08% 96.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 34 1.41% 98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 13 0.54% 98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 5 0.21% 98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 6 0.25% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 1 0.04% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 6 0.25% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 7 0.29% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 2 0.08% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 4 0.17% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 2414 # Writes before turning the bus around for reads
-system.physmem.totQLat 345783645500 # Total ticks spent queuing
-system.physmem.totMemAccLat 597905520500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 67232500000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25715.51 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 2416 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 2416 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 18.258692 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.106432 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.116221 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1 1 0.04% 0.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2 2 0.08% 0.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3 2 0.08% 0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4 1 0.04% 0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5 1 0.04% 0.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7 1 0.04% 0.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9 1 0.04% 0.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11 2 0.08% 0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15 5 0.21% 0.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 486 20.12% 20.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 13 0.54% 21.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 855 35.39% 56.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 862 35.68% 92.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 56 2.32% 94.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 20 0.83% 95.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 20 0.83% 96.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 33 1.37% 97.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 16 0.66% 98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 6 0.25% 98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 6 0.25% 98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 4 0.17% 99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 7 0.29% 99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 6 0.25% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 4 0.17% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 4 0.17% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 2 0.08% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 2416 # Writes before turning the bus around for reads
+system.physmem.totQLat 346456254750 # Total ticks spent queuing
+system.physmem.totMemAccLat 598546442250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 67224050000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25768.77 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44465.51 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 358.00 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44518.77 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 357.95 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s
system.physmem.busUtil 2.81 # Data bus utilization in percentage
system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 7.51 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 4.43 # Average write queue length when enqueuing
-system.physmem.readRowHits 12586631 # Number of row buffer hits during reads
-system.physmem.writeRowHits 37847 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 8.26 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 5.37 # Average write queue length when enqueuing
+system.physmem.readRowHits 12585053 # Number of row buffer hits during reads
+system.physmem.writeRowHits 37880 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.95 # Row buffer hit rate for writes
-system.physmem.avgGap 172952.67 # Average gap between requests
+system.physmem.writeRowHitRate 85.81 # Row buffer hit rate for writes
+system.physmem.avgGap 172972.67 # Average gap between requests
system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2167477603250 # Time in different power states
-system.physmem.memoryStateTime::REF 80269800000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2167576169750 # Time in different power states
+system.physmem.memoryStateTime::REF 80270060000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 156101819250 # Time in different power states
+system.physmem.memoryStateTime::ACT 156010779000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 55667977 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 13781620 # Transaction distribution
-system.membus.trans_dist::ReadResp 13781620 # Transaction distribution
-system.membus.trans_dist::WriteReq 432153 # Transaction distribution
-system.membus.trans_dist::WriteResp 432153 # Transaction distribution
-system.membus.trans_dist::Writeback 17099 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2365 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2365 # Transaction distribution
-system.membus.trans_dist::ReadExReq 28041 # Transaction distribution
-system.membus.trans_dist::ReadExResp 28041 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731786 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951729 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 1683729 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26821728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 26821728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 28505457 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735662 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5092356 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 5828446 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107286912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 107286912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 113115358 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 133817603 # Total data (bytes)
+system.membus.throughput 55668579 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 13780402 # Transaction distribution
+system.membus.trans_dist::ReadResp 13780402 # Transaction distribution
+system.membus.trans_dist::WriteReq 432242 # Transaction distribution
+system.membus.trans_dist::WriteResp 432242 # Transaction distribution
+system.membus.trans_dist::Writeback 17197 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2368 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2368 # Transaction distribution
+system.membus.trans_dist::ReadExReq 28083 # Transaction distribution
+system.membus.trans_dist::ReadExResp 28083 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 732930 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 952061 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 1685211 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818176 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 26818176 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 28503387 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 736825 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5104244 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 5841509 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 107272704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 113114213 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 133819459 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 416874000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 417666500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 199500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 14576510500 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 14570118500 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1596663785 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1595700088 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer2.occupancy 33229062000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 33207877250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 63248 # number of replacements
-system.l2c.tags.tagsinuse 50398.234461 # Cycle average of tags in use
-system.l2c.tags.total_refs 1749256 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 128641 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 13.597966 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2375562300000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 36845.662788 # Average occupied blocks per requestor
+system.l2c.tags.replacements 63255 # number of replacements
+system.l2c.tags.tagsinuse 50395.732810 # Cycle average of tags in use
+system.l2c.tags.total_refs 1749595 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 128654 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 13.599227 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 2375537274500 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 36859.250431 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 5231.089770 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3832.891832 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 496.025776 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 690.296020 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.797358 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1694.464698 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 1598.012760 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.562220 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst 5225.740605 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 3831.207928 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 514.351835 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 694.414886 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.820575 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 1674.526375 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 1584.426715 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.562428 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.079820 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.058485 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.079738 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.058460 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.007569 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.010533 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000134 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.025855 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.024384 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.769016 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 65389 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 6488 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 55889 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.997757 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 17683113 # Number of tag accesses
-system.l2c.tags.data_accesses 17683113 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 8690 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 468117 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 177120 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 2623 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 129717 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 64377 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 18993 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 4195 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 281260 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 131724 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1291137 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 597632 # number of Writeback hits
-system.l2c.Writeback_hits::total 597632 # number of Writeback hits
+system.l2c.tags.occ_percent::cpu1.inst 0.007848 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.010596 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000165 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.025551 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.024176 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.768978 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 65393 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 2636 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 55911 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.997818 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 17684075 # Number of tag accesses
+system.l2c.tags.data_accesses 17684075 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 8753 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 3188 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 465928 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 176871 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 2616 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 1178 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 130375 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 64441 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker 18901 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker 4190 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 282805 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 131860 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1291106 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 597736 # number of Writeback hits
+system.l2c.Writeback_hits::total 597736 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 62001 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 18409 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 33201 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 113611 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 8690 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 3137 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 468117 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 239121 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 2623 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 1184 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 129717 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 82786 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker 18993 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker 4195 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 281260 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 164925 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1404748 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 8690 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 3137 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 468117 # number of overall hits
-system.l2c.overall_hits::cpu0.data 239121 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 2623 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 1184 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 129717 # number of overall hits
-system.l2c.overall_hits::cpu1.data 82786 # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker 18993 # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker 4195 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 281260 # number of overall hits
-system.l2c.overall_hits::cpu2.data 164925 # number of overall hits
-system.l2c.overall_hits::total 1404748 # number of overall hits
+system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 61703 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 18647 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 33305 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 113655 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 8753 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 3188 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 465928 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 238574 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 2616 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 1178 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 130375 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 83088 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker 18901 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker 4190 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 282805 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 165165 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1404761 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 8753 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 3188 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 465928 # number of overall hits
+system.l2c.overall_hits::cpu0.data 238574 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 2616 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 1178 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 130375 # number of overall hits
+system.l2c.overall_hits::cpu1.data 83088 # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker 18901 # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker 4190 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 282805 # number of overall hits
+system.l2c.overall_hits::cpu2.data 165165 # number of overall hits
+system.l2c.overall_hits::total 1404761 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 7593 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6464 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 7567 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6458 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 999 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 1119 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker 9 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 2922 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 2560 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 21670 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 1416 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 469 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 1019 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 104452 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 9794 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 19124 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 133370 # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.inst 1016 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 1126 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker 12 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 2945 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 2552 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 21680 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 1411 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 481 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 1014 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 104401 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 9756 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 19200 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 133357 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 7593 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 110916 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 7567 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 110859 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 999 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 10913 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker 9 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 2922 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 21684 # number of demand (read+write) misses
-system.l2c.demand_misses::total 155040 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 1016 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 10882 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker 12 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 2945 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 21752 # number of demand (read+write) misses
+system.l2c.demand_misses::total 155037 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 7593 # number of overall misses
-system.l2c.overall_misses::cpu0.data 110916 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 7567 # number of overall misses
+system.l2c.overall_misses::cpu0.data 110859 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 999 # number of overall misses
-system.l2c.overall_misses::cpu1.data 10913 # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker 9 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 2922 # number of overall misses
-system.l2c.overall_misses::cpu2.data 21684 # number of overall misses
-system.l2c.overall_misses::total 155040 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 1016 # number of overall misses
+system.l2c.overall_misses::cpu1.data 10882 # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker 12 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 2945 # number of overall misses
+system.l2c.overall_misses::cpu2.data 21752 # number of overall misses
+system.l2c.overall_misses::total 155037 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 70879750 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 85596750 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 673000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 220789250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 196778249 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 574791499 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 71823500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 85564250 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 881750 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 224313750 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 195090250 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 577748000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 139494 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 233490 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 710505727 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 1408534646 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 2119040373 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 706910231 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 1411869896 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 2118780127 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 70879750 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 796102477 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker 673000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 220789250 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 1605312895 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 2693831872 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 71823500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 792474481 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker 881750 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 224313750 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 1606960146 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 2696528127 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 70879750 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 796102477 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker 673000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 220789250 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 1605312895 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 2693831872 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 8691 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 3139 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 475710 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 183584 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 2624 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 1184 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 130716 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 65496 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker 19002 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker 4195 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 284182 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 134284 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1312807 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 597632 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 597632 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 1430 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 473 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 1031 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data 4 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 166453 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 28203 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 52325 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246981 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 8691 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 3139 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 475710 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 350037 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 2624 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 1184 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 130716 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 93699 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker 19002 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker 4195 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 284182 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 186609 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1559788 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 8691 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 3139 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 475710 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 350037 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 2624 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 1184 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 130716 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 93699 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker 19002 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker 4195 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 284182 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 186609 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1559788 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000637 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015961 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.035210 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.007643 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.017085 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000474 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.010282 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.019064 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.016507 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990210 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991543 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.988361 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.989775 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.627516 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.347268 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.365485 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.540001 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000637 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015961 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.316869 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.007643 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.116469 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000474 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.010282 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.116200 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.099398 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000637 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015961 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.316869 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.007643 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.116469 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000474 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.010282 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.116200 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.099398 # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu1.inst 71823500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 792474481 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker 881750 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 224313750 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 1606960146 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 2696528127 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 8754 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 3190 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 473495 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 183329 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 2617 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 1178 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 131391 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 65567 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker 18913 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker 4190 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 285750 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 134412 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1312786 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 597736 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 597736 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 1425 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 485 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 1026 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 166104 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 28403 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 52505 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 247012 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 8754 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 3190 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 473495 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 349433 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 2617 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 1178 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 131391 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 93970 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker 18913 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker 4190 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 285750 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 186917 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1559798 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 8754 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 3190 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 473495 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 349433 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 2617 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 1178 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 131391 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 93970 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker 18913 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker 4190 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 285750 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 186917 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1559798 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000627 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015981 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.035226 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.007733 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.017173 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000634 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.010306 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.018986 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990175 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991753 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.988304 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.989782 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.628528 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.343485 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.365679 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.539881 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000627 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015981 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.317254 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.007733 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.115803 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000634 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.010306 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.116373 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.099396 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000627 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015981 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.317254 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000382 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.007733 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.115803 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000634 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.010306 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.116373 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.099396 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70950.700701 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 76493.967828 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 74777.777778 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75561.002738 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 76866.503516 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 26524.757683 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 200.417910 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 136.893032 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 80.402893 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72544.999694 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73652.721502 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 15888.433478 # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70692.421260 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75989.564831 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 73479.166667 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76167.657046 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 76446.022727 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 26648.892989 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 195.417879 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 137.568047 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 80.347557 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72459.023268 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73534.890417 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 15888.030827 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 70950.700701 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 72949.920004 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 74777.777778 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 75561.002738 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 74032.138674 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 17375.076574 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 70692.421260 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 72824.341206 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 73479.166667 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 76167.657046 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 73876.431868 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 17392.803827 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 70950.700701 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 72949.920004 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 74777.777778 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 75561.002738 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 74032.138674 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 17375.076574 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 70692.421260 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 72824.341206 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 73479.166667 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 76167.657046 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 73876.431868 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 17392.803827 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 58497 # number of writebacks
-system.l2c.writebacks::total 58497 # number of writebacks
+system.l2c.writebacks::writebacks 58519 # number of writebacks
+system.l2c.writebacks::total 58519 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.data 13 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.data 11 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data 13 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data 11 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data 13 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data 11 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 999 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 1119 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 9 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 2921 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 2547 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 7596 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 469 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 1019 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 1488 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 9794 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 19124 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 28918 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 1016 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 1126 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 12 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst 2944 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data 2541 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 7640 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 481 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 1014 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 1495 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 9756 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 19200 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 28956 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 999 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 10913 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 9 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 2921 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 21671 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 36514 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 1016 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 10882 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker 12 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 2944 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 21741 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 36596 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 999 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 10913 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 9 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 2921 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 21671 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 36514 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 1016 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 10882 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker 12 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 2944 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 21741 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 36596 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 58206250 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 71681250 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 562500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 184124500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 164011999 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 478648999 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4690469 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10191019 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 14881488 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 586577273 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1169906854 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 1756484127 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 58931500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 71567750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 736250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 187351500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 162682500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 481332000 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4810481 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10143513 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 14953994 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 583452269 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1173703604 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 1757155873 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 58206250 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 658258523 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 562500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 184124500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 1333918853 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 2235133126 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 58931500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 655020019 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 736250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 187351500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 1336386104 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 2238487873 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 58206250 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 658258523 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 562500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 184124500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 1333918853 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 2235133126 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25072597000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26177785500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 51250382500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 933416100 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8516272500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 9449688600 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26006013100 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34694058000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 60700071100 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017085 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018967 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.005786 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991543 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988361 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.507157 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347268 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365485 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.117086 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.116469 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.116131 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.023410 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.116469 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.116131 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.023410 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu1.inst 58931500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 655020019 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 736250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 187351500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 1336386104 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 2238487873 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25035167000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26291907500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 51327074500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 936937545 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8534582000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 9471519545 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25972104545 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34826489500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 60798594045 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017173 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018905 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.005820 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991753 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988304 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.509196 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.343485 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365679 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.117225 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.115803 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.116314 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.023462 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.115803 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.116314 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.023462 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64058.310992 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64394.188850 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 63013.296340 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63559.280639 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64023.022432 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 63001.570681 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59891.492036 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61174.798891 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60740.166229 # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.464497 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.671572 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59804.455617 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61130.396042 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60683.653578 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 58808825 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 1019736 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1019735 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 432153 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 432153 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 265208 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1508 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 80528 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 80528 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830481 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419466 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15414 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52803 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 3318164 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26553408 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37366366 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21516 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86504 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 64027794 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 141267007 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 100732 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 2176624753 # Layer occupancy (ticks)
+system.toL2Bus.throughput 58812389 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 1022771 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1022770 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 432242 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 432242 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 265826 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1511 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 80908 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 80908 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 834992 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2422460 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15408 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52756 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 3325616 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26696960 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37444261 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21472 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86120 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 64248813 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 141273763 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 102976 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 2181217728 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1870991697 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1881226404 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1845922726 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1849082178 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 10050964 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 10054967 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 31304739 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 31351984 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48758959 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 13773981 # Transaction distribution
-system.iobus.trans_dist::ReadResp 13773981 # Transaction distribution
-system.iobus.trans_dist::WriteReq 2776 # Transaction distribution
-system.iobus.trans_dist::WriteResp 2776 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11410 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes)
+system.iobus.throughput 48758810 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 13772718 # Transaction distribution
+system.iobus.trans_dist::ReadResp 13772718 # Transaction distribution
+system.iobus.trans_dist::WriteReq 2835 # Transaction distribution
+system.iobus.trans_dist::WriteResp 2835 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11646 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3040 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716788 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 717678 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 731786 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26821728 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total 26821728 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 27553514 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15374 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 732930 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818176 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 26818176 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 27551106 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15610 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6080 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713112 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 714003 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 735662 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107286912 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107286912 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 108022574 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 736825 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272704 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272704 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 108009529 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 117209343 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 7968000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 8145000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 1520000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 358898000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 359342000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 13410864000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 13409088000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 729010000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 730095000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 33767373000 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 33780437750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7995700 # DTB read hits
-system.cpu0.dtb.read_misses 6195 # DTB read misses
-system.cpu0.dtb.write_hits 6594454 # DTB write hits
-system.cpu0.dtb.write_misses 1984 # DTB write misses
+system.cpu0.dtb.read_hits 7992228 # DTB read hits
+system.cpu0.dtb.read_misses 6211 # DTB read misses
+system.cpu0.dtb.write_hits 6585208 # DTB write hits
+system.cpu0.dtb.write_misses 1983 # DTB write misses
system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 5702 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8001895 # DTB read accesses
-system.cpu0.dtb.write_accesses 6596438 # DTB write accesses
+system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7998439 # DTB read accesses
+system.cpu0.dtb.write_accesses 6587191 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14590154 # DTB hits
-system.cpu0.dtb.misses 8179 # DTB misses
-system.cpu0.dtb.accesses 14598333 # DTB accesses
+system.cpu0.dtb.hits 14577436 # DTB hits
+system.cpu0.dtb.misses 8194 # DTB misses
+system.cpu0.dtb.accesses 14585630 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 32327896 # ITB inst hits
-system.cpu0.itb.inst_misses 3449 # ITB inst misses
+system.cpu0.itb.inst_hits 32348466 # ITB inst hits
+system.cpu0.itb.inst_misses 3468 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2626 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2648 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 32331345 # ITB inst accesses
-system.cpu0.itb.hits 32327896 # DTB hits
-system.cpu0.itb.misses 3449 # DTB misses
-system.cpu0.itb.accesses 32331345 # DTB accesses
-system.cpu0.numCycles 113683212 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 32351934 # ITB inst accesses
+system.cpu0.itb.hits 32348466 # DTB hits
+system.cpu0.itb.misses 3468 # DTB misses
+system.cpu0.itb.accesses 32351934 # DTB accesses
+system.cpu0.numCycles 113676157 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 31852389 # Number of instructions committed
-system.cpu0.committedOps 42022034 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 37405417 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses
-system.cpu0.num_func_calls 1199046 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4246321 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 37405417 # number of integer instructions
-system.cpu0.num_fp_insts 4937 # number of float instructions
-system.cpu0.num_int_register_reads 193890675 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 39514617 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written
-system.cpu0.num_mem_refs 15257672 # number of memory refs
-system.cpu0.num_load_insts 8364380 # Number of load instructions
-system.cpu0.num_store_insts 6893292 # Number of store instructions
-system.cpu0.num_idle_cycles 110986808.765580 # Number of idle cycles
-system.cpu0.num_busy_cycles 2696403.234420 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.023719 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.976281 # Percentage of idle cycles
-system.cpu0.Branches 5614656 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 14792 0.04% 0.04% # Class of executed instruction
-system.cpu0.op_class::IntAlu 26773719 63.60% 63.63% # Class of executed instruction
-system.cpu0.op_class::IntMult 49650 0.12% 63.75% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.75% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 1431 0.00% 63.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 63.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.76% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.76% # Class of executed instruction
-system.cpu0.op_class::MemRead 8364380 19.87% 83.63% # Class of executed instruction
-system.cpu0.op_class::MemWrite 6893292 16.37% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 31863567 # Number of instructions committed
+system.cpu0.committedOps 42010857 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 37388293 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses
+system.cpu0.num_func_calls 1197302 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4248978 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 37388293 # number of integer instructions
+system.cpu0.num_fp_insts 5018 # number of float instructions
+system.cpu0.num_int_register_reads 193803982 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 39520708 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written
+system.cpu0.num_mem_refs 15242780 # number of memory refs
+system.cpu0.num_load_insts 8359522 # Number of load instructions
+system.cpu0.num_store_insts 6883258 # Number of store instructions
+system.cpu0.num_idle_cycles 110978931.176812 # Number of idle cycles
+system.cpu0.num_busy_cycles 2697225.823188 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.023727 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.976273 # Percentage of idle cycles
+system.cpu0.Branches 5616963 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 14526 0.03% 0.03% # Class of executed instruction
+system.cpu0.op_class::IntAlu 26777156 63.63% 63.66% # Class of executed instruction
+system.cpu0.op_class::IntMult 49712 0.12% 63.78% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 1435 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.78% # Class of executed instruction
+system.cpu0.op_class::MemRead 8359522 19.86% 83.64% # Class of executed instruction
+system.cpu0.op_class::MemWrite 6883258 16.36% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 42097264 # Class of executed instruction
+system.cpu0.op_class::total 42085609 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 891512 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.602542 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 43658005 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 892024 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 48.942635 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 8184230000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.829489 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.587272 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.185782 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966464 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014819 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017941 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 891568 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.602608 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 43675041 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 892080 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 48.958660 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 8174940250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.966915 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.710732 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.924961 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964779 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015060 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019385 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 45465874 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 45465874 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 31854091 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 8059411 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 3744503 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 43658005 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 31854091 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 8059411 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 3744503 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 43658005 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 31854091 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 8059411 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 3744503 # number of overall hits
-system.cpu0.icache.overall_hits::total 43658005 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 476451 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 130983 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 308401 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 915835 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 476451 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 130983 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 308401 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 915835 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 476451 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 130983 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 308401 # number of overall misses
-system.cpu0.icache.overall_misses::total 915835 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1767573750 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4161599099 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5929172849 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 1767573750 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 4161599099 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5929172849 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 1767573750 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 4161599099 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5929172849 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 32330542 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 8190394 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 4052904 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 44573840 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 32330542 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 8190394 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 4052904 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 44573840 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 32330542 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 8190394 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 4052904 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 44573840 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014737 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015992 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076094 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.020546 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014737 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015992 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076094 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.020546 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014737 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015992 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076094 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.020546 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13494.680607 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13494.116747 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 6474.062303 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13494.680607 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13494.116747 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 6474.062303 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13494.680607 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13494.116747 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 6474.062303 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2820 # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses 45483451 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 45483451 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 31876897 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 8043794 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 3754350 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 43675041 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 31876897 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 8043794 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 3754350 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 43675041 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 31876897 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 8043794 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 3754350 # number of overall hits
+system.cpu0.icache.overall_hits::total 43675041 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 474237 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 131660 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 310425 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 916322 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 474237 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 131660 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 310425 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 916322 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 474237 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 131660 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 310425 # number of overall misses
+system.cpu0.icache.overall_misses::total 916322 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1777118000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4193284063 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5970402063 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 1777118000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 4193284063 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5970402063 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 1777118000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 4193284063 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5970402063 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 32351134 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 8175454 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 4064775 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 44591363 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 32351134 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 8175454 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 4064775 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 44591363 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 32351134 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 8175454 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 4064775 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 44591363 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014659 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016104 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076370 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.020549 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014659 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016104 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076370 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.020549 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014659 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016104 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076370 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.020549 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13497.782166 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.203473 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 6515.615758 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13497.782166 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.203473 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 6515.615758 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13497.782166 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.203473 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 6515.615758 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 3442 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 202 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 244 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.960396 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.106557 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23800 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 23800 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 23800 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 23800 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 23800 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 23800 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 130983 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 284601 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 415584 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 130983 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 284601 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 415584 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 130983 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 284601 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 415584 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1505220250 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3386666286 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4891886536 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1505220250 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3386666286 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4891886536 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1505220250 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3386666286 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4891886536 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015992 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070222 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009323 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015992 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070222 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.009323 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015992 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070222 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.009323 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11491.722208 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11899.699179 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.113748 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11491.722208 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11899.699179 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.113748 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11491.722208 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11899.699179 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.113748 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24233 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 24233 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst 24233 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 24233 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst 24233 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 24233 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 131660 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 286192 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 417852 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 131660 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 286192 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 417852 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 131660 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 286192 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 417852 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1513402000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3408270326 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4921672326 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1513402000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3408270326 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4921672326 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1513402000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3408270326 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4921672326 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016104 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070408 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009371 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016104 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070408 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.009371 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016104 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070408 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.009371 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11778.506088 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11778.506088 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11778.506088 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 629833 # number of replacements
+system.cpu0.dcache.tags.replacements 629808 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 23224733 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 630345 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 36.844479 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs 23216736 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 630320 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 36.833253 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.042290 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.061376 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.893452 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970786 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015745 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013464 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.011918 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.087644 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.897556 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970726 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015796 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013472 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 98835293 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 98835293 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 6864775 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 1819119 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 4641948 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 13325842 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 5963046 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 1314313 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 2132881 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 9410240 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131790 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33007 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73476 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 238273 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138256 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34751 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74378 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 247385 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 12827821 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 3133432 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 6774829 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 22736082 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 12827821 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 3133432 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 6774829 # number of overall hits
-system.cpu0.dcache.overall_hits::total 22736082 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 177118 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 63752 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 270474 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 511344 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 167883 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 28676 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 609650 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 806209 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6466 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1744 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3730 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 11940 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 345001 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 92428 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 880124 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1317553 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 345001 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 92428 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 880124 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1317553 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907525000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3898427279 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 4805952279 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 994225242 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22938892543 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 23933117785 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22894750 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49919498 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 72814248 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 52000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 52000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 1901750242 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 26837319822 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 28739070064 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 1901750242 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 26837319822 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 28739070064 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 7041893 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 1882871 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 4912422 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 13837186 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 6130929 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 1342989 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 2742531 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 10216449 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138256 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34751 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77206 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 250213 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138256 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34751 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74382 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.tags.tag_accesses 98838984 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 98838984 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 6862400 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 1819912 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 4640111 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 13322423 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 5954558 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 1318615 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 2132591 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 9405764 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131484 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33204 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73477 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 238165 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137939 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34940 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74507 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 247386 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 12816958 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 3138527 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 6772702 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 22728187 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 12816958 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 3138527 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 6772702 # number of overall hits
+system.cpu0.dcache.overall_hits::total 22728187 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 176874 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 63831 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 275088 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 515793 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 167529 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 28888 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 614266 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 810683 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6455 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1736 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3758 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 11949 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 344403 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 92719 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 889354 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1326476 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 344403 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 92719 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 889354 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1326476 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 908477250 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3946035800 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 4854513050 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 993858250 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22101160686 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 23095018936 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22777000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50452248 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 73229248 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 1902335500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 26047196486 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 27949531986 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 1902335500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 26047196486 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 27949531986 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 7039274 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 1883743 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 4915199 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 13838216 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 6122087 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 1347503 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 2746857 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 10216447 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137939 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34940 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77235 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 250114 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137939 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34940 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74510 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247389 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 13172822 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 3225860 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 7654953 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 24053635 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 13172822 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 3225860 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 7654953 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 24053635 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025152 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033859 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055059 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027383 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021352 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222295 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.078913 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046768 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050186 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048312 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047719 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028652 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114974 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.054776 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028652 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114974 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.054776 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14235.239679 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.316175 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 9398.667588 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34670.987655 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37626.330752 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 29685.996789 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.723624 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13383.243432 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6098.345729 # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_accesses::cpu0.data 13161361 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 3231246 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 7662056 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 24054663 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 13161361 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 3231246 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 7662056 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 24054663 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033885 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055967 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.037273 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027365 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021438 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.223625 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.079351 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046796 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049685 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048657 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047774 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000040 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026168 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028695 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116073 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.055144 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026168 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028695 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116073 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.055144 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14232.539832 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14344.630809 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 9411.746670 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34403.844157 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35979.788375 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 28488.347401 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13120.391705 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13425.292177 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6128.483388 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 21812.458447 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 21812.458447 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 8069 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 3116 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 905 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 48 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.916022 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 64.916667 # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20517.213300 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29287.771220 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 21070.514646 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20517.213300 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 29287.771220 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21070.514646 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 7838 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 2641 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 847 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 52 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.253837 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 50.788462 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 597632 # number of writebacks
-system.cpu0.dcache.writebacks::total 597632 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139480 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 139480 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556328 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 556328 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 406 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 406 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 695808 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 695808 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 695808 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 695808 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63752 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 130994 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 194746 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28676 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53322 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 81998 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1744 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3324 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5068 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 92428 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 184316 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 276744 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 92428 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 184316 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 276744 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779830000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1694363864 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2474193864 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 934250758 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1848694495 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2782945253 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19406250 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38393502 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57799752 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714080758 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543058359 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 5257139117 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714080758 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543058359 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 5257139117 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27392049000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579464500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55971513500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1440396400 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339396963 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14779793363 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28832445400 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41918861463 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70751306863 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033859 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026666 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014074 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021352 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019443 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008026 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050186 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043054 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020255 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.011505 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.011505 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12232.243694 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12934.667725 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.722377 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32579.535430 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34670.389239 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33939.184529 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.436927 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11550.391697 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11404.844515 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 597736 # number of writebacks
+system.cpu0.dcache.writebacks::total 597736 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 143982 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 143982 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 560780 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 560780 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 407 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 407 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 704762 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 704762 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 704762 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 704762 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63831 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131106 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 194937 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28888 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53486 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 82374 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1736 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3351 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5087 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 92719 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 184592 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 277311 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 92719 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 184592 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 277311 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780623750 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1700229865 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2480853615 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 933509750 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1853484745 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2786994495 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19304000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38850752 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58154752 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714133500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3553714610 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 5267848110 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714133500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3553714610 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 5267848110 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27350994000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28703901500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56054895500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1444132955 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13356723550 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14800856505 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28795126955 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42060625050 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70855752005 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033885 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026674 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021438 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019472 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008063 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049685 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043387 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020339 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.011528 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.011528 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12229.539722 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12968.360449 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.437849 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32314.793340 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34653.642916 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33833.424321 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.815668 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11593.778574 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11432.033025 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 2096038 # DTB read hits
-system.cpu1.dtb.read_misses 2089 # DTB read misses
-system.cpu1.dtb.write_hits 1418402 # DTB write hits
-system.cpu1.dtb.write_misses 376 # DTB write misses
+system.cpu1.dtb.read_hits 2096820 # DTB read hits
+system.cpu1.dtb.read_misses 2107 # DTB read misses
+system.cpu1.dtb.write_hits 1423125 # DTB write hits
+system.cpu1.dtb.write_misses 370 # DTB write misses
system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1770 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1777 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 2098127 # DTB read accesses
-system.cpu1.dtb.write_accesses 1418778 # DTB write accesses
+system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 2098927 # DTB read accesses
+system.cpu1.dtb.write_accesses 1423495 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 3514440 # DTB hits
-system.cpu1.dtb.misses 2465 # DTB misses
-system.cpu1.dtb.accesses 3516905 # DTB accesses
+system.cpu1.dtb.hits 3519945 # DTB hits
+system.cpu1.dtb.misses 2477 # DTB misses
+system.cpu1.dtb.accesses 3522422 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 8190394 # ITB inst hits
-system.cpu1.itb.inst_misses 1200 # ITB inst misses
+system.cpu1.itb.inst_hits 8175454 # ITB inst hits
+system.cpu1.itb.inst_misses 1196 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8191594 # ITB inst accesses
-system.cpu1.itb.hits 8190394 # DTB hits
-system.cpu1.itb.misses 1200 # DTB misses
-system.cpu1.itb.accesses 8191594 # DTB accesses
-system.cpu1.numCycles 584767176 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 8176650 # ITB inst accesses
+system.cpu1.itb.hits 8175454 # DTB hits
+system.cpu1.itb.misses 1196 # DTB misses
+system.cpu1.itb.accesses 8176650 # DTB accesses
+system.cpu1.numCycles 584791217 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7979697 # Number of instructions committed
-system.cpu1.committedOps 10128513 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 9101420 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses
-system.cpu1.num_func_calls 304592 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1114093 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 9101420 # number of integer instructions
-system.cpu1.num_fp_insts 2019 # number of float instructions
-system.cpu1.num_int_register_reads 53054873 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 9892627 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written
-system.cpu1.num_mem_refs 3681879 # number of memory refs
-system.cpu1.num_load_insts 2189240 # Number of load instructions
-system.cpu1.num_store_insts 1492639 # Number of store instructions
-system.cpu1.num_idle_cycles 548440957.661697 # Number of idle cycles
-system.cpu1.num_busy_cycles 36326218.338303 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.062121 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.937879 # Percentage of idle cycles
-system.cpu1.Branches 1446987 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 5386 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 6616988 64.14% 64.19% # Class of executed instruction
-system.cpu1.op_class::IntMult 11601 0.11% 64.31% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.31% # Class of executed instruction
-system.cpu1.op_class::MemRead 2189240 21.22% 85.53% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1492639 14.47% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 7972563 # Number of instructions committed
+system.cpu1.committedOps 10134873 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 9111769 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 2002 # Number of float alu accesses
+system.cpu1.num_func_calls 305506 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1114419 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 9111769 # number of integer instructions
+system.cpu1.num_fp_insts 2002 # number of float instructions
+system.cpu1.num_int_register_reads 53111503 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 9891567 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1488 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
+system.cpu1.num_mem_refs 3688880 # number of memory refs
+system.cpu1.num_load_insts 2190803 # Number of load instructions
+system.cpu1.num_store_insts 1498077 # Number of store instructions
+system.cpu1.num_idle_cycles 549443201.253140 # Number of idle cycles
+system.cpu1.num_busy_cycles 35348015.746859 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.060446 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.939554 # Percentage of idle cycles
+system.cpu1.Branches 1447411 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 5397 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 6618001 64.10% 64.15% # Class of executed instruction
+system.cpu1.op_class::IntMult 11557 0.11% 64.27% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.27% # Class of executed instruction
+system.cpu1.op_class::MemRead 2190803 21.22% 85.49% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1498077 14.51% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 10316152 # Class of executed instruction
+system.cpu1.op_class::total 10324133 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 4788852 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 3906949 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 223643 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3181584 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2530711 # Number of BTB hits
+system.cpu2.branchPred.lookups 4844951 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 3958364 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 223288 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3209464 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2561917 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 79.542486 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 413887 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 21714 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 79.823827 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 415777 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 21493 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 10930564 # DTB read hits
-system.cpu2.dtb.read_misses 23215 # DTB read misses
-system.cpu2.dtb.write_hits 3350483 # DTB write hits
-system.cpu2.dtb.write_misses 6482 # DTB write misses
+system.cpu2.dtb.read_hits 10946099 # DTB read hits
+system.cpu2.dtb.read_misses 23259 # DTB read misses
+system.cpu2.dtb.write_hits 3358425 # DTB write hits
+system.cpu2.dtb.write_misses 6569 # DTB write misses
system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 733 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 2341 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 761 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 169 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 461 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 10953779 # DTB read accesses
-system.cpu2.dtb.write_accesses 3356965 # DTB write accesses
+system.cpu2.dtb.perms_faults 490 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 10969358 # DTB read accesses
+system.cpu2.dtb.write_accesses 3364994 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 14281047 # DTB hits
-system.cpu2.dtb.misses 29697 # DTB misses
-system.cpu2.dtb.accesses 14310744 # DTB accesses
+system.cpu2.dtb.hits 14304524 # DTB hits
+system.cpu2.dtb.misses 29828 # DTB misses
+system.cpu2.dtb.accesses 14334352 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.inst_hits 4054306 # ITB inst hits
-system.cpu2.itb.inst_misses 4589 # ITB inst misses
+system.cpu2.itb.inst_hits 4066170 # ITB inst hits
+system.cpu2.itb.inst_misses 4558 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 1707 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 1650 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 958 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 4058895 # ITB inst accesses
-system.cpu2.itb.hits 4054306 # DTB hits
-system.cpu2.itb.misses 4589 # DTB misses
-system.cpu2.itb.accesses 4058895 # DTB accesses
-system.cpu2.numCycles 88316329 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 4070728 # ITB inst accesses
+system.cpu2.itb.hits 4066170 # DTB hits
+system.cpu2.itb.misses 4558 # DTB misses
+system.cpu2.itb.accesses 4070728 # DTB accesses
+system.cpu2.numCycles 88357644 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 9351504 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 32524106 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 4788852 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 2944598 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 6861719 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1761177 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 50498 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles 19190819 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 265 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 860 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 33145 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 719724 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 402 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 4052907 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 289738 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2002 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 37419321 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.044533 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.431855 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 9387256 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 32765333 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 4844951 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 2977694 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 6914165 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1793026 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 51157 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 18399919 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 937 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 34522 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 732881 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 4064781 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 291170 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 36763653 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.071353 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.456601 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 30562706 81.68% 81.68% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 385991 1.03% 82.71% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 516133 1.38% 84.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 820285 2.19% 86.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 630351 1.68% 87.96% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 341631 0.91% 88.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1045289 2.79% 91.67% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 230176 0.62% 92.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 2886759 7.71% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 29854695 81.21% 81.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 388351 1.06% 82.26% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 517738 1.41% 83.67% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 822514 2.24% 85.91% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 639820 1.74% 87.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 344469 0.94% 88.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1061447 2.89% 91.47% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 231777 0.63% 92.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 2902842 7.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 37419321 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.054224 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.368268 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 9979534 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 19757337 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 6196813 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 326068 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1158658 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 609699 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 52950 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 36983425 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 178083 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 1158658 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 10528432 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 6814826 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 11435729 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 5959486 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1521262 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 34891179 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 96 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 325442 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 887620 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents 163 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 37432161 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 161024301 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 148452649 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 3370 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 26548024 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 10884136 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 285664 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 261962 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3325772 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6628163 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3904378 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 525369 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 781342 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 32207136 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 505175 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 34773283 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 55288 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 7195240 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 19128466 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 148705 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 37419321 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.929287 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.589860 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 36763653 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.054833 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.370826 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 9873812 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 19124591 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 6319657 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 254865 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1189808 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 613364 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 53448 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 37275302 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 179889 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 1189808 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 10379118 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 2802247 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 11780210 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 6098002 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 4513356 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 35160533 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 386 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 2869122 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 3154793 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 689173 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.FullRegisterEvents 383 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 37744497 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 162187083 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 149521715 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 3412 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 26544575 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 11199921 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 286052 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 262435 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 2598030 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6687505 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3927813 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 542106 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 758032 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 32441943 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 511673 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 34839204 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 63540 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 7431415 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 19915523 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 154345 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 36763653 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.947653 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.617979 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 24716493 66.05% 66.05% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3990546 10.66% 76.72% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 2313548 6.18% 82.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 1974351 5.28% 88.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 2779950 7.43% 95.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 967650 2.59% 98.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 497474 1.33% 99.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 144778 0.39% 99.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 34531 0.09% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 24294475 66.08% 66.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3786923 10.30% 76.38% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 2217252 6.03% 82.41% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 1918473 5.22% 87.63% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 2844306 7.74% 95.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 967223 2.63% 98.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 535277 1.46% 99.46% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 160435 0.44% 99.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 39289 0.11% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 37419321 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 36763653 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 19609 1.29% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 1392955 91.52% 92.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 109452 7.19% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 19487 1.25% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 1 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.25% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 1415927 90.74% 91.99% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 124952 8.01% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 8340 0.02% 0.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 19803061 56.95% 56.97% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 28127 0.08% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 3 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 8595 0.02% 0.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 19842102 56.95% 56.98% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 28105 0.08% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 10 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 57.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 57.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 57.06% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 11414599 32.83% 89.88% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3518761 10.12% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 11432468 32.81% 89.87% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3527522 10.13% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 34773283 # Type of FU issued
-system.cpu2.iq.rate 0.393736 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 1522017 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.043770 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 108565265 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 39912731 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 28072202 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 7477 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 4009 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 3345 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 36282976 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 3984 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 206198 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 34839204 # Type of FU issued
+system.cpu2.iq.rate 0.394298 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 1560367 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.044788 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 108088247 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 40390587 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 28132113 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 7428 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 3949 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 3288 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 36387010 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 3966 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 216264 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1536367 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 2104 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 9509 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 563915 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1592400 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1668 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 9845 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 582754 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5287425 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 344896 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5289504 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 343573 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1158658 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 5187034 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 87972 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32794480 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 61964 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6628163 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3904378 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 362952 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 29501 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2651 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 9509 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 107755 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 89629 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 197384 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 33857007 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 11143266 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 916276 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 1189808 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 2192287 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 292580 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 33037931 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 55534 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6687505 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3927813 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 368987 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 60475 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 207427 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 9845 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 107337 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 89487 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 196824 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 33922204 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 11159492 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 82169 # number of nop insts executed
-system.cpu2.iew.exec_refs 14628489 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 3765120 # Number of branches executed
-system.cpu2.iew.exec_stores 3485223 # Number of stores executed
-system.cpu2.iew.exec_rate 0.383361 # Inst execution rate
-system.cpu2.iew.wb_sent 33455826 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 28075547 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 16112995 # num instructions producing a value
-system.cpu2.iew.wb_consumers 29113416 # num instructions consuming a value
+system.cpu2.iew.exec_nop 84315 # number of nop insts executed
+system.cpu2.iew.exec_refs 14652861 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 3774133 # Number of branches executed
+system.cpu2.iew.exec_stores 3493369 # Number of stores executed
+system.cpu2.iew.exec_rate 0.383919 # Inst execution rate
+system.cpu2.iew.wb_sent 33519345 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 28135401 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 16326972 # num instructions producing a value
+system.cpu2.iew.wb_consumers 29693548 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.317898 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.553456 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.318426 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.549849 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 7147493 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 356470 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 171471 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 36260461 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.700277 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.736744 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 7376982 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 357328 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 170683 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 35573653 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.713892 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.756913 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 27338017 75.39% 75.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4438533 12.24% 87.63% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1258858 3.47% 91.11% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 640995 1.77% 92.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 514559 1.42% 94.29% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 318215 0.88% 95.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 418287 1.15% 96.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 309870 0.85% 97.18% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1023127 2.82% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 26733174 75.15% 75.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4358118 12.25% 87.40% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1232607 3.46% 90.86% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 662996 1.86% 92.73% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 505200 1.42% 94.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 312825 0.88% 95.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 424269 1.19% 96.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 302810 0.85% 97.07% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1041654 2.93% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 36260461 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 20554943 # Number of instructions committed
-system.cpu2.commit.committedOps 25392373 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 35573653 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 20550287 # Number of instructions committed
+system.cpu2.commit.committedOps 25395761 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8432259 # Number of memory references committed
-system.cpu2.commit.loads 5091796 # Number of loads committed
-system.cpu2.commit.membars 94283 # Number of memory barriers committed
-system.cpu2.commit.branches 3240263 # Number of branches committed
-system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 22648524 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 295510 # Number of function calls committed.
+system.cpu2.commit.refs 8440164 # Number of memory references committed
+system.cpu2.commit.loads 5095105 # Number of loads committed
+system.cpu2.commit.membars 94591 # Number of memory barriers committed
+system.cpu2.commit.branches 3237542 # Number of branches committed
+system.cpu2.commit.fp_insts 3235 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 22655353 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 295831 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 16933133 66.69% 66.69% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 26595 0.10% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 386 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 5091796 20.05% 86.84% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 3340463 13.16% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 16928638 66.66% 66.66% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 26577 0.10% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 382 0.00% 66.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 5095105 20.06% 86.83% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 3345059 13.17% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 25392373 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1023127 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 25395761 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1041654 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 67255841 # The number of ROB reads
-system.cpu2.rob.rob_writes 66282532 # The number of ROB writes
-system.cpu2.timesIdled 358696 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 50897008 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 3546076715 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 20499567 # Number of Instructions Simulated
-system.cpu2.committedOps 25336997 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 4.308205 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 4.308205 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.232115 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.232115 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 157113831 # number of integer regfile reads
-system.cpu2.int_regfile_writes 29893796 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 46822 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 67223937 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 297064 # number of misc regfile writes
+system.cpu2.rob.rob_reads 66778885 # The number of ROB reads
+system.cpu2.rob.rob_writes 66779605 # The number of ROB writes
+system.cpu2.timesIdled 362907 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 51593991 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 3545947336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 20495032 # Number of Instructions Simulated
+system.cpu2.committedOps 25340506 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 4.311174 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 4.311174 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.231955 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.231955 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 157422880 # number of integer regfile reads
+system.cpu2.int_regfile_writes 29963931 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 46839 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 45210 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 66597785 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 297300 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1535534030000 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1536043103750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1536043103750 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=256
-boot_loader=/dist/binaries/boot.arm
-boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
load_offset=0
machine_type=RealView_PBX
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-arm-ael.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img
read_only=true
[system.clk_domain]
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=true
pio=system.membus.default
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[6]
[system.realview]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 19:10:32
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:27:42
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x6aaf400 0x6aaf400
- 0: system.cpu1.isa: ISA system set to: 0x6aaf400 0x6aaf400
+ 0: system.cpu0.isa: ISA system set to: 0x60c5390 0x60c5390
+ 0: system.cpu1.isa: ISA system set to: 0x60c5390 0x60c5390
---------- Begin Simulation Statistics ----------
-sim_seconds 2.550603 # Number of seconds simulated
-sim_ticks 2550603285500 # Number of ticks simulated
-final_tick 2550603285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.550237 # Number of seconds simulated
+sim_ticks 2550237191000 # Number of ticks simulated
+final_tick 2550237191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56179 # Simulator instruction rate (inst/s)
-host_op_rate 72287 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2375661490 # Simulator tick rate (ticks/s)
-host_mem_usage 471120 # Number of bytes of host memory used
-host_seconds 1073.64 # Real time elapsed on the host
-sim_insts 60315997 # Number of instructions simulated
-sim_ops 77609994 # Number of ops (including micro ops) simulated
+host_inst_rate 66377 # Simulator instruction rate (inst/s)
+host_op_rate 85409 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2806608319 # Simulator tick rate (ticks/s)
+host_mem_usage 421988 # Number of bytes of host memory used
+host_seconds 908.65 # Real time elapsed on the host
+sim_insts 60314055 # Number of instructions simulated
+sim_ops 77607027 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 487168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5091220 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 310848 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4002308 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131004952 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 487168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 310848 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3785472 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1521388 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1494684 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6801544 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 2240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 507520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5298200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 292352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 3795584 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131007192 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 507520 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 292352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3786240 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1521400 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1494672 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6802312 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7612 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 79585 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4857 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 62537 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293452 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59148 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 380347 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 373671 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813166 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47483091 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 778 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 191001 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1996085 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 301 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 121872 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1569161 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51362340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 191001 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 121872 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 312873 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1484148 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 596482 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 586012 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2666641 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1484148 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47483091 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 778 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 191001 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2592566 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 121872 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2155173 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54028981 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15293452 # Number of read requests accepted
-system.physmem.writeReqs 813166 # Number of write requests accepted
-system.physmem.readBursts 15293452 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 813166 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 977025792 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 1755136 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6829888 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 131004952 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6801544 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 27424 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 706426 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 955870 # Per bank write bursts
-system.physmem.perBankRdBursts::1 953353 # Per bank write bursts
-system.physmem.perBankRdBursts::2 953267 # Per bank write bursts
-system.physmem.perBankRdBursts::3 953402 # Per bank write bursts
-system.physmem.perBankRdBursts::4 955744 # Per bank write bursts
-system.physmem.perBankRdBursts::5 953745 # Per bank write bursts
-system.physmem.perBankRdBursts::6 953482 # Per bank write bursts
-system.physmem.perBankRdBursts::7 953247 # Per bank write bursts
-system.physmem.perBankRdBursts::8 956258 # Per bank write bursts
-system.physmem.perBankRdBursts::9 953771 # Per bank write bursts
-system.physmem.perBankRdBursts::10 953551 # Per bank write bursts
-system.physmem.perBankRdBursts::11 953111 # Per bank write bursts
-system.physmem.perBankRdBursts::12 956206 # Per bank write bursts
-system.physmem.perBankRdBursts::13 953857 # Per bank write bursts
-system.physmem.perBankRdBursts::14 953612 # Per bank write bursts
-system.physmem.perBankRdBursts::15 953552 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6609 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6381 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6537 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6560 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6488 # Per bank write bursts
+system.physmem.num_reads::cpu0.dtb.walker 35 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 7930 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 82820 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 4568 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 59306 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59160 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 380350 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 373668 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47489907 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 878 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 199009 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2077532 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 114637 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1488326 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51370591 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 199009 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 114637 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 313646 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1484662 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 596572 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 586091 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2667325 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1484662 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47489907 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 878 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 199009 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2674104 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 114637 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2074417 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54037916 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15293487 # Number of read requests accepted
+system.physmem.writeReqs 813178 # Number of write requests accepted
+system.physmem.readBursts 15293487 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 813178 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 977052352 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 1730816 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6829312 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 131007192 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6802312 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 27044 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706441 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4687 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 955866 # Per bank write bursts
+system.physmem.perBankRdBursts::1 953274 # Per bank write bursts
+system.physmem.perBankRdBursts::2 953247 # Per bank write bursts
+system.physmem.perBankRdBursts::3 953514 # Per bank write bursts
+system.physmem.perBankRdBursts::4 955750 # Per bank write bursts
+system.physmem.perBankRdBursts::5 953800 # Per bank write bursts
+system.physmem.perBankRdBursts::6 953588 # Per bank write bursts
+system.physmem.perBankRdBursts::7 953504 # Per bank write bursts
+system.physmem.perBankRdBursts::8 956261 # Per bank write bursts
+system.physmem.perBankRdBursts::9 953859 # Per bank write bursts
+system.physmem.perBankRdBursts::10 953506 # Per bank write bursts
+system.physmem.perBankRdBursts::11 952990 # Per bank write bursts
+system.physmem.perBankRdBursts::12 956201 # Per bank write bursts
+system.physmem.perBankRdBursts::13 953861 # Per bank write bursts
+system.physmem.perBankRdBursts::14 953718 # Per bank write bursts
+system.physmem.perBankRdBursts::15 953504 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6593 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6395 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6535 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6562 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6485 # Per bank write bursts
system.physmem.perBankWrBursts::5 6754 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6745 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6685 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7023 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6801 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6470 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6120 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7060 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6677 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6963 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6844 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6752 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6692 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7013 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6813 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6467 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6119 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7057 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6685 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6965 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6821 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2550602119500 # Total gap between requests
+system.physmem.totGap 2550236004000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 38 # Read request sizes (log2)
system.physmem.readPktSize::3 15138816 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 154598 # Read request sizes (log2)
+system.physmem.readPktSize::6 154633 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 59148 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1066844 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1005139 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 964469 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1068011 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 971384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1033822 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2692544 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2602827 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3401172 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 112530 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 102949 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 95927 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 92392 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 19066 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 18545 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 18331 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 59160 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1068642 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1003556 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 964678 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1068028 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 971433 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1034228 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2693278 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2602966 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3400925 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 112135 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 102170 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 95874 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 92374 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 19109 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 18588 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 18396 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 289 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 280 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 278 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 268 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 265 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 263 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 286 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 283 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 279 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 278 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 274 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 3258 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3524 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4792 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6251 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6100 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6078 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6458 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 6079 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6047 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 6081 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5943 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5910 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6309 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5883 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5894 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5982 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5778 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 67 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 33 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 3279 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3544 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4723 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6033 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6064 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6482 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 6060 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 6076 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6103 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5934 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5931 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6266 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5878 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5998 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5786 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 83 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1010962 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 973.187598 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 908.669037 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 201.227455 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22588 2.23% 2.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 20116 1.99% 4.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8785 0.87% 5.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2331 0.23% 5.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2167 0.21% 5.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1761 0.17% 5.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 9115 0.90% 6.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 858 0.08% 6.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 943241 93.30% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1010962 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2514.580135 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 47785.198367 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535 6044 99.56% 99.56% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.57% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143 6 0.10% 99.80% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1011151 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 973.031391 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 908.214038 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 201.586844 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22832 2.26% 2.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 19987 1.98% 4.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8899 0.88% 5.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2276 0.23% 5.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2117 0.21% 5.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1805 0.18% 5.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 9141 0.90% 6.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 764 0.08% 6.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 943330 93.29% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1011151 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6075 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2512.992263 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 47101.457482 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535 6047 99.54% 99.54% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.56% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.69% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143 7 0.12% 99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.578158 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.392553 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.387042 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2 4 0.07% 0.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3 2 0.03% 0.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4 7 0.12% 0.28% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 6075 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.565103 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.376946 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.337614 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1 6 0.10% 0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2 5 0.08% 0.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3 2 0.03% 0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7 3 0.05% 0.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8 4 0.07% 0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::9 6 0.10% 0.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10 2 0.03% 0.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::11 3 0.05% 0.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::13 2 0.03% 0.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7 2 0.03% 0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8 4 0.07% 0.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9 5 0.08% 0.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10 2 0.03% 0.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11 3 0.05% 0.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12 3 0.05% 0.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13 1 0.02% 0.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::15 12 0.20% 0.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2739 45.12% 46.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 35 0.58% 46.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1542 25.40% 72.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1308 21.55% 93.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 93 1.53% 95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 45 0.74% 95.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 49 0.81% 96.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 58 0.96% 97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 25 0.41% 98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 17 0.28% 98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 20 0.33% 98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 16 0.26% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 13 0.21% 99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 14 0.23% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 14 0.23% 99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 16 0.26% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 10 0.16% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads
-system.physmem.totQLat 393355196000 # Total ticks spent queuing
-system.physmem.totMemAccLat 679593221000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 76330140000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25766.70 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 2721 44.79% 45.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 38 0.63% 46.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1583 26.06% 72.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1297 21.35% 93.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 91 1.50% 95.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 44 0.72% 95.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 54 0.89% 96.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 48 0.79% 97.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 29 0.48% 98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 18 0.30% 98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 20 0.33% 98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 17 0.28% 99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 13 0.21% 99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 16 0.26% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 12 0.20% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 10 0.16% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 8 0.13% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads
+system.physmem.totQLat 393209260500 # Total ticks spent queuing
+system.physmem.totMemAccLat 679455066750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 76332215000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25756.44 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44516.70 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 383.06 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44506.44 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 383.12 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.01 # Data bus utilization in percentage
system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 6.51 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 15.34 # Average write queue length when enqueuing
-system.physmem.readRowHits 14270645 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91138 # Number of row buffer hits during writes
+system.physmem.avgRdQLen 6.37 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 14.37 # Average write queue length when enqueuing
+system.physmem.readRowHits 14270960 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91040 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 85.38 # Row buffer hit rate for writes
-system.physmem.avgGap 158357.40 # Average gap between requests
+system.physmem.writeRowHitRate 85.29 # Row buffer hit rate for writes
+system.physmem.avgGap 158334.21 # Average gap between requests
system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2202343950500 # Time in different power states
-system.physmem.memoryStateTime::REF 85170020000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2202305646000 # Time in different power states
+system.physmem.memoryStateTime::REF 85157800000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 263082705750 # Time in different power states
+system.physmem.memoryStateTime::ACT 262767276500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54969203 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16346092 # Transaction distribution
-system.membus.trans_dist::ReadResp 16346092 # Transaction distribution
+system.membus.throughput 54978267 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16346128 # Transaction distribution
+system.membus.trans_dist::ReadResp 16346128 # Transaction distribution
system.membus.trans_dist::WriteReq 763361 # Transaction distribution
system.membus.trans_dist::WriteResp 763361 # Transaction distribution
-system.membus.trans_dist::Writeback 59148 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution
-system.membus.trans_dist::ReadExReq 131444 # Transaction distribution
-system.membus.trans_dist::ReadExResp 131444 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::Writeback 59160 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4687 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131439 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131439 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885816 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4272670 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885912 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4272758 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34550302 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 34550390 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16695968 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 19094102 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698976 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 19097094 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 140204630 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 140204630 # Total data (bytes)
+system.membus.tot_pkt_size::total 140207622 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 140207622 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1486938500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1487194000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3616000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3622500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17564463000 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17516054500 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4735162713 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4714051227 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 37454635709 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 37455331951 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 64370 # number of replacements
-system.l2c.tags.tagsinuse 51446.531370 # Cycle average of tags in use
-system.l2c.tags.total_refs 1904863 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 129760 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 14.679894 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 2513258094500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 36996.902854 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 21.266230 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4638.850911 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3223.219228 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.615555 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 3561.358912 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 2994.317308 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.564528 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000324 # Average percentage of cache occupancy
+system.l2c.tags.replacements 64405 # number of replacements
+system.l2c.tags.tagsinuse 51448.142618 # Cycle average of tags in use
+system.l2c.tags.total_refs 1904465 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 129797 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 14.672643 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 2540066144500 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 37002.110374 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 24.124150 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 4932.290143 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 3309.962047 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.942781 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 3265.462064 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 2905.250809 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.564607 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000368 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.070783 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.049182 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.054342 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.045690 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.785012 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3064 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 6835 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 55083 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.997437 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 18932032 # Number of tag accesses
-system.l2c.tags.data_accesses 18932032 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 32158 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 6860 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 505744 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 187679 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 31450 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 7231 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 465794 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 199404 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1436320 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 607907 # number of Writeback hits
-system.l2c.Writeback_hits::total 607907 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 58462 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 54465 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 112927 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 32158 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 6860 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 505744 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 246141 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 31450 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 7231 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 465794 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 253869 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1549247 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 32158 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 6860 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 505744 # number of overall hits
-system.l2c.overall_hits::cpu0.data 246141 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 31450 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 7231 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 465794 # number of overall hits
-system.l2c.overall_hits::cpu1.data 253869 # number of overall hits
-system.l2c.overall_hits::total 1549247 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 7502 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6162 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 4864 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 4544 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 23117 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 1628 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 1276 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 74336 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 58884 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 133220 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 31 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 7502 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 80498 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 4864 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 63428 # number of demand (read+write) misses
-system.l2c.demand_misses::total 156337 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 31 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 7502 # number of overall misses
-system.l2c.overall_misses::cpu0.data 80498 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 4864 # number of overall misses
-system.l2c.overall_misses::cpu1.data 63428 # number of overall misses
-system.l2c.overall_misses::total 156337 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2994000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker 368000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 537467000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 452401999 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 913750 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 350167750 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 341997500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1686309999 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 186492 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 326986 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 513478 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 5509515842 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 4330037632 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 9839553474 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 2994000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker 368000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 537467000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 5961917841 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 913750 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 350167750 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 4672035132 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 11525863473 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 2994000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker 368000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 537467000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 5961917841 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 913750 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 350167750 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 4672035132 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 11525863473 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 32189 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 6862 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 513246 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 193841 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 31462 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 7231 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 470658 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 203948 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1459437 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 607907 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 607907 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 1647 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 1291 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2938 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 132798 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 113349 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246147 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 32189 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 6862 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 513246 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 326639 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 31462 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 7231 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 470658 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 317297 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1705584 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 32189 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 6862 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 513246 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 326639 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 31462 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 7231 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 470658 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 317297 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1705584 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000963 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000291 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.014617 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.031789 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.010334 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.022280 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988464 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.988381 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.988428 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.559767 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.519493 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.541221 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000963 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000291 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.014617 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.246443 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.010334 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.199901 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.091662 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000963 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000291 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.014617 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.246443 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000381 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.010334 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.199901 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.091662 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96580.645161 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 184000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71643.161824 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 73418.045927 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76145.833333 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71991.724918 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 75263.534331 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 72946.749102 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 114.552826 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 256.258621 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 176.817493 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74116.388318 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73535.045717 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 73859.431572 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96580.645161 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 184000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 71643.161824 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 74062.931265 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76145.833333 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 71991.724918 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 73658.875134 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 73724.476439 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96580.645161 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 184000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 71643.161824 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 74062.931265 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76145.833333 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 71991.724918 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 73658.875134 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 73724.476439 # average overall miss latency
+system.l2c.tags.occ_percent::cpu0.inst 0.075261 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.050506 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000136 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.049827 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.044331 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.785036 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 65365 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 3060 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 6878 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.997391 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 18931296 # Number of tag accesses
+system.l2c.tags.data_accesses 18931296 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 32363 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 6829 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 504085 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 191784 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 30935 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 6925 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 466764 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 195789 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1435474 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 608464 # number of Writeback hits
+system.l2c.Writeback_hits::total 608464 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 26 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 57858 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 55192 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 113050 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 32363 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 6829 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 504085 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 249642 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 30935 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 6925 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 466764 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 250981 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1548524 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 32363 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 6829 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 504085 # number of overall hits
+system.l2c.overall_hits::cpu0.data 249642 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 30935 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 6925 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 466764 # number of overall hits
+system.l2c.overall_hits::cpu1.data 250981 # number of overall hits
+system.l2c.overall_hits::total 1548524 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 35 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 7820 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6258 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 4574 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 4456 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 23155 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 1552 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 1356 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 77511 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 55705 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 133216 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 35 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 7820 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 83769 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 4574 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 60161 # number of demand (read+write) misses
+system.l2c.demand_misses::total 156371 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 35 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 7820 # number of overall misses
+system.l2c.overall_misses::cpu0.data 83769 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 4574 # number of overall misses
+system.l2c.overall_misses::cpu1.data 60161 # number of overall misses
+system.l2c.overall_misses::total 156371 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3562250 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker 293000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 558840500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 462734249 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 914250 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 333186000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 341954000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1701484249 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 257989 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 490479 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 5723904556 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 3992494167 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 9716398723 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 3562250 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 558840500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 6186638805 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 914250 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 333186000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 4334448167 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 11417882972 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 3562250 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker 293000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 558840500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 6186638805 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 914250 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 333186000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 4334448167 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 11417882972 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 32398 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 6830 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 511905 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 198042 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 30946 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 6925 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 471338 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 200245 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1458629 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 608464 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 608464 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 1578 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 1368 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2946 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 9 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 9 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 135369 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 110897 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 246266 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 32398 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 6830 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 511905 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 333411 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 30946 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 6925 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 471338 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 311142 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1704895 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 32398 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 6830 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 511905 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 333411 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 30946 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 6925 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 471338 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 311142 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1704895 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001080 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000146 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015276 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.031599 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000355 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.009704 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.022253 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.015874 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.983523 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991228 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.987101 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.111111 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.111111 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.111111 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.572590 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.502313 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.540944 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001080 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000146 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015276 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.251248 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000355 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.009704 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.193355 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.091719 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001080 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000146 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015276 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.251248 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000355 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.009704 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.193355 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.091719 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 101778.571429 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 293000 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71462.979540 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 73942.833014 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83113.636364 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72843.463052 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76740.125673 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 73482.368776 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 149.800258 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 190.257375 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 168.665406 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73846.351563 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71672.097065 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 72937.175137 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101778.571429 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 293000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 71462.979540 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 73853.559252 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83113.636364 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 72843.463052 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 72047.475391 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 73017.905954 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101778.571429 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 293000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 71462.979540 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 73853.559252 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83113.636364 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72843.463052 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 72047.475391 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 73017.905954 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 59148 # number of writebacks
-system.l2c.writebacks::total 59148 # number of writebacks
+system.l2c.writebacks::writebacks 59160 # number of writebacks
+system.l2c.writebacks::total 59160 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data 43 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data 22 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data 43 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data 22 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 81 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 31 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 7494 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 6120 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 4857 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 4520 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 23036 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 1628 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 1276 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 2904 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 74336 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 58884 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 133220 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 31 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 7494 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 80456 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 4857 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 63404 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 156256 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 31 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 7494 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 80456 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 4857 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 63404 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 156256 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2611500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 343500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 442660000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 373109249 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 763750 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 288530250 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 284079000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1392097249 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 16281628 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12763275 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 29044903 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4584247158 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3597170868 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 8181418026 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2611500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 343500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 442660000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 4957356407 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 763750 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 288530250 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 3881249868 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 9573515275 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2611500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 343500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 442660000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 4957356407 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 763750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 288530250 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 3881249868 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 9573515275 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6521499 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83889052500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83054276000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 166949849999 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8950146108 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8426611000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 17376757108 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6521499 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92839198608 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91480887000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184326607107 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000963 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014601 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.031572 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022163 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.015784 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988464 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988381 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.988428 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.559767 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.519493 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.541221 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000963 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014601 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.246315 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.199825 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.091614 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000963 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014601 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.246315 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.199825 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.091614 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60965.563562 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62849.336283 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 60431.379102 # average ReadReq mshr miss latency
+system.l2c.overall_mshr_hits::cpu0.data 43 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data 22 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 35 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 7812 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 6215 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 4568 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 4434 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 23076 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 1552 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 1356 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 77511 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 55705 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 133216 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 35 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 7812 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 83726 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 4568 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 60139 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 156292 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 35 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 7812 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 83726 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 4568 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 60139 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 156292 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3127750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 281000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 460062000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 382258249 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 778250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 275211250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 285303500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1407021999 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15521552 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13562356 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 29083908 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 10001 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4769263944 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3305065333 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 8074329277 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3127750 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 281000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 460062000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 5151522193 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 778250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 275211250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 3590368833 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 9481351276 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3127750 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 281000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 460062000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 5151522193 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 778250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 275211250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 3590368833 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 9481351276 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6525500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83923690500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83019017000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166949233000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8966653586 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8434821998 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 17401475584 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6525500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92890344086 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91453838998 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184350708584 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001080 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.031382 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022143 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.015820 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983523 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991228 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.987101 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.111111 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.111111 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572590 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.502313 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.540944 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001080 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.251119 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.193285 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.091673 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001080 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000146 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015261 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.251119 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000355 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009692 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.193285 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.091673 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61505.752051 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64344.497068 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 60973.392226 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.566614 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.688361 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61669.274080 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61089.105156 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61412.836106 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.737463 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.343879 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61530.156287 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59331.574060 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60610.807088 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 58427348 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2677396 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2677395 # Transaction distribution
+system.toL2Bus.throughput 58447524 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2676676 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2676675 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 607907 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2938 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2945 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 246147 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 246147 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1969203 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796633 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38454 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149595 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7953885 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62977408 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85532246 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56372 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254604 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 148820630 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 148820630 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 204356 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4962673723 # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::Writeback 608464 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2946 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2964 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 246266 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 246266 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967872 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798454 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37749 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149111 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7953186 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62935104 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85607366 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55020 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253376 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 148850866 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 148850866 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 204184 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4964883974 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4436346984 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4433375902 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4483051170 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4485758372 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 24406904 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 24044394 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 86367392 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 86236537 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 48420315 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution
+system.iobus.throughput 48427259 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution
system.iobus.trans_dist::WriteReq 8177 # Transaction distribution
system.iobus.trans_dist::WriteResp 8177 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2383060 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 32660692 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390486 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 123501014 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 123501014 # Total data (bytes)
+system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 123500998 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 38146923291 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 38148865049 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
-system.cpu0.branchPred.lookups 7527303 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 6005482 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 376664 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4812068 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 3910560 # Number of BTB hits
+system.cpu0.branchPred.lookups 7661485 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 6126508 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 381527 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4905065 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 3983490 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 81.265685 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 724420 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 38989 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 81.211768 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 723596 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 38982 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 25762472 # DTB read hits
-system.cpu0.dtb.read_misses 39475 # DTB read misses
-system.cpu0.dtb.write_hits 6143291 # DTB write hits
-system.cpu0.dtb.write_misses 10324 # DTB write misses
+system.cpu0.dtb.read_hits 25785436 # DTB read hits
+system.cpu0.dtb.read_misses 39736 # DTB read misses
+system.cpu0.dtb.write_hits 6191742 # DTB write hits
+system.cpu0.dtb.write_misses 10170 # DTB write misses
system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5580 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1376 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 5474 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1453 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 639 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 25801947 # DTB read accesses
-system.cpu0.dtb.write_accesses 6153615 # DTB write accesses
+system.cpu0.dtb.perms_faults 628 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 25825172 # DTB read accesses
+system.cpu0.dtb.write_accesses 6201912 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31905763 # DTB hits
-system.cpu0.dtb.misses 49799 # DTB misses
-system.cpu0.dtb.accesses 31955562 # DTB accesses
+system.cpu0.dtb.hits 31977178 # DTB hits
+system.cpu0.dtb.misses 49906 # DTB misses
+system.cpu0.dtb.accesses 32027084 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 5893431 # ITB inst hits
-system.cpu0.itb.inst_misses 7431 # ITB inst misses
+system.cpu0.itb.inst_hits 5958651 # ITB inst hits
+system.cpu0.itb.inst_misses 7224 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2617 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2573 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1506 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 5900862 # ITB inst accesses
-system.cpu0.itb.hits 5893431 # DTB hits
-system.cpu0.itb.misses 7431 # DTB misses
-system.cpu0.itb.accesses 5900862 # DTB accesses
-system.cpu0.numCycles 242264674 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 5965875 # ITB inst accesses
+system.cpu0.itb.hits 5958651 # DTB hits
+system.cpu0.itb.misses 7224 # DTB misses
+system.cpu0.itb.accesses 5965875 # DTB accesses
+system.cpu0.numCycles 242096947 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 15531926 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 45587183 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7527303 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4634980 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10285875 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2434733 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 89107 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 50171859 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 1648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 2068 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 54478 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1474048 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 5891523 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 366856 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 79291736 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.723314 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.072188 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 15548527 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 46430150 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 7661485 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4707086 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 10443980 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2504010 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 87505 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 47991707 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 1669 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 1947 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 50069 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1492171 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 5956718 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 371320 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 77361996 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.753757 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.110815 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 69012854 87.04% 87.04% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 680232 0.86% 87.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 874808 1.10% 89.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1172230 1.48% 90.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1090891 1.38% 91.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 557599 0.70% 92.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1295199 1.63% 94.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 379880 0.48% 94.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4228043 5.33% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 66925381 86.51% 86.51% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 685980 0.89% 87.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 883677 1.14% 88.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1195178 1.54% 90.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1096516 1.42% 91.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 566437 0.73% 92.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1314357 1.70% 93.93% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 386846 0.50% 94.43% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4307624 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 79291736 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.031071 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.188171 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 16635366 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 51194908 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9213198 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 653944 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1592125 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1010665 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 90813 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 54600074 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 300654 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1592125 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 17527482 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 20299787 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 27625200 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 8910460 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3334547 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 52031373 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 331 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 485563 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 2176301 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 182 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 53736698 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 241285167 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 220106334 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 4864 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 39390817 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 14345881 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 590593 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 539084 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 6947132 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 10055649 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6962422 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1056834 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1358453 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 48348288 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1003135 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 62086915 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 89013 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 9905639 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 24691410 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 254686 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 79291736 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.783019 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.501466 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 77361996 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.031646 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.191783 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 16313273 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 49370536 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 9491475 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 529288 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1655237 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1021533 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 91523 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 55531280 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 303986 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1655237 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 17162522 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 7654348 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 28580121 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9244360 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 13063308 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 52889125 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1160 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 8605902 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 9933616 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 1829408 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 705 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 54696180 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 245103090 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 223663577 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 5274 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 39761499 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 14934681 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 590339 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 538925 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5812671 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 10214201 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 7053988 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1084092 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1355038 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 49147671 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1004891 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 62507144 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 106564 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10354652 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 26208427 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 256708 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 77361996 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.807983 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.536259 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 56790483 71.62% 71.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 7331291 9.25% 80.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3517102 4.44% 85.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2900884 3.66% 88.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6182474 7.80% 96.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1488398 1.88% 98.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 785922 0.99% 99.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 230106 0.29% 99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 65076 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 55228815 71.39% 71.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 6921867 8.95% 80.34% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3371546 4.36% 84.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2828196 3.66% 88.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6343832 8.20% 96.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1429149 1.85% 98.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 903697 1.17% 99.57% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 264810 0.34% 99.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 70084 0.09% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 79291736 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 77361996 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 31039 0.70% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 1 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4198728 94.33% 95.03% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 221343 4.97% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 34065 0.76% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 2 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.76% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4230863 93.99% 94.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 236461 5.25% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 14970 0.02% 0.02% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 29137192 46.93% 46.95% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 47374 0.08% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 1226 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 26440432 42.59% 89.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6445693 10.38% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 14977 0.02% 0.02% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 29471794 47.15% 47.17% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 48326 0.08% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 1252 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 26467836 42.34% 89.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 6502932 10.40% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 62086915 # Type of FU issued
-system.cpu0.iq.rate 0.256277 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 4451111 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.071692 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 208044448 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 59266351 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 43285904 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 10871 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 5830 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 4924 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 66517304 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 5752 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 316537 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 62507144 # Type of FU issued
+system.cpu0.iq.rate 0.258191 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 4501391 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.072014 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 207022163 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 60516960 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 43741315 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 11807 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6284 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5315 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 66987291 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6267 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 331575 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2144033 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 4052 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 15721 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 849604 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2258680 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 16640 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 890724 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17082730 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 349385 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 17025951 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 348422 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1592125 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 15682380 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 239912 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 49471978 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 105539 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 10055649 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6962422 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 704937 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 56286 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 4027 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 15721 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 184221 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 145235 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 329456 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 61023718 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 26110824 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1063197 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1655237 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 6199849 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 752551 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 50264845 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 10214201 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 7053988 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 705061 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 147463 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 536075 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 16640 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 186895 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 147787 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 334682 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 61435794 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 26133192 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1071350 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 120555 # number of nop insts executed
-system.cpu0.iew.exec_refs 32498156 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 5982225 # Number of branches executed
-system.cpu0.iew.exec_stores 6387332 # Number of stores executed
-system.cpu0.iew.exec_rate 0.251889 # Inst execution rate
-system.cpu0.iew.wb_sent 60528797 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 43290828 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 23369621 # num instructions producing a value
-system.cpu0.iew.wb_consumers 42956226 # num instructions consuming a value
+system.cpu0.iew.exec_nop 112283 # number of nop insts executed
+system.cpu0.iew.exec_refs 32576038 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 6024055 # Number of branches executed
+system.cpu0.iew.exec_stores 6442846 # Number of stores executed
+system.cpu0.iew.exec_rate 0.253765 # Inst execution rate
+system.cpu0.iew.wb_sent 60932314 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 43746630 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 24175990 # num instructions producing a value
+system.cpu0.iew.wb_consumers 44857309 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.178692 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.544033 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.180699 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.538953 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 9786876 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 748449 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 287258 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 77699611 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.504830 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.472024 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 10244306 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 748183 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 291383 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 75706759 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.522606 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.501619 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 63277588 81.44% 81.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7407512 9.53% 90.97% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1967451 2.53% 93.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1105852 1.42% 94.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 852897 1.10% 96.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 576328 0.74% 96.77% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 737114 0.95% 97.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 349768 0.45% 98.17% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1425101 1.83% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 61320530 81.00% 81.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7333121 9.69% 90.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1910409 2.52% 93.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1174950 1.55% 94.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 814971 1.08% 95.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 569506 0.75% 96.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 771340 1.02% 97.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 344904 0.46% 98.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1467028 1.94% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 77699611 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 30084753 # Number of instructions committed
-system.cpu0.commit.committedOps 39225066 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 75706759 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 30422123 # Number of instructions committed
+system.cpu0.commit.committedOps 39564795 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 14024434 # Number of memory references committed
-system.cpu0.commit.loads 7911616 # Number of loads committed
-system.cpu0.commit.membars 209739 # Number of memory barriers committed
-system.cpu0.commit.branches 5192960 # Number of branches committed
-system.cpu0.commit.fp_insts 4874 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 34907078 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 509367 # Number of function calls committed.
+system.cpu0.commit.refs 14118785 # Number of memory references committed
+system.cpu0.commit.loads 7955521 # Number of loads committed
+system.cpu0.commit.membars 210845 # Number of memory barriers committed
+system.cpu0.commit.branches 5215430 # Number of branches committed
+system.cpu0.commit.fp_insts 5270 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 35234514 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 505825 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 25154804 64.13% 64.13% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 44602 0.11% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 1226 0.00% 64.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 7911616 20.17% 84.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 6112818 15.58% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 25399613 64.20% 64.20% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 45146 0.11% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 1251 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.31% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 7955521 20.11% 84.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 6163264 15.58% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 39225066 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1425101 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 39564795 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1467028 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 124324951 # The number of ROB reads
-system.cpu0.rob.rob_writes 99658992 # The number of ROB writes
-system.cpu0.timesIdled 907419 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 162972938 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2247980405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 30002566 # Number of Instructions Simulated
-system.cpu0.committedOps 39142879 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 8.074798 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 8.074798 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.123842 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.123842 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 277224657 # number of integer regfile reads
-system.cpu0.int_regfile_writes 43993248 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 44815 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 42286 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 137449038 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 580454 # number of misc regfile writes
-system.cpu0.icache.tags.replacements 984532 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.571226 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 10502635 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 985044 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 10.662097 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 7040991250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.697202 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.874025 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620502 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378660 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999163 # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads 123090455 # The number of ROB reads
+system.cpu0.rob.rob_writes 101316686 # The number of ROB writes
+system.cpu0.timesIdled 905863 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 164734951 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2248240039 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 30347856 # Number of Instructions Simulated
+system.cpu0.committedOps 39490528 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 7.977399 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 7.977399 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.125354 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.125354 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 279159718 # number of integer regfile reads
+system.cpu0.int_regfile_writes 44499662 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 45106 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 42408 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 136236681 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 579467 # number of misc regfile writes
+system.cpu0.icache.tags.replacements 983848 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.584983 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 10572279 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 984360 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 10.740257 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6906897250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.103204 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.481778 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.625202 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.373988 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 163 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 12553911 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 12553911 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 5335132 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 5167503 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 10502635 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 5335132 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 5167503 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 10502635 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 5335132 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 5167503 # number of overall hits
-system.cpu0.icache.overall_hits::total 10502635 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 556266 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 509949 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1066215 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 556266 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 509949 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1066215 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 556266 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 509949 # number of overall misses
-system.cpu0.icache.overall_misses::total 1066215 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7659182978 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6870398274 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 14529581252 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 7659182978 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 6870398274 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 14529581252 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 7659182978 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 6870398274 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 14529581252 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 5891398 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 5677452 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 11568850 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 5891398 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 5677452 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 11568850 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 5891398 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 5677452 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 11568850 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094420 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089820 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.092163 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094420 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089820 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.092163 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094420 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089820 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.092163 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13768.921663 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13472.716436 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13627.252714 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13768.921663 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13472.716436 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13627.252714 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13768.921663 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13472.716436 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13627.252714 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 6572 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 144 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 397 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.554156 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 144 # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses 12622728 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 12622728 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 5401219 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 5171060 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 10572279 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 5401219 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 5171060 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 10572279 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 5401219 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 5171060 # number of overall hits
+system.cpu0.icache.overall_hits::total 10572279 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 555378 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 510680 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 1066058 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 555378 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 510680 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 1066058 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 555378 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 510680 # number of overall misses
+system.cpu0.icache.overall_misses::total 1066058 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7663232618 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6859208809 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 14522441427 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 7663232618 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 6859208809 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 14522441427 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 7663232618 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 6859208809 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 14522441427 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 5956597 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 5681740 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 11638337 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 5956597 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 5681740 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 11638337 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 5956597 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 5681740 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 11638337 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.093237 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089881 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.091599 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.093237 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089881 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.091599 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.093237 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089881 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.091599 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13798.228626 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13431.520343 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13622.562212 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13798.228626 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13431.520343 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13622.562212 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13798.228626 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13431.520343 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13622.562212 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 6762 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 376 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.984043 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42425 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38728 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 81153 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 42425 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst 38728 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 81153 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 42425 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst 38728 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 81153 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 513841 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 471221 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 985062 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 513841 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 471221 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 985062 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 513841 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 471221 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 985062 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6224566388 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5591223594 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 11815789982 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6224566388 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5591223594 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 11815789982 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6224566388 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5591223594 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 11815789982 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8993000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8993000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8993000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 8993000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085148 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.085148 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.085148 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11994.970857 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42863 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38803 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 81666 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 42863 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst 38803 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 81666 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 42863 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst 38803 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 81666 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 512515 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 471877 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 984392 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 512515 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 471877 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 984392 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 512515 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 471877 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 984392 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6228172986 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5583639583 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 11811812569 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6228172986 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5583639583 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 11811812569 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6228172986 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5583639583 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 11811812569 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8994500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8994500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8994500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 8994500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084582 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.084582 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086042 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.083051 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.084582 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11999.094435 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 643424 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.993257 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 21526419 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 643936 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 33.429439 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 43468250 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.820066 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.173192 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497695 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502291 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements 644041 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.993361 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 21521749 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 644553 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 33.390193 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 42479250 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.642215 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.351146 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499301 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500686 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 101635836 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 101635836 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 7044250 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 6727132 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 13771382 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3751595 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 3509581 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 7261176 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116856 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126271 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 243127 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119516 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 128128 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 247644 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 10795845 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 10236713 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 21032558 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 10795845 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 10236713 # number of overall hits
-system.cpu0.dcache.overall_hits::total 21032558 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 335526 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 413210 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 748736 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1620906 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 1341470 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2962376 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7397 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6130 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 13527 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1956432 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 1754680 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 3711112 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1956432 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 1754680 # number of overall misses
-system.cpu0.dcache.overall_misses::total 3711112 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5370959618 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6018353236 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 11389312854 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84349105443 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64286693931 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 148635799374 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105098996 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82392993 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 187491989 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 91000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 89720065061 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 70305047167 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 160025112228 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 89720065061 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 70305047167 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 160025112228 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 7379776 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 7140342 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 14520118 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 5372501 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 4851051 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 10223552 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124253 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132401 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119518 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128133 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 247651 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 12752277 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 11991393 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 24743670 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 12752277 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 11991393 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 24743670 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045466 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057870 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.051565 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.301704 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.276532 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.289760 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059532 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046299 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052705 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000039 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000028 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.153418 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.146328 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.149982 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.153418 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.146328 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.149982 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16007.580986 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14564.877994 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15211.386729 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 52038.246168 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47922.572947 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 50174.521862 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14208.327160 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13440.945024 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13860.574333 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45859.025543 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40067.161629 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 43120.528895 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45859.025543 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40067.161629 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 43120.528895 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 36695 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 25289 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 3463 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 288 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.596304 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 87.809028 # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses 101726761 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 101726761 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 7076892 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 6698233 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 13775125 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3751457 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 3500966 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 7252423 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118146 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 125300 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 243446 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120516 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 127110 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 247626 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 10828349 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 10199199 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 21027548 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 10828349 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 10199199 # number of overall hits
+system.cpu0.dcache.overall_hits::total 21027548 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 365609 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 402058 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 767667 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1663469 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 1307220 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 2970689 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7411 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6147 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 13558 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 9 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data 9 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 2029078 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 1709278 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 3738356 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 2029078 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 1709278 # number of overall misses
+system.cpu0.dcache.overall_misses::total 3738356 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5771940837 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5897981485 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 11669922322 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84085334445 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 56096709102 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 140182043547 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106232248 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 81884247 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 188116495 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 129501 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 129501 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 259002 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 89857275282 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 61994690587 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 151851965869 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 89857275282 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 61994690587 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 151851965869 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 7442501 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 7100291 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 14542792 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 5414926 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 4808186 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 10223112 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125557 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131447 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 257004 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 120525 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127119 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 247644 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 12857427 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 11908477 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 24765904 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 12857427 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 11908477 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 24765904 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.049124 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.056626 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.052787 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.307201 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.271874 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.290586 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059025 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046764 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052754 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000075 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000071 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.157814 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.143535 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.150948 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.157814 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.143535 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.150948 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15787.195712 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14669.479242 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15201.802763 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50548.182410 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42912.982591 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 47188.394190 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14334.401295 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13321.009761 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13874.944313 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14389 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14389 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14389 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44284.781207 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36269.518818 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 40619.985328 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44284.781207 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36269.518818 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 40619.985328 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 36311 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 24635 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 3444 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 311 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.543264 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 79.212219 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 607907 # number of writebacks
-system.cpu0.dcache.writebacks::total 607907 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 148329 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 214670 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 362999 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1486511 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1226891 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 2713402 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 703 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 661 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1364 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1634840 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data 1441561 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 3076401 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1634840 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data 1441561 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 3076401 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187197 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 198540 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 385737 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 134395 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 114579 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 248974 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6694 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5469 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12163 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 321592 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 313119 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 634711 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 321592 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 313119 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 634711 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2595681199 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2634071602 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5229752801 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6377279279 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5102642760 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11479922039 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 83521753 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63731007 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147252760 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 77000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8972960478 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7736714362 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 16709674840 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8972960478 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7736714362 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 16709674840 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91614967500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90722197000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182337164500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13706653581 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13072228739 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26778882320 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105321621081 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103794425739 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209116046820 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025366 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027805 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026566 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025015 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023619 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053874 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041306 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047391 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000039 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.025651 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.025651 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13866.040583 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13267.208633 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13557.819968 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47451.759954 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44533.839185 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46108.919160 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12477.106812 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11653.137137 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12106.615144 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 608464 # number of writebacks
+system.cpu0.dcache.writebacks::total 608464 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174205 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 207237 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 381442 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1526591 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1195009 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 2721600 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 704 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 669 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1700796 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 1402246 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 3103042 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1700796 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 1402246 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 3103042 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191404 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 194821 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 386225 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 136878 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 112211 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 249089 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6707 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5478 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 9 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 328282 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 307032 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 635314 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 328282 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 307032 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 635314 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2672225710 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2597817092 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5270042802 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6526900100 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4738022235 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11264922335 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84662502 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63153752 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147816254 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 111499 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 111499 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 222998 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9199125810 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7335839327 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 16534965137 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9199125810 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7335839327 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 16534965137 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91653477500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90683023500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336501000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13720132000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13077337591 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26797469591 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105373609500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103760361091 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209133970591 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025718 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026558 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025278 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023337 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024365 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053418 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041675 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000075 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000071 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13961.180069 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13334.379210 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13645.006931 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47684.069756 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42224.222536 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45224.487372 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12623.006113 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11528.614823 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.001559 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12388.777778 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12388.777778 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12388.777778 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 7300035 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5887077 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 345091 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 4651296 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3771120 # Number of BTB hits
+system.cpu1.branchPred.lookups 7344792 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5924572 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 342317 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 4758265 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3794052 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 81.076758 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 673548 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 34495 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 79.736038 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 685317 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 35371 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25450161 # DTB read hits
-system.cpu1.dtb.read_misses 36388 # DTB read misses
-system.cpu1.dtb.write_hits 5568332 # DTB write hits
-system.cpu1.dtb.write_misses 8538 # DTB write misses
+system.cpu1.dtb.read_hits 25350014 # DTB read hits
+system.cpu1.dtb.read_misses 36246 # DTB read misses
+system.cpu1.dtb.write_hits 5533315 # DTB write hits
+system.cpu1.dtb.write_misses 8540 # DTB write misses
system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2244 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 247 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 5471 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1908 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25486549 # DTB read accesses
-system.cpu1.dtb.write_accesses 5576870 # DTB write accesses
+system.cpu1.dtb.read_accesses 25386260 # DTB read accesses
+system.cpu1.dtb.write_accesses 5541855 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31018493 # DTB hits
-system.cpu1.dtb.misses 44926 # DTB misses
-system.cpu1.dtb.accesses 31063419 # DTB accesses
+system.cpu1.dtb.hits 30883329 # DTB hits
+system.cpu1.dtb.misses 44786 # DTB misses
+system.cpu1.dtb.accesses 30928115 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 5679651 # ITB inst hits
-system.cpu1.itb.inst_misses 6870 # ITB inst misses
+system.cpu1.itb.inst_hits 5683844 # ITB inst hits
+system.cpu1.itb.inst_misses 6848 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2692 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2653 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1570 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1514 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 5686521 # ITB inst accesses
-system.cpu1.itb.hits 5679651 # DTB hits
-system.cpu1.itb.misses 6870 # DTB misses
-system.cpu1.itb.accesses 5686521 # DTB accesses
-system.cpu1.numCycles 236844574 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 5690692 # ITB inst accesses
+system.cpu1.itb.hits 5683844 # DTB hits
+system.cpu1.itb.misses 6848 # DTB misses
+system.cpu1.itb.accesses 5690692 # DTB accesses
+system.cpu1.numCycles 235812118 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 14466322 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 45074741 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 7300035 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4444668 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 9928510 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2284755 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 83810 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 49428019 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 1085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 1865 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 44064 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 1232877 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 5677454 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 353029 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3058 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 76760101 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.724873 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.076516 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 14488159 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 45028124 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 7344792 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4479369 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 9950354 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2325910 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 82893 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 46948697 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 1099 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 1893 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 45519 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 1268155 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 161 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5681743 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 353393 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2950 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 74402978 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.748631 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.104884 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 66839787 87.08% 87.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 628644 0.82% 87.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 837705 1.09% 88.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1128430 1.47% 90.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1025116 1.34% 91.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 549692 0.72% 92.51% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1265677 1.65% 94.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 371391 0.48% 94.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4113659 5.36% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 64461074 86.64% 86.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 633258 0.85% 87.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 845202 1.14% 88.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1118143 1.50% 90.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1030578 1.39% 91.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 551741 0.74% 92.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1296054 1.74% 94.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 370486 0.50% 94.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4096442 5.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 76760101 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.030822 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.190314 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 15575790 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 50164874 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 8875530 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 651724 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1490012 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 958602 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 85804 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 53028773 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 286820 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1490012 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 16419373 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 19259514 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 27698423 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 8639214 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3251470 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 50560580 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 221 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 607469 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 2007282 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 572 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 52946210 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 233908561 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 213841042 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 5698 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 39345682 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 13600527 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 580708 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 537933 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 6505084 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9729570 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6369599 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 877361 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1114434 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 47034811 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 984793 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 60942495 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 91566 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 9279731 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 23349761 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 250555 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 76760101 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.793935 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.504235 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 74402978 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.031147 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.190949 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 15290128 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 48029788 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 9010807 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 535995 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1534066 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 962796 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 84486 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 53087117 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 281620 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1534066 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 16089413 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 6996685 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 28422508 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 8819964 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 12538212 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 50579819 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 715 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 8590875 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 9852379 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 1395671 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 1301 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 52976488 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 233969396 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 213834273 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 5207 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 38971918 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 14004569 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 583497 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 540607 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 5363476 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 9768473 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6353478 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 903299 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1144541 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 47001226 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 985413 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 60595640 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 98989 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 9593116 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 24473464 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 250944 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 74402978 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.814425 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.533021 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 54532875 71.04% 71.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 7326090 9.54% 80.59% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3469207 4.52% 85.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2884980 3.76% 88.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6118042 7.97% 96.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1370862 1.79% 98.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 772587 1.01% 99.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 222613 0.29% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 62845 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 52794785 70.96% 70.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 6823804 9.17% 80.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3272663 4.40% 84.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 2786608 3.75% 88.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6272134 8.43% 96.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1319081 1.77% 98.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 820611 1.10% 99.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 247257 0.33% 99.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 66035 0.09% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 76760101 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 74402978 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 29035 0.66% 0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 5 0.00% 0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 29526 0.66% 0.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4177111 94.84% 95.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4196905 94.38% 95.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 220217 4.95% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 13548 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 28887832 47.40% 47.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46127 0.08% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 887 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 26105748 42.84% 90.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 5888317 9.66% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 13541 0.02% 0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 28679065 47.33% 47.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 45344 0.07% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 858 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 26009717 42.92% 90.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 5847084 9.65% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 60942495 # Type of FU issued
-system.cpu1.iq.rate 0.257310 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4404233 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.072269 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 203173539 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 57307144 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 42269826 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 12116 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 6726 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 5381 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 65326800 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 6380 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 306796 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 60595640 # Type of FU issued
+system.cpu1.iq.rate 0.256966 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4446652 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.073382 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 200172970 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 57588554 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 41991709 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 11520 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 6240 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 4992 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 65022566 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 6185 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 323560 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 1984154 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3003 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 15089 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 749009 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2067890 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 2468 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 15600 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 783792 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 17027364 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 331342 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 16950409 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 331839 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1490012 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 14823463 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 222107 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 48121220 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 96425 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9729570 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6369599 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 709638 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 48371 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 4239 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 15089 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 167591 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 133565 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 301156 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 59912848 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25789830 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1029647 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1534066 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 5578937 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 735039 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 48101549 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 89840 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 9768473 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6353478 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 710230 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 138266 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 531900 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 15600 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 167974 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 132221 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 300195 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 59563474 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 25690610 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1032166 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 101616 # number of nop insts executed
-system.cpu1.iew.exec_refs 31626536 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 5854246 # Number of branches executed
-system.cpu1.iew.exec_stores 5836706 # Number of stores executed
-system.cpu1.iew.exec_rate 0.252963 # Inst execution rate
-system.cpu1.iew.wb_sent 59450905 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 42275207 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 23556720 # num instructions producing a value
-system.cpu1.iew.wb_consumers 42880647 # num instructions consuming a value
+system.cpu1.iew.exec_nop 114910 # number of nop insts executed
+system.cpu1.iew.exec_refs 31485549 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5840798 # Number of branches executed
+system.cpu1.iew.exec_stores 5794939 # Number of stores executed
+system.cpu1.iew.exec_rate 0.252589 # Inst execution rate
+system.cpu1.iew.wb_sent 59096440 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 41996701 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 23719594 # num instructions producing a value
+system.cpu1.iew.wb_consumers 43668575 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.178493 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.549356 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.178094 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.543173 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 9147109 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 734238 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 260548 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 75270089 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.511960 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.483838 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 9469311 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 734469 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 259123 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 72868911 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.524128 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.502288 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 60996835 81.04% 81.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 7463530 9.92% 90.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1923766 2.56% 93.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1066165 1.42% 94.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 822611 1.09% 96.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 493470 0.66% 96.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 696092 0.92% 97.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 369554 0.49% 98.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1438066 1.91% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 58802570 80.70% 80.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 7335717 10.07% 90.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1834357 2.52% 93.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1110131 1.52% 94.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 806352 1.11% 95.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 478738 0.66% 96.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 708592 0.97% 97.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 352493 0.48% 98.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1439961 1.98% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 75270089 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 30381625 # Number of instructions committed
-system.cpu1.commit.committedOps 38535309 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 72868911 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 30042313 # Number of instructions committed
+system.cpu1.commit.committedOps 38192613 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13366006 # Number of memory references committed
-system.cpu1.commit.loads 7745416 # Number of loads committed
-system.cpu1.commit.membars 193947 # Number of memory barriers committed
-system.cpu1.commit.branches 5114433 # Number of branches committed
-system.cpu1.commit.fp_insts 5338 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 34292499 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 482077 # Number of function calls committed.
+system.cpu1.commit.refs 13270269 # Number of memory references committed
+system.cpu1.commit.loads 7700583 # Number of loads committed
+system.cpu1.commit.membars 192827 # Number of memory barriers committed
+system.cpu1.commit.branches 5091642 # Number of branches committed
+system.cpu1.commit.fp_insts 4942 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 33962282 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 485556 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 25125071 65.20% 65.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 43345 0.11% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 887 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 7745416 20.10% 85.41% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 5620590 14.59% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 24878693 65.14% 65.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 42793 0.11% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 858 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 7700583 20.16% 85.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 5569686 14.58% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 38535309 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1438066 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 38192613 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1439961 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 120626402 # The number of ROB reads
-system.cpu1.rob.rob_writes 96898257 # The number of ROB writes
-system.cpu1.timesIdled 866184 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 160084473 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2317121408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 30313431 # Number of Instructions Simulated
-system.cpu1.committedOps 38467115 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 7.813189 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 7.813189 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.127989 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.127989 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 271901021 # number of integer regfile reads
-system.cpu1.int_regfile_writes 43646883 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 45279 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 42402 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 133121444 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 593543 # number of misc regfile writes
+system.cpu1.rob.rob_reads 118199712 # The number of ROB reads
+system.cpu1.rob.rob_writes 96901530 # The number of ROB writes
+system.cpu1.timesIdled 866503 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 161409140 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2317329341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 29966199 # Number of Instructions Simulated
+system.cpu1.committedOps 38116499 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 7.869270 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 7.869270 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.127077 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.127077 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 270334360 # number of integer regfile reads
+system.cpu1.int_regfile_writes 43344614 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 45048 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 42280 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 130449609 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 594503 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1734475259291 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1734475259291 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1734330533049 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1734330533049 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83062 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
+load_offset=0
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-readfile=tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-x86.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
pio=system.iobus.master[9]
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[3]
[system.smbios_table]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 22:15:55
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Jun 21 2014 11:13:07
+gem5 started Jun 21 2014 22:16:40
+gem5 executing on phenom
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5133933067000 because m5_exit instruction encountered
+Exiting @ tick 5137926173000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.141960 # Number of seconds simulated
-sim_ticks 5141959613000 # Number of ticks simulated
-final_tick 5141959613000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.137926 # Number of seconds simulated
+sim_ticks 5137926173000 # Number of ticks simulated
+final_tick 5137926173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 152486 # Simulator instruction rate (inst/s)
-host_op_rate 301416 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1922658876 # Simulator tick rate (ticks/s)
-host_mem_usage 770128 # Number of bytes of host memory used
-host_seconds 2674.40 # Real time elapsed on the host
-sim_insts 407807707 # Number of instructions simulated
-sim_ops 806107146 # Number of ops (including micro ops) simulated
+host_inst_rate 165389 # Simulator instruction rate (inst/s)
+host_op_rate 326926 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2083966500 # Simulator tick rate (ticks/s)
+host_mem_usage 742788 # Number of bytes of host memory used
+host_seconds 2465.46 # Real time elapsed on the host
+sim_insts 407759509 # Number of instructions simulated
+sim_ops 806020953 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide 2476992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide 2427584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1035072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10749056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14265280 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1035072 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1035072 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9521344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9521344 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38703 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1035776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10808512 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14275968 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1035776 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1035776 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9555328 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9555328 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 37931 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16173 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 167954 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 222895 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 148771 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 148771 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 481721 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 747 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 16184 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 168883 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 223062 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149302 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149302 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 472483 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 735 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 201299 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2090459 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2774289 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 201299 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 201299 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1851696 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1851696 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1851696 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 481721 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 747 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 201594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2103672 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2778547 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 201594 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 201594 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1859764 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1859764 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1859764 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 472483 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 735 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 201299 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2090459 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4625984 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 222895 # Number of read requests accepted
-system.physmem.writeReqs 148771 # Number of write requests accepted
-system.physmem.readBursts 222895 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 148771 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 14256576 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9520064 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 14265280 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9521344 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst 201594 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2103672 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4638310 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 223062 # Number of read requests accepted
+system.physmem.writeReqs 149302 # Number of write requests accepted
+system.physmem.readBursts 223062 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 149302 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 14267968 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9553728 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 14275968 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9555328 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1680 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 14406 # Per bank write bursts
-system.physmem.perBankRdBursts::1 13692 # Per bank write bursts
-system.physmem.perBankRdBursts::2 14137 # Per bank write bursts
-system.physmem.perBankRdBursts::3 13444 # Per bank write bursts
-system.physmem.perBankRdBursts::4 14027 # Per bank write bursts
-system.physmem.perBankRdBursts::5 13372 # Per bank write bursts
-system.physmem.perBankRdBursts::6 13359 # Per bank write bursts
-system.physmem.perBankRdBursts::7 13805 # Per bank write bursts
-system.physmem.perBankRdBursts::8 13762 # Per bank write bursts
-system.physmem.perBankRdBursts::9 13592 # Per bank write bursts
-system.physmem.perBankRdBursts::10 13956 # Per bank write bursts
-system.physmem.perBankRdBursts::11 13564 # Per bank write bursts
-system.physmem.perBankRdBursts::12 14528 # Per bank write bursts
-system.physmem.perBankRdBursts::13 14698 # Per bank write bursts
-system.physmem.perBankRdBursts::14 14291 # Per bank write bursts
-system.physmem.perBankRdBursts::15 14126 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9807 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9166 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9421 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8835 # Per bank write bursts
-system.physmem.perBankWrBursts::4 9422 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8917 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8763 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9221 # Per bank write bursts
-system.physmem.perBankWrBursts::8 9116 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9134 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9470 # Per bank write bursts
-system.physmem.perBankWrBursts::11 8904 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9718 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9806 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9580 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9471 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 1775 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 14642 # Per bank write bursts
+system.physmem.perBankRdBursts::1 13963 # Per bank write bursts
+system.physmem.perBankRdBursts::2 14587 # Per bank write bursts
+system.physmem.perBankRdBursts::3 13341 # Per bank write bursts
+system.physmem.perBankRdBursts::4 14143 # Per bank write bursts
+system.physmem.perBankRdBursts::5 13526 # Per bank write bursts
+system.physmem.perBankRdBursts::6 13007 # Per bank write bursts
+system.physmem.perBankRdBursts::7 13123 # Per bank write bursts
+system.physmem.perBankRdBursts::8 13660 # Per bank write bursts
+system.physmem.perBankRdBursts::9 13743 # Per bank write bursts
+system.physmem.perBankRdBursts::10 13657 # Per bank write bursts
+system.physmem.perBankRdBursts::11 13667 # Per bank write bursts
+system.physmem.perBankRdBursts::12 14668 # Per bank write bursts
+system.physmem.perBankRdBursts::13 14755 # Per bank write bursts
+system.physmem.perBankRdBursts::14 14289 # Per bank write bursts
+system.physmem.perBankRdBursts::15 14166 # Per bank write bursts
+system.physmem.perBankWrBursts::0 10056 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9321 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9829 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8830 # Per bank write bursts
+system.physmem.perBankWrBursts::4 9558 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8986 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8593 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8747 # Per bank write bursts
+system.physmem.perBankWrBursts::8 8969 # Per bank write bursts
+system.physmem.perBankWrBursts::9 9193 # Per bank write bursts
+system.physmem.perBankWrBursts::10 9160 # Per bank write bursts
+system.physmem.perBankWrBursts::11 9087 # Per bank write bursts
+system.physmem.perBankWrBursts::12 9894 # Per bank write bursts
+system.physmem.perBankWrBursts::13 9881 # Per bank write bursts
+system.physmem.perBankWrBursts::14 9649 # Per bank write bursts
+system.physmem.perBankWrBursts::15 9524 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 5141959559500 # Total gap between requests
+system.physmem.totGap 5137926057000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 222895 # Read request sizes (log2)
+system.physmem.readPktSize::6 223062 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 148771 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 173187 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 13769 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5947 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3181 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3035 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3711 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 3299 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 3149 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2487 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1694 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1507 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1005 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 833 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 764 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 718 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 557 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 456 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 376 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 149302 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 173856 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 14004 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5938 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3116 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2938 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3695 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 3277 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 3105 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2401 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1802 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1616 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1416 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1120 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1019 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 848 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 763 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 690 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 540 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 420 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 347 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1818 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6295 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6657 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6807 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6895 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7018 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7687 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7974 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8492 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8737 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8899 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 9209 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 9147 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 9322 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 9232 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 9176 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 1873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1747 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 1906 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 1843 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 1738 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 1562 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1696 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1831 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6323 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6727 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6895 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7003 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7385 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 8119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8610 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 8803 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8913 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 9245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 9110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 9225 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 9112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 9115 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1831 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 1696 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 1783 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 1762 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 1670 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 1529 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1335 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1057 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 632 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 196 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 652 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 516 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 372 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 247 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 94 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 74587 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 318.776409 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 185.138812 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 338.199277 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 28275 37.91% 37.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 16828 22.56% 60.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7503 10.06% 70.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4244 5.69% 76.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3057 4.10% 80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2068 2.77% 83.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1382 1.85% 84.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1175 1.58% 86.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 10055 13.48% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 74587 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 8285 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 26.884007 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 527.034010 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 8284 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 75897 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 313.867900 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 181.633012 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 336.529129 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 29529 38.91% 38.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 16915 22.29% 61.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7566 9.97% 71.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4259 5.61% 76.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2981 3.93% 80.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2008 2.65% 83.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1459 1.92% 85.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1171 1.54% 86.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 10009 13.19% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 75897 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 8307 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.835320 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 526.600201 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 8306 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 8285 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 8285 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.954255 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.428609 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 5.676130 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 6158 74.33% 74.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 1338 16.15% 90.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 52 0.63% 91.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 77 0.93% 92.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 47 0.57% 92.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 55 0.66% 93.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 103 1.24% 94.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 89 1.07% 95.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 47 0.57% 96.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35 58 0.70% 96.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37 37 0.45% 97.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39 45 0.54% 97.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41 69 0.83% 98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43 27 0.33% 99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45 11 0.13% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47 16 0.19% 99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49 22 0.27% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51 4 0.05% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53 7 0.08% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55 3 0.04% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57 2 0.02% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59 3 0.04% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61 5 0.06% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63 4 0.05% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-65 3 0.04% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::66-67 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-81 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-89 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 8285 # Writes before turning the bus around for reads
-system.physmem.totQLat 4923822749 # Total ticks spent queuing
-system.physmem.totMemAccLat 9100553999 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1113795000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 22103.81 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 8307 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 8307 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.970025 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.437156 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 5.734930 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17 6174 74.32% 74.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19 1334 16.06% 90.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21 66 0.79% 91.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23 64 0.77% 91.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25 51 0.61% 92.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27 45 0.54% 93.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29 113 1.36% 94.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31 87 1.05% 95.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33 56 0.67% 96.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35 56 0.67% 96.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37 34 0.41% 97.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39 52 0.63% 97.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41 60 0.72% 98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43 31 0.37% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45 10 0.12% 99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47 10 0.12% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49 28 0.34% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51 7 0.08% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53 4 0.05% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55 3 0.04% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57 5 0.06% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59 4 0.05% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61 2 0.02% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63 3 0.04% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-65 2 0.02% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::66-67 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-69 2 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-77 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::78-79 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::90-91 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 8307 # Writes before turning the bus around for reads
+system.physmem.totQLat 4966355250 # Total ticks spent queuing
+system.physmem.totMemAccLat 9146424000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1114685000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 22276.94 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 40853.81 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 41026.94 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.78 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.78 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing
-system.physmem.readRowHits 186870 # Number of row buffer hits during reads
-system.physmem.writeRowHits 110052 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.97 # Row buffer hit rate for writes
-system.physmem.avgGap 13834893.59 # Average gap between requests
-system.physmem.pageHitRate 79.92 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4934274417750 # Time in different power states
-system.physmem.memoryStateTime::REF 171701140000 # Time in different power states
+system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.93 # Average write queue length when enqueuing
+system.physmem.readRowHits 185691 # Number of row buffer hits during reads
+system.physmem.writeRowHits 110625 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.09 # Row buffer hit rate for writes
+system.physmem.avgGap 13798127.79 # Average gap between requests
+system.physmem.pageHitRate 79.60 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4930575819000 # Time in different power states
+system.physmem.memoryStateTime::REF 171566460000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 35983950250 # Time in different power states
+system.physmem.memoryStateTime::ACT 35783789000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 5095093 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 662466 # Transaction distribution
-system.membus.trans_dist::ReadResp 662464 # Transaction distribution
-system.membus.trans_dist::WriteReq 13782 # Transaction distribution
-system.membus.trans_dist::WriteResp 13782 # Transaction distribution
-system.membus.trans_dist::Writeback 148771 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution
-system.membus.trans_dist::ReadExReq 179320 # Transaction distribution
-system.membus.trans_dist::ReadExResp 179319 # Transaction distribution
-system.membus.trans_dist::MessageReq 1645 # Transaction distribution
-system.membus.trans_dist::MessageResp 1645 # Transaction distribution
-system.membus.trans_dist::BadAddressError 2 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775082 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475021 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721191 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132996 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 132996 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1857477 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550161 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322944 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20114933 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463680 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 5463680 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 25585193 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 25585193 # Total data (bytes)
-system.membus.snoop_data_through_bus 613568 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 250592000 # Layer occupancy (ticks)
+system.membus.throughput 5117506 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 662560 # Transaction distribution
+system.membus.trans_dist::ReadResp 662552 # Transaction distribution
+system.membus.trans_dist::WriteReq 13764 # Transaction distribution
+system.membus.trans_dist::WriteResp 13764 # Transaction distribution
+system.membus.trans_dist::Writeback 149302 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2261 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1794 # Transaction distribution
+system.membus.trans_dist::ReadExReq 180173 # Transaction distribution
+system.membus.trans_dist::ReadExResp 180170 # Transaction distribution
+system.membus.trans_dist::MessageReq 1643 # Transaction distribution
+system.membus.trans_dist::MessageResp 1643 # Transaction distribution
+system.membus.trans_dist::BadAddressError 8 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471036 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775076 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477605 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723733 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132228 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 132228 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1859247 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241801 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550149 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18417024 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20208974 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5414272 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 5414272 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 25629818 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 25629818 # Total data (bytes)
+system.membus.snoop_data_through_bus 663552 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 250523000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 583283000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 583102000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1610033997 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1620731000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 3152758703 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 3164060842 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 429601748 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 429649499 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47571 # number of replacements
-system.iocache.tags.tagsinuse 0.128712 # Cycle average of tags in use
+system.iocache.tags.replacements 47575 # number of replacements
+system.iocache.tags.tagsinuse 0.116331 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4992977133000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128712 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008045 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.008045 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 4992948576000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116331 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007271 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.007271 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428634 # Number of tag accesses
-system.iocache.tags.data_accesses 428634 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 906 # number of ReadReq misses
+system.iocache.tags.tag_accesses 428670 # Number of tag accesses
+system.iocache.tags.data_accesses 428670 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47626 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses
-system.iocache.overall_misses::total 47626 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147491196 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 147491196 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11109159898 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 11109159898 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 11256651094 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 11256651094 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 11256651094 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 11256651094 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47630 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses
+system.iocache.overall_misses::total 47630 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151620185 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 151620185 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11039278588 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 11039278588 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 11190898773 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 11190898773 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 11190898773 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 11190898773 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 162793.814570 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 237781.675899 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 236355.165120 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 236355.165120 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 159859 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166615.587912 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 166615.587912 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 236285.928682 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 236285.928682 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 234954.834621 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 234954.834621 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 234954.834621 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 234954.834621 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 159238 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 14672 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 14593 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.895515 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.911944 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100353196 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 100353196 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8677810402 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8677810402 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8778163598 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8778163598 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104274685 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 104274685 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8607905090 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8607905090 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8712179775 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8712179775 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8712179775 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8712179775 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114587.565934 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 114587.565934 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 184244.543878 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 184244.543878 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 182913.705123 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 182913.705123 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.throughput 637150 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 225562 # Transaction distribution
-system.iobus.trans_dist::ReadResp 225562 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
+system.iobus.throughput 637650 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 225557 # Transaction distribution
+system.iobus.trans_dist::ReadResp 225557 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57591 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57591 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427354 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 569626 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 471036 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 569582 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213677 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 3276200 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 3276200 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 3930346 # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total 241801 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 3276197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 3276197 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 3919904 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy 213678000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 424685346 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 424855274 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 460165000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 53671252 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 53596501 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 85633263 # Number of BP lookups
-system.cpu.branchPred.condPredicted 85633263 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 884686 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 79267379 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 77548662 # Number of BTB hits
+system.cpu.branchPred.lookups 85854110 # Number of BP lookups
+system.cpu.branchPred.condPredicted 85854110 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 890492 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 79431123 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 77651636 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.831747 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1440338 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 180105 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.759711 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1460640 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 181048 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 453234333 # number of cpu cycles simulated
+system.cpu.numCycles 452853570 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 25483623 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 422835891 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85633263 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 78989000 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 162683938 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4002747 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 108573 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 70983982 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 43526 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 92374 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8487571 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 384793 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 2466 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 262469836 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.181706 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.411661 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 25683785 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 423946474 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 85854110 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79112276 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 162997927 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4233083 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 105681 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 69250991 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 42777 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 91487 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 266 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8611652 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 409614 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 2534 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 261469410 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.201181 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.413215 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 100201994 38.18% 38.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1531970 0.58% 38.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71824716 27.36% 66.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 909581 0.35% 66.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1572022 0.60% 67.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2391233 0.91% 67.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1015593 0.39% 68.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1327813 0.51% 68.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81694914 31.13% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 98890192 37.82% 37.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1558006 0.60% 38.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71842115 27.48% 65.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 921619 0.35% 66.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1585920 0.61% 66.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2431144 0.93% 67.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1036910 0.40% 68.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1345104 0.51% 68.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 81858400 31.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 262469836 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.188938 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.932930 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29410093 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 68121182 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 158520657 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3344277 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3073627 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 832752013 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3073627 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 32108860 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 42947155 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 12423337 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158815296 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 13101561 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 829828808 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20476 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6069323 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 5155919 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 991491995 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1800757525 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1107104494 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964043985 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27448008 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 454148 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 459927 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 29603104 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 16744391 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 9834089 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1098610 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 922271 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 825029586 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1184674 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 821050392 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 152353 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 19282759 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 29404306 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 129800 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 262469836 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.128170 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.399623 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 261469410 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.189585 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.936167 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29046589 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 66961601 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159616384 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 2548340 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3296496 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 834624632 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 895 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3296496 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 31320829 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 35759496 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 12826241 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159575235 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 18691113 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 831621243 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 271968 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 7201596 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 103405 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 9490411 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 993545092 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1805477878 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1109904628 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 111 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 963933701 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 29611389 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 457228 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 464601 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 24223020 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 16966534 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 9968316 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1221781 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 988150 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 826572087 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1194475 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 821819105 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 208862 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 20915933 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 32275833 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 139879 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 261469410 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.143079 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.407689 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 76068971 28.98% 28.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15764450 6.01% 34.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10561557 4.02% 39.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7380977 2.81% 41.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75732754 28.85% 70.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3744713 1.43% 72.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72297753 27.55% 99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 770490 0.29% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 148171 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 76437702 29.23% 29.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14614697 5.59% 34.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10065724 3.85% 38.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7027094 2.69% 41.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75658650 28.94% 70.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3979218 1.52% 71.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72575299 27.76% 99.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 879014 0.34% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 232012 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 262469836 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 261469410 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 351121 33.32% 33.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 242 0.02% 33.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 235 0.02% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 548827 52.08% 85.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 153397 14.56% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 395534 35.48% 35.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 246 0.02% 35.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 260 0.02% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 578947 51.93% 87.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 139812 12.54% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 310274 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 793553745 96.65% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 150127 0.02% 96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 124319 0.02% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17682976 2.15% 98.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9228951 1.12% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 313841 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 794169455 96.64% 96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 150148 0.02% 96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 125336 0.02% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 17790783 2.16% 98.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9269542 1.13% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 821050392 # Type of FU issued
-system.cpu.iq.rate 1.811536 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1053822 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1905885622 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 845507474 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 817131376 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 174 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 198 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 821819105 # Type of FU issued
+system.cpu.iq.rate 1.814757 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1114799 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001357 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1906543911 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 848693742 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 817833447 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 176 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 821793858 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 822619981 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1694774 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 1787791 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2743773 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 18703 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12097 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1404751 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2974113 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 16000 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 13012 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1545780 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1931902 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 12205 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1935112 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 35450 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3073627 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 31062869 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2159597 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 826214260 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 248339 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 16744391 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 9834089 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 689465 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1620816 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 13300 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12097 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 498594 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 510068 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1008662 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 819639552 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17378500 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1410839 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3296496 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 15966541 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 12762115 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 827766562 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 204474 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 16966534 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 9968316 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 698992 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1766485 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 10560079 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 13012 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 503157 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 519909 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1023066 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 820377360 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17471183 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1441744 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26423310 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83104184 # Number of branches executed
-system.cpu.iew.exec_stores 9044810 # Number of stores executed
-system.cpu.iew.exec_rate 1.808423 # Inst execution rate
-system.cpu.iew.wb_sent 819235043 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 817131426 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 638623234 # num instructions producing a value
-system.cpu.iew.wb_consumers 1043962608 # num instructions consuming a value
+system.cpu.iew.exec_refs 26545601 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83164783 # Number of branches executed
+system.cpu.iew.exec_stores 9074418 # Number of stores executed
+system.cpu.iew.exec_rate 1.811573 # Inst execution rate
+system.cpu.iew.wb_sent 819943769 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 817833497 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 640559141 # num instructions producing a value
+system.cpu.iew.wb_consumers 1047723157 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.802890 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.805956 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611382 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 19998130 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1054874 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 894775 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 259396209 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.107629 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.863349 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 21640086 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1054596 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 900184 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 258172914 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.122020 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.868515 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 87828444 33.86% 33.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11868241 4.58% 38.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3842531 1.48% 39.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74752258 28.82% 68.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2384729 0.92% 69.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1479281 0.57% 70.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 859408 0.33% 70.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70845236 27.31% 97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5536081 2.13% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 87519981 33.90% 33.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11178946 4.33% 38.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3524931 1.37% 39.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74556840 28.88% 68.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2487891 0.96% 69.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1503617 0.58% 70.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 865491 0.34% 70.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70822706 27.43% 97.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5712511 2.21% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 259396209 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407807707 # Number of instructions committed
-system.cpu.commit.committedOps 806107146 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 258172914 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407759509 # Number of instructions committed
+system.cpu.commit.committedOps 806020953 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22429955 # Number of memory references committed
-system.cpu.commit.loads 14000617 # Number of loads committed
-system.cpu.commit.membars 474711 # Number of memory barriers committed
-system.cpu.commit.branches 82167469 # Number of branches committed
+system.cpu.commit.refs 22414956 # Number of memory references committed
+system.cpu.commit.loads 13992420 # Number of loads committed
+system.cpu.commit.membars 474659 # Number of memory barriers committed
+system.cpu.commit.branches 82156165 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 734952495 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1155627 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 174437 0.02% 0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 783236239 97.16% 97.18% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 144862 0.02% 97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 121653 0.02% 97.22% # Class of committed instruction
+system.cpu.commit.int_insts 734866809 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1155346 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 174342 0.02% 0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 783165220 97.16% 97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 144784 0.02% 97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 121651 0.02% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 14000617 1.74% 98.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 8429338 1.05% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 13992420 1.74% 98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 8422536 1.04% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 806107146 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5536081 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 806020953 # Class of committed instruction
+system.cpu.commit.bw_lim_events 5712511 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1079887016 # The number of ROB reads
-system.cpu.rob.rob_writes 1655298855 # The number of ROB writes
-system.cpu.timesIdled 1259672 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 190764497 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9830690598 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407807707 # Number of Instructions Simulated
-system.cpu.committedOps 806107146 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.111392 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.111392 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.899772 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.899772 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1088844162 # number of integer regfile reads
-system.cpu.int_regfile_writes 653876789 # number of integer regfile writes
+system.cpu.rob.rob_reads 1080043164 # The number of ROB reads
+system.cpu.rob.rob_writes 1658634797 # The number of ROB writes
+system.cpu.timesIdled 1275471 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 191384160 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9823003775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407759509 # Number of Instructions Simulated
+system.cpu.committedOps 806020953 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.110590 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.110590 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.900422 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.900422 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1089597141 # number of integer regfile reads
+system.cpu.int_regfile_writes 654482969 # number of integer regfile writes
system.cpu.fp_regfile_reads 50 # number of floating regfile reads
-system.cpu.cc_regfile_reads 415644137 # number of cc regfile reads
-system.cpu.cc_regfile_writes 321521730 # number of cc regfile writes
-system.cpu.misc_regfile_reads 264115519 # number of misc regfile reads
-system.cpu.misc_regfile_writes 402672 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 53624827 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 3015737 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3015197 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13782 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13782 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1584798 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 336401 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 289692 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908205 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6128379 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19318 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159676 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8215578 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61059136 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207801717 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 607680 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5615104 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 275083637 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 275059381 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 677312 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4044441846 # Layer occupancy (ticks)
+system.cpu.cc_regfile_reads 415870022 # number of cc regfile reads
+system.cpu.cc_regfile_writes 321677512 # number of cc regfile writes
+system.cpu.misc_regfile_reads 264445635 # number of misc regfile reads
+system.cpu.misc_regfile_writes 402422 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 53724216 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 3026047 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3025482 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13764 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13764 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1581183 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2322 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2322 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 334322 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 287613 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928223 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126020 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18717 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 156212 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8229172 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61697728 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207710542 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 574144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5436928 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 275419342 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 275396046 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 635008 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 4043112921 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 568500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 546000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1434613560 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1449735220 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3141764506 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3140330868 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 14738244 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 14620748 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 107967138 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 106945143 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 953583 # number of replacements
-system.cpu.icache.tags.tagsinuse 509.342760 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 7479724 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 954095 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 7.839601 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 147639960250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 509.342760 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.994810 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.994810 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 963566 # number of replacements
+system.cpu.icache.tags.tagsinuse 509.311037 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 7590970 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 964078 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 7.873813 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 147613206250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 509.311037 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.994748 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.994748 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 9441724 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 9441724 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 7479724 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7479724 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7479724 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7479724 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7479724 # number of overall hits
-system.cpu.icache.overall_hits::total 7479724 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1007844 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1007844 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1007844 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1007844 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1007844 # number of overall misses
-system.cpu.icache.overall_misses::total 1007844 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14035582232 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14035582232 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14035582232 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14035582232 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14035582232 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14035582232 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 8487568 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8487568 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 8487568 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8487568 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 8487568 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8487568 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118744 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.118744 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.118744 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.118744 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.118744 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.118744 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13926.343990 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13926.343990 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13926.343990 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13926.343990 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 4168 # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses 9575846 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 9575846 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 7590970 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7590970 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 7590970 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 7590970 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 7590970 # number of overall hits
+system.cpu.icache.overall_hits::total 7590970 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1020680 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1020680 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1020680 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1020680 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1020680 # number of overall misses
+system.cpu.icache.overall_misses::total 1020680 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179701612 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14179701612 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14179701612 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14179701612 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14179701612 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14179701612 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 8611650 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 8611650 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 8611650 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 8611650 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 8611650 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 8611650 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118523 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.118523 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.118523 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.118523 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.118523 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.118523 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13892.406643 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13892.406643 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13892.406643 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13892.406643 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13892.406643 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13892.406643 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 4723 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 198 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 21.936842 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 23.853535 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53688 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 53688 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 53688 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 53688 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 53688 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 53688 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954156 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 954156 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 954156 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 954156 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 954156 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 954156 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587558437 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11587558437 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587558437 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11587558437 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587558437 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11587558437 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112418 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.112418 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.112418 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12144.301809 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12144.301809 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56484 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 56484 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 56484 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 56484 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 56484 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 56484 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 964196 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 964196 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 964196 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 964196 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 964196 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 964196 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11690907021 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11690907021 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11690907021 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11690907021 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11690907021 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11690907021 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.111964 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.111964 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.111964 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12125.031654 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12125.031654 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12125.031654 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12125.031654 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12125.031654 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12125.031654 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements 8939 # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse 6.031288 # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs 21114 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs 8953 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs 2.358316 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031288 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376956 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total 0.376956 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses 71741 # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses 71741 # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21134 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 21134 # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.replacements 8862 # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse 6.026427 # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs 19635 # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs 8877 # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs 2.211896 # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5109382719500 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.026427 # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376652 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total 0.376652 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses 68718 # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses 68718 # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 19738 # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total 19738 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21136 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 21136 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21136 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 21136 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 107949749 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total 107949749 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 107949749 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total 107949749 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 107949749 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total 107949749 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30957 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 30957 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 19740 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total 19740 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 19740 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 19740 # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9746 # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total 9746 # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9746 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total 9746 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9746 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total 9746 # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 105945749 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total 105945749 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 105945749 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total 105945749 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 105945749 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 105945749 # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 29484 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total 29484 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30959 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 30959 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30959 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 30959 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.317311 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.317311 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.317291 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total 0.317291 # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.317291 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total 0.317291 # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10989.488853 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10989.488853 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10989.488853 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10989.488853 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29486 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 29486 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29486 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total 29486 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.330552 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.330552 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.330530 # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total 0.330530 # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.330530 # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total 0.330530 # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10870.690437 # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10870.690437 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10870.690437 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10870.690437 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10870.690437 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10870.690437 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 1983 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 1983 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88296261 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 88296261 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 88296261 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 88296261 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 88296261 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 88296261 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.317311 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.317311 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.317291 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.317291 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8988.726560 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks 1636 # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total 1636 # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9746 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9746 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9746 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total 9746 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9746 # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total 9746 # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86450253 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86450253 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86450253 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86450253 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86450253 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86450253 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.330552 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.330552 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.330530 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.330530 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.330530 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.330530 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8870.331726 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8870.331726 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8870.331726 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements 70861 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 12.940736 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 90199 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 70877 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.272613 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 12.940736 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.808796 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total 0.808796 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.replacements 70197 # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse 14.820412 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs 92434 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs 70211 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs 1.316517 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5101611575500 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.820412 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.926276 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total 0.926276 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses 396218 # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses 396218 # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90199 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 90199 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90199 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 90199 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90199 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 90199 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71940 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 71940 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71940 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 71940 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71940 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 71940 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 878693205 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 878693205 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 878693205 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total 878693205 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 878693205 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total 878693205 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162139 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 162139 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162139 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 162139 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162139 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 162139 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.443693 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.443693 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.443693 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.443693 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.443693 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.443693 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834 # average overall miss latency
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses 398660 # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses 398660 # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92440 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 92440 # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92440 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total 92440 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92440 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 92440 # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71260 # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total 71260 # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71260 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total 71260 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71260 # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total 71260 # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 875246716 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 875246716 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 875246716 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total 875246716 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 875246716 # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total 875246716 # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 163700 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 163700 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 163700 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 163700 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 163700 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 163700 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435308 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435308 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435308 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435308 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435308 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435308 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12282.440584 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12282.440584 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12282.440584 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12282.440584 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12282.440584 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12282.440584 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 22838 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 22838 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71940 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71940 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71940 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 71940 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71940 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 71940 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 734698929 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 734698929 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 734698929 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 734698929 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 734698929 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 734698929 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.443693 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.443693 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.443693 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks 20047 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total 20047 # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71260 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71260 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71260 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total 71260 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71260 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total 71260 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 732616430 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 732616430 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 732616430 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 732616430 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 732616430 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 732616430 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435308 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435308 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435308 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10280.892927 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10280.892927 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10280.892927 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1658766 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.994288 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 19002910 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1659278 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.452517 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 1657713 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.996506 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 19009946 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1658225 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.464033 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 39778250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.994288 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.996506 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 87874474 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 87874474 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 10896738 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 10896738 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8103479 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8103479 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 19000217 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 19000217 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 19000217 # number of overall hits
-system.cpu.dcache.overall_hits::total 19000217 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2237270 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2237270 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 316309 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 316309 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2553579 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2553579 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2553579 # number of overall misses
-system.cpu.dcache.overall_misses::total 2553579 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 32758938054 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 32758938054 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 12034849454 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 12034849454 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 44793787508 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 44793787508 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 44793787508 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 44793787508 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 13134008 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13134008 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8419788 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8419788 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21553796 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21553796 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21553796 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21553796 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170342 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.170342 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037567 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.037567 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.118475 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.118475 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.118475 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.118475 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17541.571069 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17541.571069 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 388234 # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses 87793833 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 87793833 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 10909808 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 10909808 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 8097329 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8097329 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 19007137 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 19007137 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 19007137 # number of overall hits
+system.cpu.dcache.overall_hits::total 19007137 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2211100 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2211100 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 315662 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 315662 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2526762 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2526762 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2526762 # number of overall misses
+system.cpu.dcache.overall_misses::total 2526762 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 32878750930 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 32878750930 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 12078727781 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 12078727781 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 44957478711 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 44957478711 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 44957478711 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 44957478711 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 13120908 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13120908 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 8412991 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 8412991 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 21533899 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 21533899 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 21533899 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 21533899 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168517 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.168517 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037521 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.037521 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.117339 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.117339 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.117339 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.117339 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14869.861576 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14869.861576 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38264.750844 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38264.750844 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17792.526052 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17792.526052 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17792.526052 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17792.526052 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 428041 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 42159 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 36530 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.208805 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.717520 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1559977 # number of writebacks
-system.cpu.dcache.writebacks::total 1559977 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867558 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 867558 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24476 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 24476 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 892034 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 892034 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 892034 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 892034 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369712 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1369712 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291833 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 291833 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1661545 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1661545 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1661545 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1661545 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17680675970 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17680675970 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11138475501 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11138475501 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28819151471 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 28819151471 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28819151471 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 28819151471 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364609500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364609500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539074000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539074000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903683500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903683500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104287 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104287 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034660 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034660 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.316471 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 1559500 # number of writebacks
+system.cpu.dcache.writebacks::total 1559500 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840350 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 840350 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25845 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 25845 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 866195 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 866195 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 866195 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 866195 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1370750 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1370750 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289817 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 289817 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1660567 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1660567 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1660567 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1660567 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17852039460 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 17852039460 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11191134624 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11191134624 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29043174084 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 29043174084 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29043174084 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 29043174084 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363185500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363185500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536205500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536205500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899391000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899391000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104471 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104471 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034449 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034449 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077114 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.077114 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077114 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.077114 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13023.556053 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13023.556053 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38614.486466 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38614.486466 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17489.914038 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17489.914038 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17489.914038 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17489.914038 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 111887 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 64820.177016 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3787056 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 176012 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 21.515897 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 112318 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 64820.835708 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3791752 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 176203 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 21.519225 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50551.329322 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.553377 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.127382 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2956.401453 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11298.765482 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.771352 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000207 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50598.140423 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.189472 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125676 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2974.923375 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11234.456763 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.772066 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045111 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.172405 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.989077 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 64125 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3391 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5259 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54885 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978470 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 34647865 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 34647865 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64838 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7507 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 937874 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1332851 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2343070 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1584798 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1584798 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 327 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 327 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 156813 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 156813 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 64838 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 7507 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 937874 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1489664 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2499883 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 64838 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 7507 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 937874 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1489664 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2499883 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 60 # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045394 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.171424 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.989087 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 534 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3396 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6277 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53619 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 34689659 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 34689659 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7330 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 947840 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1333918 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2353934 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1581183 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1581183 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 324 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 324 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 153879 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 153879 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 64846 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 7330 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 947840 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1487797 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2507813 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 64846 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 7330 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 947840 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1487797 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2507813 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 16175 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 36023 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 52263 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 1437 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 1437 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 132861 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 132861 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 60 # number of demand (read+write) misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 16187 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 36112 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 52363 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 1531 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 1531 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133713 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133713 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 16175 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 168884 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 185124 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 60 # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst 16187 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 169825 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 186076 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 59 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 16175 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 168884 # number of overall misses
-system.cpu.l2cache.overall_misses::total 185124 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5066750 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst 16187 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 169825 # number of overall misses
+system.cpu.l2cache.overall_misses::total 186076 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4865250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 378250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1233234983 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2788798959 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 4027478942 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17149821 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 17149821 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9234678927 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 9234678927 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5066750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1226165489 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2849475947 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 4080884936 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 18074783 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 18074783 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9317667167 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 9317667167 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4865250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 378250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 1233234983 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 12023477886 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 13262157869 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5066750 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 1226165489 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 12167143114 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 13398552103 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4865250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 378250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 1233234983 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 12023477886 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 13262157869 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64898 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7512 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 954049 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1368874 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2395333 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1584798 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1584798 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1764 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 1764 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 289674 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 289674 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64898 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 7512 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 954049 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1658548 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2685007 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64898 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 7512 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 954049 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1658548 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2685007 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000925 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000666 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016954 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026316 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.021819 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814626 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814626 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.458657 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.458657 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000925 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000666 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016954 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.101826 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.068947 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000925 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000666 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016954 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.101826 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.068947 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84445.833333 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_latency::cpu.inst 1226165489 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 12167143114 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 13398552103 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64905 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7335 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 964027 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1370030 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2406297 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1581183 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1581183 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1855 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 1855 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 287592 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 287592 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64905 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 7335 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 964027 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1657622 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2693889 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64905 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 7335 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 964027 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1657622 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2693889 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000909 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000682 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016791 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026359 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.021761 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.825337 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.825337 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464940 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.464940 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000909 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000682 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016791 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.102451 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.069073 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000909 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000682 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016791 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.102451 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.069073 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82461.864407 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75650 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76243.275611 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77417.176776 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 77061.763427 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11934.461378 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11934.461378 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69506.318084 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69506.318084 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84445.833333 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75750.014765 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78906.622369 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 77934.513607 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11805.867407 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11805.867407 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69684.078339 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69684.078339 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82461.864407 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75650 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76243.275611 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71193.706248 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71639.322125 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84445.833333 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75750.014765 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71645.182476 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72005.804634 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82461.864407 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75650 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76243.275611 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71193.706248 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71639.322125 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75750.014765 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71645.182476 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72005.804634 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 102104 # number of writebacks
-system.cpu.l2cache.writebacks::total 102104 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks 102635 # number of writebacks
+system.cpu.l2cache.writebacks::total 102635 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 60 # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16173 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36021 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 52259 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1437 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 1437 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132861 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 132861 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 60 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16184 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36110 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 52358 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1531 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 1531 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133713 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133713 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 16173 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 168882 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 185120 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 60 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 16184 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 169823 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 186071 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 16173 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 168882 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 185120 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4324750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 16184 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 169823 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 186071 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4137750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 315250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1030094767 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2339275539 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3374010306 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15289917 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15289917 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7567196573 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7567196573 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4324750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1022850261 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2399724551 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3427027812 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16292512 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16292512 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7636829333 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7636829333 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4137750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 315250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1030094767 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9906472112 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 10941206879 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4324750 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1022850261 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10036553884 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 11063857145 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4137750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1030094767 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9906472112 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 10941206879 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251381500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251381500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373144500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373144500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624526000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624526000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026314 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021817 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814626 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814626 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.458657 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.458657 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.068946 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.068946 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1022850261 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10036553884 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 11063857145 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250074000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250074000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370675000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370675000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620749000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620749000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026357 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021759 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.825337 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.825337 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464940 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464940 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102450 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.069072 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102450 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.069072 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63201.326063 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66455.955442 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65453.757057 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10641.745265 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10641.745265 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57113.589053 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57113.589053 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63201.326063 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.085878 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59460.405678 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63201.326063 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.085878 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59460.405678 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
Initializing CPU#0\r
PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 2000.008 MHz processor.\r
+time.c: Detected 1999.999 MHz processor.\r
Console: colour dummy device 80x25\r
console handover: boot [earlyser0] -> real [ttyS0]\r
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
ACPI: Unable to load the System Description Tables\r
Using local APIC timer interrupts.\r
-result 7812560\r
+result 7812524\r
Detected 7.812 MHz APIC timer.\r
NET: Registered protocol family 16\r
PCI: Using configuration type 1\r
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-readfile=/z/stever/hg/gem5/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
warn: x86 cpuid: unknown family 0xbacc
+warn: x86 cpuid: unknown family 0xbacc
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unimplemented function 8
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 12 2014 12:50:47
-gem5 started May 12 2014 15:35:34
-gem5 executing on zizzer
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /z/stever/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+gem5 compiled Jun 21 2014 11:13:07
+gem5 started Jun 21 2014 22:18:32
+gem5 executing on phenom
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
---------- Begin Simulation Statistics ----------
-sim_seconds 5.133875 # Number of seconds simulated
-sim_ticks 5133874673500 # Number of ticks simulated
-final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.135764 # Number of seconds simulated
+sim_ticks 5135763847500 # Number of ticks simulated
+final_tick 5135763847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 236000 # Simulator instruction rate (inst/s)
-host_op_rate 469116 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4968557721 # Simulator tick rate (ticks/s)
-host_mem_usage 928744 # Number of bytes of host memory used
-host_seconds 1033.27 # Real time elapsed on the host
-sim_insts 243852609 # Number of instructions simulated
-sim_ops 484724493 # Number of ops (including micro ops) simulated
+host_inst_rate 259782 # Simulator instruction rate (inst/s)
+host_op_rate 516376 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5470381356 # Simulator tick rate (ticks/s)
+host_mem_usage 959692 # Number of bytes of host memory used
+host_seconds 938.83 # Real time elapsed on the host
+sim_insts 243891279 # Number of instructions simulated
+sim_ops 484789360 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 500480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5911104 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 139776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1689280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 1344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 309696 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2752128 # Number of bytes read from this memory
-system.physmem.bytes_read::total 13749568 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 500480 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 139776 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 309696 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 949952 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9083392 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9083392 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38210 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7820 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 92361 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2184 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 26395 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 21 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 4839 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 43002 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 214837 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 141928 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 141928 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 476334 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 97486 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1151392 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 27226 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 329046 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 262 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 60324 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 536072 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2678205 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 97486 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 27226 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 60324 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 185036 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1769305 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1769305 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1769305 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 476334 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 97486 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1151392 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 27226 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 329046 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 262 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 60324 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 536072 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4447510 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 96612 # Number of read requests accepted
-system.physmem.writeReqs 73475 # Number of write requests accepted
-system.physmem.readBursts 96612 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 73475 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 6177024 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4701248 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 6183168 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4702400 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::pc.south_bridge.ide 2442432 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 470912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 6169536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 114240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1582592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 379456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2632640 # Number of bytes read from this memory
+system.physmem.bytes_read::total 13794368 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 470912 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 114240 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 379456 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 964608 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9131520 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9131520 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38163 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 7358 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 96399 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1785 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 24728 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5929 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 41135 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 215537 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 142680 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 142680 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 475573 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 91693 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1201289 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 22244 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 308151 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 73885 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 512609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2685943 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 91693 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 22244 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 73885 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 187822 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1778026 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1778026 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1778026 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 475573 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 91693 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1201289 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 22244 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 308151 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 73885 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 512609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4463968 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 94056 # Number of read requests accepted
+system.physmem.writeReqs 72760 # Number of write requests accepted
+system.physmem.readBursts 94056 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 72760 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 6015488 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 4096 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4656640 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 6019584 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4656640 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 64 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 831 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 5404 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5964 # Per bank write bursts
-system.physmem.perBankRdBursts::2 6149 # Per bank write bursts
-system.physmem.perBankRdBursts::3 6338 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5414 # Per bank write bursts
-system.physmem.perBankRdBursts::5 6001 # Per bank write bursts
-system.physmem.perBankRdBursts::6 5201 # Per bank write bursts
-system.physmem.perBankRdBursts::7 6053 # Per bank write bursts
-system.physmem.perBankRdBursts::8 5779 # Per bank write bursts
-system.physmem.perBankRdBursts::9 5783 # Per bank write bursts
-system.physmem.perBankRdBursts::10 5919 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5801 # Per bank write bursts
-system.physmem.perBankRdBursts::12 6766 # Per bank write bursts
-system.physmem.perBankRdBursts::13 6809 # Per bank write bursts
-system.physmem.perBankRdBursts::14 6844 # Per bank write bursts
-system.physmem.perBankRdBursts::15 6291 # Per bank write bursts
-system.physmem.perBankWrBursts::0 4307 # Per bank write bursts
-system.physmem.perBankWrBursts::1 4604 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4694 # Per bank write bursts
-system.physmem.perBankWrBursts::3 4750 # Per bank write bursts
-system.physmem.perBankWrBursts::4 4088 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4371 # Per bank write bursts
-system.physmem.perBankWrBursts::6 3767 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4522 # Per bank write bursts
-system.physmem.perBankWrBursts::8 4168 # Per bank write bursts
-system.physmem.perBankWrBursts::9 4368 # Per bank write bursts
-system.physmem.perBankWrBursts::10 4606 # Per bank write bursts
-system.physmem.perBankWrBursts::11 4444 # Per bank write bursts
-system.physmem.perBankWrBursts::12 5448 # Per bank write bursts
-system.physmem.perBankWrBursts::13 5248 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5481 # Per bank write bursts
-system.physmem.perBankWrBursts::15 4591 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 766 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 5609 # Per bank write bursts
+system.physmem.perBankRdBursts::1 5668 # Per bank write bursts
+system.physmem.perBankRdBursts::2 5585 # Per bank write bursts
+system.physmem.perBankRdBursts::3 5594 # Per bank write bursts
+system.physmem.perBankRdBursts::4 6037 # Per bank write bursts
+system.physmem.perBankRdBursts::5 6612 # Per bank write bursts
+system.physmem.perBankRdBursts::6 5733 # Per bank write bursts
+system.physmem.perBankRdBursts::7 5990 # Per bank write bursts
+system.physmem.perBankRdBursts::8 5523 # Per bank write bursts
+system.physmem.perBankRdBursts::9 5460 # Per bank write bursts
+system.physmem.perBankRdBursts::10 5647 # Per bank write bursts
+system.physmem.perBankRdBursts::11 6128 # Per bank write bursts
+system.physmem.perBankRdBursts::12 6059 # Per bank write bursts
+system.physmem.perBankRdBursts::13 6267 # Per bank write bursts
+system.physmem.perBankRdBursts::14 6194 # Per bank write bursts
+system.physmem.perBankRdBursts::15 5886 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4545 # Per bank write bursts
+system.physmem.perBankWrBursts::1 4402 # Per bank write bursts
+system.physmem.perBankWrBursts::2 4127 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4299 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4675 # Per bank write bursts
+system.physmem.perBankWrBursts::5 5126 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4327 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4679 # Per bank write bursts
+system.physmem.perBankWrBursts::8 4360 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4207 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4528 # Per bank write bursts
+system.physmem.perBankWrBursts::11 4822 # Per bank write bursts
+system.physmem.perBankWrBursts::12 4836 # Per bank write bursts
+system.physmem.perBankWrBursts::13 4641 # Per bank write bursts
+system.physmem.perBankWrBursts::14 4944 # Per bank write bursts
+system.physmem.perBankWrBursts::15 4242 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 5132874544500 # Total gap between requests
+system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
+system.physmem.totGap 5131947184500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 96612 # Read request sizes (log2)
+system.physmem.readPktSize::6 94056 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 73475 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 73469 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4666 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2797 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1564 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1988 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1759 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1657 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1283 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 72760 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 71094 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4372 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2882 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1652 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1622 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1995 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1751 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 996 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 876 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 745 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 587 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 557 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 459 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 400 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 371 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 290 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 228 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 192 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 893 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 759 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 598 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 528 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 422 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 352 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 273 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 218 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 184 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1067 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3056 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 3261 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 3324 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 3456 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3620 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1038 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2990 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3162 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 3202 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 3262 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 3405 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 3645 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 3779 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 4073 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4198 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4250 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 4441 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 4429 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 4453 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 4398 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 4414 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 960 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 974 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 979 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 929 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 852 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 724 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 573 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 466 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 383 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 284 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 211 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 48 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 37 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 35709 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 304.633118 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 178.344584 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 328.042030 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 13828 38.72% 38.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8395 23.51% 62.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 3582 10.03% 72.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1962 5.49% 77.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1409 3.95% 81.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 988 2.77% 84.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 701 1.96% 86.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 566 1.59% 88.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4278 11.98% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 35709 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 4100 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.539756 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 117.618727 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 4089 99.73% 99.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 8 0.20% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 4100 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 4100 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.916341 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.808533 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 6.372443 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-1 61 1.49% 1.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2-3 8 0.20% 1.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-5 2 0.05% 1.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6-7 3 0.07% 1.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-9 1 0.02% 1.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::10-11 1 0.02% 1.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-13 1 0.02% 1.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::14-15 5 0.12% 2.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 2769 67.54% 69.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 821 20.02% 89.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 36 0.88% 90.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 38 0.93% 91.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 31 0.76% 92.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 30 0.73% 92.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 54 1.32% 94.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 53 1.29% 95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 24 0.59% 96.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35 28 0.68% 96.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37 12 0.29% 97.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38-39 22 0.54% 97.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41 34 0.83% 98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43 16 0.39% 98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45 10 0.24% 99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47 6 0.15% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49 8 0.20% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51 2 0.05% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53 4 0.10% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::54-55 5 0.12% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-57 2 0.05% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58-59 2 0.05% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61 1 0.02% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63 8 0.20% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4100 # Writes before turning the bus around for reads
-system.physmem.totQLat 2438372750 # Total ticks spent queuing
-system.physmem.totMemAccLat 4248047750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 482580000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25263.92 # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::25 4031 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4114 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4151 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4380 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 4369 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 4401 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 4387 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 4409 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1056 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 1031 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 961 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 898 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 802 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 688 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 557 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 463 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 343 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 250 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 134 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 48 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 43 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 35723 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 298.746690 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 173.799684 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 327.095227 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 14318 40.08% 40.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 8282 23.18% 63.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 3507 9.82% 73.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1954 5.47% 78.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1307 3.66% 82.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 922 2.58% 84.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 623 1.74% 86.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 530 1.48% 88.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4280 11.98% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 35723 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3978 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 23.627954 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 119.433357 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255 3969 99.77% 99.77% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511 7 0.18% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 3978 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3978 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 18.290598 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.208175 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 6.685696 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-1 45 1.13% 1.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2-3 5 0.13% 1.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-5 3 0.08% 1.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6-7 4 0.10% 1.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10-11 1 0.03% 1.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14-15 5 0.13% 1.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17 2627 66.04% 67.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19 818 20.56% 88.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21 28 0.70% 88.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23 32 0.80% 89.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25 32 0.80% 90.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27 35 0.88% 91.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29 65 1.63% 93.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31 48 1.21% 94.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33 35 0.88% 95.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35 29 0.73% 95.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37 29 0.73% 96.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39 26 0.65% 97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41 31 0.78% 97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43 18 0.45% 98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45 10 0.25% 98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47 17 0.43% 99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49 8 0.20% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51 6 0.15% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53 2 0.05% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55 2 0.05% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57 7 0.18% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59 1 0.03% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61 3 0.08% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63 4 0.10% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::66-67 2 0.05% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3978 # Writes before turning the bus around for reads
+system.physmem.totQLat 2424873249 # Total ticks spent queuing
+system.physmem.totMemAccLat 4187223249 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 469960000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25798.72 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44013.92 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44548.72 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.91 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.91 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 7.46 # Average write queue length when enqueuing
-system.physmem.readRowHits 79177 # Number of row buffer hits during reads
-system.physmem.writeRowHits 55086 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes
-system.physmem.avgGap 30177935.67 # Average gap between requests
-system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4939989054000 # Time in different power states
-system.physmem.memoryStateTime::REF 171431260000 # Time in different power states
+system.physmem.avgWrQLen 6.97 # Average write queue length when enqueuing
+system.physmem.readRowHits 76538 # Number of row buffer hits during reads
+system.physmem.writeRowHits 54491 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.89 # Row buffer hit rate for writes
+system.physmem.avgGap 30764118.46 # Average gap between requests
+system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4942425043001 # Time in different power states
+system.physmem.memoryStateTime::REF 171494180000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 22454242000 # Time in different power states
+system.physmem.memoryStateTime::ACT 21844559499 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 6437004 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 422289 # Transaction distribution
-system.membus.trans_dist::ReadResp 422287 # Transaction distribution
-system.membus.trans_dist::WriteReq 6118 # Transaction distribution
-system.membus.trans_dist::WriteResp 6118 # Transaction distribution
-system.membus.trans_dist::Writeback 73475 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 843 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 843 # Transaction distribution
-system.membus.trans_dist::ReadExReq 76388 # Transaction distribution
-system.membus.trans_dist::ReadExResp 76388 # Transaction distribution
-system.membus.trans_dist::MessageReq 850 # Transaction distribution
-system.membus.trans_dist::MessageResp 850 # Transaction distribution
+system.membus.throughput 6452408 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 421921 # Transaction distribution
+system.membus.trans_dist::ReadResp 421919 # Transaction distribution
+system.membus.trans_dist::WriteReq 5915 # Transaction distribution
+system.membus.trans_dist::WriteResp 5915 # Transaction distribution
+system.membus.trans_dist::Writeback 72760 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 778 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 778 # Transaction distribution
+system.membus.trans_dist::ReadExReq 75224 # Transaction distribution
+system.membus.trans_dist::ReadExResp 75224 # Transaction distribution
+system.membus.trans_dist::MessageReq 825 # Transaction distribution
+system.membus.trans_dist::MessageResp 825 # Transaction distribution
system.membus.trans_dist::BadAddressError 2 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1700 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 1700 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308658 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497514 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 204215 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1650 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 1650 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308134 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497586 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196326 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 1010391 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 69253 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 69253 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1081344 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3400 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total 3400 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158115 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995025 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8047552 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 9200692 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2838016 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 2838016 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 12042108 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 32720690 # Total data (bytes)
-system.membus.snoop_data_through_bus 326080 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 162128500 # Layer occupancy (ticks)
+system.membus.pkt_count_system.l2c.mem_side::total 1002050 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72232 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72232 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1075932 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3300 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total 3300 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 157715 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995169 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7734720 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 8887604 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2941504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 2941504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 11832408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 32744958 # Total data (bytes)
+system.membus.snoop_data_through_bus 393088 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 161596500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 315102000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 315113000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1650000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 806327999 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 794070497 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 850000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 825000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1598914090 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1569908183 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 224687998 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 236956000 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 103794 # number of replacements
-system.l2c.tags.tagsinuse 64810.608353 # Cycle average of tags in use
-system.l2c.tags.total_refs 3657966 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 167984 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 21.775681 # Average number of references to valid blocks.
+system.l2c.tags.replacements 104346 # number of replacements
+system.l2c.tags.tagsinuse 64811.945905 # Cycle average of tags in use
+system.l2c.tags.total_refs 3669840 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 168730 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 21.749778 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 51486.278563 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125055 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1295.377972 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 4270.696448 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 302.542141 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 1483.932036 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.824361 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1349.140567 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 4614.691210 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.785618 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks 51276.768453 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121941 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 1221.298902 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 4234.138382 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002961 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 249.507225 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 1581.676468 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.253356 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 1493.843089 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 4747.335130 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.782421 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.019766 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.065166 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004616 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.022643 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000119 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.020586 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.070415 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.988931 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 64190 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3206 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 7166 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 53256 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.979462 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 33587388 # Number of tag accesses
-system.l2c.tags.data_accesses 33587388 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 20605 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 11266 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 339595 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 520668 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 10906 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 6430 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 151391 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 219548 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 53731 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 8985 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 345046 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 563659 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2251830 # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst 0.018636 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.064608 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.003807 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.024134 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000111 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.022794 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.072439 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.988952 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 64384 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 2861 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 7799 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 53379 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.982422 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 33692585 # Number of tag accesses
+system.l2c.tags.data_accesses 33692585 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 19944 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 10836 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 348846 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 522725 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 9533 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 5021 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 144714 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 221166 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker 56163 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker 10079 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 347465 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 563204 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 2259696 # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks 1542066 # number of Writeback hits
-system.l2c.Writeback_hits::total 1542066 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 52 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 72 # number of UpgradeReq hits
+system.l2c.Writeback_hits::writebacks 1546042 # number of Writeback hits
+system.l2c.Writeback_hits::total 1546042 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data 73 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 259 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 66169 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 39322 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 60638 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 166129 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 20605 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 11268 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 339595 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 586837 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 10906 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 6430 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 151391 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 258870 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker 53731 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker 8985 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 345046 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 624297 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2417961 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 20605 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 11268 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 339595 # number of overall hits
-system.l2c.overall_hits::cpu0.data 586837 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 10906 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 6430 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 151391 # number of overall hits
-system.l2c.overall_hits::cpu1.data 258870 # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker 53731 # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker 8985 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 345046 # number of overall hits
-system.l2c.overall_hits::cpu2.data 624297 # number of overall hits
-system.l2c.overall_hits::total 2417961 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 7821 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 15227 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 2184 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 4071 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker 21 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 4840 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 13473 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 47642 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 650 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 279 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 401 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1330 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 77547 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 22505 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 29870 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 129922 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 7821 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 92774 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 2184 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 26576 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker 21 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 4840 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 43343 # number of demand (read+write) misses
-system.l2c.demand_misses::total 177564 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 7821 # number of overall misses
-system.l2c.overall_misses::cpu0.data 92774 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 2184 # number of overall misses
-system.l2c.overall_misses::cpu1.data 26576 # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker 21 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 4840 # number of overall misses
-system.l2c.overall_misses::cpu2.data 43343 # number of overall misses
-system.l2c.overall_misses::total 177564 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst 158048000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 307638493 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1706500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 369793991 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 1035932237 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1873119221 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 4516343 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 3653343 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 8169686 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 1564766446 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 2136302067 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 3701068513 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 158048000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 1872404939 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker 1706500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 369793991 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 3172234304 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 5574187734 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 158048000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 1872404939 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker 1706500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 369793991 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 3172234304 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 5574187734 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 20605 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 11271 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 347416 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 535895 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 10906 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 6430 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 153575 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 223619 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker 53752 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker 8985 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 349886 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 577132 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2299472 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadExReq_hits::cpu0.data 69718 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 41748 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 55006 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 166472 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 19944 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 10838 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 348846 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 592443 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 9533 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 5021 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 144714 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 262914 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker 56163 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker 10079 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 347465 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 618210 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2426170 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 19944 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 10838 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 348846 # number of overall hits
+system.l2c.overall_hits::cpu0.data 592443 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 9533 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 5021 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 144714 # number of overall hits
+system.l2c.overall_hits::cpu1.data 262914 # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker 56163 # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker 10079 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 347465 # number of overall hits
+system.l2c.overall_hits::cpu2.data 618210 # number of overall hits
+system.l2c.overall_hits::total 2426170 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 7359 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 16415 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 1785 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 4252 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker 35 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 5929 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 12239 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 48019 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 765 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 259 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 351 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1375 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 80419 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 20642 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 29214 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 130275 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 7359 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 96834 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 1785 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 24894 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker 35 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 5929 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 41453 # number of demand (read+write) misses
+system.l2c.demand_misses::total 178294 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 7359 # number of overall misses
+system.l2c.overall_misses::cpu0.data 96834 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 1785 # number of overall misses
+system.l2c.overall_misses::cpu1.data 24894 # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker 35 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 5929 # number of overall misses
+system.l2c.overall_misses::cpu2.data 41453 # number of overall misses
+system.l2c.overall_misses::total 178294 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 131076749 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 324093246 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2710500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 449940247 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 930919976 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1838815218 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 3606379 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data 3766341 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 7372720 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 1430517449 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 2081702090 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 3512219539 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 131076749 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 1754610695 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker 2710500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 449940247 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 3012622066 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 5351034757 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 131076749 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 1754610695 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker 2710500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 449940247 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 3012622066 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 5351034757 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 19944 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 10840 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 356205 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 539140 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 9533 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 5022 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 146499 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 225418 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker 56198 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker 10079 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 353394 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 575443 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2307715 # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 1542066 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1542066 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 785 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 331 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 473 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1589 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 143716 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 61827 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 90508 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 296051 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 20605 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 11273 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 347416 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 679611 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 10906 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 6430 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 153575 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 285446 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker 53752 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker 8985 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 349886 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 667640 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2595525 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 20605 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 11273 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 347416 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 679611 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 10906 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 6430 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 153575 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 285446 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker 53752 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker 8985 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 349886 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 667640 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2595525 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000444 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.022512 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.028414 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.014221 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.018205 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000391 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.013833 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.023345 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.020719 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.828025 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.842900 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.847780 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.837004 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.539585 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.364000 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.330026 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.438850 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000444 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.022512 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.136510 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.014221 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.093103 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000391 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.013833 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.064920 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.068412 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000444 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.022512 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.136510 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.014221 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.093103 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000391 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.013833 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.064920 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.068412 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72366.300366 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 75568.286170 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 81261.904762 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76403.717149 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 76889.500260 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 39316.553062 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16187.609319 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 9110.581047 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 6142.621053 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69529.724328 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71519.988852 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 28486.849902 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72366.300366 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 70454.731299 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 81261.904762 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 76403.717149 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 73189.080221 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 31392.555552 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72366.300366 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 70454.731299 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 81261.904762 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 76403.717149 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 73189.080221 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 31392.555552 # average overall miss latency
+system.l2c.Writeback_accesses::writebacks 1546042 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1546042 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 904 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 306 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 424 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1634 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 150137 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 62390 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 84220 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 296747 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 19944 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 10842 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 356205 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 689277 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 9533 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 5022 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 146499 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 287808 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker 56198 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker 10079 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 353394 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 659663 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2604464 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 19944 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 10842 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 356205 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 689277 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 9533 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 5022 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 146499 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 287808 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker 56198 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker 10079 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 353394 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 659663 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2604464 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000369 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.020659 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.030447 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000199 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.012184 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.018863 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000623 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.016777 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.021269 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.020808 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.846239 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.846405 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.827830 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.841493 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.535637 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.330854 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.346877 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.439010 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000369 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.020659 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.140486 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.000199 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.012184 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.086495 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000623 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.016777 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.062840 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.068457 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000369 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.020659 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.140486 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.000199 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.012184 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.086495 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000623 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.016777 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.062840 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.068457 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73432.352381 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76221.365475 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 77442.857143 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75888.049755 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 76061.767791 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 38293.492534 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 13924.243243 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10730.316239 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 5361.978182 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69301.300698 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71257.003149 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 26960.042518 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 73432.352381 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 70483.276894 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77442.857143 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 75888.049755 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 72675.610113 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 30012.421938 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 73432.352381 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 70483.276894 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77442.857143 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 75888.049755 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 72675.610113 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 30012.421938 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 95261 # number of writebacks
-system.l2c.writebacks::total 95261 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.inst 2184 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 4071 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 21 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 4839 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 13473 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 24588 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 279 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 401 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 680 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 22505 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 29870 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 52375 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 2184 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 26576 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 21 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 4839 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 43343 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 76963 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 2184 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 26576 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 21 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 4839 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 43343 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 76963 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 130319000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 256773507 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1447000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 309153509 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 867568261 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1565261277 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3390267 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 4022901 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 7413168 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1276355554 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1752679887 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 3029035441 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 130319000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 1533129061 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1447000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 309153509 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 2620248148 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 4594296718 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 130319000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 1533129061 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1447000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 309153509 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 2620248148 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 4594296718 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28014543000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30421291000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 58435834000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 368226500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 707215000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 1075441500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28382769500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31128506000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 59511275500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014221 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018205 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000391 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013830 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.023345 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.010693 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.842900 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.847780 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.427942 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.364000 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.330026 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.176912 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014221 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.093103 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000391 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013830 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.064920 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.029652 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014221 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.093103 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000391 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013830 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.064920 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.029652 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59669.871795 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63073.816507 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 68904.761905 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63887.891920 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64393.101833 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 63659.560639 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12151.494624 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10032.172070 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10901.717647 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56714.310331 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58676.929595 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 57833.612239 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59669.871795 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57688.480622 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 68904.761905 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63887.891920 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60453.779111 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59694.875694 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59669.871795 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57688.480622 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68904.761905 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63887.891920 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60453.779111 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59694.875694 # average overall mshr miss latency
+system.l2c.writebacks::writebacks 96013 # number of writebacks
+system.l2c.writebacks::total 96013 # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 1785 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 4252 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 35 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst 5929 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data 12239 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 24241 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 259 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 351 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 610 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 20642 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 29214 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 49856 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 1785 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 24894 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker 35 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 5929 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 41453 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 74097 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 1785 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 24894 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker 35 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 5929 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 41453 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 74097 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 108413751 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 270880754 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2276000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 375699253 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 777979024 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1535311282 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3140248 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3570349 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 6710597 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1166132051 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1707521864 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 2873653915 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 108413751 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 1437012805 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2276000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 375699253 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 2485500888 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 4408965197 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 108413751 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 1437012805 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2276000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 375699253 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 2485500888 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 4408965197 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28030608000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30401443000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 58432051000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 366838500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 681386000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 1048224500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28397446500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31082829000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 59480275500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000199 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012184 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018863 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000623 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.016777 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021269 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.010504 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846405 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.827830 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.373317 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330854 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.346877 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.168008 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000199 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012184 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.086495 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000623 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.016777 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.062840 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.028450 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000199 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012184 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.086495 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000623 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.016777 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.062840 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.028450 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60735.994958 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63706.668391 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63366.377635 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63565.571043 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 63335.311332 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12124.509653 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10171.934473 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11000.978689 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56493.171737 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58448.752790 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57639.078847 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60735.994958 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57725.267333 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63366.377635 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59959.493595 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59502.614100 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60735.994958 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57725.267333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63366.377635 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59959.493595 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59502.614100 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 47575 # number of replacements
-system.iocache.tags.tagsinuse 0.089403 # Cycle average of tags in use
+system.iocache.tags.replacements 47573 # number of replacements
+system.iocache.tags.tagsinuse 0.095086 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5000209950509 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.089403 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005588 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.005588 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 5000199085509 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095086 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005943 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.005943 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428670 # Number of tag accesses
-system.iocache.tags.data_accesses 428670 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
+system.iocache.tags.tag_accesses 428652 # Number of tag accesses
+system.iocache.tags.data_accesses 428652 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 908 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47630 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses
-system.iocache.overall_misses::total 47630 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131527041 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 131527041 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5824382656 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 5824382656 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 5955909697 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 5955909697 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 5955909697 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 5955909697 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47628 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses
+system.iocache.overall_misses::total 47628 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130701291 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 130701291 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6017123258 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 6017123258 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 6147824549 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 6147824549 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 6147824549 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 6147824549 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144535.209890 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 144535.209890 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 124665.724658 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 124665.724658 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125045.343208 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125045.343208 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 88795 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143944.153084 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 143944.153084 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 128791.165625 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 128791.165625 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 129080.048480 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 129080.048480 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 86048 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 8200 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 7909 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.828659 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.879757 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 733 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24176 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 24176 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 24909 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 24909 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 24909 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 24909 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93385041 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 93385041 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4566242660 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 4566242660 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 4659627701 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 4659627701 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.805495 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.805495 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.517466 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 0.517466 # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.522969 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.522969 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127401.147340 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 127401.147340 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 188875.027300 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 188875.027300 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 735 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 735 # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 25536 # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total 25536 # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 26271 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 26271 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 26271 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 26271 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92456791 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 92456791 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4688241758 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 4688241758 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 4780698549 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 4780698549 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.809471 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.809471 # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.546575 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 0.546575 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.551587 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.551587 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125791.552381 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 125791.552381 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 183593.427240 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 183593.427240 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.toL2Bus.throughput 52260442 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 1795853 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 1795321 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 6118 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 6118 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 903975 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 804 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 804 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 176511 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 152342 # Transaction distribution
+system.toL2Bus.throughput 52407719 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 1793633 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1793101 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 5915 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 5915 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 899960 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 730 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 730 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 172146 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 146613 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006951 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3618137 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34540 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 139444 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 4799072 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32221504 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120018356 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 123320 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 517264 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 152880444 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 268161042 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 137520 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 5048228823 # Layer occupancy (ticks)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 999818 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3602290 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 141650 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 4778107 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31993152 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119401652 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120808 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 525848 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 152041460 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 269011854 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 141816 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 5025953302 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2267749080 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2251918114 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4703679799 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4677619434 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 19140467 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 19272449 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 74891774 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 76057203 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 1277477 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 149797 # Transaction distribution
-system.iobus.trans_dist::ReadResp 149797 # Transaction distribution
-system.iobus.trans_dist::WriteReq 29441 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29441 # Transaction distribution
-system.iobus.trans_dist::MessageReq 850 # Transaction distribution
-system.iobus.trans_dist::MessageResp 850 # Transaction distribution
+system.iobus.throughput 1276582 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 149714 # Transaction distribution
+system.iobus.trans_dist::ReadResp 149714 # Transaction distribution
+system.iobus.trans_dist::WriteReq 30624 # Transaction distribution
+system.iobus.trans_dist::WriteResp 30624 # Transaction distribution
+system.iobus.trans_dist::MessageReq 825 # Transaction distribution
+system.iobus.trans_dist::MessageResp 825 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5466 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4890 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 558 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 38 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 588 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287110 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 224 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287208 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 156 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13026 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 308658 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49818 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49818 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1700 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1700 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 360176 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 308134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 52542 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 52542 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1650 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1650 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 362326 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3084 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2760 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 279 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 19 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 294 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143555 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 448 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143604 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 312 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6513 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 158115 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1583592 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1583592 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3400 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3400 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 1745107 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 6558405 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 2044244 # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total 157715 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1670648 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1670648 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3300 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 1831663 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 6556225 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 1987954 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 4518000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 4046000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 367000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy 387000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 33000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 143556000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy 143605000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 178000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 124000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 9750000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 9774000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 220209699 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 232428549 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 303393000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 303046000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 30099002 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 31488000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 850000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 825000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 1160444400 # number of cpu cycles simulated
+system.cpu0.numCycles 1167096017 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 72635405 # Number of instructions committed
-system.cpu0.committedOps 147758080 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 135731001 # Number of integer alu accesses
+system.cpu0.committedInsts 72932334 # Number of instructions committed
+system.cpu0.committedOps 148186849 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 136173063 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 1010341 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 14309822 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 135731001 # number of integer instructions
+system.cpu0.num_func_calls 1014433 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 14332221 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 136173063 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 249546871 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 116495894 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 250637191 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 116800630 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 84252648 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 56217158 # number of times the CC registers were written
-system.cpu0.num_mem_refs 14168966 # number of memory refs
-system.cpu0.num_load_insts 10366088 # Number of load instructions
-system.cpu0.num_store_insts 3802878 # Number of store instructions
-system.cpu0.num_idle_cycles 1101978015.213226 # Number of idle cycles
-system.cpu0.num_busy_cycles 58466384.786774 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.050383 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.949617 # Percentage of idle cycles
-system.cpu0.Branches 15683494 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 100234 0.07% 0.07% # Class of executed instruction
-system.cpu0.op_class::IntAlu 133376064 90.27% 90.33% # Class of executed instruction
-system.cpu0.op_class::IntMult 62929 0.04% 90.38% # Class of executed instruction
-system.cpu0.op_class::IntDiv 50413 0.03% 90.41% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.41% # Class of executed instruction
-system.cpu0.op_class::MemRead 10366088 7.02% 97.43% # Class of executed instruction
-system.cpu0.op_class::MemWrite 3802878 2.57% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 84487712 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 56367816 # number of times the CC registers were written
+system.cpu0.num_mem_refs 14369378 # number of memory refs
+system.cpu0.num_load_insts 10451844 # Number of load instructions
+system.cpu0.num_store_insts 3917534 # Number of store instructions
+system.cpu0.num_idle_cycles 1108227141.183960 # Number of idle cycles
+system.cpu0.num_busy_cycles 58868875.816040 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.050440 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.949560 # Percentage of idle cycles
+system.cpu0.Branches 15712912 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 100385 0.07% 0.07% # Class of executed instruction
+system.cpu0.op_class::IntAlu 133601927 90.16% 90.23% # Class of executed instruction
+system.cpu0.op_class::IntMult 62763 0.04% 90.27% # Class of executed instruction
+system.cpu0.op_class::IntDiv 53014 0.04% 90.30% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.30% # Class of executed instruction
+system.cpu0.op_class::MemRead 10451844 7.05% 97.36% # Class of executed instruction
+system.cpu0.op_class::MemWrite 3917534 2.64% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 147758606 # Class of executed instruction
+system.cpu0.op_class::total 148187467 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 850385 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.795763 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 129494152 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 850897 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 152.185461 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 147465545000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 306.120317 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.033154 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 67.642292 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.597891 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267643 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.132114 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.997648 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 855609 # number of replacements
+system.cpu0.icache.tags.tagsinuse 510.820181 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 129797062 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 856121 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 151.610651 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 147456803500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 296.387192 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 131.510981 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 82.922008 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.578881 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.256857 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.161957 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.997696 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 131214879 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 131214879 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 88330268 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 38415630 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 2748254 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 129494152 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 88330268 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 38415630 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 2748254 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 129494152 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 88330268 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 38415630 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 2748254 # number of overall hits
-system.cpu0.icache.overall_hits::total 129494152 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 347417 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 153575 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 368828 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 869820 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 347417 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 153575 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 368828 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 869820 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 347417 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 153575 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 368828 # number of overall misses
-system.cpu0.icache.overall_misses::total 869820 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2140572500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5126974995 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 7267547495 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 2140572500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 5126974995 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 7267547495 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 2140572500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 5126974995 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 7267547495 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 88677685 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 38569205 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 3117082 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 130363972 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 88677685 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 38569205 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 3117082 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 130363972 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 88677685 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 38569205 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 3117082 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 130363972 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003918 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003982 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.118325 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.006672 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003918 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003982 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.118325 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.006672 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003918 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003982 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.118325 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.006672 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13938.287482 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13900.720648 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 8355.231536 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13938.287482 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13900.720648 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 8355.231536 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13938.287482 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13900.720648 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 8355.231536 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2303 # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses 131529533 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 131529533 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 88736608 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 38254506 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 2805948 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 129797062 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 88736608 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 38254506 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 2805948 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 129797062 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 88736608 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 38254506 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 2805948 # number of overall hits
+system.cpu0.icache.overall_hits::total 129797062 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 356206 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 146499 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 373635 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 876340 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 356206 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 146499 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 373635 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 876340 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 356206 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 146499 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 373635 # number of overall misses
+system.cpu0.icache.overall_misses::total 876340 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2025173751 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5266260197 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 7291433948 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 2025173751 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 5266260197 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 7291433948 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 2025173751 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 5266260197 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 7291433948 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 89092814 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 38401005 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 3179583 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 130673402 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 89092814 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 38401005 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 3179583 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 130673402 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 89092814 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 38401005 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 3179583 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 130673402 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003998 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003815 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117511 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.006706 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003998 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003815 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117511 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.006706 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003998 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003815 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117511 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.006706 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13823.805971 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14094.665106 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 8320.325385 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13823.805971 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14094.665106 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 8320.325385 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13823.805971 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14094.665106 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 8320.325385 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 3206 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 142 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.218310 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.970414 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18913 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 18913 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 18913 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 18913 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 18913 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 18913 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 153575 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 349915 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 503490 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 153575 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 349915 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 503490 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 153575 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 349915 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 503490 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1832623500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4249045164 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 6081668664 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1832623500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4249045164 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 6081668664 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1832623500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4249045164 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 6081668664 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003982 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.112257 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003862 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003982 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.112257 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.003862 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003982 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.112257 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.003862 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11933.084812 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12143.078073 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12079.025728 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11933.084812 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12143.078073 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12079.025728 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11933.084812 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12143.078073 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12079.025728 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 20209 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 20209 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst 20209 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 20209 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst 20209 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 20209 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 146499 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 353426 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 499925 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 146499 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 353426 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 499925 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 146499 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 353426 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 499925 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1731523249 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4361398381 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 6092921630 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1731523249 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4361398381 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 6092921630 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1731523249 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4361398381 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 6092921630 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003826 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11819.352002 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12340.343894 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12187.671411 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11819.352002 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12340.343894 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12187.671411 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11819.352002 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12340.343894 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12187.671411 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 1632172 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999414 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 19616450 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1632684 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 12.014848 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 1636191 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999281 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 19675203 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1636703 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 12.021242 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 243.807235 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 263.156885 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.035294 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.476186 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.513978 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009835 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.563820 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 233.097338 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.338124 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534304 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.455268 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010426 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 210 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 88185539 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 88185539 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 5216887 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 2373282 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 3941483 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 11531652 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3654093 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 1632238 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 2796808 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 8083139 # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 8870980 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 4005520 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 6738291 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 19614791 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 8870980 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 4005520 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 6738291 # number of overall hits
-system.cpu0.dcache.overall_hits::total 19614791 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 535895 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 223619 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 948939 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1708453 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 144501 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 62158 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 108308 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 314967 # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 680396 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 285777 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 1057247 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2023420 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 680396 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 285777 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 1057247 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2023420 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3182430507 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15408252283 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 18590682790 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2166727821 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3257890503 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 5424618324 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 5349158328 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 18666142786 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 24015301114 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 5349158328 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 18666142786 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 24015301114 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 5752782 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 2596901 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 4890422 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 13240105 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 3798594 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 1694396 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 2905116 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 8398106 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 9551376 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 4291297 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 7795538 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 21638211 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 9551376 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 4291297 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 7795538 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 21638211 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093154 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086110 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.194040 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.129036 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038041 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036684 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037282 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.037505 # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071235 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.066595 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.135622 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.093511 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071235 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.066595 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135622 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.093511 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14231.485281 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16237.347483 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10881.588659 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34858.390247 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30079.869474 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17222.814847 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18717.945559 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17655.422797 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 11868.668449 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18717.945559 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17655.422797 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11868.668449 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 173678 # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses 88326830 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 88326830 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 5302140 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 2350453 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 3934991 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 11587584 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3761995 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 1605612 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 2718349 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 8085956 # number of WriteReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 9064135 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 3956065 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 6653340 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 19673540 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 9064135 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 3956065 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 6653340 # number of overall hits
+system.cpu0.dcache.overall_hits::total 19673540 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 539140 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 225418 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 918731 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1683289 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 151041 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 62696 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 101955 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 315692 # number of WriteReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 690181 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 288114 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 1020686 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1998981 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 690181 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 288114 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 1020686 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1998981 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3220560254 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 14575132809 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 17795693063 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2058114299 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3117330338 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 5175444637 # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 5278674553 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 17692463147 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 22971137700 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 5278674553 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 17692463147 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 22971137700 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 5841280 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 2575871 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 4853722 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 13270873 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 3913036 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 1668308 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 2820304 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 8401648 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 9754316 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 4244179 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 7674026 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 21672521 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 9754316 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 4244179 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 7674026 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 21672521 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.092298 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.087511 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.189284 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.126841 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038599 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037581 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.036150 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.037575 # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.070756 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.067885 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.133005 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.092236 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070756 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.067885 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133005 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.092236 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14287.058948 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15864.418213 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10571.977280 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32826.883677 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30575.551351 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 16393.968289 # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18321.478835 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17333.894211 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 11491.423730 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18321.478835 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17333.894211 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 11491.423730 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 80099 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 11797 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 18060 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.722218 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.435161 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 1542066 # number of writebacks
-system.cpu0.dcache.writebacks::total 1542066 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 371761 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 371761 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17373 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 17373 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 389134 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 389134 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 389134 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 389134 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 223619 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 577178 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 800797 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62158 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 90935 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 153093 # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 285777 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 668113 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 953890 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 285777 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 668113 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 953890 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2734176493 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8368429033 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11102605526 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032053179 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2876927496 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4908980675 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4766229672 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11245356529 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 16011586201 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4766229672 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11245356529 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 16011586201 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30475246000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33186567000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63661813000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 395642000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 753351500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1148993500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30870888000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33939918500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64810806500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086110 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118022 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060483 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036684 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031302 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018229 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.044084 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.044084 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12226.941776 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14498.870423 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13864.444455 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32691.740066 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31637.185858 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32065.350310 # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 1546042 # number of writebacks
+system.cpu0.dcache.writebacks::total 1546042 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 343252 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 343252 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17347 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 17347 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 360599 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 360599 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 360599 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 360599 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 225418 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 575479 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 800897 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62696 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 84608 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 147304 # number of WriteReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 288114 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 660087 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 948201 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 288114 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 660087 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 948201 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2768607746 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8066658535 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10835266281 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1923226701 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2756691504 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4679918205 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4691834447 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10823350039 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 15515184486 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4691834447 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10823350039 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 15515184486 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30492689000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33165040000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63657729000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 394150500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 725206000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1119356500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30886839500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33890246000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64777085500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087511 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118564 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060350 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037581 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030000 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017533 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.043751 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.043751 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12282.105892 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14017.294350 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13528.913557 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30675.429070 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32581.924924 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31770.476056 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 2606021866 # number of cpu cycles simulated
+system.cpu1.numCycles 2604023259 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 34914129 # Number of instructions committed
-system.cpu1.committedOps 67869828 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 62995297 # Number of integer alu accesses
+system.cpu1.committedInsts 34762499 # Number of instructions committed
+system.cpu1.committedOps 67606793 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 62736553 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 438942 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 62995297 # number of integer instructions
+system.cpu1.num_func_calls 437056 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 6403696 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 62736553 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 116271710 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 54373007 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 115724590 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 54164636 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 35773638 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 26686136 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4480512 # number of memory refs
-system.cpu1.num_load_insts 2784989 # Number of load instructions
-system.cpu1.num_store_insts 1695523 # Number of store instructions
-system.cpu1.num_idle_cycles 2483027076.334052 # Number of idle cycles
-system.cpu1.num_busy_cycles 122994789.665948 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles
-system.cpu1.Branches 7029914 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 63308003 93.28% 93.32% # Class of executed instruction
-system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction
-system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::MemRead 2784989 4.10% 97.50% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1695523 2.50% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 35537675 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 26584960 # number of times the CC registers were written
+system.cpu1.num_mem_refs 4433444 # number of memory refs
+system.cpu1.num_load_insts 2764122 # Number of load instructions
+system.cpu1.num_store_insts 1669322 # Number of store instructions
+system.cpu1.num_idle_cycles 2476870816.288117 # Number of idle cycles
+system.cpu1.num_busy_cycles 127152442.711883 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.048829 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.951171 # Percentage of idle cycles
+system.cpu1.Branches 7001569 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 28648 0.04% 0.04% # Class of executed instruction
+system.cpu1.op_class::IntAlu 63095899 93.33% 93.37% # Class of executed instruction
+system.cpu1.op_class::IntMult 28577 0.04% 93.41% # Class of executed instruction
+system.cpu1.op_class::IntDiv 20525 0.03% 93.44% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.44% # Class of executed instruction
+system.cpu1.op_class::MemRead 2764122 4.09% 97.53% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1669322 2.47% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 67870143 # Class of executed instruction
+system.cpu1.op_class::total 67607093 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 28758894 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 28758894 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 306803 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 26351534 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 25737629 # Number of BTB hits
+system.cpu2.branchPred.lookups 28894520 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 28894520 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 314484 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 26386768 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 25807983 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 97.670325 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 530881 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 61512 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 154845080 # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct 97.806533 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 541788 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 61672 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 154118891 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 9460785 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 141747704 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 28758894 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 26268510 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 54302787 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1434244 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 58972 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles 24471854 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 4161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 6545 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 20028 # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3117082 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 139514 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 1749 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 89437217 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 3.124405 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.409858 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 9526926 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 142222809 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 28894520 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 26349771 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 54464711 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1558370 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 64917 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 23183087 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 4981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 6096 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 25004 # Number of stall cycles due to pending traps
+system.cpu2.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3179586 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 151181 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 1925 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 88503258 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 3.167922 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.413230 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 35270123 39.44% 39.44% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 589507 0.66% 40.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 23704151 26.50% 66.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 307246 0.34% 66.94% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 603965 0.68% 67.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 802586 0.90% 68.51% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 334965 0.37% 68.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 517417 0.58% 69.47% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 27307257 30.53% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 34173678 38.61% 38.61% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 596420 0.67% 39.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 23721602 26.80% 66.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 320974 0.36% 66.45% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 619988 0.70% 67.15% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 815233 0.92% 68.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 353145 0.40% 68.47% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 523827 0.59% 69.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 27378391 30.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 89437217 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.185727 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.915416 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10926187 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 23367960 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 31523393 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 1298286 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1115198 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 278635226 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 49 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 1115198 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 11921655 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 13834152 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 4411879 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 31656208 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 5292001 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 277656292 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 6764 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 2483668 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 2130930 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 331880087 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 604361998 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 371268132 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 6 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 321920244 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 9959841 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 147988 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 148926 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 11485411 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6218482 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3410117 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 341148 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 274139 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 276004640 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 412430 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 274449569 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 59781 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 7023554 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 10820295 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 55045 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 89437217 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 3.068628 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.396853 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 88503258 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.187482 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.922812 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 10770329 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 22316529 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 33210052 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 993418 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1230628 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 279539625 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 15 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 1230628 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 11632631 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 11620518 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 4366536 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 33251587 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 6419117 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 278526444 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 145793 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 2942087 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 39888 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 2722851 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 332982462 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 606515542 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 372413837 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 321866415 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 11116047 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 145000 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 146469 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 9034946 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6263244 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3375371 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 381006 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 309187 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 276743563 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 411647 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 274777165 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 83308 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 7862427 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 12385425 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 57804 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 88503258 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 3.104712 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 2.400001 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 26098480 29.18% 29.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 6131096 6.86% 36.04% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3936751 4.40% 40.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 2730796 3.05% 43.49% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 25025448 27.98% 71.47% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1337810 1.50% 72.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 23830586 26.65% 99.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 291775 0.33% 99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 54475 0.06% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 25772149 29.12% 29.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 5479119 6.19% 35.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3780646 4.27% 39.58% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 2658058 3.00% 42.59% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 25098242 28.36% 70.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1415095 1.60% 72.54% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 23897363 27.00% 99.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 310729 0.35% 99.90% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 91857 0.10% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 89437217 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 88503258 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 125312 33.75% 33.75% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 120 0.03% 33.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 109 0.03% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 191005 51.44% 85.24% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 54802 14.76% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 130084 34.74% 34.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 34.74% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 103 0.03% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 196279 52.42% 87.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 48005 12.82% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 76601 0.03% 0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 264560846 96.40% 96.42% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 54414 0.02% 96.44% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 50942 0.02% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 6508971 2.37% 98.83% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3197795 1.17% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 79957 0.03% 0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 264964709 96.43% 96.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 54296 0.02% 96.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 50937 0.02% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.50% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 6495012 2.36% 98.86% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3132254 1.14% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 274449569 # Type of FU issued
-system.cpu2.iq.rate 1.772414 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 371348 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001353 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 638809448 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 283444416 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 273102485 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 12 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 274744310 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 6 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 641561 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 274777165 # Type of FU issued
+system.cpu2.iq.rate 1.782891 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 374471 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001363 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 638559252 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 285021199 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 273394851 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 275071659 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 20 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 655974 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 993516 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 6753 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 4280 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 500329 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1102337 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 6308 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4079 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 550460 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 656426 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 10045 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 656385 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 7890 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1115198 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 9119918 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 823405 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 276417070 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 70631 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6218482 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3410117 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 233790 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 637954 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 3900 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 4280 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 173413 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 173644 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 347057 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 273959168 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 6398525 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 490400 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 1230628 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 6003858 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 2680102 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 277155210 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 55656 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6263266 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3375371 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 233323 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 631738 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 1840063 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4079 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 177700 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 182074 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 359774 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 274266101 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 6377623 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 511064 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 9531292 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 27864904 # Number of branches executed
-system.cpu2.iew.exec_stores 3132767 # Number of stores executed
-system.cpu2.iew.exec_rate 1.769247 # Inst execution rate
-system.cpu2.iew.wb_sent 273810478 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 273102491 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 212979431 # num instructions producing a value
-system.cpu2.iew.wb_consumers 348314367 # num instructions consuming a value
+system.cpu2.iew.exec_refs 9440682 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 27899539 # Number of branches executed
+system.cpu2.iew.exec_stores 3063059 # Number of stores executed
+system.cpu2.iew.exec_rate 1.779575 # Inst execution rate
+system.cpu2.iew.wb_sent 274107922 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 273394865 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 213810949 # num instructions producing a value
+system.cpu2.iew.wb_consumers 349940477 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.763714 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.611457 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.773922 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.610992 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 7316358 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 357385 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 309115 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 88322018 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 3.046767 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.870309 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 8157845 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 353843 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 317282 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 87272630 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 3.082246 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.874009 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 30852434 34.93% 34.93% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4395307 4.98% 39.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1238857 1.40% 41.31% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24650858 27.91% 69.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 865215 0.98% 70.20% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 585749 0.66% 70.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 347954 0.39% 71.26% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23291491 26.37% 97.63% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 2094153 2.37% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 30201439 34.61% 34.61% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4017102 4.60% 39.21% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1154677 1.32% 40.53% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 24628965 28.22% 68.75% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 905267 1.04% 69.79% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 589610 0.68% 70.47% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 344278 0.39% 70.86% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23302755 26.70% 97.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 2128537 2.44% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 88322018 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 136303075 # Number of instructions committed
-system.cpu2.commit.committedOps 269096585 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 87272630 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 136196446 # Number of instructions committed
+system.cpu2.commit.committedOps 268995718 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8134753 # Number of memory references committed
-system.cpu2.commit.loads 5224965 # Number of loads committed
-system.cpu2.commit.membars 164376 # Number of memory barriers committed
-system.cpu2.commit.branches 27532187 # Number of branches committed
+system.cpu2.commit.refs 7985840 # Number of memory references committed
+system.cpu2.commit.loads 5160929 # Number of loads committed
+system.cpu2.commit.membars 163767 # Number of memory barriers committed
+system.cpu2.commit.branches 27540439 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 245708361 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 429087 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 43848 0.02% 0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 260815603 96.92% 96.94% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 52558 0.02% 96.96% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 49823 0.02% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.98% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 5224965 1.94% 98.92% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 2909788 1.08% 100.00% # Class of committed instruction
+system.cpu2.commit.int_insts 245590309 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 428081 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 46387 0.02% 0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 260861796 96.98% 96.99% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 52266 0.02% 97.01% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 49429 0.02% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 5160929 1.92% 98.95% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 2824911 1.05% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 269096585 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 2094153 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 268995718 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 2128537 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 362613065 # The number of ROB reads
-system.cpu2.rob.rob_writes 553944877 # The number of ROB writes
-system.cpu2.timesIdled 473034 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 65407863 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4900873955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 136303075 # Number of Instructions Simulated
-system.cpu2.committedOps 269096585 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.136035 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.136035 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.880254 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.880254 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 364552649 # number of integer regfile reads
-system.cpu2.int_regfile_writes 218803003 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 72918 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 139316304 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 107298284 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 88761943 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 132629 # number of misc regfile writes
+system.cpu2.rob.rob_reads 362270810 # The number of ROB reads
+system.cpu2.rob.rob_writes 555542201 # The number of ROB writes
+system.cpu2.timesIdled 475518 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 65615633 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4908375985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 136196446 # Number of Instructions Simulated
+system.cpu2.committedOps 268995718 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.131593 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.131593 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.883710 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.883710 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 364616127 # number of integer regfile reads
+system.cpu2.int_regfile_writes 219111496 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 72926 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes
+system.cpu2.cc_regfile_reads 139466740 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 107376389 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 88828545 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 129118 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
ACPI: Unable to load the System Description Tables\r
Using local APIC timer interrupts.\r
-result 7812444\r
+result 7812464\r
Detected 7.812 MHz APIC timer.\r
NET: Registered protocol family 16\r
PCI: Using configuration type 1\r
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/mcf
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:268435455
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:10:45
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:33:12
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x50d0380
+ 0: system.cpu.isa: ISA system set to: 0 0x666d940
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 26911921000 because target called exit()
+Exiting @ tick 26894328500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.026909 # Number of seconds simulated
-sim_ticks 26909234500 # Number of ticks simulated
-final_tick 26909234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.026894 # Number of seconds simulated
+sim_ticks 26894328500 # Number of ticks simulated
+final_tick 26894328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 142304 # Simulator instruction rate (inst/s)
-host_op_rate 143325 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42270537 # Simulator tick rate (ticks/s)
-host_mem_usage 446544 # Number of bytes of host memory used
-host_seconds 636.60 # Real time elapsed on the host
+host_inst_rate 165934 # Simulator instruction rate (inst/s)
+host_op_rate 167125 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 49262466 # Simulator tick rate (ticks/s)
+host_mem_usage 394132 # Number of bytes of host memory used
+host_seconds 545.94 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 45184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory
system.physmem.bytes_read::total 992640 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst 45184 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 45184 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 706 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1671991 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35216461 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 36888452 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1671991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1671991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1671991 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35216461 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 36888452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1680057 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 35228840 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 36908897 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1680057 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1680057 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1680057 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 35228840 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 36908897 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15510 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 987 # Per bank write bursts
system.physmem.perBankRdBursts::1 885 # Per bank write bursts
system.physmem.perBankRdBursts::2 942 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
-system.physmem.perBankRdBursts::4 1049 # Per bank write bursts
+system.physmem.perBankRdBursts::3 1029 # Per bank write bursts
+system.physmem.perBankRdBursts::4 1048 # Per bank write bursts
system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1078 # Per bank write bursts
+system.physmem.perBankRdBursts::7 1080 # Per bank write bursts
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
system.physmem.perBankRdBursts::9 957 # Per bank write bursts
-system.physmem.perBankRdBursts::10 935 # Per bank write bursts
+system.physmem.perBankRdBursts::10 936 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 905 # Per bank write bursts
-system.physmem.perBankRdBursts::13 865 # Per bank write bursts
-system.physmem.perBankRdBursts::14 877 # Per bank write bursts
+system.physmem.perBankRdBursts::13 863 # Per bank write bursts
+system.physmem.perBankRdBursts::14 876 # Per bank write bursts
system.physmem.perBankRdBursts::15 896 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 26909036500 # Total gap between requests
+system.physmem.totGap 26894128500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 10635 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4635 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 219 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 10369 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4857 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1363 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 726.491563 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 533.334896 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 387.223532 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 140 10.27% 10.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 158 11.59% 21.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 56 4.11% 25.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 68 4.99% 30.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 57 4.18% 35.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 39 2.86% 38.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 24 1.76% 39.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 39 2.86% 42.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 782 57.37% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1363 # Bytes accessed per row activation
-system.physmem.totQLat 83369750 # Total ticks spent queuing
-system.physmem.totMemAccLat 374182250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 1366 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 726.489019 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 530.637647 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 387.552146 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 153 11.20% 11.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 146 10.69% 21.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 54 3.95% 25.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 65 4.76% 30.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 57 4.17% 34.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 41 3.00% 37.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 35 2.56% 40.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 33 2.42% 42.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 782 57.25% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1366 # Bytes accessed per row activation
+system.physmem.totQLat 88775250 # Total ticks spent queuing
+system.physmem.totMemAccLat 379587750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5375.23 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5723.74 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24125.23 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24473.74 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.29 # Data bus utilization in percentage
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 14137 # Number of row buffer hits during reads
+system.physmem.readRowHits 14143 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1734947.55 # Average gap between requests
-system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 24303660500 # Time in different power states
-system.physmem.memoryStateTime::REF 898300000 # Time in different power states
+system.physmem.avgGap 1733986.36 # Average gap between requests
+system.physmem.pageHitRate 91.19 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 24303280500 # Time in different power states
+system.physmem.memoryStateTime::REF 898040000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1704463000 # Time in different power states
+system.physmem.memoryStateTime::ACT 1692660750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 36888452 # Throughput (bytes/s)
+system.membus.throughput 36908897 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 972 # Transaction distribution
system.membus.trans_dist::ReadResp 972 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31026 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31026 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31022 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 31022 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 992640 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 19094500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 18401000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 145899997 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 145166999 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 26684247 # Number of BP lookups
-system.cpu.branchPred.condPredicted 22003797 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 841589 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11372801 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11278925 # Number of BTB hits
+system.cpu.branchPred.lookups 27364118 # Number of BP lookups
+system.cpu.branchPred.condPredicted 22575249 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 843312 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11626081 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 11546341 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.174557 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 69990 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.314128 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 70079 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 187 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53818470 # number of cpu cycles simulated
+system.cpu.numCycles 53788658 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 14166768 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127874482 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26684247 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11348915 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24030832 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4761225 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11326508 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 14474692 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 130915195 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 27364118 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11616420 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24576695 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5106515 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 9886759 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13838942 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 329737 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53427318 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.409937 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.214887 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 14156505 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 349331 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 53187301 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.478661 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.235073 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29434889 55.09% 55.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3387974 6.34% 61.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2027945 3.80% 65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1552978 2.91% 68.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1665988 3.12% 71.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2918810 5.46% 76.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1512193 2.83% 79.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1089826 2.04% 81.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9836715 18.41% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 28648969 53.86% 53.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3469200 6.52% 60.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2052434 3.86% 64.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1567853 2.95% 67.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1679873 3.16% 70.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 3021837 5.68% 76.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1566641 2.95% 78.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1116795 2.10% 81.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10063699 18.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53427318 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.495820 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.376033 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16930628 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9172800 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22402161 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1027234 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3894495 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4441775 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8644 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126055074 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42561 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3894495 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18710503 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3595532 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 186271 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21547494 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5493023 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123139917 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 426575 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4604902 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1527 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143588109 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536432016 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 499923969 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 641 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 53187301 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.508734 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.433881 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16310855 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8657573 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 23455900 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 522552 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4240421 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4543490 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 8671 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 129206748 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 42514 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4240421 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 17921369 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2850180 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 191379 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 22351654 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5632298 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 126131712 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1889841 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 3251328 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 563418 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 3246 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 146876533 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 549573070 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 512042051 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 826 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36173923 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4624 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4622 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12547663 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29472846 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5519091 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2169224 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1269381 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118159243 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8489 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105145248 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 78272 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26728441 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65602174 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 271 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53427318 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.968005 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.908888 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 39462347 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4633 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 4631 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 9072079 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 30275485 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5599467 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2184620 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1363504 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 120806561 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 8485 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 105954089 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 91175 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 29372689 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 73925597 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 267 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 53187301 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.992094 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.919550 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15370604 28.77% 28.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11662585 21.83% 50.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8230563 15.41% 66.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6832993 12.79% 78.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4979120 9.32% 88.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2926966 5.48% 93.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2444206 4.57% 98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 536236 1.00% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 444045 0.83% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 15526622 29.19% 29.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10753574 20.22% 49.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8641028 16.25% 65.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6157106 11.58% 77.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5949684 11.19% 88.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2742880 5.16% 93.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2429206 4.57% 98.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 538839 1.01% 99.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 448362 0.84% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53427318 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 53187301 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 46059 6.94% 6.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 26 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 341162 51.43% 58.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 276052 41.62% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 44574 8.99% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 27 0.01% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 174239 35.13% 44.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 277108 55.87% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74418244 70.78% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 122 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 157 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25603497 24.35% 95.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5112252 4.86% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 75094311 70.87% 70.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10550 0.01% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 140 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 196 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25720178 24.27% 95.16% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5128709 4.84% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105145248 # Type of FU issued
-system.cpu.iq.rate 1.953702 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 663299 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006308 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264458762 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144900942 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102674293 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 623 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 845 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 263 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105808235 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 312 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 440410 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105954089 # Type of FU issued
+system.cpu.iq.rate 1.969822 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 495948 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.004681 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 265681854 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 150192687 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 103425723 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 748 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1061 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 319 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 106449666 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 371 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 469381 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6898880 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6071 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6331 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 774247 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 7701519 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7870 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 6982 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 854623 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31563 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 30068 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3894495 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 960394 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 127228 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118180427 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309851 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29472846 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5519091 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4601 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 65954 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6808 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6331 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446096 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 445462 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 891558 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104169534 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25284727 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 975714 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4240421 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 731718 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 478226 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 120827778 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 309730 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 30275485 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5599467 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 4597 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 72415 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 359917 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 6982 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 447833 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 447193 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 895026 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104954211 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25387781 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 999878 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12695 # number of nop insts executed
-system.cpu.iew.exec_refs 30339844 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21324580 # Number of branches executed
-system.cpu.iew.exec_stores 5055117 # Number of stores executed
-system.cpu.iew.exec_rate 1.935572 # Inst execution rate
-system.cpu.iew.wb_sent 102952816 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102674556 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62244775 # num instructions producing a value
-system.cpu.iew.wb_consumers 104288684 # num instructions consuming a value
+system.cpu.iew.exec_nop 12732 # number of nop insts executed
+system.cpu.iew.exec_refs 30458601 # number of memory reference insts executed
+system.cpu.iew.exec_branches 21526378 # Number of branches executed
+system.cpu.iew.exec_stores 5070820 # Number of stores executed
+system.cpu.iew.exec_rate 1.951233 # Inst execution rate
+system.cpu.iew.wb_sent 103717343 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 103426042 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 62672484 # num instructions producing a value
+system.cpu.iew.wb_consumers 105780863 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.907794 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596851 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.922823 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.592475 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26930418 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 29588025 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 833018 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 49532823 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.842273 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.541112 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 834722 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 48946880 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.864326 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.553843 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 20056290 40.49% 40.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13134081 26.52% 67.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4165062 8.41% 75.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3431851 6.93% 82.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1531687 3.09% 85.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 719294 1.45% 86.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 966848 1.95% 88.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 252784 0.51% 89.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5274926 10.65% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 19590544 40.02% 40.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13003525 26.57% 66.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4154420 8.49% 75.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3492472 7.14% 82.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1473630 3.01% 85.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 727145 1.49% 86.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 923215 1.89% 88.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 261788 0.53% 89.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5320141 10.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 49532823 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 48946880 # Number of insts commited each cycle
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5274926 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5320141 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162435541 # The number of ROB reads
-system.cpu.rob.rob_writes 240280947 # The number of ROB writes
-system.cpu.timesIdled 46113 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 391152 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 164461990 # The number of ROB reads
+system.cpu.rob.rob_writes 245943119 # The number of ROB writes
+system.cpu.timesIdled 58216 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 601357 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.594090 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.594090 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.683247 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.683247 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495503749 # number of integer regfile reads
-system.cpu.int_regfile_writes 120538753 # number of integer regfile writes
-system.cpu.fp_regfile_reads 136 # number of floating regfile reads
-system.cpu.fp_regfile_writes 324 # number of floating regfile writes
-system.cpu.misc_regfile_reads 29202777 # number of misc regfile reads
+system.cpu.cpi 0.593761 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.593761 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.684180 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.684180 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 499033245 # number of integer regfile reads
+system.cpu.int_regfile_writes 121427335 # number of integer regfile writes
+system.cpu.fp_regfile_reads 166 # number of floating regfile reads
+system.cpu.fp_regfile_writes 402 # number of floating regfile writes
+system.cpu.misc_regfile_reads 29301616 # number of misc regfile reads
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 4498112646 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 904542 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 904541 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 942913 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 43808 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 43808 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1459 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838157 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2839616 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993984 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 1888546500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 4500548582 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 907410 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 907410 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 942895 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 40933 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 40933 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1463 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838119 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 2839582 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120992384 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 121039168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 121039168 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 1888514500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1214249 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1215999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1424437743 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1424171240 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
-system.cpu.icache.tags.replacements 4 # number of replacements
-system.cpu.icache.tags.tagsinuse 629.782020 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 13837957 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 727 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 19034.328748 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 3 # number of replacements
+system.cpu.icache.tags.tagsinuse 631.006365 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 14155509 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 731 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 19364.581395 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 629.782020 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.307511 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.307511 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 723 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 671 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.353027 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 27678613 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 27678613 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 13837957 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13837957 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13837957 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13837957 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13837957 # number of overall hits
-system.cpu.icache.overall_hits::total 13837957 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
-system.cpu.icache.overall_misses::total 984 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 66510498 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 66510498 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 66510498 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 66510498 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 66510498 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 66510498 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13838941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13838941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13838941 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13838941 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13838941 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13838941 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67591.969512 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67591.969512 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67591.969512 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67591.969512 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67591.969512 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67591.969512 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 649 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 631.006365 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.308109 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.308109 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 728 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.355469 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 28313740 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 28313740 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 14155509 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 14155509 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 14155509 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 14155509 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 14155509 # number of overall hits
+system.cpu.icache.overall_hits::total 14155509 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 995 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 995 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 995 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 995 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 995 # number of overall misses
+system.cpu.icache.overall_misses::total 995 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 67178998 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 67178998 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 67178998 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 67178998 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 67178998 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 67178998 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 14156504 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 14156504 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 14156504 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 14156504 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 14156504 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 14156504 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67516.580905 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67516.580905 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 593 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 54.083333 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 59.300000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 252 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 252 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 252 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 252 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 252 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 263 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 263 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 263 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 263 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 732 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50737500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 50737500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50737500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 50737500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50737500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 50737500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69313.524590 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69313.524590 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69313.524590 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69313.524590 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69313.524590 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69313.524590 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50814250 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 50814250 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50814250 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 50814250 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50814250 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 50814250 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69418.374317 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69418.374317 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 10725.417134 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1831324 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 15493 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 118.203318 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 10751.524012 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1834202 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 15494 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 118.381438 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 9880.636903 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 615.219172 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 229.561060 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.301533 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018775 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.007006 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.327314 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 15493 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 9904.575959 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 617.996997 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 228.951056 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.302264 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018860 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.006987 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.328110 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 15494 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1303 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13611 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472809 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 15189406 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 15189406 # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1306 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13614 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472839 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 15186331 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 15186331 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 903531 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 903555 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 942913 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 942913 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 29270 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 29270 # number of ReadExReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 906402 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 906426 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 942895 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 942895 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 26395 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 26395 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 932801 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 932825 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 932797 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 932821 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 932801 # number of overall hits
-system.cpu.l2cache.overall_hits::total 932825 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses
+system.cpu.l2cache.overall_hits::cpu.data 932797 # number of overall hits
+system.cpu.l2cache.overall_hits::total 932821 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 707 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 983 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 707 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15521 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 707 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses
system.cpu.l2cache.overall_misses::total 15521 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49767750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21366250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 71134000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 972292000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 972292000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 49767750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 993658250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 1043426000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 49767750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 993658250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 1043426000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 728 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 903810 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 904538 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 942913 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 942913 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 43808 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 43808 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 728 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 947618 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 948346 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 728 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 947618 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 948346 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.001087 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.331857 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.331857 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49834500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21050250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 70884750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 978125750 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 978125750 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 49834500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 999176000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 1049010500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 49834500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 999176000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 1049010500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 731 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 906678 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 907409 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 942895 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 942895 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 40933 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 40933 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 731 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 947611 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 948342 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 731 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 947611 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 948342 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967168 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000304 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.355166 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.355166 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967168 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016366 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967168 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016366 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70692.826705 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76581.541219 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72364.191251 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66879.350667 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66879.350667 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70692.826705 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67062.040224 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67226.725082 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70692.826705 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67062.040224 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67226.725082 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70487.270156 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76269.021739 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72110.630722 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67280.626634 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67280.626634 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67586.527930 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67586.527930 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 706 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 266 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 706 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15510 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 706 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15510 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40904000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17399000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58303000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 788854000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 788854000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40904000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 806253000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 847157000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40904000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 806253000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 847157000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001075 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.331857 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.331857 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40933250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17118000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58051250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 795610750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 795610750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40933250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 812728750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 853662000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40933250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 812728750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 853662000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.355166 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.355166 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016355 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016355 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58184.921764 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64680.297398 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59982.510288 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57979.107649 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64353.383459 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59723.508230 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54261.521530 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54261.521530 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58184.921764 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54450.800297 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54620.051580 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58184.921764 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54450.800297 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54620.051580 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54726.286284 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54726.286284 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 943522 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3671.877894 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 28137275 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 947618 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 29.692635 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 8001790250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3671.877894 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.896455 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.896455 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 943515 # number of replacements
+system.cpu.dcache.tags.tagsinuse 3673.207831 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 28229578 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 947611 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 29.790260 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 7976079250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 3673.207831 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.896779 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.896779 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 461 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 3114 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 521 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 452 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 3133 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 59974850 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 59974850 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23597129 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23597129 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4532332 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4532332 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3919 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3919 # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses 60126081 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 60126081 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 23676805 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 23676805 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4544974 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4544974 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 28129461 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28129461 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28129461 # number of overall hits
-system.cpu.dcache.overall_hits::total 28129461 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1173693 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1173693 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 202649 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 202649 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1376342 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1376342 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1376342 # number of overall misses
-system.cpu.dcache.overall_misses::total 1376342 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 13892857479 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 13892857479 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8552070346 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8552070346 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 22444927825 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 22444927825 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 22444927825 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 22444927825 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24770822 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24770822 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 28221779 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 28221779 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 28221779 # number of overall hits
+system.cpu.dcache.overall_hits::total 28221779 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1169644 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1169644 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 190007 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 190007 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1359651 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1359651 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1359651 # number of overall misses
+system.cpu.dcache.overall_misses::total 1359651 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 13867675477 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 13867675477 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 8610605390 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8610605390 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 264500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 264500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 22478280867 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 22478280867 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 22478280867 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 22478280867 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 24846449 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 24846449 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3926 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3926 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 29505803 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 29505803 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 29505803 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 29505803 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047382 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.047382 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042798 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.042798 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001783 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001783 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.046646 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.046646 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.046646 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.046646 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.875127 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.875127 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42201.394263 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42201.394263 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16307.667589 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16307.667589 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16307.667589 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16307.667589 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 154301 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 29581430 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 29581430 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 29581430 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 29581430 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047075 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.047075 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040128 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.040128 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002042 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002042 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.045963 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.045963 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.045963 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.045963 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16532.390199 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16532.390199 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 136970 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 23947 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 24472 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.443438 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.597009 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942913 # number of writebacks
-system.cpu.dcache.writebacks::total 942913 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269863 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 269863 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158857 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 158857 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 428720 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 428720 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 428720 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 428720 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903830 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 903830 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43792 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43792 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947622 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947622 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947622 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947622 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9993578260 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9993578260 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1330001932 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1330001932 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323580192 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11323580192 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323580192 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11323580192 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036488 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036488 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009249 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009249 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.922496 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.922496 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30370.888107 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30370.888107 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.469506 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.469506 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.469506 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.469506 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 942895 # number of writebacks
+system.cpu.dcache.writebacks::total 942895 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262958 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 262958 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 149081 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 149081 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 412039 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 412039 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 412039 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 412039 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906686 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 906686 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40926 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 40926 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 947612 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 947612 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 947612 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 947612 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10019308761 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 10019308761 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1304642257 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1304642257 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323951018 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 11323951018 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323951018 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 11323951018 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036492 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036492 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008643 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008643 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032034 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032034 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/x86/linux/mcf
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:268435455
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 19:53:01
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+gem5 compiled Jun 21 2014 11:13:07
+gem5 started Jun 21 2014 16:50:55
+gem5 executing on phenom
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 65613727000 because target called exit()
+Exiting @ tick 64361067000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.065585 # Number of seconds simulated
-sim_ticks 65585340000 # Number of ticks simulated
-final_tick 65585340000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.064361 # Number of seconds simulated
+sim_ticks 64361067000 # Number of ticks simulated
+final_tick 64361067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 87128 # Simulator instruction rate (inst/s)
-host_op_rate 153419 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36169402 # Simulator tick rate (ticks/s)
-host_mem_usage 428764 # Number of bytes of host memory used
-host_seconds 1813.28 # Real time elapsed on the host
+host_inst_rate 110006 # Simulator instruction rate (inst/s)
+host_op_rate 193702 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44813910 # Simulator tick rate (ticks/s)
+host_mem_usage 383472 # Number of bytes of host memory used
+host_seconds 1436.19 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1883456 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1947520 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory
-system.physmem.bytes_written::total 11200 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29429 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30430 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 175 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 976804 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28717637 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29694441 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 976804 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 976804 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 170770 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 170770 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 170770 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 976804 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28717637 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 29865211 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30432 # Number of read requests accepted
-system.physmem.writeReqs 175 # Number of write requests accepted
-system.physmem.readBursts 30432 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1942848 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 4800 # Total number of bytes read from write queue
-system.physmem.bytesWritten 10048 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 1947648 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 64000 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 64000 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 64000 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 10944 # Number of bytes written to this memory
+system.physmem.bytes_written::total 10944 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1000 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 171 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 171 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 994390 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 29256942 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 30251332 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 994390 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 994390 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 170041 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 170041 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 170041 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 994390 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 29256942 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 30421373 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 30424 # Number of read requests accepted
+system.physmem.writeReqs 171 # Number of write requests accepted
+system.physmem.readBursts 30424 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 171 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 1942272 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 4864 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9152 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 1947136 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 10944 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 76 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 1922 # Per bank write bursts
-system.physmem.perBankRdBursts::1 2061 # Per bank write bursts
-system.physmem.perBankRdBursts::2 2029 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1929 # Per bank write bursts
+system.physmem.perBankRdBursts::0 1923 # Per bank write bursts
+system.physmem.perBankRdBursts::1 2059 # Per bank write bursts
+system.physmem.perBankRdBursts::2 2030 # Per bank write bursts
+system.physmem.perBankRdBursts::3 1927 # Per bank write bursts
system.physmem.perBankRdBursts::4 2025 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1900 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1964 # Per bank write bursts
+system.physmem.perBankRdBursts::5 1901 # Per bank write bursts
+system.physmem.perBankRdBursts::6 1962 # Per bank write bursts
system.physmem.perBankRdBursts::7 1863 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1940 # Per bank write bursts
-system.physmem.perBankRdBursts::9 1934 # Per bank write bursts
+system.physmem.perBankRdBursts::8 1938 # Per bank write bursts
+system.physmem.perBankRdBursts::9 1933 # Per bank write bursts
system.physmem.perBankRdBursts::10 1804 # Per bank write bursts
system.physmem.perBankRdBursts::11 1796 # Per bank write bursts
system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
-system.physmem.perBankRdBursts::14 1820 # Per bank write bursts
+system.physmem.perBankRdBursts::14 1817 # Per bank write bursts
system.physmem.perBankRdBursts::15 1778 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7 # Per bank write bursts
-system.physmem.perBankWrBursts::1 84 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9 # Per bank write bursts
-system.physmem.perBankWrBursts::3 29 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::0 9 # Per bank write bursts
+system.physmem.perBankWrBursts::1 79 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8 # Per bank write bursts
+system.physmem.perBankWrBursts::3 14 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7 # Per bank write bursts
system.physmem.perBankWrBursts::6 12 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6 # Per bank write bursts
+system.physmem.perBankWrBursts::9 5 # Per bank write bursts
system.physmem.perBankWrBursts::10 3 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 65585323000 # Total gap between requests
+system.physmem.totGap 64361050000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 30432 # Read request sizes (log2)
+system.physmem.readPktSize::6 30424 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 175 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 357 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 171 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 29879 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 374 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 2701 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 722.766383 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 519.037520 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 387.855736 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 380 14.07% 14.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 203 7.52% 21.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 114 4.22% 25.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 105 3.89% 29.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 110 4.07% 33.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 132 4.89% 38.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 83 3.07% 41.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 80 2.96% 44.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 1494 55.31% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 2701 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 3366.777778 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 25.330646 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 10057.961719 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.444444 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.423969 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.881917 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2 22.22% 22.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1 11.11% 33.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 6 66.67% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads
-system.physmem.totQLat 122012500 # Total ticks spent queuing
-system.physmem.totMemAccLat 691206250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 151785000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 4019.25 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 2692 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 724.017831 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 522.534866 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 387.414799 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 354 13.15% 13.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 226 8.40% 21.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 117 4.35% 25.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 114 4.23% 30.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 102 3.79% 33.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 97 3.60% 37.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 103 3.83% 41.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 99 3.68% 45.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 1480 54.98% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 2692 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 3785.250000 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 36.090663 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 10663.878800 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.875000 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.857209 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.834523 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 6 75.00% 87.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1 12.50% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads
+system.physmem.totQLat 124712250 # Total ticks spent queuing
+system.physmem.totMemAccLat 693737250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 151740000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 4109.41 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 22769.25 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 29.62 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 22859.41 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 30.18 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 30.25 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.23 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.24 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 15.09 # Average write queue length when enqueuing
-system.physmem.readRowHits 27699 # Number of row buffer hits during reads
-system.physmem.writeRowHits 110 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 91.24 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.86 # Row buffer hit rate for writes
-system.physmem.avgGap 2142821.02 # Average gap between requests
-system.physmem.pageHitRate 91.08 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 59149173500 # Time in different power states
-system.physmem.memoryStateTime::REF 2189980000 # Time in different power states
+system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing
+system.physmem.readRowHits 27697 # Number of row buffer hits during reads
+system.physmem.writeRowHits 92 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 91.26 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 53.80 # Row buffer hit rate for writes
+system.physmem.avgGap 2103646.02 # Average gap between requests
+system.physmem.pageHitRate 91.05 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 58016949500 # Time in different power states
+system.physmem.memoryStateTime::REF 2148900000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 4244704000 # Time in different power states
+system.physmem.memoryStateTime::ACT 4191773500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 29864235 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 1427 # Transaction distribution
-system.membus.trans_dist::ReadResp 1424 # Transaction distribution
-system.membus.trans_dist::Writeback 175 # Transaction distribution
-system.membus.trans_dist::ReadExReq 29005 # Transaction distribution
-system.membus.trans_dist::ReadExResp 29005 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61036 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61036 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 61036 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1958656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 1958656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 1958656 # Total data (bytes)
+system.membus.throughput 30420378 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1422 # Transaction distribution
+system.membus.trans_dist::ReadResp 1419 # Transaction distribution
+system.membus.trans_dist::Writeback 171 # Transaction distribution
+system.membus.trans_dist::ReadExReq 29002 # Transaction distribution
+system.membus.trans_dist::ReadExResp 29002 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61016 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61016 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 61016 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957888 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957888 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1957888 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1957888 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 35026000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 35504500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 284359000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 284722250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 33857939 # Number of BP lookups
-system.cpu.branchPred.condPredicted 33857939 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 774699 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 19294742 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 19202488 # Number of BTB hits
+system.cpu.branchPred.lookups 34798086 # Number of BP lookups
+system.cpu.branchPred.condPredicted 34798086 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 784118 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 19722572 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 19623609 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.521870 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 5017287 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 5447 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.498225 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 5229209 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 5537 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 131170685 # number of cpu cycles simulated
+system.cpu.numCycles 128722137 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 26133192 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 182246280 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 33857939 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24219775 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 55455334 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5351155 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 44937204 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 289 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 26886538 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 188337970 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 34798086 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24852818 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 57142929 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6497811 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 38531317 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 400 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 25572777 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 166462 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 131067108 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.451414 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.313936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 26333180 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 202728 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 128229739 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.583672 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.351921 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 78089059 59.58% 59.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1960403 1.50% 61.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2941378 2.24% 63.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3833422 2.92% 66.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7766051 5.93% 72.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4756858 3.63% 75.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2667148 2.03% 77.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1317375 1.01% 78.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 27735414 21.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 73621715 57.41% 57.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2024375 1.58% 58.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 3018246 2.35% 61.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3935135 3.07% 64.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7973611 6.22% 70.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4963159 3.87% 74.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2723923 2.12% 76.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1373007 1.07% 77.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 28596568 22.30% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 131067108 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.258121 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.389383 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 36820362 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37159698 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 43897766 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8648241 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4541041 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 318820485 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 4541041 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 42311218 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 9731436 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7378 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 46747775 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 27728260 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 314978384 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 26284 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 25867087 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 317148193 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 836430617 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 514996548 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 444 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 128229739 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.270335 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.463136 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 33273315 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 35123523 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 52275495 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1888908 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5668498 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 328717141 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 5668498 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37218540 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3059312 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 10022 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 50252159 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 32021208 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 323526783 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1441 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 292036 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 27143978 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 4136186 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 325451198 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 859036392 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 529005653 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 495 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 37935446 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 481 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 479 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 62636107 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 101548078 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 34773749 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 39632863 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5801803 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 311454794 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1640 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 300260019 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 90405 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 32683934 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 46065887 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1195 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 131067108 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.290888 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.699985 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 46238451 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 482 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 38827180 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 104278858 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 35723148 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 46025226 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 6660051 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 319586854 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1670 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 304359156 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 192192 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 40795282 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 60346573 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1225 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 128229739 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.373546 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.813536 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24336657 18.57% 18.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 23236619 17.73% 36.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25445511 19.41% 55.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 25817468 19.70% 75.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 18870400 14.40% 89.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 8268823 6.31% 96.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 3966909 3.03% 99.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 944963 0.72% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 179758 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 28989242 22.61% 22.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 17448953 13.61% 36.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 19181395 14.96% 51.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 24360940 19.00% 70.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 22567411 17.60% 87.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 10236760 7.98% 95.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4240558 3.31% 99.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1068039 0.83% 99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 136441 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 131067108 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 128229739 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 31509 1.53% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1916553 93.05% 94.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 111592 5.42% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 85597 3.62% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2173481 92.00% 95.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 103394 4.38% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 169826780 56.56% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11192 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 97302133 32.41% 88.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 33088277 11.02% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 172841480 56.79% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11196 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 41 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 97881417 32.16% 88.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 33591350 11.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 300260019 # Type of FU issued
-system.cpu.iq.rate 2.289079 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2059654 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006860 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 733736743 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 344172361 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 298003080 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 638 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 138 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 302288185 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 212 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 54177955 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 304359156 # Type of FU issued
+system.cpu.iq.rate 2.364466 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2362472 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007762 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 739502310 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 360419132 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 302118974 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 682 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 306688087 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 202 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 56122672 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 10768693 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 31319 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 33463 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3333997 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 13499473 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 33923 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 36991 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 4283396 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3215 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3583 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 18172 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4541041 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2814889 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 161942 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 311456434 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 197084 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 101548078 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 34773749 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2528 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 73554 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 33463 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 393542 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 427902 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 821444 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 298855458 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 96888981 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1404561 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 5668498 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 78601 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2898580 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 319588524 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 72060 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 104278858 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 35723148 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 467 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4947 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2697345 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 36991 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 397417 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 436010 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 833427 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 302993807 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 97430054 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1365349 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 129814280 # number of memory reference insts executed
-system.cpu.iew.exec_branches 30819367 # Number of branches executed
-system.cpu.iew.exec_stores 32925299 # Number of stores executed
-system.cpu.iew.exec_rate 2.278371 # Inst execution rate
-system.cpu.iew.wb_sent 298372320 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 298003218 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 218247752 # num instructions producing a value
-system.cpu.iew.wb_consumers 296740863 # num instructions consuming a value
+system.cpu.iew.exec_refs 130824453 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31189297 # Number of branches executed
+system.cpu.iew.exec_stores 33394399 # Number of stores executed
+system.cpu.iew.exec_rate 2.353859 # Inst execution rate
+system.cpu.iew.wb_sent 302554101 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 302119118 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 223057856 # num instructions producing a value
+system.cpu.iew.wb_consumers 305896063 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.271874 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.735483 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.347064 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.729195 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 33277101 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 41496946 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 774736 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 126526067 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.198697 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.971805 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 784165 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 122561241 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.269824 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 3.033262 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58264985 46.05% 46.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 19162475 15.15% 61.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 11581155 9.15% 70.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9447794 7.47% 77.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1880712 1.49% 79.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2075089 1.64% 80.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1295892 1.02% 81.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 693068 0.55% 82.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22124897 17.49% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 56600375 46.18% 46.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 17466589 14.25% 60.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 11063696 9.03% 69.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 8855238 7.23% 76.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1990404 1.62% 78.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1890723 1.54% 79.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1087341 0.89% 80.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 761508 0.62% 81.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22845367 18.64% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 126526067 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 122561241 # Number of insts commited each cycle
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
-system.cpu.commit.bw_lim_events 22124897 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22845367 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 415870735 # The number of ROB reads
-system.cpu.rob.rob_writes 627483927 # The number of ROB writes
-system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 103577 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 419405284 # The number of ROB reads
+system.cpu.rob.rob_writes 645053666 # The number of ROB writes
+system.cpu.timesIdled 104925 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 492398 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.830254 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.830254 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.204450 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.204450 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 483721911 # number of integer regfile reads
-system.cpu.int_regfile_writes 234579114 # number of integer regfile writes
-system.cpu.fp_regfile_reads 126 # number of floating regfile reads
-system.cpu.fp_regfile_writes 70 # number of floating regfile writes
-system.cpu.cc_regfile_reads 107055944 # number of cc regfile reads
-system.cpu.cc_regfile_writes 64002928 # number of cc regfile writes
-system.cpu.misc_regfile_reads 191820739 # number of misc regfile reads
+system.cpu.cpi 0.814756 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.814756 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.227361 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.227361 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 488589645 # number of integer regfile reads
+system.cpu.int_regfile_writes 237913555 # number of integer regfile writes
+system.cpu.fp_regfile_reads 124 # number of floating regfile reads
+system.cpu.fp_regfile_writes 93 # number of floating regfile writes
+system.cpu.cc_regfile_reads 107415229 # number of cc regfile reads
+system.cpu.cc_regfile_writes 64109444 # number of cc regfile writes
+system.cpu.misc_regfile_reads 194048137 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 4043936892 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1995332 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1995329 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2066459 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 82321 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 82321 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2030 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219732 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6221762 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64960 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265158016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 265222976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 265222976 # Total data (bytes)
+system.cpu.toL2Bus.throughput 4120563135 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1995370 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1995367 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2066178 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 82265 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 82265 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2034 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219411 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 6221445 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65088 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265138752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 265203840 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 265203840 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4138515000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1696250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 4138084500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 6.4 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1694000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3121723249 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%)
-system.cpu.icache.tags.replacements 55 # number of replacements
-system.cpu.icache.tags.tagsinuse 822.073751 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 25571467 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1015 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 25193.563547 # Average number of references to valid blocks.
+system.cpu.toL2Bus.respLayer1.occupancy 3121568749 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 4.9 # Layer utilization (%)
+system.cpu.icache.tags.replacements 56 # number of replacements
+system.cpu.icache.tags.tagsinuse 820.274669 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 26331871 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1017 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 25891.711898 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 822.073751 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.401403 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.401403 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 51146569 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 51146569 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 25571467 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 25571467 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 25571467 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 25571467 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 25571467 # number of overall hits
-system.cpu.icache.overall_hits::total 25571467 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1310 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1310 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1310 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1310 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1310 # number of overall misses
-system.cpu.icache.overall_misses::total 1310 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 88805250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 88805250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 88805250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 88805250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 88805250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 88805250 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 25572777 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 25572777 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 25572777 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 25572777 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 25572777 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 25572777 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67790.267176 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67790.267176 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67790.267176 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67790.267176 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67790.267176 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67790.267176 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 116 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 820.274669 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.400525 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.400525 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 961 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.469238 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 52667377 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 52667377 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 26331871 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 26331871 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 26331871 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 26331871 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 26331871 # number of overall hits
+system.cpu.icache.overall_hits::total 26331871 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1309 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1309 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1309 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1309 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1309 # number of overall misses
+system.cpu.icache.overall_misses::total 1309 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 89709250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 89709250 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 89709250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 89709250 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 89709250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 89709250 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 26333180 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 26333180 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 26333180 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 26333180 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 26333180 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 26333180 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68532.658518 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68532.658518 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68532.658518 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68532.658518 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68532.658518 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68532.658518 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 38.666667 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 39 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 295 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 295 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 295 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 295 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1015 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1015 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1015 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1015 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1015 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1015 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69941750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 69941750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69941750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 69941750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69941750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 69941750 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68908.128079 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68908.128079 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68908.128079 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68908.128079 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68908.128079 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68908.128079 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 292 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 292 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 292 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 292 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 292 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1017 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1017 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1017 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70297000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 70297000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70297000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 70297000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70297000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 70297000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69121.927237 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69121.927237 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69121.927237 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69121.927237 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69121.927237 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69121.927237 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 490 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 20815.284491 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 4029213 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 30412 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 132.487604 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 489 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 20838.141939 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 4029004 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 132.511232 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19896.837490 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.064611 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 247.382390 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.607203 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020479 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.007550 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.635232 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 29922 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 19919.361133 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.825750 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 250.955056 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.607891 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020380 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.007659 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.635930 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 29916 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 769 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1376 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27649 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913147 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 33265629 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 33265629 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1993891 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1993905 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 2066459 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 2066459 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 53316 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 53316 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2047207 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2047221 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2047207 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2047221 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 1001 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 426 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1427 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 29005 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 29005 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 1001 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 29431 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 30432 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 1001 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 29431 # number of overall misses
-system.cpu.l2cache.overall_misses::total 30432 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68781250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30133000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 98914250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1888274750 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 1888274750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 68781250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 1918407750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 1987189000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 68781250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 1918407750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 1987189000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1994317 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1995332 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 2066459 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 2066459 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 82321 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 82321 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2076638 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2077653 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2076638 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2077653 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986207 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.000715 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352340 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.352340 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986207 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.014172 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.014647 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986207 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.014172 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.014647 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68712.537463 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70734.741784 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69316.222845 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65101.697983 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65101.697983 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68712.537463 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65183.233665 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 65299.323081 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68712.537463 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65183.233665 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 65299.323081 # average overall miss latency
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.912964 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 33263174 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 33263174 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1993931 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1993948 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 2066178 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 2066178 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 53263 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 53263 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 2047194 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2047211 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 2047194 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2047211 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 1000 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1422 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 29002 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 29002 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 1000 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 29424 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 30424 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 1000 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses
+system.cpu.l2cache.overall_misses::total 30424 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 69106000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29389750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 98495750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1891412500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1891412500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 69106000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 1920802250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 1989908250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 69106000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 1920802250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 1989908250 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1017 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1994353 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1995370 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 2066178 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 2066178 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 82265 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 82265 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 1017 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2076618 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2077635 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1017 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2076618 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2077635 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983284 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000212 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.000713 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352544 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.352544 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983284 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983284 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69643.957346 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69265.646976 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65216.622992 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65216.622992 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69106 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65280.119970 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 65405.872009 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69106 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65280.119970 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 65405.872009 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks
-system.cpu.l2cache.writebacks::total 175 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1001 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1427 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29005 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 29005 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1001 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29431 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 30432 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1001 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29431 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 30432 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 56223750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24897500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 81121250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1523473250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1523473250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56223750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1548370750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 1604594500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56223750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1548370750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1604594500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986207 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000715 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352340 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352340 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986207 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014172 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014647 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986207 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014172 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014647 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56167.582418 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58444.835681 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56847.407148 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52524.504396 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52524.504396 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56167.582418 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52610.198430 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52727.211488 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56167.582418 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52610.198430 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52727.211488 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 171 # number of writebacks
+system.cpu.l2cache.writebacks::total 171 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1000 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1422 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29002 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 29002 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1000 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 29424 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 30424 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1000 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 30424 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 56577000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24214250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80791250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526186500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526186500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56577000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1550400750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 1606977750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56577000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1550400750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 1606977750 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000212 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000713 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352544 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352544 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57379.739336 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56815.225035 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52623.491483 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52623.491483 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56577 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52691.705750 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52819.410663 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56577 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52691.705750 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52819.410663 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 2072539 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4069.510002 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 71382775 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2076635 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 34.374252 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 20654566000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4069.510002 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.993533 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.993533 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 2072519 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4069.536250 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 69938402 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2076615 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 33.679041 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 20171577250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4069.536250 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.993539 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.993539 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 584 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 3362 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 3363 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 150290167 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 150290167 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 40041040 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 40041040 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31341735 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31341735 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 71382775 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 71382775 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 71382775 # number of overall hits
-system.cpu.dcache.overall_hits::total 71382775 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2625974 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2625974 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 98017 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 98017 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2723991 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2723991 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2723991 # number of overall misses
-system.cpu.dcache.overall_misses::total 2723991 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399512249 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 31399512249 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2790424746 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2790424746 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 34189936995 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 34189936995 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 34189936995 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 34189936995 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 42667014 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 42667014 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 147464213 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 147464213 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 38592969 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 38592969 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 31345433 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 31345433 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 69938402 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 69938402 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 69938402 # number of overall hits
+system.cpu.dcache.overall_hits::total 69938402 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2661078 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2661078 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 94319 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 94319 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2755397 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2755397 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2755397 # number of overall misses
+system.cpu.dcache.overall_misses::total 2755397 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 31651251499 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 31651251499 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2775683247 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2775683247 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 34426934746 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 34426934746 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 34426934746 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 34426934746 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 41254047 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 41254047 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 74106766 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 74106766 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 74106766 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 74106766 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061546 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.061546 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003118 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003118 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.036758 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.036758 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.036758 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.036758 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11957.282231 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11957.282231 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28468.783436 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28468.783436 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12551.413347 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12551.413347 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12551.413347 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12551.413347 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32593 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 72693799 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 72693799 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 72693799 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 72693799 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064505 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.064505 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003000 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003000 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037904 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.037904 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037904 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.037904 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11894.146470 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11894.146470 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29428.675527 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29428.675527 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12494.364604 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12494.364604 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12494.364604 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12494.364604 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 86474 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9513 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 16255 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.426154 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.319840 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2066459 # number of writebacks
-system.cpu.dcache.writebacks::total 2066459 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631537 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 631537 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15816 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 15816 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 647353 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 647353 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 647353 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 647353 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994437 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1994437 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82201 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 82201 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2076638 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2076638 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2076638 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2076638 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996919001 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996919001 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502949746 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502949746 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24499868747 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 24499868747 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24499868747 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 24499868747 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046744 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046744 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028022 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.028022 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028022 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028022 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.137045 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.137045 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30449.139864 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30449.139864 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.852465 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.852465 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.852465 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.852465 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2066178 # number of writebacks
+system.cpu.dcache.writebacks::total 2066178 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666601 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 666601 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 12178 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 12178 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 678779 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 678779 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 678779 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 678779 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994477 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1994477 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82141 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 82141 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2076618 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2076618 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2076618 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2076618 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21991461751 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21991461751 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2506217997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2506217997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24497679748 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 24497679748 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24497679748 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 24497679748 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048346 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048346 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028567 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028567 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.179671 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.179671 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30511.169781 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30511.169781 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11796.911973 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11796.911973 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11796.911973 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11796.911973 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/parser
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:14:04
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:42:28
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x4cfd380
+ 0: system.cpu.isa: ISA system set to: 0 0x6824800
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 202696649500 because target called exit()
+Exiting @ tick 201639641000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.202425 # Number of seconds simulated
-sim_ticks 202425052500 # Number of ticks simulated
-final_tick 202425052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.201640 # Number of seconds simulated
+sim_ticks 201639641000 # Number of ticks simulated
+final_tick 201639641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 117924 # Simulator instruction rate (inst/s)
-host_op_rate 132952 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47246555 # Simulator tick rate (ticks/s)
-host_mem_usage 317744 # Number of bytes of host memory used
-host_seconds 4284.44 # Real time elapsed on the host
+host_inst_rate 135689 # Simulator instruction rate (inst/s)
+host_op_rate 152980 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54153116 # Simulator tick rate (ticks/s)
+host_mem_usage 265540 # Number of bytes of host memory used
+host_seconds 3723.51 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 569624283 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 216128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9265920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9482048 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 216128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 216128 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6248320 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6248320 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3377 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144780 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 148157 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97630 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97630 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1067694 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 45774571 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 46842265 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1067694 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1067694 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 30867326 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 30867326 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 30867326 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1067694 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 45774571 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 77709591 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 148159 # Number of read requests accepted
-system.physmem.writeReqs 97630 # Number of write requests accepted
-system.physmem.readBursts 148159 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 97630 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9473600 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6247040 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9482176 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6248320 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 217344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9271296 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9488640 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 217344 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 217344 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6252864 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6252864 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3396 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 144864 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 148260 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97701 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97701 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1077883 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 45979530 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 47057414 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1077883 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1077883 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 31010093 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 31010093 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 31010093 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1077883 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 45979530 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 78067507 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 148261 # Number of read requests accepted
+system.physmem.writeReqs 97701 # Number of write requests accepted
+system.physmem.readBursts 148261 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 97701 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9478784 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6251328 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9488704 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6252864 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 5 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9589 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9250 # Per bank write bursts
-system.physmem.perBankRdBursts::2 9271 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8997 # Per bank write bursts
-system.physmem.perBankRdBursts::4 9766 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9623 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9103 # Per bank write bursts
-system.physmem.perBankRdBursts::7 8296 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8815 # Per bank write bursts
-system.physmem.perBankRdBursts::9 8915 # Per bank write bursts
-system.physmem.perBankRdBursts::10 8926 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9755 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9632 # Per bank write bursts
-system.physmem.perBankRdBursts::13 9741 # Per bank write bursts
-system.physmem.perBankRdBursts::14 8922 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9424 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6257 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6164 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6102 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5898 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6263 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6268 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6040 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5542 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5815 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5905 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5986 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 8 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 9600 # Per bank write bursts
+system.physmem.perBankRdBursts::1 9245 # Per bank write bursts
+system.physmem.perBankRdBursts::2 9272 # Per bank write bursts
+system.physmem.perBankRdBursts::3 9002 # Per bank write bursts
+system.physmem.perBankRdBursts::4 9776 # Per bank write bursts
+system.physmem.perBankRdBursts::5 9633 # Per bank write bursts
+system.physmem.perBankRdBursts::6 9118 # Per bank write bursts
+system.physmem.perBankRdBursts::7 8324 # Per bank write bursts
+system.physmem.perBankRdBursts::8 8782 # Per bank write bursts
+system.physmem.perBankRdBursts::9 8907 # Per bank write bursts
+system.physmem.perBankRdBursts::10 8927 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9740 # Per bank write bursts
+system.physmem.perBankRdBursts::12 9612 # Per bank write bursts
+system.physmem.perBankRdBursts::13 9774 # Per bank write bursts
+system.physmem.perBankRdBursts::14 8952 # Per bank write bursts
+system.physmem.perBankRdBursts::15 9442 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6262 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6157 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6103 # Per bank write bursts
+system.physmem.perBankWrBursts::3 5900 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6261 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6280 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6052 # Per bank write bursts
+system.physmem.perBankWrBursts::7 5550 # Per bank write bursts
+system.physmem.perBankWrBursts::8 5797 # Per bank write bursts
+system.physmem.perBankWrBursts::9 5910 # Per bank write bursts
+system.physmem.perBankWrBursts::10 5990 # Per bank write bursts
system.physmem.perBankWrBursts::11 6523 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6368 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6315 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6035 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6129 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6359 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6344 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6057 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6132 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 202425037000 # Total gap between requests
+system.physmem.totGap 201639615000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 148159 # Read request sizes (log2)
+system.physmem.readPktSize::6 148261 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 97630 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 138435 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9034 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 97701 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 138302 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9255 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 486 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2247 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5335 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5818 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5824 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5835 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5828 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5866 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5860 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5849 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5863 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5973 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5919 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5829 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5845 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5807 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5734 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2250 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2402 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5790 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5812 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5837 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5837 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5855 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5870 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5853 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5913 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6010 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5828 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5805 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5732 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 65421 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 240.288837 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 153.819388 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 255.394880 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 26636 40.71% 40.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17331 26.49% 67.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6016 9.20% 76.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 6235 9.53% 85.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3111 4.76% 90.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1372 2.10% 92.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 907 1.39% 94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 656 1.00% 95.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 3157 4.83% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 65421 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 65483 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 240.203045 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 153.557671 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 255.515687 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 26845 41.00% 41.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17105 26.12% 67.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6057 9.25% 76.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 6227 9.51% 85.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3215 4.91% 90.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1344 2.05% 92.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 866 1.32% 94.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 634 0.97% 95.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 3190 4.87% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 65483 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.864057 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 376.771836 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5718 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 25.877861 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 376.772634 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 5719 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.055740 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.965515 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.130372 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 3465 60.55% 60.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 2071 36.19% 96.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 82 1.43% 98.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 27 0.47% 98.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 23 0.40% 99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 13 0.23% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 7 0.12% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 3 0.05% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35 3 0.05% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37 1 0.02% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43 3 0.05% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-45 1 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47 2 0.03% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-69 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.067447 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.968448 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.305335 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17 3462 60.49% 60.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19 2077 36.29% 96.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21 88 1.54% 98.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23 26 0.45% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25 19 0.33% 99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27 9 0.16% 99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29 14 0.24% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31 5 0.09% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33 2 0.03% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35 1 0.02% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37 6 0.10% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39 2 0.03% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41 3 0.05% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45 2 0.03% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47 1 0.02% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53 2 0.03% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55 2 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads
-system.physmem.totQLat 1821123750 # Total ticks spent queuing
-system.physmem.totMemAccLat 4596592500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 740125000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12302.81 # Average queueing delay per DRAM burst
+system.physmem.totQLat 1816896000 # Total ticks spent queuing
+system.physmem.totMemAccLat 4593883500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 740530000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12267.54 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31052.81 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 46.80 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 30.86 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 46.84 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 30.87 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31017.54 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 47.01 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 31.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 47.06 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 31.01 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.61 # Data bus utilization in percentage
system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 19.22 # Average write queue length when enqueuing
-system.physmem.readRowHits 115945 # Number of row buffer hits during reads
-system.physmem.writeRowHits 64262 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.33 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 65.82 # Row buffer hit rate for writes
-system.physmem.avgGap 823572.40 # Average gap between requests
-system.physmem.pageHitRate 73.36 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 121085417750 # Time in different power states
-system.physmem.memoryStateTime::REF 6759220000 # Time in different power states
+system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 19.04 # Average write queue length when enqueuing
+system.physmem.readRowHits 116026 # Number of row buffer hits during reads
+system.physmem.writeRowHits 64266 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 65.78 # Row buffer hit rate for writes
+system.physmem.avgGap 819799.87 # Average gap between requests
+system.physmem.pageHitRate 73.35 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 120286035750 # Time in different power states
+system.physmem.memoryStateTime::REF 6732960000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 74577349250 # Time in different power states
+system.physmem.memoryStateTime::ACT 74617456750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 77709591 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 46864 # Transaction distribution
-system.membus.trans_dist::ReadResp 46862 # Transaction distribution
-system.membus.trans_dist::Writeback 97630 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 5 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 5 # Transaction distribution
-system.membus.trans_dist::ReadExReq 101295 # Transaction distribution
-system.membus.trans_dist::ReadExResp 101295 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393956 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 393956 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15730368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 15730368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 15730368 # Total data (bytes)
+system.membus.throughput 78067507 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 46965 # Transaction distribution
+system.membus.trans_dist::ReadResp 46964 # Transaction distribution
+system.membus.trans_dist::Writeback 97701 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 8 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
+system.membus.trans_dist::ReadExReq 101296 # Transaction distribution
+system.membus.trans_dist::ReadExResp 101296 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394238 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 394238 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15741504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 15741504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 15741504 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1082435500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1079764000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1397409745 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1396376742 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 182802818 # Number of BP lookups
-system.cpu.branchPred.condPredicted 143112021 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7267941 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 93011295 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 87213055 # Number of BTB hits
+system.cpu.branchPred.lookups 185905498 # Number of BP lookups
+system.cpu.branchPred.condPredicted 145717903 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 7288959 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 95047377 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 88827374 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.766090 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 12678218 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 116271 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 93.455892 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 12842646 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 117058 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 404850106 # number of cpu cycles simulated
+system.cpu.numCycles 403279283 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 119389916 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 761628718 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 182802818 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 99891273 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 170150143 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 35691365 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 77449263 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 486 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 114538694 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2440341 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 394609388 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.164838 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.986971 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 120682752 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 776131290 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 185905498 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 101670020 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 172998904 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 37503258 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 68039482 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 481 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 115897812 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2525334 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 391132406 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.225985 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.009732 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 224471880 56.88% 56.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14182431 3.59% 60.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22892997 5.80% 66.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22746730 5.76% 72.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20891038 5.29% 77.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 11596009 2.94% 80.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13056866 3.31% 83.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 12000205 3.04% 86.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52771232 13.37% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 218146201 55.77% 55.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14394493 3.68% 59.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 23167694 5.92% 65.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22933314 5.86% 71.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 21066439 5.39% 76.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 11728153 3.00% 79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13552888 3.47% 83.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 12244725 3.13% 86.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 53898499 13.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 394609388 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.451532 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.881261 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 129090145 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 72932890 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 158811519 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 6229483 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 27545351 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26129524 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 76858 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 825625828 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 295316 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 27545351 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 135687065 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 10105791 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 47805401 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158260364 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15205416 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 800656323 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1334 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3053839 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8954907 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 385 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 954272169 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3518760229 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3237464445 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 391132406 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.460984 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.924550 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 127941260 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 66012107 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 164309835 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3533487 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 29335717 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26533351 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 77647 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 841607037 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 303900 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 29335717 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 132935936 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 7523486 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 48032128 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 162776327 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 10528812 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 816179204 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4868 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4457827 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 3314300 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1212194 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 4787 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 972434380 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3587695415 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3300630013 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 288019878 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2292922 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2292918 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 41836509 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 170268509 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 73501316 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 28634884 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15888043 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 755077640 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3775313 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 665327015 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1386285 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 187386746 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 479953007 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 797681 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 394609388 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.686039 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.735073 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 306182089 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2293511 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2293509 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 23291983 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 173719051 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 74905434 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 30225729 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 17207987 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 768522572 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3775769 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 668800812 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1727981 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 200793138 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 527082191 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 798137 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 391132406 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.709909 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.765965 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 139096453 35.25% 35.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 69938770 17.72% 52.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 71532009 18.13% 71.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53395901 13.53% 84.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31139583 7.89% 92.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15999118 4.05% 96.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8786717 2.23% 98.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2904396 0.74% 99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1816441 0.46% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 138616997 35.44% 35.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 67517265 17.26% 52.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 69869307 17.86% 70.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 51755005 13.23% 83.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 32440287 8.29% 92.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16135836 4.13% 96.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 9617335 2.46% 98.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3307412 0.85% 99.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1872962 0.48% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 394609388 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 391132406 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 479561 5.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6536466 68.14% 73.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2577260 26.87% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 630442 6.26% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6879641 68.30% 74.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2562211 25.44% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 447787138 67.30% 67.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 383414 0.06% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 153368040 23.05% 90.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 63788326 9.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 449864838 67.26% 67.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 383889 0.06% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 154509639 23.10% 90.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 64042341 9.58% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 665327015 # Type of FU issued
-system.cpu.iq.rate 1.643391 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9593287 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014419 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1736242767 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 947046337 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 646056325 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 668800812 # Type of FU issued
+system.cpu.iq.rate 1.658406 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 10072294 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.015060 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1740534066 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 973902079 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 649227410 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 239 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 674920189 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8551877 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 678872985 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 121 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 9444118 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 44238954 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 41472 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 810610 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16640839 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 47689496 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 34046 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 814715 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 18044957 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19493 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 7969 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19567 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 5233 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 27545351 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 5256121 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 385567 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 760412013 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1120947 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 170268509 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 73501316 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2286771 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 219704 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 12090 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 810610 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4341838 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4001214 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8343052 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 655907838 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 150084771 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9419177 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 29335717 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 3955691 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1178658 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 773883644 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1025688 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 173719051 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 74905434 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2287227 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 242970 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 870100 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 814715 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4363839 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4034750 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8398589 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 659340001 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 151050186 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9460811 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1559060 # number of nop insts executed
-system.cpu.iew.exec_refs 212583673 # number of memory reference insts executed
-system.cpu.iew.exec_branches 138498504 # Number of branches executed
-system.cpu.iew.exec_stores 62498902 # Number of stores executed
-system.cpu.iew.exec_rate 1.620125 # Inst execution rate
-system.cpu.iew.wb_sent 651026464 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 646056341 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 374698942 # num instructions producing a value
-system.cpu.iew.wb_consumers 646299992 # num instructions consuming a value
+system.cpu.iew.exec_nop 1585303 # number of nop insts executed
+system.cpu.iew.exec_refs 213740794 # number of memory reference insts executed
+system.cpu.iew.exec_branches 139088077 # Number of branches executed
+system.cpu.iew.exec_stores 62690608 # Number of stores executed
+system.cpu.iew.exec_rate 1.634946 # Inst execution rate
+system.cpu.iew.wb_sent 654323635 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 649227426 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 378014910 # num instructions producing a value
+system.cpu.iew.wb_consumers 657704988 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.595791 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.609871 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.574748 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 189472037 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 202955681 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7193780 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 367064037 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.555500 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.230573 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 7214032 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 361796689 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.578146 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.256071 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 159337830 43.41% 43.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 98602437 26.86% 70.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 33803348 9.21% 79.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18720540 5.10% 84.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 16173781 4.41% 88.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7454535 2.03% 91.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6985415 1.90% 92.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3172083 0.86% 93.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22814068 6.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 156712744 43.32% 43.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 96319147 26.62% 69.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 33326252 9.21% 79.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 17957546 4.96% 84.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 16748053 4.63% 88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7262749 2.01% 90.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6923592 1.91% 92.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3096479 0.86% 93.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 23450127 6.48% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 367064037 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 361796689 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 570968167 # Class of committed instruction
-system.cpu.commit.bw_lim_events 22814068 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 23450127 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1104683035 # The number of ROB reads
-system.cpu.rob.rob_writes 1548546574 # The number of ROB writes
-system.cpu.timesIdled 329089 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 10240718 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 1112263272 # The number of ROB reads
+system.cpu.rob.rob_writes 1577313182 # The number of ROB writes
+system.cpu.timesIdled 375340 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 12146877 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.801306 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.801306 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.247962 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.247962 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3058680468 # number of integer regfile reads
-system.cpu.int_regfile_writes 751974394 # number of integer regfile writes
+system.cpu.cpi 0.798197 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.798197 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.252823 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.252823 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3074448522 # number of integer regfile reads
+system.cpu.int_regfile_writes 755651134 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 237852228 # number of misc regfile reads
+system.cpu.misc_regfile_reads 238959520 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 734945552 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 864760 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 864758 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1110914 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 348881 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 348881 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33826 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504415 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 3538241 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079872 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147686464 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 148766336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 148766336 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2273224996 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 738060588 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 865494 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 865493 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1111057 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 86 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 86 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 348798 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 348798 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34444 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505273 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 3539717 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1099136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147717056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 148816192 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 148816192 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 6080 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 2273774999 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 26000486 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 26477230 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1824563475 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1825044731 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 15031 # number of replacements
-system.cpu.icache.tags.tagsinuse 1100.518238 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 114517542 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 16885 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 6782.205626 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 15336 # number of replacements
+system.cpu.icache.tags.tagsinuse 1096.367650 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 115876238 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 17184 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 6743.263385 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1100.518238 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.537362 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.537362 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1854 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 292 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.905273 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 229094338 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 229094338 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 114517542 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 114517542 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 114517542 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 114517542 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 114517542 # number of overall hits
-system.cpu.icache.overall_hits::total 114517542 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 21151 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 21151 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 21151 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 21151 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 21151 # number of overall misses
-system.cpu.icache.overall_misses::total 21151 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 554005735 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 554005735 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 554005735 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 554005735 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 554005735 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 554005735 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 114538693 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 114538693 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 114538693 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 114538693 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 114538693 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 114538693 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26192.886152 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 26192.886152 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 26192.886152 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 26192.886152 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 26192.886152 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 26192.886152 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 775 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1096.367650 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.535336 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.535336 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1848 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.902344 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 231812889 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 231812889 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 115876248 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 115876248 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 115876248 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 115876248 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 115876248 # number of overall hits
+system.cpu.icache.overall_hits::total 115876248 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 21562 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 21562 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 21562 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 21562 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 21562 # number of overall misses
+system.cpu.icache.overall_misses::total 21562 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 560819979 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 560819979 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 560819979 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 560819979 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 560819979 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 560819979 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 115897810 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 115897810 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 115897810 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 115897810 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 115897810 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 115897810 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26009.645627 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 26009.645627 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 26009.645627 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 26009.645627 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1208 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 51.666667 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 75.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4198 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 4198 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 4198 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 4198 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 4198 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 4198 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16953 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 16953 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 16953 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 16953 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 16953 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 16953 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401201263 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 401201263 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 401201263 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 401201263 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401201263 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 401201263 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23665.502448 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23665.502448 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23665.502448 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 23665.502448 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23665.502448 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 23665.502448 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4292 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 4292 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 4292 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 4292 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 4292 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 4292 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17270 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 17270 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 17270 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 17270 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 17270 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 17270 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 408247770 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 408247770 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 408247770 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 408247770 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 408247770 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 408247770 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23639.129705 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23639.129705 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 115416 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 27085.834103 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1781268 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 146665 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 12.145147 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 89916309500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23017.620858 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 361.438946 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 3706.774299 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.702442 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011030 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.113122 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.826594 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements 115515 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 27068.910861 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1781873 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 146764 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 12.141077 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 90165895500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 22998.912938 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 364.941054 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 3705.056868 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.701871 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011137 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.113069 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.826078 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31249 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7681 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21304 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2187 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7697 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21300 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953644 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 19091917 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 19091917 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 13492 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 804297 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 817789 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1110914 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1110914 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 59 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 59 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 247585 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 247585 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 13492 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1051882 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1065374 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 13492 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1051882 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1065374 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3382 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 43510 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 46892 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 101296 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 101296 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 144806 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 148188 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 144806 # number of overall misses
-system.cpu.l2cache.overall_misses::total 148188 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 248983750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3325064500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 3574048250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7369870249 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 7369870249 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 248983750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10694934749 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 10943918499 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 248983750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10694934749 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 10943918499 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 16874 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 847807 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 864681 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1110914 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1110914 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 348881 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 348881 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 16874 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1196688 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1213562 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 16874 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1196688 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1213562 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200427 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051321 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.054230 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.063492 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.063492 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290345 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.290345 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200427 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.121006 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.122110 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200427 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.121006 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.122110 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73620.269072 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76420.696392 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76218.720677 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72755.787484 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72755.787484 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73620.269072 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73856.986237 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73851.583792 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73620.269072 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73856.986237 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73851.583792 # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses 19098361 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 19098361 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 13774 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 804634 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 818408 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1111057 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1111057 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 79 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 79 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 247501 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 247501 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 13774 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1052135 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1065909 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 13774 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1052135 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1065909 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3401 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 43590 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 46991 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 101297 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 101297 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3401 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 144887 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 148288 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3401 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 144887 # number of overall misses
+system.cpu.l2cache.overall_misses::total 148288 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 252890250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3330417250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 3583307500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7356301749 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 7356301749 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 252890250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10686718999 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 10939609249 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 252890250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10686718999 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 10939609249 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 17175 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 848224 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 865399 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1111057 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1111057 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 86 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 348798 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 348798 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 17175 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1197022 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1214197 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 17175 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1197022 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1214197 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.198020 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051390 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.054300 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.081395 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.081395 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290417 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.290417 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.198020 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.121040 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.122128 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.198020 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.121040 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.122128 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74357.615407 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76403.240422 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 76255.187163 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72621.121544 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72621.121544 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74357.615407 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73758.991483 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73772.720982 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74357.615407 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73758.991483 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73772.720982 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 97630 # number of writebacks
-system.cpu.l2cache.writebacks::total 97630 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 97701 # number of writebacks
+system.cpu.l2cache.writebacks::total 97701 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3378 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43486 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 46864 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101296 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 101296 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3378 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 144782 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 148160 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3378 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 144782 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 148160 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 206192500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2779400500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2985593000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 40004 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 40004 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6084575751 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6084575751 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206192500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8863976251 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 9070168751 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206192500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8863976251 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 9070168751 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051292 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054198 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.063492 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290345 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290345 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.122087 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200190 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.122087 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61039.816459 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63914.834659 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.600717 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3397 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43568 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 46965 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101297 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 101297 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3397 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 144865 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 148262 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3397 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 144865 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 148262 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 209923500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2783807500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2993731000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70007 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70007 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6072932751 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6072932751 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 209923500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8856740251 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 9066663751 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 209923500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8856740251 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 9066663751 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.197787 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051364 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054270 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.081395 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.081395 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290417 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290417 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.197787 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121021 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.122107 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.197787 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121021 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.122107 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61796.732411 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63895.691792 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63743.873097 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60067.285490 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60067.285490 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61039.816459 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61222.916184 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61218.741570 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61039.816459 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61222.916184 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61218.741570 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59951.753270 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59951.753270 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61796.732411 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61137.888731 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61152.984251 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61796.732411 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61137.888731 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61152.984251 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1192591 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4057.481628 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 190175522 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1196687 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 158.918349 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 4252802250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4057.481628 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.990596 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.990596 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 1192926 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4057.383105 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 190117545 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1197022 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 158.825439 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 4253859250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4057.383105 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.990572 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.990572 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1688 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 1689 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 391451119 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 391451119 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 136209146 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 136209146 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 50988846 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 50988846 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488796 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1488796 # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses 391573870 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 391573870 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 136255144 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 136255144 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 50884737 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 50884737 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488854 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 1488854 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 187197992 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 187197992 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 187197992 # number of overall hits
-system.cpu.dcache.overall_hits::total 187197992 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1701390 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1701390 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3250460 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3250460 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 4951850 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4951850 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4951850 # number of overall misses
-system.cpu.dcache.overall_misses::total 4951850 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 29115477457 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 29115477457 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 71211038449 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 71211038449 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 100326515906 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 100326515906 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 100326515906 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 100326515906 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 137910536 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 137910536 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 187139881 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 187139881 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 187139881 # number of overall hits
+system.cpu.dcache.overall_hits::total 187139881 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1716538 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1716538 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3354569 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3354569 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 5071107 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 5071107 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 5071107 # number of overall misses
+system.cpu.dcache.overall_misses::total 5071107 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 29658271464 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 29658271464 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 73164049214 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 73164049214 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 726000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 726000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 102822320678 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 102822320678 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 102822320678 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 102822320678 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 137971682 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 137971682 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488833 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1488833 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488895 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1488895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 192149842 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 192149842 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 192149842 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 192149842 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012337 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012337 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059928 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.059928 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025771 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025771 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025771 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025771 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17112.759248 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17112.759248 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21907.987931 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21907.987931 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20260.410939 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20260.410939 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 17276 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 49920 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1691 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 664 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.216440 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 75.180723 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 192210988 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 192210988 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 192210988 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 192210988 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012441 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012441 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061848 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.061848 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.026383 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.026383 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.026383 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.026383 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17277.957997 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17277.957997 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21810.268089 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21810.268089 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17707.317073 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17707.317073 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20276.109472 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20276.109472 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 17575 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 53737 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1744 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 663 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.077408 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 81.051282 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1110914 # number of writebacks
-system.cpu.dcache.writebacks::total 1110914 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853047 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 853047 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902052 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2902052 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3755099 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3755099 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3755099 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3755099 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848343 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 848343 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348408 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348408 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1196751 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1196751 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1196751 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1196751 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12254549779 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 12254549779 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10243730741 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10243730741 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22498280520 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 22498280520 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22498280520 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 22498280520 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.writebacks::writebacks 1111057 # number of writebacks
+system.cpu.dcache.writebacks::total 1111057 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867776 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 867776 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3006223 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3006223 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3873999 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3873999 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3873999 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3873999 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848762 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 848762 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348346 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 348346 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1197108 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1197108 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1197108 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1197108 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264084776 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264084776 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10175822989 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10175822989 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22439907765 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 22439907765 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22439907765 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 22439907765 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14445.277180 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14445.277180 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29401.537109 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29401.537109 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14449.380128 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14449.380128 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29211.826715 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29211.826715 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/x86/linux/parser
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
gid=100
-input=/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
-Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 15 2014 16:30:59
-gem5 started Feb 16 2014 01:49:09
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
+gem5 compiled Jun 21 2014 11:13:07
+gem5 started Jun 21 2014 22:34:22
+gem5 executing on phenom
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *********info: Increasing stack size by one page.
-****************************************
+info: Increasing stack size by one page.
+******************************info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+**********
58924 words stored in 3784810 bytes
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
the man with whom I play tennis is here
there is a dog in the park
this is not the man we know and love
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
we like to eat at restaurants , usually on weekends
what did John say he thought you should do
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 459118646000 because target called exit()
+Exiting @ tick 456433328000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.458513 # Number of seconds simulated
-sim_ticks 458512999500 # Number of ticks simulated
-final_tick 458512999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.456433 # Number of seconds simulated
+sim_ticks 456433328000 # Number of ticks simulated
+final_tick 456433328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75448 # Simulator instruction rate (inst/s)
-host_op_rate 139512 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41836736 # Simulator tick rate (ticks/s)
-host_mem_usage 384056 # Number of bytes of host memory used
-host_seconds 10959.58 # Real time elapsed on the host
+host_inst_rate 93655 # Simulator instruction rate (inst/s)
+host_op_rate 173179 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 51697488 # Simulator tick rate (ticks/s)
+host_mem_usage 350856 # Number of bytes of host memory used
+host_seconds 8828.93 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 201856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24474368 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24676224 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 201856 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 201856 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18792384 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18792384 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3154 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 382412 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 385566 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293631 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293631 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 440241 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 53377697 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 53817938 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 440241 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 440241 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 40985499 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 40985499 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 40985499 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 440241 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 53377697 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 94803436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 385568 # Number of read requests accepted
-system.physmem.writeReqs 293631 # Number of write requests accepted
-system.physmem.readBursts 385568 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 293631 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24654400 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18790528 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24676352 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18792384 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 210304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24488448 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24698752 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 210304 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 210304 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18796480 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18796480 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3286 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 382632 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 385918 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 293695 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 293695 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 460755 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 53651753 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54112508 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 460755 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 460755 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 41181217 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 41181217 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 41181217 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 460755 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 53651753 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 95293725 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 385918 # Number of read requests accepted
+system.physmem.writeReqs 293695 # Number of write requests accepted
+system.physmem.readBursts 385918 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 293695 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24677440 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18795136 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24698752 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18796480 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 136756 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24002 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26346 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24809 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24514 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23427 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 143951 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 24030 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26462 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24796 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24548 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23428 # Per bank write bursts
system.physmem.perBankRdBursts::5 23679 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24437 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24240 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23642 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23833 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24803 # Per bank write bursts
-system.physmem.perBankRdBursts::11 23968 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23115 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22838 # Per bank write bursts
-system.physmem.perBankRdBursts::14 23649 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23923 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24455 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24282 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23646 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23871 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24701 # Per bank write bursts
+system.physmem.perBankRdBursts::11 23965 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23120 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22899 # Per bank write bursts
+system.physmem.perBankRdBursts::14 23768 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23935 # Per bank write bursts
system.physmem.perBankWrBursts::0 18533 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19811 # Per bank write bursts
-system.physmem.perBankWrBursts::2 18961 # Per bank write bursts
-system.physmem.perBankWrBursts::3 18917 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18087 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18414 # Per bank write bursts
-system.physmem.perBankWrBursts::6 18972 # Per bank write bursts
-system.physmem.perBankWrBursts::7 18944 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18562 # Per bank write bursts
-system.physmem.perBankWrBursts::9 18116 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18832 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17714 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17339 # Per bank write bursts
-system.physmem.perBankWrBursts::13 16924 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17682 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17794 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19857 # Per bank write bursts
+system.physmem.perBankWrBursts::2 18944 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18929 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18079 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18409 # Per bank write bursts
+system.physmem.perBankWrBursts::6 18979 # Per bank write bursts
+system.physmem.perBankWrBursts::7 18957 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18565 # Per bank write bursts
+system.physmem.perBankWrBursts::9 18141 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18792 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17687 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17335 # Per bank write bursts
+system.physmem.perBankWrBursts::13 16957 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17714 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17796 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 458512983000 # Total gap between requests
+system.physmem.totGap 456433277000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 385568 # Read request sizes (log2)
+system.physmem.readPktSize::6 385918 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 293631 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 380696 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4209 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 293695 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 380841 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4378 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 326 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6409 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6808 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16841 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17378 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6284 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6678 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 16870 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 17435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17536 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17527 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17556 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17556 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17549 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17549 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17561 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17619 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17583 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17431 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 17522 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17553 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17543 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 17585 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 17598 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 17605 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 17759 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17628 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17808 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17489 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17442 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 146743 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 296.052173 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.726027 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 323.657452 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54056 36.84% 36.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 40668 27.71% 64.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13398 9.13% 73.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7234 4.93% 78.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5377 3.66% 82.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3862 2.63% 84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3026 2.06% 86.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2779 1.89% 88.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16343 11.14% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 146743 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17400 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.138621 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 209.351810 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17386 99.92% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 146599 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 296.532446 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.978677 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 323.931077 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54105 36.91% 36.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 40284 27.48% 64.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13640 9.30% 73.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7345 5.01% 78.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5124 3.50% 82.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3885 2.65% 84.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3054 2.08% 86.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16360 11.16% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 146599 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17413 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.143169 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 209.002812 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17400 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17400 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17400 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.873678 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.805032 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.403017 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17211 98.91% 98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 144 0.83% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 22 0.13% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 3 0.02% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 2 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 2 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 17413 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17413 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.865216 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.791721 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.763276 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17216 98.87% 98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 134 0.77% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 42 0.24% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 4 0.02% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 2 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 2 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 2 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17400 # Writes before turning the bus around for reads
-system.physmem.totQLat 4188887000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11411855750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1926125000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10873.87 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17413 # Writes before turning the bus around for reads
+system.physmem.totQLat 4238739250 # Total ticks spent queuing
+system.physmem.totMemAccLat 11468458000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1927925000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10993.01 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29623.87 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 53.77 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 40.98 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 53.82 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 40.99 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29743.01 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 54.07 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 41.18 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 54.11 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 41.18 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.74 # Data bus utilization in percentage
system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.82 # Average write queue length when enqueuing
-system.physmem.readRowHits 316892 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215180 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes
-system.physmem.avgGap 675079.00 # Average gap between requests
-system.physmem.pageHitRate 78.38 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 318092069500 # Time in different power states
-system.physmem.memoryStateTime::REF 15310620000 # Time in different power states
+system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing
+system.physmem.readRowHits 317362 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215286 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes
+system.physmem.avgGap 671607.63 # Average gap between requests
+system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 317298172500 # Time in different power states
+system.physmem.memoryStateTime::REF 15241200000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 125106520750 # Time in different power states
+system.physmem.memoryStateTime::ACT 123890904750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 94803436 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 178732 # Transaction distribution
-system.membus.trans_dist::ReadResp 178730 # Transaction distribution
-system.membus.trans_dist::Writeback 293631 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 136756 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 136756 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206836 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206836 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1338277 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1338277 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1338277 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43468608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43468608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 43468608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 43468608 # Total data (bytes)
+system.membus.throughput 95293725 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 179074 # Transaction distribution
+system.membus.trans_dist::ReadResp 179074 # Transaction distribution
+system.membus.trans_dist::Writeback 293695 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 143951 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 143951 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206844 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206844 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1353433 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1353433 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1353433 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43495232 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43495232 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 43495232 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 43495232 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 3392871500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 3409046000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3899245261 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3919297073 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 205578466 # Number of BP lookups
-system.cpu.branchPred.condPredicted 205578466 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 9901534 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 117029392 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 114680074 # Number of BTB hits
+system.cpu.branchPred.lookups 214172576 # Number of BP lookups
+system.cpu.branchPred.condPredicted 214172576 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 10017048 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 122104582 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 119561484 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.992540 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 25067972 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1805738 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.917279 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 25755339 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1811393 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 917184655 # number of cpu cycles simulated
+system.cpu.numCycles 913134033 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 167397549 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1131555944 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 205578466 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 139748046 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 352223186 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 71069558 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 304555909 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 47998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 253720 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 161997167 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2518791 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 885395126 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.377906 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.324319 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 172957677 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1180093576 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 214172576 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 145316823 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 366593738 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 80936667 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 266990637 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 56859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 326654 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 167839999 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2941367 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 877562871 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.500418 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.366055 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 537236750 60.68% 60.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 23398648 2.64% 63.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 25254202 2.85% 66.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 27875613 3.15% 69.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 17735392 2.00% 71.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 22920767 2.59% 73.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 29423422 3.32% 77.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 26636426 3.01% 80.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 174913906 19.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 515232459 58.71% 58.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 24457756 2.79% 61.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 25984112 2.96% 64.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 28771124 3.28% 67.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 18396810 2.10% 69.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 23701764 2.70% 72.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 30460841 3.47% 76.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 27790154 3.17% 79.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 182767851 20.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 885395126 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.224141 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.233728 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 222654978 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 259567656 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 295344640 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 46911146 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 60916706 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2071122559 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 60916706 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 256101136 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 115302026 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 17668 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 306678759 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 146378831 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2034998452 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20313 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 24722090 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 106340501 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2137925960 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5150186774 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3273147321 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 41991 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 877562871 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.234547 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.292355 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 214899100 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 235918889 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 323832333 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 32275243 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 70637306 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2159083489 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 22 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 70637306 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 235683125 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 99102790 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 23033 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 334766565 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 137350052 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2116178959 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 79091 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 86333515 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 11675978 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 34385645 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2221828274 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5358350843 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3404407883 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 44462 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 523885106 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1288 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1219 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 345625652 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 495840221 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 194409464 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 195351813 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 54649414 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1975275020 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 13975 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1772033700 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 489443 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 441377933 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 734704744 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13423 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 885395126 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.001404 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.883479 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 607787420 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1530 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1409 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 224967788 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 514990281 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 202517058 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 220543258 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 63035338 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2048951027 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 18335 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1800520380 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 873481 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 514890445 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 886881463 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 17783 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 877562871 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.051728 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.961101 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 268930520 30.37% 30.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 151513258 17.11% 47.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 137639902 15.55% 63.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 131544541 14.86% 77.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 91741507 10.36% 88.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 55934371 6.32% 94.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 34425935 3.89% 98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 11907214 1.34% 99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1757878 0.20% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 278621882 31.75% 31.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 139650345 15.91% 47.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 122145227 13.92% 61.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 121221287 13.81% 75.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 101661945 11.58% 86.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 58080162 6.62% 93.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 39790509 4.53% 98.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 14008036 1.60% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2383478 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 885395126 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 877562871 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4908226 32.44% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 7617033 50.35% 82.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2603803 17.21% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 8996464 42.62% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9189518 43.53% 86.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2923144 13.85% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2622809 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1165654727 65.78% 65.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 353604 0.02% 65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3880790 0.22% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 51 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 429257765 24.22% 90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 170263954 9.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2650510 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1189351111 66.06% 66.20% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 365099 0.02% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3880777 0.22% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 71 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 432328086 24.01% 90.45% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 171944726 9.55% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1772033700 # Type of FU issued
-system.cpu.iq.rate 1.932036 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 15129062 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008538 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4445065609 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2416869316 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1744809668 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15422 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 52952 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 3677 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1784532643 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7310 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 172476568 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1800520380 # Type of FU issued
+system.cpu.iq.rate 1.971803 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 21109126 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011724 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4500567659 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2564101057 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1771520383 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 18579 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 42290 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 4796 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1818970082 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 8914 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 181603573 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 111739174 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 389536 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 327115 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 45249278 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 130889258 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 280840 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 356982 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 53356872 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 14923 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 606 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17048 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 593 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 60916706 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 67511680 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 7160873 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1975288995 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 782662 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 495841331 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 194409464 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 3475 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4447984 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 83109 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 327115 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 5905027 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4421064 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 10326091 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1752917365 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 424127416 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 19116335 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 70637306 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 60567761 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 9830463 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2048969362 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 565538 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 514991415 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 202517058 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 4133 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4684109 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2987973 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 356982 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 5998592 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4475905 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10474497 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1780058647 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 427019742 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 20461733 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 590948442 # number of memory reference insts executed
-system.cpu.iew.exec_branches 167460417 # Number of branches executed
-system.cpu.iew.exec_stores 166821026 # Number of stores executed
-system.cpu.iew.exec_rate 1.911194 # Inst execution rate
-system.cpu.iew.wb_sent 1749660983 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1744813345 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1324821434 # num instructions producing a value
-system.cpu.iew.wb_consumers 1945562364 # num instructions consuming a value
+system.cpu.iew.exec_refs 595482816 # number of memory reference insts executed
+system.cpu.iew.exec_branches 169731635 # Number of branches executed
+system.cpu.iew.exec_stores 168463074 # Number of stores executed
+system.cpu.iew.exec_rate 1.949395 # Inst execution rate
+system.cpu.iew.wb_sent 1776808975 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1771525179 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1358454852 # num instructions producing a value
+system.cpu.iew.wb_consumers 2034017500 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.902358 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.680945 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.940049 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.667868 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 446329306 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 520066569 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 9930052 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 824478420 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.854492 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.436428 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 10054119 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 806925565 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.894832 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.501115 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 332514113 40.33% 40.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 193200456 23.43% 63.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 63249703 7.67% 71.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 92516022 11.22% 82.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 24944995 3.03% 85.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 27441019 3.33% 89.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9353308 1.13% 90.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11434582 1.39% 91.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 69824222 8.47% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 332217224 41.17% 41.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 181470930 22.49% 63.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 58010021 7.19% 70.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 87470883 10.84% 81.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 24768584 3.07% 84.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 27525249 3.41% 88.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 9963607 1.23% 89.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11389679 1.41% 90.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 74109388 9.18% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 824478420 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 806925565 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
-system.cpu.commit.bw_lim_events 69824222 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 74109388 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2729972205 # The number of ROB reads
-system.cpu.rob.rob_writes 4011712950 # The number of ROB writes
-system.cpu.timesIdled 3360559 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 31789529 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2781871447 # The number of ROB reads
+system.cpu.rob.rob_writes 4168935238 # The number of ROB writes
+system.cpu.timesIdled 4004498 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 35571162 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.109215 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.109215 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.901538 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.901538 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2716307472 # number of integer regfile reads
-system.cpu.int_regfile_writes 1420359444 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3689 # number of floating regfile reads
-system.cpu.fp_regfile_writes 68 # number of floating regfile writes
-system.cpu.cc_regfile_reads 597203936 # number of cc regfile reads
-system.cpu.cc_regfile_writes 405421760 # number of cc regfile writes
-system.cpu.misc_regfile_reads 964666021 # number of misc regfile reads
+system.cpu.cpi 1.104316 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.104316 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.905537 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.905537 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2740022491 # number of integer regfile reads
+system.cpu.int_regfile_writes 1443498634 # number of integer regfile writes
+system.cpu.fp_regfile_reads 4829 # number of floating regfile reads
+system.cpu.fp_regfile_writes 113 # number of floating regfile writes
+system.cpu.cc_regfile_reads 599382503 # number of cc regfile reads
+system.cpu.cc_regfile_writes 407768692 # number of cc regfile writes
+system.cpu.misc_regfile_reads 978269285 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 699262879 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1907311 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1907308 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2330645 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 138184 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 138184 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 771752 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 771752 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 151977 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7674879 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7826856 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 438272 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311332928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 311771200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 311771200 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 8849920 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4908820525 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 703796459 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1916652 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1916650 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2331152 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 145500 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 145500 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 771513 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 771513 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160475 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7692392 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7852867 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 475520 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311441408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 311916928 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 311916928 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 9319232 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 4920349397 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 218162491 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3952575691 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 230044243 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3958184582 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 5306 # number of replacements
-system.cpu.icache.tags.tagsinuse 1035.768369 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 161848074 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 6885 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 23507.345534 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 5899 # number of replacements
+system.cpu.icache.tags.tagsinuse 1053.974853 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 167683081 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 7506 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 22339.872236 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1035.768369 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.505746 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.505746 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1579 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 1053.974853 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.514636 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.514636 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 250 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1221 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.770996 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 324139462 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 324139462 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 161850058 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 161850058 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 161850058 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 161850058 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 161850058 # number of overall hits
-system.cpu.icache.overall_hits::total 161850058 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 147109 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 147109 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 147109 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 147109 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 147109 # number of overall misses
-system.cpu.icache.overall_misses::total 147109 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 933905482 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 933905482 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 933905482 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 933905482 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 933905482 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 933905482 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 161997167 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 161997167 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 161997167 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 161997167 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 161997167 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 161997167 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000908 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000908 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000908 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000908 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000908 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000908 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.391207 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 6348.391207 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 6348.391207 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 6348.391207 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1203 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 335833041 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 335833041 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 167684909 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 167684909 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 167684909 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 167684909 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 167684909 # number of overall hits
+system.cpu.icache.overall_hits::total 167684909 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 155090 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 155090 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 155090 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 155090 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 155090 # number of overall misses
+system.cpu.icache.overall_misses::total 155090 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 984545992 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 984545992 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 984545992 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 984545992 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 984545992 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 984545992 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 167839999 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 167839999 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 167839999 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 167839999 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 167839999 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 167839999 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000924 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000924 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000924 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000924 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000924 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000924 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.223561 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 6348.223561 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 6348.223561 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 6348.223561 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 296 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 55.555556 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1980 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1980 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1980 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1980 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1980 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1980 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 145129 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 145129 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 145129 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 145129 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 145129 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 145129 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558373758 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 558373758 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558373758 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 558373758 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558373758 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 558373758 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000896 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000896 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000896 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000896 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3847.430617 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3847.430617 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3847.430617 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 3847.430617 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3847.430617 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 3847.430617 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2045 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2045 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2045 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2045 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2045 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2045 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 153045 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 153045 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 153045 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 153045 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 153045 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 153045 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 588350757 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 588350757 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 588350757 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 588350757 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 588350757 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 588350757 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000912 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000912 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000912 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3844.299108 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3844.299108 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3844.299108 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 3844.299108 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3844.299108 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 3844.299108 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 352885 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 29666.734110 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3697072 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 385254 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 9.596453 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 198759422000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21121.357308 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 222.494139 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 8322.882663 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.644573 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006790 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.253994 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.905357 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 32369 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11715 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20331 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987823 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 41235634 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 41235634 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 3694 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1586604 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1590298 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 2330645 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 2330645 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 1450 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 1450 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 564894 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 564894 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 3694 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2151498 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2155192 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 3694 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2151498 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2155192 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3155 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 175578 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 178733 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 136734 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 136734 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 206858 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 206858 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3155 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 382436 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 385591 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3155 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 382436 # number of overall misses
-system.cpu.l2cache.overall_misses::total 385591 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234254750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12845252206 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 13079506956 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6557218 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 6557218 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14818754478 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 14818754478 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 234254750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 27664006684 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 27898261434 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 234254750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 27664006684 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 27898261434 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 6849 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1762182 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1769031 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 2330645 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 2330645 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 138184 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 138184 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 771752 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 771752 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 6849 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2533934 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2540783 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 6849 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2533934 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2540783 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.460651 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099637 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.101034 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989507 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989507 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268037 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.268037 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.460651 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.150926 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.151761 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.460651 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.150926 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.151761 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74248.732171 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73159.804793 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73179.026570 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.956017 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.956017 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71637.328399 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71637.328399 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74248.732171 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72336.303810 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72351.951768 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74248.732171 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72336.303810 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72351.951768 # average overall miss latency
+system.cpu.l2cache.tags.replacements 353238 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 29693.365830 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3699378 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 385610 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 9.593574 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 198448245500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21154.679974 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 231.567464 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 8307.118393 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.645590 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007067 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.253513 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.906170 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32372 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 250 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11726 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20309 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987915 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 41312633 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 41312633 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 4144 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1587819 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1591963 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 2331152 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 2331152 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 1571 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 1571 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 564647 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 564647 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 4144 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 2152466 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2156610 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 4144 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 2152466 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2156610 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3288 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 175788 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 179076 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 143929 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 143929 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 206866 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 206866 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3288 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 382654 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 385942 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3288 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 382654 # number of overall misses
+system.cpu.l2cache.overall_misses::total 385942 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 243230500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12860278959 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 13103509459 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7140193 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 7140193 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14872236978 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 14872236978 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 243230500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 27732515937 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 27975746437 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 243230500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 27732515937 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 27975746437 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 7432 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1763607 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1771039 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 2331152 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 2331152 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 145500 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 145500 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 771513 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 771513 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 7432 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2535120 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2542552 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 7432 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2535120 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2542552 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.442411 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099675 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.101114 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989203 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989203 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268130 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.268130 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.442411 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.150941 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.151793 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.442411 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.150941 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.151793 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73975.212895 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73157.888815 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73172.895636 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.609134 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.609134 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71893.094941 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71893.094941 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73975.212895 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72474.130512 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72486.918856 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73975.212895 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72474.130512 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72486.918856 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 293631 # number of writebacks
-system.cpu.l2cache.writebacks::total 293631 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3155 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175578 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 178733 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 136734 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 136734 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206858 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 206858 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3155 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 382436 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 385591 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3155 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 382436 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 385591 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 194803750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10608113206 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10802916956 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1371755972 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1371755972 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12195917522 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12195917522 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 194803750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22804030728 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 22998834478 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 194803750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22804030728 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 22998834478 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099637 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101034 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989507 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989507 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268037 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268037 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.151761 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460651 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150926 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.151761 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61744.453249 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60418.236943 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60441.647351 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.296079 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.296079 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58957.920516 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58957.920516 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61744.453249 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59628.358021 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59645.672430 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61744.453249 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59628.358021 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59645.672430 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 293696 # number of writebacks
+system.cpu.l2cache.writebacks::total 293696 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3287 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175788 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 179075 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 143929 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 143929 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206866 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 206866 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3287 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 382654 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 385941 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3287 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 382654 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 385941 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 202076500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10620308959 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10822385459 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1446267081 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1446267081 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12245262522 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12245262522 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202076500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22865571481 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23067647981 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202076500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22865571481 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23067647981 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.442277 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099675 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101113 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989203 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989203 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268130 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268130 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.442277 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150941 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.151793 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.442277 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150941 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.151793 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61477.487070 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60415.437681 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60434.932062 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10048.475853 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10048.475853 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59194.176530 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59194.176530 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61477.487070 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59755.213538 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59769.881876 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61477.487070 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59755.213538 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59769.881876 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 2529836 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4088.247019 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 396128893 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2533932 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 156.329725 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 1791176250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247019 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 2531024 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4088.627952 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 389841381 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2535120 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 153.776303 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1681469250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4088.627952 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.998200 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.998200 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 741 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3311 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 738 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3313 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 801380064 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 801380064 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 247376910 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 247376910 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148233547 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148233547 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 395610457 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 395610457 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 395610457 # number of overall hits
-system.cpu.dcache.overall_hits::total 395610457 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2885954 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2885954 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 926655 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 926655 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3812609 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3812609 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3812609 # number of overall misses
-system.cpu.dcache.overall_misses::total 3812609 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 57615846746 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 57615846746 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 26561972442 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 26561972442 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 84177819188 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 84177819188 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 84177819188 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 84177819188 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 250262864 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 250262864 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 788808720 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 788808720 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 241135682 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 241135682 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148226318 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148226318 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 389362000 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 389362000 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 389362000 # number of overall hits
+system.cpu.dcache.overall_hits::total 389362000 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2840916 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2840916 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 933884 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 933884 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 3774800 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3774800 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3774800 # number of overall misses
+system.cpu.dcache.overall_misses::total 3774800 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 57099614849 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 57099614849 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 26803520330 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 26803520330 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 83903135179 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 83903135179 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 83903135179 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 83903135179 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 243976598 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 243976598 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 399423066 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 399423066 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 399423066 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 399423066 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011532 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.011532 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006212 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006212 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19964.229072 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19964.229072 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28664.359920 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28664.359920 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22078.796747 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22078.796747 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 6778 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 393136800 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 393136800 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 393136800 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 393136800 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011644 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.011644 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006261 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.006261 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.009602 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.009602 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.009602 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.009602 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20099.015546 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20099.015546 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28701.123833 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28701.123833 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22227.173673 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22227.173673 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 6549 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 684 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 751 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.909357 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.720373 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2330645 # number of writebacks
-system.cpu.dcache.writebacks::total 2330645 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123517 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1123517 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16974 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16974 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1140491 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1140491 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1140491 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1140491 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762437 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1762437 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909681 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 909681 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2672118 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2672118 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2672118 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2672118 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30508505001 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 30508505001 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24438286308 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 24438286308 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54946791309 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 54946791309 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54946791309 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 54946791309 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007042 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007042 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006690 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006690 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17310.408827 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17310.408827 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26864.677077 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26864.677077 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2331152 # number of writebacks
+system.cpu.dcache.writebacks::total 2331152 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1077049 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1077049 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17132 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 17132 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1094181 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1094181 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1094181 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1094181 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763867 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1763867 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 916752 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 916752 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2680619 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2680619 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2680619 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2680619 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30539375250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 30539375250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24659789417 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 24659789417 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55199164667 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 55199164667 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55199164667 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 55199164667 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007230 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007230 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006146 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006819 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006819 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17313.876415 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17313.876415 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26899.084395 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26899.084395 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:48:27
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 11:54:16
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.066667
-Exiting @ tick 77516381000 because target called exit()
+Exiting @ tick 72880000500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.077558 # Number of seconds simulated
-sim_ticks 77558022000 # Number of ticks simulated
-final_tick 77558022000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.072880 # Number of seconds simulated
+sim_ticks 72880000500 # Number of ticks simulated
+final_tick 72880000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184821 # Simulator instruction rate (inst/s)
-host_op_rate 184821 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38166348 # Simulator tick rate (ticks/s)
-host_mem_usage 274476 # Number of bytes of host memory used
-host_seconds 2032.10 # Real time elapsed on the host
+host_inst_rate 218596 # Simulator instruction rate (inst/s)
+host_op_rate 218596 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42418396 # Simulator tick rate (ticks/s)
+host_mem_usage 228344 # Number of bytes of host memory used
+host_seconds 1718.12 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory
-system.physmem.bytes_read::total 476544 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7446 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2851852 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3292503 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6144355 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2851852 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2851852 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2851852 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3292503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6144355 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7446 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory
+system.physmem.bytes_read::total 476992 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7453 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 3041932 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3502964 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6544896 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 3041932 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 3041932 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3041932 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3502964 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6544896 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7453 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 7446 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 7453 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 476544 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 476992 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 476544 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 476992 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 526 # Per bank write bursts
+system.physmem.perBankRdBursts::0 527 # Per bank write bursts
system.physmem.perBankRdBursts::1 653 # Per bank write bursts
system.physmem.perBankRdBursts::2 448 # Per bank write bursts
-system.physmem.perBankRdBursts::3 600 # Per bank write bursts
+system.physmem.perBankRdBursts::3 602 # Per bank write bursts
system.physmem.perBankRdBursts::4 447 # Per bank write bursts
system.physmem.perBankRdBursts::5 455 # Per bank write bursts
-system.physmem.perBankRdBursts::6 516 # Per bank write bursts
+system.physmem.perBankRdBursts::6 515 # Per bank write bursts
system.physmem.perBankRdBursts::7 524 # Per bank write bursts
-system.physmem.perBankRdBursts::8 439 # Per bank write bursts
+system.physmem.perBankRdBursts::8 438 # Per bank write bursts
system.physmem.perBankRdBursts::9 405 # Per bank write bursts
-system.physmem.perBankRdBursts::10 339 # Per bank write bursts
+system.physmem.perBankRdBursts::10 337 # Per bank write bursts
system.physmem.perBankRdBursts::11 306 # Per bank write bursts
system.physmem.perBankRdBursts::12 414 # Per bank write bursts
-system.physmem.perBankRdBursts::13 543 # Per bank write bursts
-system.physmem.perBankRdBursts::14 452 # Per bank write bursts
-system.physmem.perBankRdBursts::15 379 # Per bank write bursts
+system.physmem.perBankRdBursts::13 544 # Per bank write bursts
+system.physmem.perBankRdBursts::14 457 # Per bank write bursts
+system.physmem.perBankRdBursts::15 381 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 77557932500 # Total gap between requests
+system.physmem.totGap 72879898500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 7446 # Read request sizes (log2)
+system.physmem.readPktSize::6 7453 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4325 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2039 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 758 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4278 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1960 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 858 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 294 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1343 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 351.356664 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 209.733129 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 347.313012 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 424 31.57% 31.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 321 23.90% 55.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 148 11.02% 66.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 81 6.03% 72.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 60 4.47% 76.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 47 3.50% 80.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 36 2.68% 83.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 32 2.38% 85.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 194 14.45% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1343 # Bytes accessed per row activation
-system.physmem.totQLat 64732500 # Total ticks spent queuing
-system.physmem.totMemAccLat 204345000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 37230000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8693.59 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1352 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 352.520710 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 211.357899 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 348.521013 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 414 30.62% 30.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 333 24.63% 55.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 156 11.54% 66.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 86 6.36% 73.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 58 4.29% 77.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 36 2.66% 80.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 33 2.44% 82.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 35 2.59% 85.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 201 14.87% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1352 # Bytes accessed per row activation
+system.physmem.totQLat 65605500 # Total ticks spent queuing
+system.physmem.totMemAccLat 205349250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 37265000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8802.56 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27443.59 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 6.14 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27552.56 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 6.14 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 6090 # Number of row buffer hits during reads
+system.physmem.readRowHits 6099 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.79 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 10416053.25 # Average gap between requests
-system.physmem.pageHitRate 81.79 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 73756071000 # Time in different power states
-system.physmem.memoryStateTime::REF 2589600000 # Time in different power states
+system.physmem.avgGap 9778599.02 # Average gap between requests
+system.physmem.pageHitRate 81.83 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 69326847500 # Time in different power states
+system.physmem.memoryStateTime::REF 2433600000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1205652750 # Time in different power states
+system.physmem.memoryStateTime::ACT 1119126250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 6144355 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 4314 # Transaction distribution
-system.membus.trans_dist::ReadResp 4314 # Transaction distribution
-system.membus.trans_dist::ReadExReq 3132 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3132 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14892 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 14892 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 476544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 476544 # Total data (bytes)
+system.membus.throughput 6544896 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4323 # Transaction distribution
+system.membus.trans_dist::ReadResp 4323 # Transaction distribution
+system.membus.trans_dist::ReadExReq 3130 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3130 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14906 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 14906 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 476992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 476992 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 9331000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 9314500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 69621500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 69584750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 50345417 # Number of BP lookups
-system.cpu.branchPred.condPredicted 29291104 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1215969 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 26826828 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 23310375 # Number of BTB hits
+system.cpu.branchPred.lookups 50777064 # Number of BP lookups
+system.cpu.branchPred.condPredicted 29451932 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1209851 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 26262147 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 23434234 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 86.892028 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 9011574 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1048 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 89.231981 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 9219036 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1140 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 101817662 # DTB read hits
-system.cpu.dtb.read_misses 78218 # DTB read misses
+system.cpu.dtb.read_hits 102450301 # DTB read hits
+system.cpu.dtb.read_misses 84837 # DTB read misses
system.cpu.dtb.read_acv 48604 # DTB read access violations
-system.cpu.dtb.read_accesses 101895880 # DTB read accesses
-system.cpu.dtb.write_hits 78432784 # DTB write hits
-system.cpu.dtb.write_misses 1485 # DTB write misses
-system.cpu.dtb.write_acv 3 # DTB write access violations
-system.cpu.dtb.write_accesses 78434269 # DTB write accesses
-system.cpu.dtb.data_hits 180250446 # DTB hits
-system.cpu.dtb.data_misses 79703 # DTB misses
-system.cpu.dtb.data_acv 48607 # DTB access violations
-system.cpu.dtb.data_accesses 180330149 # DTB accesses
-system.cpu.itb.fetch_hits 50303452 # ITB hits
-system.cpu.itb.fetch_misses 374 # ITB misses
+system.cpu.dtb.read_accesses 102535138 # DTB read accesses
+system.cpu.dtb.write_hits 78798145 # DTB write hits
+system.cpu.dtb.write_misses 1517 # DTB write misses
+system.cpu.dtb.write_acv 2 # DTB write access violations
+system.cpu.dtb.write_accesses 78799662 # DTB write accesses
+system.cpu.dtb.data_hits 181248446 # DTB hits
+system.cpu.dtb.data_misses 86354 # DTB misses
+system.cpu.dtb.data_acv 48606 # DTB access violations
+system.cpu.dtb.data_accesses 181334800 # DTB accesses
+system.cpu.itb.fetch_hits 50876988 # ITB hits
+system.cpu.itb.fetch_misses 370 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 50303826 # ITB accesses
+system.cpu.itb.fetch_accesses 50877358 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.numCycles 155116046 # number of cpu cycles simulated
+system.cpu.numCycles 145760003 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 51199541 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 449368258 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 50345417 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 32321949 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 78906536 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6198249 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 19757533 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 10530 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 50303452 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 417357 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 154817464 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.902568 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.324801 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 51716425 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 453983948 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 50777064 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 32653270 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 79737605 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6706722 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8534058 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 10415 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 50876988 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 470753 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 145449114 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.121256 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.346528 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 75910928 49.03% 49.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4292900 2.77% 51.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6887952 4.45% 56.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 5378426 3.47% 59.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 11777021 7.61% 67.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 7819850 5.05% 72.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5605225 3.62% 76.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1835804 1.19% 77.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 35309358 22.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 65711509 45.18% 45.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4353129 2.99% 48.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 6951535 4.78% 52.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 5417508 3.72% 56.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 11887137 8.17% 64.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 7943266 5.46% 70.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5717445 3.93% 74.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1835003 1.26% 75.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 35632582 24.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 154817464 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.324566 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.896981 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 56574106 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 15095997 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 74265148 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3943304 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4938909 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 9501741 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 4271 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 445384778 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 12171 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4938909 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 59715078 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4876409 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 419715 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 75168099 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 9699254 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 440873304 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 26337 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8019570 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 287561386 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 579637001 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 414043720 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 165593280 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 145449114 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.348361 # Number of branch fetches per cycle
+system.cpu.fetch.rate 3.114599 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 53474843 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 7565433 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 78027173 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 935486 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5446179 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 9541832 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4276 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 449545046 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 12399 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 5446179 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 54745977 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 756567 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 422703 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 77638167 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6439521 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 445569466 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 326953 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1035803 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1822362 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 2964059 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 290831608 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 586091926 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 418076358 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 168015567 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 28029057 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 36796 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 273 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 27775978 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 104708247 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 80640808 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 8927201 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6403621 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 408496151 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 259 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 401987429 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 970780 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 32786458 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 15509808 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 154817464 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.596525 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.995719 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 31299279 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 36843 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 279 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 7560708 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 105663529 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 81235477 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 11146516 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 7815881 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 412301107 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 261 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 404056264 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1312815 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 35808008 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 18428665 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 145449114 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.777991 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.042688 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 28475792 18.39% 18.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 25868593 16.71% 35.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25622739 16.55% 51.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 24250418 15.66% 67.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 21294797 13.75% 81.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15492171 10.01% 91.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8526240 5.51% 96.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3969091 2.56% 99.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1317623 0.85% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 25098996 17.26% 17.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 21117633 14.52% 31.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 22669138 15.59% 47.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 22701668 15.61% 62.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 23036562 15.84% 78.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15514820 10.67% 89.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8774349 6.03% 95.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 5158675 3.55% 99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1377273 0.95% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 154817464 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 145449114 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 33961 0.29% 0.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 60734 0.51% 0.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 4893 0.04% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 5332 0.05% 0.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 1940982 16.38% 17.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 1755182 14.82% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5081532 42.89% 74.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2964138 25.02% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 102079 0.82% 0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 61666 0.50% 1.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 48308 0.39% 1.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 3198 0.03% 1.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 1785372 14.39% 16.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 1353790 10.91% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5374985 43.31% 70.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3681074 29.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 155819959 38.76% 38.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2126233 0.53% 39.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 32858833 8.17% 47.47% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 7513495 1.87% 49.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2793143 0.69% 50.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 16555819 4.12% 54.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 1584570 0.39% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 103403919 25.72% 80.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 79297877 19.73% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 156664975 38.77% 38.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2127225 0.53% 39.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 32964847 8.16% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 7504684 1.86% 49.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2799878 0.69% 50.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 16685729 4.13% 54.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 1581715 0.39% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 104147450 25.78% 80.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 79546180 19.69% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 401987429 # Type of FU issued
-system.cpu.iq.rate 2.591527 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 11846754 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.029470 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 634443309 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 260407475 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 234772020 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 337166547 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 180924376 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 161447715 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 241509351 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 172291251 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 15019191 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 404056264 # Type of FU issued
+system.cpu.iq.rate 2.772065 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 12410472 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.030715 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 628197329 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 263376555 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 235877430 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 339087600 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 184792904 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 162158669 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 243128966 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 173304189 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 17056087 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 9953760 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 111699 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 48994 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 7120079 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 10909042 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 154314 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 60406 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 7714748 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 260856 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 3918 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 360272 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4287 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4938909 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2515248 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 368703 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 433326930 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 121866 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 104708247 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 80640808 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 259 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 84 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 84 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 48994 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 963874 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 408153 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1372027 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 398387733 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 101944518 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3599696 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 5446179 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1032 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 211342 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 437229791 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 59050 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 105663529 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 81235477 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 261 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4770 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 204982 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 60406 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 953368 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 408257 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1361625 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 400360320 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 102583778 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3695944 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 24830520 # number of nop insts executed
-system.cpu.iew.exec_refs 180378816 # number of memory reference insts executed
-system.cpu.iew.exec_branches 46578472 # Number of branches executed
-system.cpu.iew.exec_stores 78434298 # Number of stores executed
-system.cpu.iew.exec_rate 2.568321 # Inst execution rate
-system.cpu.iew.wb_sent 396855480 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 396219735 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 193571599 # num instructions producing a value
-system.cpu.iew.wb_consumers 271152784 # num instructions consuming a value
+system.cpu.iew.exec_nop 24928423 # number of nop insts executed
+system.cpu.iew.exec_refs 181383470 # number of memory reference insts executed
+system.cpu.iew.exec_branches 46799473 # Number of branches executed
+system.cpu.iew.exec_stores 78799692 # Number of stores executed
+system.cpu.iew.exec_rate 2.746709 # Inst execution rate
+system.cpu.iew.wb_sent 398772945 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 398036099 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 201124096 # num instructions producing a value
+system.cpu.iew.wb_consumers 293988661 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.554344 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.713884 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.730764 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.684122 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 34693909 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 38564789 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1211780 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149878555 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.659917 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.995453 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1205629 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 140002935 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.847544 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 3.108853 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 55522565 37.05% 37.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 22544256 15.04% 52.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13057076 8.71% 60.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11473348 7.66% 68.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 8182798 5.46% 73.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 5442795 3.63% 77.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 5157024 3.44% 80.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3290724 2.20% 83.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 25207969 16.82% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 50426990 36.02% 36.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 20519996 14.66% 50.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 11173587 7.98% 58.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 9865184 7.05% 65.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 7560021 5.40% 71.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 4963241 3.55% 74.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 4885893 3.49% 78.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3033970 2.17% 80.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 27574053 19.70% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149878555 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 140002935 # Number of insts commited each cycle
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
-system.cpu.commit.bw_lim_events 25207969 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 27574053 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 558026101 # The number of ROB reads
-system.cpu.rob.rob_writes 871664409 # The number of ROB writes
-system.cpu.timesIdled 3592 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 298582 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 549655277 # The number of ROB reads
+system.cpu.rob.rob_writes 879919465 # The number of ROB writes
+system.cpu.timesIdled 3916 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 310889 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.413010 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.413010 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.421251 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.421251 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 398150942 # number of integer regfile reads
-system.cpu.int_regfile_writes 170167166 # number of integer regfile writes
-system.cpu.fp_regfile_reads 156627293 # number of floating regfile reads
-system.cpu.fp_regfile_writes 104100522 # number of floating regfile writes
+system.cpu.cpi 0.388098 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.388098 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.576666 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.576666 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 400324800 # number of integer regfile reads
+system.cpu.int_regfile_writes 170964393 # number of integer regfile writes
+system.cpu.fp_regfile_reads 157088507 # number of floating regfile reads
+system.cpu.fp_regfile_writes 104631166 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 7339228 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 5048 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 655 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 3191 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 3191 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8126 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9007 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 17133 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260032 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 569216 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 569216 # Total data (bytes)
+system.cpu.toL2Bus.throughput 7854226 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 5074 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 5074 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 670 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 3200 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 3200 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8166 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9052 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 17218 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311104 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 572416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 572416 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 5102000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 5142000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 6747750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 6782500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 6677500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 2136 # number of replacements
-system.cpu.icache.tags.tagsinuse 1830.591331 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 50297811 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 4063 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 12379.476003 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 2155 # number of replacements
+system.cpu.icache.tags.tagsinuse 1832.273556 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 50871213 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 4083 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 12459.273328 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1830.591331 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.893843 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.893843 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1340 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 100610967 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 100610967 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 50297811 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 50297811 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 50297811 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 50297811 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 50297811 # number of overall hits
-system.cpu.icache.overall_hits::total 50297811 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5641 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5641 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5641 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5641 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5641 # number of overall misses
-system.cpu.icache.overall_misses::total 5641 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 335074000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 335074000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 335074000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 335074000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 335074000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 335074000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 50303452 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 50303452 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 50303452 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 50303452 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 50303452 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 50303452 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59399.751817 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 59399.751817 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 59399.751817 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 59399.751817 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 59399.751817 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 59399.751817 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 446 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 49.555556 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1832.273556 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.894665 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.894665 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 101758059 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 101758059 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 50871213 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 50871213 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 50871213 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 50871213 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 50871213 # number of overall hits
+system.cpu.icache.overall_hits::total 50871213 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 5775 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 5775 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 5775 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 5775 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 5775 # number of overall misses
+system.cpu.icache.overall_misses::total 5775 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 343384000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 343384000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 343384000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 343384000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 343384000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 343384000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 50876988 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 50876988 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 50876988 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 50876988 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 50876988 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 50876988 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000114 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000114 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000114 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000114 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000114 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000114 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59460.432900 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 59460.432900 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 59460.432900 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 59460.432900 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 59460.432900 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 59460.432900 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 389 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 400 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 55.571429 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 400 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1578 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1578 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1578 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1578 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1578 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1578 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4063 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 4063 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 4063 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 4063 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 4063 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 4063 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249433250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 249433250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249433250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 249433250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249433250 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 249433250 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61391.397982 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61391.397982 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61391.397982 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61391.397982 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61391.397982 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61391.397982 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1692 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1692 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1692 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1692 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1692 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1692 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4083 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 4083 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 4083 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 4083 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 4083 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 4083 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250419500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 250419500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250419500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 250419500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250419500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 250419500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61332.231203 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61332.231203 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61332.231203 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61332.231203 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61332.231203 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61332.231203 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 4004.954677 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 821 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 4850 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.169278 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 4014.278169 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 853 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 4857 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.175623 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 371.321858 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2975.631846 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 658.000972 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.011332 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090809 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.020081 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.122222 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 4850 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 573 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4031 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148010 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 79193 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 79193 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 607 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 127 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 734 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 655 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 655 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 59 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 59 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 607 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 186 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 793 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 607 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 186 # number of overall hits
-system.cpu.l2cache.overall_hits::total 793 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3456 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 858 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 4314 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3456 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 3990 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 7446 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3456 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 3990 # number of overall misses
-system.cpu.l2cache.overall_misses::total 7446 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239290500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65195250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 304485750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 229768250 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 229768250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 239290500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 294963500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 534254000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 239290500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 294963500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 534254000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 4063 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 985 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 5048 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 655 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 655 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 3191 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 3191 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 4063 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 4176 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 8239 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 4063 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 4176 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 8239 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.850603 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.871066 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.854596 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981510 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.981510 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.850603 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.955460 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.903750 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.850603 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.955460 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.903750 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69239.149306 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75985.139860 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70580.841446 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73361.510217 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73361.510217 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69239.149306 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73925.689223 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71750.470051 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69239.149306 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73925.689223 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71750.470051 # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 371.130590 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.232986 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 659.914592 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091041 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.020139 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.122506 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 4857 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 572 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4039 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148224 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 79609 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 79609 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 619 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 132 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 751 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 670 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 670 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 70 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 70 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 619 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 202 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 821 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 619 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 202 # number of overall hits
+system.cpu.l2cache.overall_hits::total 821 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3464 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 859 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 4323 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3464 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 3989 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 7453 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3464 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses
+system.cpu.l2cache.overall_misses::total 7453 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240129250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65475000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 305604250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231013500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 231013500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 240129250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 296488500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 536617750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 240129250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 296488500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 536617750 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 4083 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 991 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 5074 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 670 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 670 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 3200 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 3200 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 4083 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4191 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 8274 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 4083 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4191 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 8274 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.848396 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.866801 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.851991 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.978125 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.978125 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.848396 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.951801 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.900774 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.848396 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.951801 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.900774 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69321.377021 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76222.351572 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70692.632431 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73806.230032 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73806.230032 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69321.377021 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74326.522938 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72000.234805 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69321.377021 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74326.522938 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72000.234805 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3456 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 4314 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3456 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7446 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3456 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7446 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195490000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54612750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250102750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191098750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191098750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195490000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 245711500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 441201500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195490000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 245711500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 441201500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.850603 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871066 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.854596 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981510 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981510 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.850603 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.903750 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850603 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.903750 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56565.393519 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63651.223776 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57974.675475 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61014.926564 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61014.926564 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56565.393519 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61581.829574 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59253.491808 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56565.393519 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61581.829574 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59253.491808 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3464 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 859 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4323 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3464 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7453 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3464 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7453 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196216750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54882000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 251098750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 192525500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 192525500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196216750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247407500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 443624250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196216750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247407500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 443624250 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848396 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866801 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.851991 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978125 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978125 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.848396 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951801 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.900774 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848396 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951801 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.900774 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56644.558314 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63890.570431 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58084.374277 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61509.744409 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61509.744409 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56644.558314 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62022.436701 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59522.910237 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56644.558314 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62022.436701 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59522.910237 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 774 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3296.550770 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 160033276 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4176 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 38322.144636 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 790 # number of replacements
+system.cpu.dcache.tags.tagsinuse 3294.829760 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 158529737 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 4191 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 37826.231687 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3296.550770 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.804822 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.804822 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 3294.829760 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.804402 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.804402 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 3401 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 320114012 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 320114012 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 86532394 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 86532394 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73500878 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73500878 # number of WriteReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 3117 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.830322 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 317106037 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 317106037 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 85028391 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 85028391 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 73501342 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 73501342 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 160033272 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 160033272 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 160033272 # number of overall hits
-system.cpu.dcache.overall_hits::total 160033272 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1791 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1791 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 19851 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 19851 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 21642 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 21642 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 21642 # number of overall misses
-system.cpu.dcache.overall_misses::total 21642 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 112278750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 112278750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1112532070 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1112532070 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 1224810820 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 1224810820 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 1224810820 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 1224810820 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 86534185 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 86534185 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 158529733 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 158529733 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 158529733 # number of overall hits
+system.cpu.dcache.overall_hits::total 158529733 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1799 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1799 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 19387 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 19387 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 21186 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 21186 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 21186 # number of overall misses
+system.cpu.dcache.overall_misses::total 21186 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 115077500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 115077500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1124516028 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1124516028 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 1239593528 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 1239593528 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 1239593528 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 1239593528 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 85030190 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 85030190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 160054914 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 160054914 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 160054914 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 160054914 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 158550919 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 158550919 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 158550919 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 158550919 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62690.536013 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62690.536013 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56044.132286 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 56044.132286 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56594.160429 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56594.160429 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 56594.160429 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 56594.160429 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 40644 # number of cycles access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000264 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000264 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63967.481934 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63967.481934 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58003.612111 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 58003.612111 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 58510.031530 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 58510.031530 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 58510.031530 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 58510.031530 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 44616 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 797 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.682819 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.979925 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 655 # number of writebacks
-system.cpu.dcache.writebacks::total 655 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 806 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 806 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16660 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16660 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 17466 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 17466 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 17466 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 17466 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 985 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 985 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4176 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4176 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4176 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4176 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67500250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 67500250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 233649750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 233649750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 301150000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 301150000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 301150000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 301150000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.writebacks::writebacks 670 # number of writebacks
+system.cpu.dcache.writebacks::total 670 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 808 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 808 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16187 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 16187 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 991 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 991 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3200 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 3200 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4191 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4191 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4191 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4191 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67828000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 67828000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235012500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 235012500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 302840500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 302840500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 302840500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 302840500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68528.172589 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68528.172589 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73221.482294 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73221.482294 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72114.463602 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72114.463602 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72114.463602 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72114.463602 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68443.995964 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68443.995964 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73441.406250 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73441.406250 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72259.723216 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72259.723216 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72259.723216 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72259.723216 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/eon
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
warn: Sockets disabled, not accepting gdb connections
-warn: CP14 unimplemented crn[15], opc1[7], crm[4], opc2[6]
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:23:42
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:42:59
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x4718040
+ 0: system.cpu.isa: ISA system set to: 0 0x6560400
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.060000
-Exiting @ tick 68503867000 because target called exit()
+Exiting @ tick 64766858000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.068540 # Number of seconds simulated
-sim_ticks 68540241500 # Number of ticks simulated
-final_tick 68540241500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.064767 # Number of seconds simulated
+sim_ticks 64766858000 # Number of ticks simulated
+final_tick 64766858000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 122061 # Simulator instruction rate (inst/s)
-host_op_rate 156050 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 30641006 # Simulator tick rate (ticks/s)
-host_mem_usage 321880 # Number of bytes of host memory used
-host_seconds 2236.88 # Real time elapsed on the host
+host_inst_rate 139181 # Simulator instruction rate (inst/s)
+host_op_rate 177937 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33015138 # Simulator tick rate (ticks/s)
+host_mem_usage 270440 # Number of bytes of host memory used
+host_seconds 1961.73 # Real time elapsed on the host
sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory
-system.physmem.bytes_read::total 466368 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7287 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2829287 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3975008 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6804295 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2829287 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2829287 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2829287 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3975008 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6804295 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7287 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 272960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 467648 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 4265 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 3005982 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4214501 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 7220483 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 3005982 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 3005982 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3005982 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4214501 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7220483 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7307 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 7287 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 7307 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 466368 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 467648 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 466368 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 467648 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 604 # Per bank write bursts
-system.physmem.perBankRdBursts::1 802 # Per bank write bursts
-system.physmem.perBankRdBursts::2 607 # Per bank write bursts
-system.physmem.perBankRdBursts::3 525 # Per bank write bursts
-system.physmem.perBankRdBursts::4 444 # Per bank write bursts
-system.physmem.perBankRdBursts::5 349 # Per bank write bursts
-system.physmem.perBankRdBursts::6 161 # Per bank write bursts
+system.physmem.perBankRdBursts::1 805 # Per bank write bursts
+system.physmem.perBankRdBursts::2 608 # Per bank write bursts
+system.physmem.perBankRdBursts::3 526 # Per bank write bursts
+system.physmem.perBankRdBursts::4 446 # Per bank write bursts
+system.physmem.perBankRdBursts::5 361 # Per bank write bursts
+system.physmem.perBankRdBursts::6 162 # Per bank write bursts
system.physmem.perBankRdBursts::7 221 # Per bank write bursts
-system.physmem.perBankRdBursts::8 206 # Per bank write bursts
-system.physmem.perBankRdBursts::9 292 # Per bank write bursts
-system.physmem.perBankRdBursts::10 324 # Per bank write bursts
-system.physmem.perBankRdBursts::11 416 # Per bank write bursts
-system.physmem.perBankRdBursts::12 533 # Per bank write bursts
-system.physmem.perBankRdBursts::13 685 # Per bank write bursts
-system.physmem.perBankRdBursts::14 612 # Per bank write bursts
-system.physmem.perBankRdBursts::15 506 # Per bank write bursts
+system.physmem.perBankRdBursts::8 208 # Per bank write bursts
+system.physmem.perBankRdBursts::9 290 # Per bank write bursts
+system.physmem.perBankRdBursts::10 326 # Per bank write bursts
+system.physmem.perBankRdBursts::11 415 # Per bank write bursts
+system.physmem.perBankRdBursts::12 530 # Per bank write bursts
+system.physmem.perBankRdBursts::13 688 # Per bank write bursts
+system.physmem.perBankRdBursts::14 613 # Per bank write bursts
+system.physmem.perBankRdBursts::15 504 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 68540041000 # Total gap between requests
+system.physmem.totGap 64766656000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 7287 # Read request sizes (log2)
+system.physmem.readPktSize::6 7307 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2168 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 588 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 170 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4265 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2120 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 623 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 69 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1441 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 322.087439 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 187.561369 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 340.705535 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 517 35.88% 35.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 362 25.12% 61.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 132 9.16% 70.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 71 4.93% 75.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 61 4.23% 79.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 42 2.91% 82.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 35 2.43% 84.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 26 1.80% 86.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 195 13.53% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1441 # Bytes accessed per row activation
-system.physmem.totQLat 60227500 # Total ticks spent queuing
-system.physmem.totMemAccLat 196858750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 36435000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8265.06 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1462 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 319.430917 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 186.825713 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 340.055999 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 519 35.50% 35.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 381 26.06% 61.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 138 9.44% 71.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 81 5.54% 76.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 49 3.35% 79.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 41 2.80% 82.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 27 1.85% 84.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 24 1.64% 86.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 202 13.82% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1462 # Bytes accessed per row activation
+system.physmem.totQLat 61897500 # Total ticks spent queuing
+system.physmem.totMemAccLat 198903750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 36535000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8470.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27015.06 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 6.80 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27220.99 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 7.22 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 6.80 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 7.22 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.05 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.06 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 5834 # Number of row buffer hits during reads
+system.physmem.readRowHits 5841 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 79.94 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 9405796.76 # Average gap between requests
-system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 64419207500 # Time in different power states
-system.physmem.memoryStateTime::REF 2288520000 # Time in different power states
+system.physmem.avgGap 8863645.27 # Average gap between requests
+system.physmem.pageHitRate 79.94 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 60826618500 # Time in different power states
+system.physmem.memoryStateTime::REF 2162680000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1827118750 # Time in different power states
+system.physmem.memoryStateTime::ACT 1777002750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 6804295 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 4468 # Transaction distribution
-system.membus.trans_dist::ReadResp 4468 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
+system.membus.throughput 7220483 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4488 # Transaction distribution
+system.membus.trans_dist::ReadResp 4488 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
system.membus.trans_dist::ReadExReq 2819 # Transaction distribution
system.membus.trans_dist::ReadExResp 2819 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14578 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 14578 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 466368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 466368 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14620 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 14620 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 467648 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 467648 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 8924000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 8747000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 67911998 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 67869997 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 35427097 # Number of BP lookups
-system.cpu.branchPred.condPredicted 21222481 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1662305 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 19504890 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 16830620 # Number of BTB hits
+system.cpu.branchPred.lookups 36489443 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21873029 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1677086 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 19094793 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 17269038 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 86.289233 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6785276 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 8391 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 90.438467 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7051020 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 13969 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 137080484 # number of cpu cycles simulated
+system.cpu.numCycles 129533717 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 39013094 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 318011666 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 35427097 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 23615896 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 70957700 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6891338 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 21536315 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 110 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1697 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 56 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 37608451 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 511125 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 136726497 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.983044 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.454276 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 40065447 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 327212599 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 36489443 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24320058 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 72959266 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 8220576 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 9614052 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 38688978 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 553522 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 129167933 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.246487 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.483221 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 66399200 48.56% 48.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 6788638 4.97% 53.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 5707530 4.17% 57.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6111990 4.47% 62.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4922665 3.60% 65.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4080012 2.98% 68.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3180881 2.33% 71.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4139139 3.03% 74.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 35396442 25.89% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 56843632 44.01% 44.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 6961373 5.39% 49.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5946764 4.60% 54.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 6307392 4.88% 58.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 5037669 3.90% 62.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4117601 3.19% 65.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3252291 2.52% 68.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4297115 3.33% 71.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 36404096 28.18% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 136726497 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.258440 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.319890 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45526376 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16684464 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 66829825 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2537018 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5148814 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7346336 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 69128 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 401912579 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 214046 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 5148814 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 51079671 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1913308 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 333807 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 63753347 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14497550 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 394307650 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1657315 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 10195595 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 22429 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 432708181 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2738145852 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1575813049 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 200323476 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 129167933 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.281698 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.526081 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 43040295 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8294549 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 70704377 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 671384 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6457328 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 7532389 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 70819 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 413867422 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 226829 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 6457328 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 45867800 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 237018 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 350499 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 68547941 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 7707347 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 406294876 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2372159 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1808118 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 3023073 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 35743 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 447044512 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2837901709 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1622364142 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 210216215 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 48141988 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 11963 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 11962 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 36553940 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 103619662 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 91398989 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4293575 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5309451 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 384641768 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 22898 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 374271543 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1203075 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 34859337 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 100548351 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 778 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 136726497 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.737374 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.024550 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 62478319 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 12155 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 12154 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 14556867 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 106022236 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 93881214 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5184446 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5926802 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 394612578 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 23007 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 378124394 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 2730874 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 45321613 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 166213653 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 887 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 129167933 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.927386 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.138502 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 25150398 18.39% 18.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19938048 14.58% 32.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 20598425 15.07% 48.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 18168946 13.29% 61.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 24025170 17.57% 78.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15741501 11.51% 90.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8821837 6.45% 96.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3366776 2.46% 99.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 915396 0.67% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 23289729 18.03% 18.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 17219322 13.33% 31.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 17000952 13.16% 44.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 16863081 13.06% 57.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 22471092 17.40% 74.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15547625 12.04% 87.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10749417 8.32% 95.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 4018790 3.11% 98.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2007925 1.55% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 136726497 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 129167933 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8454 0.05% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4686 0.03% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 46141 0.26% 0.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 3549 0.02% 0.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 438 0.00% 0.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 186673 1.05% 1.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 3981 0.02% 1.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 241129 1.36% 2.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9262679 52.30% 55.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 7952866 44.90% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 70479 0.37% 0.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4864 0.03% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 116556 0.60% 1.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 10208 0.05% 1.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 2498 0.01% 1.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 1.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 192000 1.00% 2.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 6622 0.03% 2.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 104426 0.54% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 10354293 53.72% 56.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 8412591 43.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 126495771 33.80% 33.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2175574 0.58% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6778108 1.81% 36.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8473024 2.26% 38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3429632 0.92% 39.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1595745 0.43% 39.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 20862309 5.57% 45.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7172511 1.92% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7129172 1.90% 49.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 101679299 27.17% 76.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 88305111 23.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 127925021 33.83% 33.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2175908 0.58% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 6 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6792348 1.80% 36.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.20% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8524841 2.25% 38.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3465145 0.92% 39.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1600581 0.42% 39.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 21035851 5.56% 45.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7175261 1.90% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134800 1.89% 49.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 103072110 27.26% 76.45% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 89047235 23.55% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 374271543 # Type of FU issued
-system.cpu.iq.rate 2.730305 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 17710599 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.047320 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 654796096 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 289211293 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 250149926 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 249387161 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 130326745 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 118060008 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 263377407 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 128604735 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 11093990 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 378124394 # Type of FU issued
+system.cpu.iq.rate 2.919119 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 19274540 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.050974 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 653351237 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 300092831 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 252502629 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 254070898 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 139884609 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 118704168 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 266903131 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 130495803 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 12681428 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 8970914 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 108859 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14127 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 9023406 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 11373488 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 85866 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 20564 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11505631 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 175522 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1863 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 299397 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 2800 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5148814 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 279698 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 35585 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 384666248 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 872586 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 103619662 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 91398989 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 11864 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 344 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14127 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1301679 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 370144 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1671823 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 370317109 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 100386827 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3954434 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 6457328 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 4758 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 17342 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 394637253 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 715920 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 106022236 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 93881214 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 11972 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 602 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 17793 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 20564 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1298443 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 381522 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1679965 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 373834206 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 101210545 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4290188 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1582 # number of nop insts executed
-system.cpu.iew.exec_refs 187618668 # number of memory reference insts executed
-system.cpu.iew.exec_branches 32015275 # Number of branches executed
-system.cpu.iew.exec_stores 87231841 # Number of stores executed
-system.cpu.iew.exec_rate 2.701458 # Inst execution rate
-system.cpu.iew.wb_sent 368883883 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 368209934 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 183051685 # num instructions producing a value
-system.cpu.iew.wb_consumers 363776414 # num instructions consuming a value
+system.cpu.iew.exec_nop 1668 # number of nop insts executed
+system.cpu.iew.exec_refs 189079864 # number of memory reference insts executed
+system.cpu.iew.exec_branches 32211788 # Number of branches executed
+system.cpu.iew.exec_stores 87869319 # Number of stores executed
+system.cpu.iew.exec_rate 2.885999 # Inst execution rate
+system.cpu.iew.wb_sent 372104883 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 371206797 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 194146455 # num instructions producing a value
+system.cpu.iew.wb_consumers 400678068 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.686086 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.503198 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.865716 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.484545 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 35601258 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 45577363 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1593594 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 131577683 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.652920 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.658674 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1607073 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 122710605 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.844620 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.797026 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 34743119 26.41% 26.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 28469178 21.64% 48.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13363377 10.16% 58.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11438386 8.69% 66.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 13773451 10.47% 77.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7412867 5.63% 82.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3865563 2.94% 85.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3891482 2.96% 88.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 14620260 11.11% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 31366686 25.56% 25.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 25118346 20.47% 46.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 12977285 10.58% 56.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 10004590 8.15% 64.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 11874018 9.68% 74.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 6164142 5.02% 79.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 4197962 3.42% 82.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3586787 2.92% 85.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 17420789 14.20% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 131577683 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 122710605 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273037337 # Number of instructions committed
system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 349065061 # Class of committed instruction
-system.cpu.commit.bw_lim_events 14620260 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 17420789 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 501621219 # The number of ROB reads
-system.cpu.rob.rob_writes 774485510 # The number of ROB writes
-system.cpu.timesIdled 6746 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 353987 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 499929717 # The number of ROB reads
+system.cpu.rob.rob_writes 795751266 # The number of ROB writes
+system.cpu.timesIdled 6646 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 365784 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273036725 # Number of Instructions Simulated
system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.502059 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.502059 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.991799 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.991799 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1770130874 # number of integer regfile reads
-system.cpu.int_regfile_writes 233038396 # number of integer regfile writes
-system.cpu.fp_regfile_reads 188133896 # number of floating regfile reads
-system.cpu.fp_regfile_writes 132498519 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1201060026 # number of misc regfile reads
+system.cpu.cpi 0.474419 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.474419 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.107843 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.107843 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1785673756 # number of integer regfile reads
+system.cpu.int_regfile_writes 235086257 # number of integer regfile writes
+system.cpu.fp_regfile_reads 188627632 # number of floating regfile reads
+system.cpu.fp_regfile_writes 133402932 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1210936846 # number of misc regfile reads
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 20063659 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 17609 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 17609 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1041 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2837 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2837 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31648 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10285 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 41933 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012608 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 362304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 1374912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 1374912 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 11785500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 21331404 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 17706 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 17706 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1042 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2839 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2839 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31825 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10310 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 42135 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1018304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 363072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 1381376 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 1381376 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 11837000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 24279239 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 24407489 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 7466709 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 7420712 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 13936 # number of replacements
-system.cpu.icache.tags.tagsinuse 1847.607729 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 37591137 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 15825 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 2375.427299 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 14019 # number of replacements
+system.cpu.icache.tags.tagsinuse 1852.281625 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 38671572 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 15912 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 2430.340121 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1847.607729 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.902152 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.902152 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1525 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 75232724 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 75232724 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 37591137 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 37591137 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 37591137 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 37591137 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 37591137 # number of overall hits
-system.cpu.icache.overall_hits::total 37591137 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 17312 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 17312 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 17312 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 17312 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 17312 # number of overall misses
-system.cpu.icache.overall_misses::total 17312 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 452091985 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 452091985 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 452091985 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 452091985 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 452091985 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 452091985 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 37608449 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 37608449 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 37608449 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 37608449 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 37608449 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 37608449 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000460 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000460 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000460 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000460 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000460 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000460 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26114.370668 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 26114.370668 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 26114.370668 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 26114.370668 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 26114.370668 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 26114.370668 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 970 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1852.281625 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.904434 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.904434 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1893 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.924316 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 77393866 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 77393866 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 38671572 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 38671572 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 38671572 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 38671572 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 38671572 # number of overall hits
+system.cpu.icache.overall_hits::total 38671572 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 17404 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 17404 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 17404 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 17404 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 17404 # number of overall misses
+system.cpu.icache.overall_misses::total 17404 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 452089736 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 452089736 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 452089736 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 452089736 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 452089736 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 452089736 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 38688976 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 38688976 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 38688976 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 38688976 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 38688976 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 38688976 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000450 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000450 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000450 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000450 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000450 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000450 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25976.197196 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 25976.197196 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 25976.197196 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 25976.197196 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1041 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 51.052632 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 47.318182 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15826 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 15826 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 15826 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 15826 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 15826 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 15826 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 356931509 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 356931509 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 356931509 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 356931509 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 356931509 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 356931509 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22553.488500 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22553.488500 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22553.488500 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22553.488500 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22553.488500 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22553.488500 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15914 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 15914 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 15914 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 15914 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359079759 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 359079759 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359079759 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 359079759 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359079759 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 359079759 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000411 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000411 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000411 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22563.765175 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22563.765175 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22563.765175 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22563.765175 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 3938.278477 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 13178 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 2.443085 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 3952.099762 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 13258 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 5413 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 2.449289 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 377.930800 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2772.496816 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 787.850861 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.011534 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084610 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.024043 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.120187 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 5394 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4004 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164612 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 180111 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 180111 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 12781 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 302 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 13083 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1041 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1041 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 12781 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 320 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 13101 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 12781 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 320 # number of overall hits
-system.cpu.l2cache.overall_hits::total 13101 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3041 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1481 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 4522 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 379.383220 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2782.580366 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 790.136176 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.011578 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084918 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.024113 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.120609 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 5413 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1243 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4021 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165192 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 180948 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 180948 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 12858 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 305 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 13163 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1042 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1042 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 20 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 20 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 12858 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 325 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 13183 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 12858 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 325 # number of overall hits
+system.cpu.l2cache.overall_hits::total 13183 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3053 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1487 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 4540 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3041 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 4300 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 7341 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3041 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 4300 # number of overall misses
-system.cpu.l2cache.overall_misses::total 7341 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 213267000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109185750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 322452750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 198902000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 198902000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 213267000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 308087750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 521354750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 213267000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 308087750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 521354750 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 15822 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1783 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 17605 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1041 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1041 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 2837 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 2837 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 15822 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 4620 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 20442 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 15822 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 4620 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 20442 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192201 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830623 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.256859 # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_misses::cpu.inst 3053 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 4306 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 7359 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3053 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 4306 # number of overall misses
+system.cpu.l2cache.overall_misses::total 7359 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 214550000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 110145250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 324695250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 200330000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 200330000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 214550000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 310475250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 525025250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 214550000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 310475250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 525025250 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 15911 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1792 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 17703 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1042 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1042 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2839 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 2839 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 15911 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4631 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 20542 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 15911 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4631 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 20542 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.191880 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.829799 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.256454 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993655 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.993655 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192201 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.930736 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.359114 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192201 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.930736 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.359114 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70130.549161 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73724.341661 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71307.551968 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70557.644555 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70557.644555 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70130.549161 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71648.313953 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71019.581801 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70130.549161 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71648.313953 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71019.581801 # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992955 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.992955 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.191880 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.929821 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.358242 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.191880 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.929821 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.358242 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70275.139207 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74072.125084 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71518.777533 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71064.207166 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71064.207166 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70275.139207 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72102.937761 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71344.646012 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70275.139207 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72102.937761 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71344.646012 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 43 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 54 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 43 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 54 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3030 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1438 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 4468 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3042 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1446 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4488 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2819 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2819 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3030 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 4257 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7287 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3030 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 4257 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7287 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 174561000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88459500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 263020500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 163883500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 163883500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 174561000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252343000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 426904000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 174561000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252343000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 426904000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191505 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.806506 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253792 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3042 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 4265 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7307 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3042 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4265 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7307 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175689250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89225250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264914500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165556500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165556500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175689250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254781750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 430471000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175689250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254781750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 430471000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.806920 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253516 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993655 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993655 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191505 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921429 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.356472 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191505 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921429 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.356472 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57610.891089 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61515.646732 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58867.614145 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992955 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992955 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.920967 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.355710 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.920967 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.355710 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57754.520053 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61704.875519 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59027.295009 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58135.331678 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58135.331678 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57610.891089 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59277.190510 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58584.328256 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57610.891089 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59277.190510 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58584.328256 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58728.804541 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58728.804541 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57754.520053 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59737.807737 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.139045 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57754.520053 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59737.807737 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.139045 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1423 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3106.690369 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 170987022 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4620 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 37010.177922 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 1426 # number of replacements
+system.cpu.dcache.tags.tagsinuse 3109.599416 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 170089338 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 4631 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 36728.425394 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3106.690369 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.758469 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.758469 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 683 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 2448 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 342028974 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 342028974 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 88933648 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 88933648 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82031473 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82031473 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 10994 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 10994 # number of LoadLockedReq hits
+system.cpu.dcache.tags.occ_blocks::cpu.data 3109.599416 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.759180 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.759180 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 3205 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 688 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.782471 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 340235219 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 340235219 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 88036573 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 88036573 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 82030829 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 82030829 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 11027 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 11027 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 170965121 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 170965121 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 170965121 # number of overall hits
-system.cpu.dcache.overall_hits::total 170965121 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 3973 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 3973 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 21192 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 21192 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 170067402 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 170067402 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 170067402 # number of overall hits
+system.cpu.dcache.overall_hits::total 170067402 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 4132 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 4132 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 21836 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 21836 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 25165 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 25165 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 25165 # number of overall misses
-system.cpu.dcache.overall_misses::total 25165 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 236002703 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 236002703 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1249306876 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1249306876 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 25968 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 25968 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 25968 # number of overall misses
+system.cpu.dcache.overall_misses::total 25968 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 240617705 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 240617705 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1280155018 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1280155018 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 1485309579 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 1485309579 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 1485309579 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 1485309579 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 88937621 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 88937621 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 1520772723 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 1520772723 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 1520772723 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 1520772723 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 88040705 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 88040705 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10996 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 10996 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11029 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 11029 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 170990286 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 170990286 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 170990286 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 170990286 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59401.636798 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59401.636798 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58951.815591 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 58951.815591 # average WriteReq miss latency
+system.cpu.dcache.demand_accesses::cpu.data 170093370 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 170093370 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 170093370 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 170093370 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000266 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000266 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000153 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000153 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000153 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000153 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58232.745644 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58232.745644 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58625.893845 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 58625.893845 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59022.832466 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59022.832466 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59022.832466 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59022.832466 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 25911 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1248 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 444 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.358108 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 96 # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 58563.336530 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 58563.336530 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 30153 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1162 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 553 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.526221 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 96.833333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks
-system.cpu.dcache.writebacks::total 1041 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2189 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2189 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18354 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18354 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 1042 # number of writebacks
+system.cpu.dcache.writebacks::total 1042 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2339 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2339 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18995 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 18995 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 20543 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 20543 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 20543 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 20543 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1784 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1784 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2838 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2838 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4622 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4622 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4622 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4622 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114103043 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 114103043 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201967248 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 201967248 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316070291 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 316070291 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316070291 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 316070291 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 21334 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 21334 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 21334 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 21334 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1793 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1793 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4634 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4634 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4634 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4634 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115097041 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 115097041 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203424247 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 203424247 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 318521288 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 318521288 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318521288 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 318521288 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63959.104821 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63959.104821 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71165.344609 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71165.344609 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68383.879489 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68383.879489 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68383.879489 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68383.879489 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64192.437814 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64192.437814 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71603.043647 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71603.043647 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:50:38
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 21:27:33
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 631518097500 because target called exit()
+Exiting @ tick 635929494500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.629061 # Number of seconds simulated
-sim_ticks 629060517500 # Number of ticks simulated
-final_tick 629060517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.635929 # Number of seconds simulated
+sim_ticks 635929494500 # Number of ticks simulated
+final_tick 635929494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 141618 # Simulator instruction rate (inst/s)
-host_op_rate 141618 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48866772 # Simulator tick rate (ticks/s)
-host_mem_usage 278492 # Number of bytes of host memory used
-host_seconds 12872.97 # Real time elapsed on the host
+host_inst_rate 162504 # Simulator instruction rate (inst/s)
+host_op_rate 162504 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56685894 # Simulator tick rate (ticks/s)
+host_mem_usage 228544 # Number of bytes of host memory used
+host_seconds 11218.48 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 177024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30295744 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30472768 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 177024 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 177024 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 176704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30295616 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 176704 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 176704 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2766 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 473371 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 476137 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2761 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 473369 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 281410 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48160301 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48441711 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 281410 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 281410 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6807154 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6807154 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6807154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 281410 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48160301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55248866 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 476137 # Number of read requests accepted
+system.physmem.bw_read::cpu.inst 277867 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 47639898 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 47917765 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 277867 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 277867 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6733627 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6733627 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6733627 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 277867 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 47639898 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54651392 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 476130 # Number of read requests accepted
system.physmem.writeReqs 66908 # Number of write requests accepted
-system.physmem.readBursts 476137 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 476130 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30454016 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 18752 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4280576 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30472768 # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM 30454144 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4280960 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 30472320 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 293 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 29448 # Per bank write bursts
-system.physmem.perBankRdBursts::1 29785 # Per bank write bursts
-system.physmem.perBankRdBursts::2 29839 # Per bank write bursts
-system.physmem.perBankRdBursts::3 29775 # Per bank write bursts
-system.physmem.perBankRdBursts::4 29682 # Per bank write bursts
-system.physmem.perBankRdBursts::5 29757 # Per bank write bursts
-system.physmem.perBankRdBursts::6 29851 # Per bank write bursts
-system.physmem.perBankRdBursts::7 29843 # Per bank write bursts
-system.physmem.perBankRdBursts::8 29760 # Per bank write bursts
-system.physmem.perBankRdBursts::9 29872 # Per bank write bursts
-system.physmem.perBankRdBursts::10 29842 # Per bank write bursts
-system.physmem.perBankRdBursts::11 29921 # Per bank write bursts
-system.physmem.perBankRdBursts::12 29772 # Per bank write bursts
-system.physmem.perBankRdBursts::13 29569 # Per bank write bursts
+system.physmem.perBankRdBursts::0 29443 # Per bank write bursts
+system.physmem.perBankRdBursts::1 29787 # Per bank write bursts
+system.physmem.perBankRdBursts::2 29841 # Per bank write bursts
+system.physmem.perBankRdBursts::3 29778 # Per bank write bursts
+system.physmem.perBankRdBursts::4 29678 # Per bank write bursts
+system.physmem.perBankRdBursts::5 29749 # Per bank write bursts
+system.physmem.perBankRdBursts::6 29855 # Per bank write bursts
+system.physmem.perBankRdBursts::7 29842 # Per bank write bursts
+system.physmem.perBankRdBursts::8 29764 # Per bank write bursts
+system.physmem.perBankRdBursts::9 29879 # Per bank write bursts
+system.physmem.perBankRdBursts::10 29841 # Per bank write bursts
+system.physmem.perBankRdBursts::11 29912 # Per bank write bursts
+system.physmem.perBankRdBursts::12 29773 # Per bank write bursts
+system.physmem.perBankRdBursts::13 29578 # Per bank write bursts
system.physmem.perBankRdBursts::14 29495 # Per bank write bursts
-system.physmem.perBankRdBursts::15 29633 # Per bank write bursts
+system.physmem.perBankRdBursts::15 29631 # Per bank write bursts
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
system.physmem.perBankWrBursts::9 4334 # Per bank write bursts
-system.physmem.perBankWrBursts::10 4224 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4230 # Per bank write bursts
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 629060434500 # Total gap between requests
+system.physmem.totGap 635929412000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 476137 # Read request sizes (log2)
+system.physmem.readPktSize::6 476130 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66908 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 408337 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66853 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 494 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 143 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 408324 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66857 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 139 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2738 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4080 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4137 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4090 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5067 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4048 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4093 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 4064 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 4062 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4053 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 4057 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2734 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4071 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4133 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5069 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4046 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 4084 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 4071 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 4061 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4059 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 4047 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 186678 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 186.061046 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 133.793811 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 215.276022 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 65820 35.26% 35.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 88170 47.23% 82.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 20719 11.10% 93.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 470 0.25% 93.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 393 0.21% 94.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 522 0.28% 94.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 523 0.28% 94.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 573 0.31% 94.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 9488 5.08% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 186678 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 115.896168 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 36.909110 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 1130.293958 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 4026 99.53% 99.53% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335 6 0.15% 99.68% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383 12 0.30% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 185909 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 186.826200 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 134.409449 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 215.527814 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 65070 35.00% 35.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 87777 47.22% 82.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 21119 11.36% 93.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 448 0.24% 93.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 430 0.23% 94.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 462 0.25% 94.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 533 0.29% 94.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 575 0.31% 94.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 9495 5.11% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 185909 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 117.004698 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 36.982691 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 1132.774880 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 4024 99.51% 99.51% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.53% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335 3 0.07% 99.60% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383 15 0.37% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.534981 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.512135 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.885131 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 2961 73.20% 73.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 5 0.12% 73.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 1078 26.65% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads
-system.physmem.totQLat 5368112500 # Total ticks spent queuing
-system.physmem.totMemAccLat 14290187500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2379220000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11281.24 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.540554 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.517518 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.888872 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 2948 72.90% 72.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 11 0.27% 73.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 1080 26.71% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads
+system.physmem.totQLat 4824243250 # Total ticks spent queuing
+system.physmem.totMemAccLat 13746355750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2379230000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10138.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30031.24 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 48.41 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 48.44 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 6.81 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28888.24 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 47.89 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 47.92 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
+system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing
-system.physmem.readRowHits 305539 # Number of row buffer hits during reads
-system.physmem.writeRowHits 50504 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.21 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.48 # Row buffer hit rate for writes
-system.physmem.avgGap 1158394.67 # Average gap between requests
-system.physmem.pageHitRate 65.60 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 166526885000 # Time in different power states
-system.physmem.memoryStateTime::REF 21005660000 # Time in different power states
+system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing
+system.physmem.readRowHits 306274 # Number of row buffer hits during reads
+system.physmem.writeRowHits 50544 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.36 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes
+system.physmem.avgGap 1171058.77 # Average gap between requests
+system.physmem.pageHitRate 65.74 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 176454220250 # Time in different power states
+system.physmem.memoryStateTime::REF 21234980000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 441526652500 # Time in different power states
+system.physmem.memoryStateTime::ACT 438237480500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 55248866 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 409283 # Transaction distribution
-system.membus.trans_dist::ReadResp 409283 # Transaction distribution
+system.membus.throughput 54651392 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 409276 # Transaction distribution
+system.membus.trans_dist::ReadResp 409276 # Transaction distribution
system.membus.trans_dist::Writeback 66908 # Transaction distribution
system.membus.trans_dist::ReadExReq 66854 # Transaction distribution
system.membus.trans_dist::ReadExResp 66854 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019182 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1019182 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 34754880 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 34754880 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019168 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1019168 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 34754432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34754432 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1216375500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1134499000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4475214250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4452935500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 388838415 # Number of BP lookups
-system.cpu.branchPred.condPredicted 256496026 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 25500542 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 313163608 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 257889708 # Number of BTB hits
+system.cpu.branchPred.lookups 402497188 # Number of BP lookups
+system.cpu.branchPred.condPredicted 262794086 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 25809520 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 329924346 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 269779526 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 82.349833 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 56962894 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 6655 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.770118 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 58338435 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6772 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 520477201 # DTB read hits
-system.cpu.dtb.read_misses 601468 # DTB read misses
+system.cpu.dtb.read_hits 522325129 # DTB read hits
+system.cpu.dtb.read_misses 599769 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 521078669 # DTB read accesses
-system.cpu.dtb.write_hits 282725842 # DTB write hits
-system.cpu.dtb.write_misses 50160 # DTB write misses
+system.cpu.dtb.read_accesses 522924898 # DTB read accesses
+system.cpu.dtb.write_hits 290323928 # DTB write hits
+system.cpu.dtb.write_misses 50170 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 282776002 # DTB write accesses
-system.cpu.dtb.data_hits 803203043 # DTB hits
-system.cpu.dtb.data_misses 651628 # DTB misses
+system.cpu.dtb.write_accesses 290374098 # DTB write accesses
+system.cpu.dtb.data_hits 812649057 # DTB hits
+system.cpu.dtb.data_misses 649939 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 803854671 # DTB accesses
-system.cpu.itb.fetch_hits 392472204 # ITB hits
-system.cpu.itb.fetch_misses 553 # ITB misses
+system.cpu.dtb.data_accesses 813298996 # DTB accesses
+system.cpu.itb.fetch_hits 408884134 # ITB hits
+system.cpu.itb.fetch_misses 679 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 392472757 # ITB accesses
+system.cpu.itb.fetch_accesses 408884813 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
-system.cpu.numCycles 1258121036 # number of cpu cycles simulated
+system.cpu.numCycles 1271858990 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 407549546 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3264335293 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 388838415 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 314852602 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 627934120 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 156719825 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 76880186 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 6672 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 392472204 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11052250 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1243100397 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.625963 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.139695 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 427176335 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3374139678 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 402497188 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 328117961 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 650903682 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 174116050 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 24391105 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 7638 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 408884134 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8158289 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1250296288 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.698672 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.147490 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 615166277 49.49% 49.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 57172656 4.60% 54.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 43000211 3.46% 57.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 71551989 5.76% 63.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 128968214 10.37% 73.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 45505183 3.66% 77.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 41223100 3.32% 80.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8333259 0.67% 81.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 232179508 18.68% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 599392606 47.94% 47.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 59914511 4.79% 52.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 43339464 3.47% 56.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 76172685 6.09% 62.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 135820925 10.86% 73.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46245373 3.70% 76.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 41570756 3.32% 80.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7626661 0.61% 80.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 240213307 19.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1243100397 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.309063 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.594611 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 435930978 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 62933874 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 604150213 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9367719 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 130717613 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 31718395 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12462 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3186570357 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 46425 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 130717613 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 465229496 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 27790939 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 27122 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 583871323 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 35463904 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3087907389 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 154 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 15123 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 29163905 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2049179896 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3572157572 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3486780085 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 85377486 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1250296288 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.652920 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 437590524 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 25041136 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 638845250 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1014076 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 147805302 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 33122555 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12366 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3318032791 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 46593 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 147805302 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 458553010 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 7909851 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 27396 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 618894367 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 17106362 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3208538957 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 6484 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 32278 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 17594215 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 887362 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2130246681 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3706452753 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3620701555 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 85751197 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 664210826 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4225 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 110011827 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 740901505 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 350460770 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 68439311 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8785014 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2617226795 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 84 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2156646647 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 17944068 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 794119367 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 722832560 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1243100397 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.734893 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.803138 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 745277611 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4240 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12056800 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 776684532 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 361655801 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 80427234 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 13113632 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2720222433 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 90 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2182396478 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 17917271 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 897142134 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 813907304 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1250296288 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.745503 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.834496 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 448302243 36.06% 36.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 195655717 15.74% 51.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 250740933 20.17% 71.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 121021830 9.74% 81.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 105318972 8.47% 90.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 78084268 6.28% 96.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 24856581 2.00% 98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 17351964 1.40% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1767889 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 456063276 36.48% 36.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 196937863 15.75% 52.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 246215948 19.69% 71.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 118632312 9.49% 81.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 96039549 7.68% 89.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 85322198 6.82% 95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 31637786 2.53% 98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 19044967 1.52% 99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 402389 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1243100397 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1250296288 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1146209 3.14% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 25356136 69.42% 72.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 10022815 27.44% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1147020 2.84% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 25333961 62.75% 65.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 13891524 34.41% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1232880422 57.17% 57.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 17089 0.00% 57.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 27851287 1.29% 58.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 8254693 0.38% 58.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 7204650 0.33% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 587626615 27.25% 86.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 292809135 13.58% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1250439249 57.30% 57.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 17094 0.00% 57.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 27851471 1.28% 58.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 592678275 27.16% 86.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 295948284 13.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2156646647 # Type of FU issued
-system.cpu.iq.rate 1.714181 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 36525160 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016936 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5459761542 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3323347360 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1987047608 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 151101377 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 88072510 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 73609915 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2115719202 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 77449853 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62169429 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2182396478 # Type of FU issued
+system.cpu.iq.rate 1.715911 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 40372505 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.018499 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5521594502 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3528574475 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2004997019 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 151784518 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 88865161 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 73949462 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2144972289 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 77793942 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 63261686 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 229831479 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 44309 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 76170 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 139665874 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 265614506 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 19945 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 77572 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 150860905 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4419 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 2971 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4433 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 3083 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 130717613 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 13757635 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 540247 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2980698105 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 730543 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 740901505 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 350460770 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 137779 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1477 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 76170 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 25493824 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 28812 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 25522636 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2062857125 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 521078821 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 93789522 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 147805302 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 7602167 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 279549 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 3087695808 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 56386 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 776684532 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 361655801 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 90 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 141634 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 84137 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 77572 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 25803318 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 28659 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 25831977 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2081430874 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 522925034 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 100965604 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 363471226 # number of nop insts executed
-system.cpu.iew.exec_refs 803855281 # number of memory reference insts executed
-system.cpu.iew.exec_branches 277329051 # Number of branches executed
-system.cpu.iew.exec_stores 282776460 # Number of stores executed
-system.cpu.iew.exec_rate 1.639633 # Inst execution rate
-system.cpu.iew.wb_sent 2062712429 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2060657523 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1180065693 # num instructions producing a value
-system.cpu.iew.wb_consumers 1751826527 # num instructions consuming a value
+system.cpu.iew.exec_nop 367473285 # number of nop insts executed
+system.cpu.iew.exec_refs 813299641 # number of memory reference insts executed
+system.cpu.iew.exec_branches 277669733 # Number of branches executed
+system.cpu.iew.exec_stores 290374607 # Number of stores executed
+system.cpu.iew.exec_rate 1.636526 # Inst execution rate
+system.cpu.iew.wb_sent 2081298559 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2078946481 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1190563677 # num instructions producing a value
+system.cpu.iew.wb_consumers 1779120207 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.637885 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.673620 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.634573 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.669187 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 954754652 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1061256381 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 25488461 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1112382784 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.806022 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.513006 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 25797472 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1102490986 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.822226 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.529076 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 494456583 44.45% 44.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 227533438 20.45% 64.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 120160218 10.80% 75.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 59129443 5.32% 81.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 49651229 4.46% 85.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 24161906 2.17% 87.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 18831378 1.69% 89.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 16326025 1.47% 90.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 102132564 9.18% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 487378417 44.21% 44.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 227745323 20.66% 64.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 117618714 10.67% 75.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 58023945 5.26% 80.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 49786654 4.52% 85.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22711490 2.06% 87.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 18023785 1.63% 89.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 18535022 1.68% 90.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 102667636 9.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1112382784 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1102490986 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 2008987604 # Class of committed instruction
-system.cpu.commit.bw_lim_events 102132564 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 102667636 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3968356066 # The number of ROB reads
-system.cpu.rob.rob_writes 6058204314 # The number of ROB writes
-system.cpu.timesIdled 347595 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 15020639 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 4064430925 # The number of ROB reads
+system.cpu.rob.rob_writes 6288295371 # The number of ROB writes
+system.cpu.timesIdled 345316 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 21562702 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.690121 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.690121 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.449021 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.449021 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2624396322 # number of integer regfile reads
-system.cpu.int_regfile_writes 1493942666 # number of integer regfile writes
-system.cpu.fp_regfile_reads 78811215 # number of floating regfile reads
-system.cpu.fp_regfile_writes 52660991 # number of floating regfile writes
+system.cpu.cpi 0.697657 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.697657 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.433369 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.433369 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2650222632 # number of integer regfile reads
+system.cpu.int_regfile_writes 1504597172 # number of integer regfile writes
+system.cpu.fp_regfile_reads 79149378 # number of floating regfile reads
+system.cpu.fp_regfile_writes 52661639 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 166637932 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1470284 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1470283 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 71642 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 71642 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20095 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159727 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 3179822 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643008 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104182336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 104825344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 104825344 # Total data (bytes)
+system.cpu.toL2Bus.throughput 164848262 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1470375 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1470374 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 95981 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 71643 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 71643 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20103 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159913 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 3180016 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104188608 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 104831872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 104831872 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 914919500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 914980500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 15573249 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 15576999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2360853250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2360120750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 8332 # number of replacements
-system.cpu.icache.tags.tagsinuse 1660.987430 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 392459292 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 10047 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 39062.336220 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 8337 # number of replacements
+system.cpu.icache.tags.tagsinuse 1659.365799 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 408871331 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 10051 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 40679.666799 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1660.987430 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.811029 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.811029 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1715 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 1659.365799 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.810237 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.810237 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1714 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1559 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.837402 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 784954455 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 784954455 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 392459292 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 392459292 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 392459292 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 392459292 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 392459292 # number of overall hits
-system.cpu.icache.overall_hits::total 392459292 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 12912 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 12912 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 12912 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 12912 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 12912 # number of overall misses
-system.cpu.icache.overall_misses::total 12912 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 385616248 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 385616248 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 385616248 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 385616248 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 385616248 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 385616248 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 392472204 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 392472204 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 392472204 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 392472204 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 392472204 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 392472204 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29864.951053 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29864.951053 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29864.951053 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29864.951053 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29864.951053 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29864.951053 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 750 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 129 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 46.875000 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.836914 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 817778319 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 817778319 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 408871331 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 408871331 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 408871331 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 408871331 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 408871331 # number of overall hits
+system.cpu.icache.overall_hits::total 408871331 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 12803 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 12803 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 12803 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 12803 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 12803 # number of overall misses
+system.cpu.icache.overall_misses::total 12803 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 381292998 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 381292998 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 381292998 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 381292998 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 381292998 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 381292998 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 408884134 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 408884134 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 408884134 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 408884134 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 408884134 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 408884134 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000031 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000031 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000031 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000031 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000031 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000031 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29781.535421 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 29781.535421 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 29781.535421 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 29781.535421 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 57.500000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2864 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2864 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2864 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2864 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2864 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2864 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10048 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 10048 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 10048 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 10048 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 10048 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 10048 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281334000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 281334000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281334000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 281334000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281334000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 281334000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000026 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27999.004777 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27999.004777 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27999.004777 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 27999.004777 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27999.004777 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 27999.004777 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2751 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2751 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2751 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2751 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2751 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2751 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10052 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 10052 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 10052 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 10052 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 10052 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 10052 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281850750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 281850750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281850750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 281850750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281850750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 281850750 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28039.270792 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28039.270792 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28039.270792 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 28039.270792 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28039.270792 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 28039.270792 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 443359 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 32688.762679 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1090020 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 476096 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 2.289496 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 443352 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 32689.433900 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1090130 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 476087 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 2.289771 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 1338.461138 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.181240 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31315.120300 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.040847 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001074 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.955662 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.997582 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 32737 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 505 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5028 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26846 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999054 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 13650914 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 13650914 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 7281 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1053719 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1061000 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 95971 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 95971 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 7281 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1058507 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1065788 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 7281 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1058507 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1065788 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 2767 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 406517 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 409284 # number of ReadReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 1333.307331 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.512650 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31320.613920 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.040689 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001084 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.955829 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.997602 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32735 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26895 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998993 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 13651722 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 13651722 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 7290 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1053808 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1061098 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 95981 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 95981 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 4789 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 4789 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 7290 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1058597 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1065887 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 7290 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1058597 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1065887 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2762 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 406515 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 409277 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 66854 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66854 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2767 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 473371 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 476138 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2767 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 473371 # number of overall misses
-system.cpu.l2cache.overall_misses::total 476138 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198468500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29469883250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 29668351750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5231809500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5231809500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 198468500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 34701692750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 34900161250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 198468500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 34701692750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 34900161250 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 10048 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1460236 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1470284 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 95971 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 95971 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 71642 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 71642 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 10048 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1531878 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1541926 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 10048 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1531878 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1541926 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.275378 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278391 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.278371 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933168 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.933168 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.275378 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.309014 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.308794 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.275378 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.309014 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.308794 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71726.960607 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72493.606048 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72488.423075 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78257.239657 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78257.239657 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71726.960607 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73307.601754 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73298.416110 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71726.960607 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73307.601754 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73298.416110 # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst 2762 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 473369 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 476131 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2762 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 473369 # number of overall misses
+system.cpu.l2cache.overall_misses::total 476131 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198889750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28901614750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 29100504500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5230880500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5230880500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 198889750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 34132495250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 34331385000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 198889750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 34132495250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 34331385000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 10052 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1460323 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1470375 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 95981 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 95981 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 71643 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 71643 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 10052 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1531966 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1542018 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 10052 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1531966 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1542018 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.274771 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278373 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.278349 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933155 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.933155 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274771 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.308994 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.308771 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274771 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.308994 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.308771 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72009.322954 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71096.059801 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71102.222944 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78243.343704 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78243.343704 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72009.322954 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72105.472158 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72104.914404 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72009.322954 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72105.472158 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72104.914404 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks
system.cpu.l2cache.writebacks::total 66908 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2767 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406517 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 409284 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2762 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406515 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 409277 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2767 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 473371 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 476138 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2767 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 473371 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 476138 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163545500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24343035750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24506581250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4426416000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4426416000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163545500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28769451750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 28932997250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163545500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28769451750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 28932997250 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.275378 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278391 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278371 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.275378 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.308794 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.275378 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.308794 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59105.710155 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59881.962501 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.714580 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66210.189368 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66210.189368 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59105.710155 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60775.695490 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60765.990637 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59105.710155 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60775.695490 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60765.990637 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2762 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 473369 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 476131 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2762 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 473369 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 476131 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164041750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23797651250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23961693000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4425694500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4425694500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164041750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28223345750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 28387387500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164041750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28223345750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 28387387500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278373 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278349 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933155 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933155 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308994 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.308771 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308994 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.308771 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59392.378711 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58540.647332 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58546.395229 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66199.397194 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66199.397194 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59392.378711 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59622.294130 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59620.960408 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59392.378711 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59622.294130 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59620.960408 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1527782 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4094.589786 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 666108987 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1531878 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 434.831616 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 407842250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4094.589786 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999656 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999656 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 1527870 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4094.609891 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 666862520 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1531966 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 435.298512 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 407274250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4094.609891 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999661 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999661 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 2366 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 2348 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 409 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1339722798 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1339722798 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 456374888 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 456374888 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 209734080 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 209734080 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 19 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 19 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 666108968 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 666108968 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 666108968 # number of overall hits
-system.cpu.dcache.overall_hits::total 666108968 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1925656 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1925656 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1060816 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1060816 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2986472 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2986472 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2986472 # number of overall misses
-system.cpu.dcache.overall_misses::total 2986472 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 77376197750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 77376197750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 46509308117 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 46509308117 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 74750 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 74750 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 123885505867 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 123885505867 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 123885505867 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 123885505867 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 458300544 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 458300544 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 1341234178 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1341234178 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 457128371 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 457128371 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 209734126 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 209734126 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data 666862497 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 666862497 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 666862497 # number of overall hits
+system.cpu.dcache.overall_hits::total 666862497 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1927816 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1927816 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1060770 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1060770 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2988586 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2988586 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2988586 # number of overall misses
+system.cpu.dcache.overall_misses::total 2988586 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 76893359750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 76893359750 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 46482150765 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 46482150765 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 123375510515 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 123375510515 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 123375510515 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 123375510515 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 459056187 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 459056187 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 669095440 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 669095440 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 669095440 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 669095440 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 23 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 23 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 669851083 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 669851083 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 669851083 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 669851083 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004200 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004200 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005032 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005032 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.050000 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.050000 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.004463 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.004463 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004463 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.004463 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40181.734302 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40181.734302 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43842.954968 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 43842.954968 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74750 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41482.225806 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41482.225806 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41482.225806 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41482.225806 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 18571 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 133 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 384 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.004462 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.004462 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.004462 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.004462 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39886.254575 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39886.254575 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43819.254659 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43819.254659 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41282.235316 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41282.235316 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41282.235316 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41282.235316 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 19699 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 140 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 433 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.361979 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 133 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.494226 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 140 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks
-system.cpu.dcache.writebacks::total 95971 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465420 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 465420 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 989174 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 989174 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1454594 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1454594 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1454594 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1454594 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460236 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1460236 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1531878 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1531878 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1531878 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1531878 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41467915750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 41467915750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5351919500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5351919500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46819835250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 46819835250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46819835250 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 46819835250 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003186 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003186 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 95981 # number of writebacks
+system.cpu.dcache.writebacks::total 95981 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467493 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 467493 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 989127 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 989127 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1456620 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1456620 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1456620 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1456620 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460323 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1460323 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71643 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 71643 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1531966 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1531966 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1531966 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1531966 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40901282750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 40901282750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5350796500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5350796500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46252079250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 46252079250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46252079250 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 46252079250 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003181 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003181 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002289 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002289 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28398.091644 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28398.091644 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74703.658468 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74703.658468 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30563.684086 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30563.684086 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30563.684086 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30563.684086 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002287 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002287 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002287 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002287 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28008.380851 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28008.380851 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74686.940804 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74686.940804 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30191.322294 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30191.322294 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30191.322294 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30191.322294 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:31:04
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:43:02
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x4c3a340
+ 0: system.cpu.isa: ISA system set to: 0 0x5c9e4b0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 629535413500 because target called exit()
+Exiting @ tick 634728078000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.628792 # Number of seconds simulated
-sim_ticks 628791732500 # Number of ticks simulated
-final_tick 628791732500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.634728 # Number of seconds simulated
+sim_ticks 634728078000 # Number of ticks simulated
+final_tick 634728078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86286 # Simulator instruction rate (inst/s)
-host_op_rate 117510 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39191918 # Simulator tick rate (ticks/s)
-host_mem_usage 321468 # Number of bytes of host memory used
-host_seconds 16043.91 # Real time elapsed on the host
+host_inst_rate 97161 # Simulator instruction rate (inst/s)
+host_op_rate 132320 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44547849 # Simulator tick rate (ticks/s)
+host_mem_usage 267228 # Number of bytes of host memory used
+host_seconds 14248.23 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30242560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30397504 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 156032 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30243456 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 156032 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 156032 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 472540 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 474961 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2438 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 472554 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 246415 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48096307 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48342722 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 246415 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 246415 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6727620 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6727620 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6727620 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 246415 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48096307 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55070342 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 474962 # Number of read requests accepted
+system.physmem.bw_read::cpu.inst 245825 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 47647894 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 47893719 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 245825 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 245825 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6664700 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6664700 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6664700 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 245825 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 47647894 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54558418 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 474992 # Number of read requests accepted
system.physmem.writeReqs 66098 # Number of write requests accepted
-system.physmem.readBursts 474962 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 474992 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30374848 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4229184 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30397568 # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM 30375808 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 23680 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4229120 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 30399488 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 370 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4292 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 29853 # Per bank write bursts
-system.physmem.perBankRdBursts::1 29663 # Per bank write bursts
-system.physmem.perBankRdBursts::2 29734 # Per bank write bursts
-system.physmem.perBankRdBursts::3 29691 # Per bank write bursts
-system.physmem.perBankRdBursts::4 29781 # Per bank write bursts
-system.physmem.perBankRdBursts::5 29812 # Per bank write bursts
-system.physmem.perBankRdBursts::6 29626 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 4530 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 29868 # Per bank write bursts
+system.physmem.perBankRdBursts::1 29664 # Per bank write bursts
+system.physmem.perBankRdBursts::2 29737 # Per bank write bursts
+system.physmem.perBankRdBursts::3 29712 # Per bank write bursts
+system.physmem.perBankRdBursts::4 29799 # Per bank write bursts
+system.physmem.perBankRdBursts::5 29810 # Per bank write bursts
+system.physmem.perBankRdBursts::6 29625 # Per bank write bursts
system.physmem.perBankRdBursts::7 29426 # Per bank write bursts
-system.physmem.perBankRdBursts::8 29463 # Per bank write bursts
-system.physmem.perBankRdBursts::9 29476 # Per bank write bursts
-system.physmem.perBankRdBursts::10 29540 # Per bank write bursts
-system.physmem.perBankRdBursts::11 29638 # Per bank write bursts
-system.physmem.perBankRdBursts::12 29686 # Per bank write bursts
-system.physmem.perBankRdBursts::13 29802 # Per bank write bursts
-system.physmem.perBankRdBursts::14 29621 # Per bank write bursts
-system.physmem.perBankRdBursts::15 29795 # Per bank write bursts
-system.physmem.perBankWrBursts::0 4173 # Per bank write bursts
+system.physmem.perBankRdBursts::8 29475 # Per bank write bursts
+system.physmem.perBankRdBursts::9 29463 # Per bank write bursts
+system.physmem.perBankRdBursts::10 29528 # Per bank write bursts
+system.physmem.perBankRdBursts::11 29636 # Per bank write bursts
+system.physmem.perBankRdBursts::12 29682 # Per bank write bursts
+system.physmem.perBankRdBursts::13 29788 # Per bank write bursts
+system.physmem.perBankRdBursts::14 29619 # Per bank write bursts
+system.physmem.perBankRdBursts::15 29790 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
system.physmem.perBankWrBursts::2 4137 # Per bank write bursts
-system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4147 # Per bank write bursts
system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
system.physmem.perBankWrBursts::6 4171 # Per bank write bursts
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
-system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
-system.physmem.perBankWrBursts::10 4094 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4090 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4093 # Per bank write bursts
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
-system.physmem.perBankWrBursts::15 4139 # Per bank write bursts
+system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 628791712500 # Total gap between requests
+system.physmem.totGap 634728009000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 474962 # Read request sizes (log2)
+system.physmem.readPktSize::6 474992 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 407661 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66594 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 407642 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66616 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3990 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4006 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3992 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4007 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 4014 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4011 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4013 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 194074 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 178.290755 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 128.832062 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 207.398992 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 73771 38.01% 38.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 88634 45.67% 83.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 20233 10.43% 94.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 463 0.24% 94.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 411 0.21% 94.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 515 0.27% 94.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 585 0.30% 95.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 564 0.29% 95.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8898 4.58% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 194074 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 192766 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 179.514147 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 129.738688 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 208.062403 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 72454 37.59% 37.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 88147 45.73% 83.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 20712 10.74% 94.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 450 0.23% 94.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 454 0.24% 94.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 512 0.27% 94.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 512 0.27% 95.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 605 0.31% 95.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8920 4.63% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 192766 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 48.655603 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 36.114528 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 505.912792 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 48.628151 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 36.096624 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 506.030557 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.491390 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.469672 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.863565 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.491141 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.469437 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.863273 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1 0.02% 75.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 975 24.33% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 2 0.05% 75.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 974 24.31% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads
-system.physmem.totQLat 5771153000 # Total ticks spent queuing
-system.physmem.totMemAccLat 14670034250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2373035000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12159.86 # Average queueing delay per DRAM burst
+system.physmem.totQLat 4985394000 # Total ticks spent queuing
+system.physmem.totMemAccLat 13884556500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2373110000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10503.93 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30909.86 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 48.31 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 48.34 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29253.93 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 47.86 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 47.89 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 6.66 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
+system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 18.42 # Average write queue length when enqueuing
-system.physmem.readRowHits 296657 # Number of row buffer hits during reads
-system.physmem.writeRowHits 49944 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 62.51 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.56 # Row buffer hit rate for writes
-system.physmem.avgGap 1162147.84 # Average gap between requests
-system.physmem.pageHitRate 64.10 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 162139876750 # Time in different power states
-system.physmem.memoryStateTime::REF 20996560000 # Time in different power states
+system.physmem.avgWrQLen 19.25 # Average write queue length when enqueuing
+system.physmem.readRowHits 298015 # Number of row buffer hits during reads
+system.physmem.writeRowHits 49917 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 62.79 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes
+system.physmem.avgGap 1173054.41 # Average gap between requests
+system.physmem.pageHitRate 64.35 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 171675355500 # Time in different power states
+system.physmem.memoryStateTime::REF 21194940000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 445650242000 # Time in different power states
+system.physmem.memoryStateTime::ACT 441857292000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 55070241 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 408884 # Transaction distribution
-system.membus.trans_dist::ReadResp 408882 # Transaction distribution
+system.membus.throughput 54558418 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 408916 # Transaction distribution
+system.membus.trans_dist::ReadResp 408916 # Transaction distribution
system.membus.trans_dist::Writeback 66098 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4292 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4292 # Transaction distribution
-system.membus.trans_dist::ReadExReq 66078 # Transaction distribution
-system.membus.trans_dist::ReadExResp 66078 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024604 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1024604 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 34627712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 34627712 # Total data (bytes)
+system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4530 # Transaction distribution
+system.membus.trans_dist::ReadExReq 66076 # Transaction distribution
+system.membus.trans_dist::ReadExResp 66076 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1025142 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1025142 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 34629760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34629760 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1214449500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1216030000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4441072458 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4441818720 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 439434227 # Number of BP lookups
-system.cpu.branchPred.condPredicted 352242826 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 30627071 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 250632586 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 230940186 # Number of BTB hits
+system.cpu.branchPred.lookups 478607550 # Number of BP lookups
+system.cpu.branchPred.condPredicted 378292816 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 30666231 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 334166811 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 254063804 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.142921 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 52229993 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2805540 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 76.029036 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 60780885 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2806336 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1257583466 # number of cpu cycles simulated
+system.cpu.numCycles 1269456157 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 355252330 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2281557009 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 439434227 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 283170179 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 601713503 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 156847289 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 133155767 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 595 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 11076 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 125 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 335955320 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11758504 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1216301526 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.576674 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.174492 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 382172768 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2398528075 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 478607550 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 314844689 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 646500630 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 176126555 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 55590458 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 12318 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 358033766 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6993732 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1229682095 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.711139 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.182068 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 614632846 50.53% 50.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42470987 3.49% 54.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 96126752 7.90% 61.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 57281313 4.71% 66.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 72527941 5.96% 72.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 45003441 3.70% 76.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31089370 2.56% 78.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 31572340 2.60% 81.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 225596536 18.55% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 583226842 47.43% 47.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 47324489 3.85% 51.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 105202734 8.56% 59.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 59348034 4.83% 64.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 82117278 6.68% 71.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 49221552 4.00% 75.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 36109976 2.94% 78.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 30221135 2.46% 80.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 236910055 19.27% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1216301526 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.349427 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.814239 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 405937331 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105620938 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 561845304 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16741500 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 126156453 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 44653834 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 11972 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3026383079 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 27573 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 126156453 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 441649817 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37679339 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 449718 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 540872152 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 69494047 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2944559238 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4802711 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 54195204 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 788 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2928884357 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14250328437 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 12163279231 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 83987601 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1229682095 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.377018 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.889414 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 407354221 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 47938688 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 625726372 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3270610 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 145392204 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 52977001 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 97525 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3244658117 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 31782 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 145392204 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 431843071 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 21602754 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 464275 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 603219561 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 27160230 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3179170609 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 6664902 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 18155043 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 78588 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 2271 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 3142601872 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 15333387016 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13133730346 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 83988681 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 935744267 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 20476 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 17997 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 177752072 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 970380112 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 488270478 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36212412 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 40741930 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2792865970 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 27850 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2433397099 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13404605 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 895018158 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2348989049 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 6466 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1216301526 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.000653 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.872636 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 1149461782 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 21762 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 19092 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 48856011 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 1039047790 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 516447707 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 54890431 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 57377876 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2969017113 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 28780 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2494321710 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 29655363 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1083496611 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2947742555 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 7396 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1229682095 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.028428 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.901891 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 380324245 31.27% 31.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 183454055 15.08% 46.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 204117167 16.78% 63.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 169768830 13.96% 77.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 132683622 10.91% 88.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 92575300 7.61% 95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 37909888 3.12% 98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12415448 1.02% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 3052971 0.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 391713450 31.85% 31.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 177167826 14.41% 46.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 194208889 15.79% 62.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 164750014 13.40% 75.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 152000166 12.36% 87.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 91333270 7.43% 95.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 42323460 3.44% 98.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 13601870 1.11% 99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2583150 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1216301526 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1229682095 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 714605 0.81% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 24383 0.03% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 55145870 62.89% 63.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 31799244 36.27% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1141867 1.24% 1.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 24392 0.03% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 58632065 63.67% 64.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 32290785 35.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1104322039 45.38% 45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11223967 0.46% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5502004 0.23% 46.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23392771 0.96% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 838298218 34.45% 81.82% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 442406331 18.18% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1135683319 45.53% 45.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11247917 0.45% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5502263 0.22% 46.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23390431 0.94% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 860090981 34.48% 81.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 450155032 18.05% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2433397099 # Type of FU issued
-system.cpu.iq.rate 1.934979 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 87684102 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.036034 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6061689588 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3605336566 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2248845458 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 122494843 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 82642602 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56425705 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2457771318 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63309883 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 84349734 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2494321710 # Type of FU issued
+system.cpu.iq.rate 1.964874 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 92089109 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.036919 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6216205899 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3969996640 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2305202146 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 123864088 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 82618605 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 56425277 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2521728263 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 64682556 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 98529432 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 338992931 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 10163 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1428185 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 211275181 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 407660609 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5276533 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 2500816 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 239452410 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 448 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 420 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 126156453 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 15953141 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1561672 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2792906296 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1415032 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 970380112 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 488270478 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 17864 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1555530 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1428185 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 32514856 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1483129 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 33997985 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2358061254 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 792590559 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 75335845 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 145392204 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 15914893 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1611898 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2969058590 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 2618613 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 1039047790 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 516447707 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 18794 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1555522 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 56228 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 2500816 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 33181152 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1519240 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 34700392 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2424200983 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 818208051 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 70120727 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12476 # number of nop insts executed
-system.cpu.iew.exec_refs 1216220468 # number of memory reference insts executed
-system.cpu.iew.exec_branches 319843836 # Number of branches executed
-system.cpu.iew.exec_stores 423629909 # Number of stores executed
-system.cpu.iew.exec_rate 1.875073 # Inst execution rate
-system.cpu.iew.wb_sent 2330961284 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2305271163 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1347649196 # num instructions producing a value
-system.cpu.iew.wb_consumers 2523801543 # num instructions consuming a value
+system.cpu.iew.exec_nop 12697 # number of nop insts executed
+system.cpu.iew.exec_refs 1248100004 # number of memory reference insts executed
+system.cpu.iew.exec_branches 329019811 # Number of branches executed
+system.cpu.iew.exec_stores 429891953 # Number of stores executed
+system.cpu.iew.exec_rate 1.909637 # Inst execution rate
+system.cpu.iew.wb_sent 2388820620 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2361627423 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1389701712 # num instructions producing a value
+system.cpu.iew.wb_consumers 2644997142 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.833096 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.533976 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.860346 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.525408 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 907570051 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1083730173 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 30615394 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1090145073 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.729436 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.397108 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 30653233 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1084289891 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.738775 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.404247 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 449857024 41.27% 41.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 288588820 26.47% 67.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 95106380 8.72% 76.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 70218402 6.44% 82.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 46473981 4.26% 87.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22183134 2.03% 89.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15845043 1.45% 90.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10980592 1.01% 91.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 90891697 8.34% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 445713482 41.11% 41.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 287271007 26.49% 67.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 94862412 8.75% 76.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 69719327 6.43% 82.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 46233776 4.26% 87.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22314720 2.06% 89.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 15854088 1.46% 90.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11019318 1.02% 91.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 91301761 8.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1090145073 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1084289891 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction
-system.cpu.commit.bw_lim_events 90891697 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 91301761 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3792141440 # The number of ROB reads
-system.cpu.rob.rob_writes 5711980108 # The number of ROB writes
-system.cpu.timesIdled 352856 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 41281940 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3962036316 # The number of ROB reads
+system.cpu.rob.rob_writes 6083536675 # The number of ROB writes
+system.cpu.timesIdled 355726 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 39774062 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.908415 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.908415 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.100818 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.100818 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11756762903 # number of integer regfile reads
-system.cpu.int_regfile_writes 2218718479 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49537143 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1677857394 # number of misc regfile reads
+system.cpu.cpi 0.916992 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.916992 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.090523 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.090523 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12060176633 # number of integer regfile reads
+system.cpu.int_regfile_writes 2272688052 # number of integer regfile writes
+system.cpu.fp_regfile_reads 68797676 # number of floating regfile reads
+system.cpu.fp_regfile_writes 49536165 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1701422665 # number of misc regfile reads
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 169149196 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1493034 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1493032 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 96318 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 4295 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 4295 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52723 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178995 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 3231718 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1549696 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104535104 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 106084800 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 106084800 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 274816 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 929401499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 167841675 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1495790 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1495789 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 96290 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 4533 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 4533 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 72512 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 72512 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57900 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179527 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 3237427 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1707776 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 106243776 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 106243776 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 290048 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 930852999 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 43182746 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 47253245 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2371256268 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2371526007 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 22529 # number of replacements
-system.cpu.icache.tags.tagsinuse 1644.627190 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 335917634 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 24213 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 13873.441292 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 24993 # number of replacements
+system.cpu.icache.tags.tagsinuse 1647.783456 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 357995053 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 26684 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 13416.094026 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1644.627190 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.803041 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.803041 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1684 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 1647.783456 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.804582 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.804582 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1691 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1552 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 671939144 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 671939144 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 335924107 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 335924107 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 335924107 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 335924107 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 335924107 # number of overall hits
-system.cpu.icache.overall_hits::total 335924107 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 31211 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 31211 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 31211 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 31211 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 31211 # number of overall misses
-system.cpu.icache.overall_misses::total 31211 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 530208992 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 530208992 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 530208992 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 530208992 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 530208992 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 530208992 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 335955318 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 335955318 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 335955318 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 335955318 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 335955318 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 335955318 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16987.888629 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16987.888629 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16987.888629 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16987.888629 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16987.888629 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16987.888629 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1881 # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.825684 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 716098748 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 716098748 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 357999320 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 357999320 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 357999320 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 357999320 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 357999320 # number of overall hits
+system.cpu.icache.overall_hits::total 357999320 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 34446 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 34446 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 34446 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 34446 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 34446 # number of overall misses
+system.cpu.icache.overall_misses::total 34446 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 570147243 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 570147243 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 570147243 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 570147243 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 570147243 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 570147243 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 358033766 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 358033766 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 358033766 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 358033766 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 358033766 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 358033766 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16551.914388 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16551.914388 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16551.914388 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16551.914388 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1683 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 58.781250 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 60.107143 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2702 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2702 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2702 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2702 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2702 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2702 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28509 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 28509 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 28509 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 28509 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 28509 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 28509 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424344751 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 424344751 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424344751 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 424344751 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424344751 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 424344751 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14884.589112 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14884.589112 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14884.589112 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14884.589112 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14884.589112 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14884.589112 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3230 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 3230 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 3230 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 3230 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 3230 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 3230 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31216 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 31216 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 31216 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 31216 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 31216 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 31216 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 454582253 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 454582253 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 454582253 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 454582253 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 454582253 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 454582253 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14562.476070 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14562.476070 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14562.476070 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14562.476070 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14562.476070 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14562.476070 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 442179 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 32677.883650 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1109649 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 474925 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 2.336472 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 442210 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 32678.682015 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1111317 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 474958 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 2.339822 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 1317.007846 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.079905 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31309.795899 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.040192 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001559 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.955499 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.997250 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5033 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26955 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 13842423 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 13842423 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 21791 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1058039 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1079830 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 96318 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 96318 # number of Writeback hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 1315.086004 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.777344 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31312.818667 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.040133 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001550 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.955591 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.997274 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32748 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4974 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27020 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999390 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 13864217 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 13864217 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 24244 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1058074 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1082318 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 96290 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 96290 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 21791 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1064480 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1086271 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 21791 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1064480 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1086271 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 2424 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 408910 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 4292 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 4292 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 66078 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 66078 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2424 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 472564 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 474988 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2424 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 472564 # number of overall misses
-system.cpu.l2cache.overall_misses::total 474988 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 173590500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30155031750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 30328622250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756999500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 4756999500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 173590500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 34912031250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 35085621750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 173590500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 34912031250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 35085621750 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 24215 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1464525 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1488740 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 96318 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 96318 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4295 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 4295 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 72519 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 24215 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1537044 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1561259 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 24215 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1537044 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1561259 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100103 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_hits::cpu.data 6436 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 6436 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 24244 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1064510 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1088754 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 24244 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1064510 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1088754 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2440 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 406500 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 408940 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 4530 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 4530 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 66076 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 66076 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2440 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 472576 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 475016 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2440 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 472576 # number of overall misses
+system.cpu.l2cache.overall_misses::total 475016 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176349750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29369544500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 29545894250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756102500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 4756102500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 176349750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 34125647000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 34301996750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 176349750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 34125647000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 34301996750 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 26684 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1464574 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1491258 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 96290 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 96290 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4533 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 4533 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 72512 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 72512 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 26684 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1537086 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1563770 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 26684 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1537086 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1563770 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.091441 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277555 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.274669 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999302 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999302 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911182 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.911182 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100103 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.307450 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.304234 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100103 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.307450 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.304234 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71613.242574 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74184.674872 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74169.431538 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71990.670117 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71990.670117 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71613.242574 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73877.890085 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73866.332939 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71613.242574 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73877.890085 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73866.332939 # average overall miss latency
+system.cpu.l2cache.ReadReq_miss_rate::total 0.274225 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999338 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999338 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911242 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.911242 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.091441 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.307449 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.303763 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.091441 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.307449 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.303763 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72274.487705 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72249.801968 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72249.949259 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71979.273866 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71979.273866 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72274.487705 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.976486 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72212.297586 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72274.487705 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.976486 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72212.297586 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2422 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406462 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 408884 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4292 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 4292 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66078 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 66078 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 472540 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 474962 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 472540 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 474962 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143052750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25094264500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25237317250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42924292 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42924292 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924413500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924413500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143052750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29018678000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 29161730750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143052750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29018678000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 29161730750 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277538 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999302 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999302 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911182 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911182 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307434 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.304217 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307434 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.304217 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59063.893476 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61738.279347 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61722.437782 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2438 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406478 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 408916 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4530 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 4530 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66076 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 66076 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2438 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 472554 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 474992 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2438 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 472554 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 474992 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145569750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24308392500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24453962250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45304530 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45304530 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3923643500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3923643500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145569750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28232036000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 28377605750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145569750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28232036000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 28377605750 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277540 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274209 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999338 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999338 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911242 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911242 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.303748 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.303748 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59708.675144 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59802.480085 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59801.920810 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.621690 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.621690 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59063.893476 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61409.992805 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61398.029211 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59063.893476 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61409.992805 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61398.029211 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59380.766088 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59380.766088 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 1532947 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4094.376885 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 969983510 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1537043 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 631.071161 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 400583250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376885 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 1532989 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4094.399228 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 981387634 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1537085 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 638.473236 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 399634250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4094.399228 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999609 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999609 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 978 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 980 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 2382 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 428 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1947074947 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1947074947 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 693859178 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 693859178 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 276090749 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 276090749 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 10001 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 10001 # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses 1969885597 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1969885597 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 705264252 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 705264252 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276089331 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276089331 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 969949927 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 969949927 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 969949927 # number of overall hits
-system.cpu.dcache.overall_hits::total 969949927 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1954107 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1954107 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 844929 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 844929 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 981353583 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 981353583 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 981353583 # number of overall hits
+system.cpu.dcache.overall_hits::total 981353583 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1954339 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1954339 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 846347 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 846347 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2799036 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2799036 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2799036 # number of overall misses
-system.cpu.dcache.overall_misses::total 2799036 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 79576585056 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 79576585056 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 58758638704 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 58758638704 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 210750 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 210750 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 138335223760 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 138335223760 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 138335223760 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 138335223760 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 695813285 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 695813285 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 2800686 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2800686 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2800686 # number of overall misses
+system.cpu.dcache.overall_misses::total 2800686 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 78948283141 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 78948283141 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 58782925343 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 58782925343 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 464000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 464000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 137731208484 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 137731208484 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 137731208484 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 137731208484 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 707218591 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 707218591 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10004 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 10004 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 972748963 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 972748963 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 972748963 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 972748963 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003051 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003051 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 984154269 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 984154269 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 984154269 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 984154269 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002763 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002763 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003056 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003056 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002877 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002877 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002877 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002877 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40722.736808 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40722.736808 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69542.693770 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69542.693770 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70250 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70250 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 49422.452502 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 49422.452502 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 49422.452502 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 49422.452502 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 2414 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 988 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 54 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.703704 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 10.739130 # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002846 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002846 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002846 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002846 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 49177.668787 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 49177.668787 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2986 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 861 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 79 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.766667 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 10.898734 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96318 # number of writebacks
-system.cpu.dcache.writebacks::total 96318 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489582 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 489582 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 768115 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 768115 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 96290 # number of writebacks
+system.cpu.dcache.writebacks::total 96290 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489763 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 489763 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769304 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 769304 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1257697 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1257697 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1257697 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1257697 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464525 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1464525 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541339 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541339 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541339 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541339 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42200288024 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 42200288024 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993959708 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993959708 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47194247732 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 47194247732 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47194247732 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 47194247732 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28815.000102 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28815.000102 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65013.665582 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65013.665582 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30618.992793 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30618.992793 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30618.992793 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30618.992793 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 1259067 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1259067 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1259067 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1259067 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464576 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1464576 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77043 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 77043 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541619 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541619 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541619 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541619 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41415183522 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 41415183522 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4998292971 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4998292971 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46413476493 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 46413476493 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46413476493 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 46413476493 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002071 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002071 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001566 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001566 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28277.934038 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28277.934038 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64876.665901 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64876.665901 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 18:24:06
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 12:22:04
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 24876941500 because target called exit()
+Exiting @ tick 24220559500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.024636 # Number of seconds simulated
-sim_ticks 24636200500 # Number of ticks simulated
-final_tick 24636200500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.024221 # Number of seconds simulated
+sim_ticks 24220559500 # Number of ticks simulated
+final_tick 24220559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166481 # Simulator instruction rate (inst/s)
-host_op_rate 166481 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51531279 # Simulator tick rate (ticks/s)
-host_mem_usage 277620 # Number of bytes of host memory used
-host_seconds 478.08 # Real time elapsed on the host
+host_inst_rate 197323 # Simulator instruction rate (inst/s)
+host_op_rate 197323 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60047490 # Simulator tick rate (ticks/s)
+host_mem_usage 230944 # Number of bytes of host memory used
+host_seconds 403.36 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 491136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10153600 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10644736 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 491136 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 491136 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7296704 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7296704 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 7674 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 158650 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 166324 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 114011 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 114011 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 19935542 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 412141474 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 432077016 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 19935542 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 19935542 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 296178138 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 296178138 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 296178138 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 19935542 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 412141474 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 728255154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 166324 # Number of read requests accepted
-system.physmem.writeReqs 114011 # Number of write requests accepted
-system.physmem.readBursts 166324 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 114011 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10644224 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7295040 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10644736 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7296704 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 490880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10153984 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10644864 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 490880 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 490880 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 7670 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 158656 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 166326 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 20267079 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 419229952 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 439497031 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 20267079 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 20267079 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 301273965 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 301273965 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 301273965 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 20267079 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 419229952 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 740770997 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 166326 # Number of read requests accepted
+system.physmem.writeReqs 114016 # Number of write requests accepted
+system.physmem.readBursts 166326 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 114016 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10644288 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7295168 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10644864 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7297024 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10435 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10464 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10314 # Per bank write bursts
+system.physmem.perBankRdBursts::0 10433 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10462 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10311 # Per bank write bursts
system.physmem.perBankRdBursts::3 10058 # Per bank write bursts
-system.physmem.perBankRdBursts::4 10432 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10406 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9849 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10311 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10614 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10643 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10549 # Per bank write bursts
+system.physmem.perBankRdBursts::4 10424 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10410 # Per bank write bursts
+system.physmem.perBankRdBursts::6 9846 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10316 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10611 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10645 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10555 # Per bank write bursts
system.physmem.perBankRdBursts::11 10230 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10275 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10619 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10489 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10628 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10281 # Per bank write bursts
+system.physmem.perBankRdBursts::13 10621 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10488 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10626 # Per bank write bursts
system.physmem.perBankWrBursts::0 7082 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7254 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7257 # Per bank write bursts
system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
system.physmem.perBankWrBursts::3 6997 # Per bank write bursts
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
system.physmem.perBankWrBursts::5 7170 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6770 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7085 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7222 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6772 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7086 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7220 # Per bank write bursts
system.physmem.perBankWrBursts::9 6941 # Per bank write bursts
system.physmem.perBankWrBursts::10 7083 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6990 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6966 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7286 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7286 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6989 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7288 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7285 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 24636167000 # Total gap between requests
+system.physmem.totGap 24220526000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 166324 # Read request sizes (log2)
+system.physmem.readPktSize::6 166326 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 114011 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 69812 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 50543 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 36166 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9786 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 114016 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 68881 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 45477 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 37755 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 14195 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 885 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2157 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5229 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6200 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6528 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6848 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7185 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7398 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 7670 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 7981 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8505 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 9167 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8234 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8402 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8401 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7660 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 322 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 63 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 846 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 893 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3043 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4983 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6450 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 7076 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 7439 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 7786 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 8078 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8708 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 9322 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 8469 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8647 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 7930 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 350 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 195 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 52591 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 341.105360 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 200.170415 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 342.733138 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 18652 35.47% 35.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 10746 20.43% 55.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5782 10.99% 66.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3058 5.81% 72.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2757 5.24% 77.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1645 3.13% 81.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1894 3.60% 84.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1108 2.11% 86.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6949 13.21% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 52591 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6971 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.856692 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 342.122530 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 6970 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 52493 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 341.720229 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 200.667520 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 342.624937 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 18531 35.30% 35.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 10783 20.54% 55.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5620 10.71% 66.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3233 6.16% 72.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2663 5.07% 77.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1771 3.37% 81.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1746 3.33% 84.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1279 2.44% 86.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6867 13.08% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 52493 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6963 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 23.883814 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 342.440327 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 6961 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6971 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6971 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.351313 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.323948 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.004197 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 6065 87.00% 87.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 30 0.43% 87.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 507 7.27% 94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 200 2.87% 97.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 92 1.32% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 44 0.63% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 23 0.33% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 4 0.06% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 3 0.04% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 3 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6971 # Writes before turning the bus around for reads
-system.physmem.totQLat 4932812500 # Total ticks spent queuing
-system.physmem.totMemAccLat 8051237500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 831580000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 29659.28 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6963 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6963 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.370386 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.340039 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.063738 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 6043 86.79% 86.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 33 0.47% 87.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 485 6.97% 94.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 209 3.00% 97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 93 1.34% 98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 61 0.88% 99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 21 0.30% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 6 0.09% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 8 0.11% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 2 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6963 # Writes before turning the bus around for reads
+system.physmem.totQLat 4923415500 # Total ticks spent queuing
+system.physmem.totMemAccLat 8041859250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 831585000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29602.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 48409.28 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 432.06 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 296.11 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 432.08 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 296.18 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 48352.60 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 439.47 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 301.20 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 439.50 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 301.27 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 5.69 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 2.31 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
-system.physmem.readRowHits 145935 # Number of row buffer hits during reads
-system.physmem.writeRowHits 81773 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.75 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.72 # Row buffer hit rate for writes
-system.physmem.avgGap 87881.17 # Average gap between requests
-system.physmem.pageHitRate 81.23 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 10235619000 # Time in different power states
-system.physmem.memoryStateTime::REF 822640000 # Time in different power states
+system.physmem.busUtil 5.79 # Data bus utilization in percentage
+system.physmem.busUtilRead 3.43 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 2.35 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
+system.physmem.readRowHits 145967 # Number of row buffer hits during reads
+system.physmem.writeRowHits 81830 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.76 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 71.77 # Row buffer hit rate for writes
+system.physmem.avgGap 86396.35 # Average gap between requests
+system.physmem.pageHitRate 81.26 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 10036891500 # Time in different power states
+system.physmem.memoryStateTime::REF 808600000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 13577715750 # Time in different power states
+system.physmem.memoryStateTime::ACT 13370021250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 728255154 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 35531 # Transaction distribution
-system.membus.trans_dist::ReadResp 35531 # Transaction distribution
-system.membus.trans_dist::Writeback 114011 # Transaction distribution
-system.membus.trans_dist::ReadExReq 130793 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130793 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446659 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 446659 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17941440 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 17941440 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 17941440 # Total data (bytes)
+system.membus.throughput 740770997 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 35544 # Transaction distribution
+system.membus.trans_dist::ReadResp 35544 # Transaction distribution
+system.membus.trans_dist::Writeback 114016 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130782 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130782 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446668 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 446668 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17941888 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 17941888 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 17941888 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1239417000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 5.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1541901750 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1251548500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 5.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1536730000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 16532258 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10678400 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 414272 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11254854 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7335293 # Number of BTB hits
+system.cpu.branchPred.lookups 16751824 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10815024 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 427504 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 12114862 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7449714 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 65.174484 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1985053 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 41515 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.492355 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 2011177 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 42536 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 22389116 # DTB read hits
-system.cpu.dtb.read_misses 220601 # DTB read misses
-system.cpu.dtb.read_acv 47 # DTB read access violations
-system.cpu.dtb.read_accesses 22609717 # DTB read accesses
-system.cpu.dtb.write_hits 15701492 # DTB write hits
-system.cpu.dtb.write_misses 40930 # DTB write misses
-system.cpu.dtb.write_acv 4 # DTB write access violations
-system.cpu.dtb.write_accesses 15742422 # DTB write accesses
-system.cpu.dtb.data_hits 38090608 # DTB hits
-system.cpu.dtb.data_misses 261531 # DTB misses
-system.cpu.dtb.data_acv 51 # DTB access violations
-system.cpu.dtb.data_accesses 38352139 # DTB accesses
-system.cpu.itb.fetch_hits 13899561 # ITB hits
-system.cpu.itb.fetch_misses 35223 # ITB misses
+system.cpu.dtb.read_hits 22508658 # DTB read hits
+system.cpu.dtb.read_misses 223827 # DTB read misses
+system.cpu.dtb.read_acv 56 # DTB read access violations
+system.cpu.dtb.read_accesses 22732485 # DTB read accesses
+system.cpu.dtb.write_hits 15810202 # DTB write hits
+system.cpu.dtb.write_misses 43571 # DTB write misses
+system.cpu.dtb.write_acv 3 # DTB write access violations
+system.cpu.dtb.write_accesses 15853773 # DTB write accesses
+system.cpu.dtb.data_hits 38318860 # DTB hits
+system.cpu.dtb.data_misses 267398 # DTB misses
+system.cpu.dtb.data_acv 59 # DTB access violations
+system.cpu.dtb.data_accesses 38586258 # DTB accesses
+system.cpu.itb.fetch_hits 14110575 # ITB hits
+system.cpu.itb.fetch_misses 33841 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 13934784 # ITB accesses
+system.cpu.itb.fetch_accesses 14144416 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 49272404 # number of cpu cycles simulated
+system.cpu.numCycles 48441123 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15777525 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 105311558 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16532258 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9320346 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 19533612 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1991452 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7584858 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 7736 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 311235 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 81 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13899561 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 206313 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 44661692 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.357984 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.120695 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 15991541 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 106726758 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16751824 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9460891 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 19798045 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2119165 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 5548537 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 5780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 330003 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 14110575 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 235048 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 43228418 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.468903 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.149982 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 25128080 56.26% 56.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1526401 3.42% 59.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1371052 3.07% 62.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1506745 3.37% 66.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4140649 9.27% 75.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1845293 4.13% 79.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 672736 1.51% 81.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1068547 2.39% 83.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 7402189 16.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 23430373 54.20% 54.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1549768 3.59% 57.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1389630 3.21% 61.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1530327 3.54% 64.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4182492 9.68% 74.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1877886 4.34% 78.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 686601 1.59% 80.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1082983 2.51% 82.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7498358 17.35% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 44661692 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.335528 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.137333 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16866897 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 7111825 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18558707 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 782025 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1342238 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3745907 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 106790 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 103587056 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 304363 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1342238 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 17337019 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4756497 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 85160 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18837400 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2303378 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102332178 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 523 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2649 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2191032 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 61618182 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 123319781 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 123000606 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 319174 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 43228418 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.345818 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.203226 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16783976 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5410543 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19277752 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 307681 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1448466 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3794458 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 108182 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 104881075 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 317541 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1448466 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 17188880 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4589733 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 87878 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19270658 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 642803 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 103574244 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 2041 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 123118 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 133246 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 383447 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 62411257 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 124921798 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 124593189 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 328608 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9071301 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5539 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5537 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 4823048 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 23221608 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16268601 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1205921 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 453901 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 90714313 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5368 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 88410610 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 95528 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10671258 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4645313 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 785 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 44661692 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.979562 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.108908 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 9864376 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5611 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5609 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 1424158 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 23418596 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16455537 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1234609 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 506012 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 91610357 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 5443 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 89041530 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 152798 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11549535 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 5161371 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 860 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 43228418 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.059792 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.166400 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 16438268 36.81% 36.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 6883864 15.41% 52.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5570491 12.47% 64.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4772833 10.69% 75.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4726674 10.58% 85.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2623655 5.87% 91.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1921880 4.30% 96.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1281202 2.87% 99.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 442825 0.99% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 16020950 37.06% 37.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 5899567 13.65% 50.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5167698 11.95% 62.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4624013 10.70% 73.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4881657 11.29% 84.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2705075 6.26% 90.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2091187 4.84% 95.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1370765 3.17% 98.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 467506 1.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 44661692 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 43228418 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 125753 6.74% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 787939 42.23% 48.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 952099 51.03% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 122844 6.34% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 826331 42.62% 48.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 989497 51.04% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49354396 55.82% 55.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 43843 0.05% 55.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 121164 0.14% 56.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 56.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 120950 0.14% 56.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 59 0.00% 56.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 22839676 25.83% 82.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 15891479 17.97% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49689736 55.81% 55.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 43878 0.05% 55.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.85% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 121254 0.14% 55.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 121079 0.14% 56.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 38922 0.04% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 22993595 25.82% 81.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 16032920 18.01% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 88410610 # Type of FU issued
-system.cpu.iq.rate 1.794323 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1865791 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.021104 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 222840563 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 100994037 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86537266 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 603668 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 414920 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 294049 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 89974489 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 301912 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1467836 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 89041530 # Type of FU issued
+system.cpu.iq.rate 1.838139 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1938672 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.021773 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 222789760 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 102752204 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87020411 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 613188 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 432642 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 299262 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 90673556 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 306646 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1613513 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2944970 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 5006 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18410 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1655224 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3141958 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5326 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 19773 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1842160 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2933 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 89330 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3009 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 163446 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1342238 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3674629 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 72016 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100198527 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 23221608 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16268601 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5368 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 49821 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6531 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18410 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 194109 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 159104 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 353213 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 87568841 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 22612881 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 841769 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1448466 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 3237152 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1283757 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 101157149 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 209803 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 23418596 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16455537 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5443 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 41968 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1233080 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 19773 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 207340 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 162214 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 369554 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 88099058 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 22735868 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 942472 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9478846 # number of nop insts executed
-system.cpu.iew.exec_refs 38355645 # number of memory reference insts executed
-system.cpu.iew.exec_branches 15084252 # Number of branches executed
-system.cpu.iew.exec_stores 15742764 # Number of stores executed
-system.cpu.iew.exec_rate 1.777239 # Inst execution rate
-system.cpu.iew.wb_sent 87220375 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86831315 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 33345689 # num instructions producing a value
-system.cpu.iew.wb_consumers 43460058 # num instructions consuming a value
+system.cpu.iew.exec_nop 9541349 # number of nop insts executed
+system.cpu.iew.exec_refs 38590030 # number of memory reference insts executed
+system.cpu.iew.exec_branches 15163094 # Number of branches executed
+system.cpu.iew.exec_stores 15854162 # Number of stores executed
+system.cpu.iew.exec_rate 1.818683 # Inst execution rate
+system.cpu.iew.wb_sent 87723103 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87319673 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 33922471 # num instructions producing a value
+system.cpu.iew.wb_consumers 44377340 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.762271 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.767272 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.802594 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.764410 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 8854011 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9580594 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 309865 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 43319454 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.039284 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.791171 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 321519 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 41779952 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.114427 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.873182 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 20467997 47.25% 47.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 7041159 16.25% 63.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3392321 7.83% 71.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2059744 4.75% 76.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2024611 4.67% 80.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1169642 2.70% 83.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1101426 2.54% 86.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 720003 1.66% 87.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5342551 12.33% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 19839464 47.49% 47.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 6575552 15.74% 63.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3029914 7.25% 70.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 1889529 4.52% 75.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1770667 4.24% 79.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1150899 2.75% 81.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1116698 2.67% 84.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 758478 1.82% 86.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5648751 13.52% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 43319454 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 41779952 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5342551 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5648751 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 133854244 # The number of ROB reads
-system.cpu.rob.rob_writes 195734344 # The number of ROB writes
-system.cpu.timesIdled 83887 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 4610712 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 132735125 # The number of ROB reads
+system.cpu.rob.rob_writes 197294055 # The number of ROB writes
+system.cpu.timesIdled 86991 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5212705 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.619064 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.619064 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.615341 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.615341 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 115895624 # number of integer regfile reads
-system.cpu.int_regfile_writes 57505324 # number of integer regfile writes
-system.cpu.fp_regfile_reads 249507 # number of floating regfile reads
-system.cpu.fp_regfile_writes 239755 # number of floating regfile writes
-system.cpu.misc_regfile_reads 38031 # number of misc regfile reads
+system.cpu.cpi 0.608620 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.608620 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.643062 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.643062 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 116607972 # number of integer regfile reads
+system.cpu.int_regfile_writes 57833573 # number of integer regfile writes
+system.cpu.fp_regfile_reads 254535 # number of floating regfile reads
+system.cpu.fp_regfile_writes 240366 # number of floating regfile writes
+system.cpu.misc_regfile_reads 38019 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1215125035 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 155398 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 155397 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 168938 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 143416 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 143416 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186521 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580044 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 766565 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5968640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967424 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 29936064 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 29936064 # Total data (bytes)
+system.cpu.toL2Bus.throughput 1241063981 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 157229 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 157228 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 169024 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 143424 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 143424 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189945 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580384 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 770329 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6078208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23981056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 30059264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 30059264 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 402814000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 141250965 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 403862500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 143810707 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 328598748 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 325706997 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
-system.cpu.icache.tags.replacements 91212 # number of replacements
-system.cpu.icache.tags.tagsinuse 1925.511317 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 13793650 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 93260 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 147.905318 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 19818994250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1925.511317 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.940191 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.940191 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 92924 # number of replacements
+system.cpu.icache.tags.tagsinuse 1926.308876 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 14002846 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 94972 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 147.441835 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 19458186000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 1926.308876 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.940581 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.940581 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 1531 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 356 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 1533 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 355 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 27892378 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 27892378 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 13793650 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13793650 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13793650 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13793650 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13793650 # number of overall hits
-system.cpu.icache.overall_hits::total 13793650 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 105909 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 105909 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 105909 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 105909 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 105909 # number of overall misses
-system.cpu.icache.overall_misses::total 105909 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1976186457 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1976186457 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1976186457 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1976186457 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1976186457 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1976186457 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13899559 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13899559 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13899559 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13899559 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13899559 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13899559 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007620 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.007620 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.007620 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.007620 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.007620 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.007620 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18659.287284 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18659.287284 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18659.287284 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18659.287284 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18659.287284 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18659.287284 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 681 # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses 28316122 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 28316122 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 14002846 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 14002846 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 14002846 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 14002846 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 14002846 # number of overall hits
+system.cpu.icache.overall_hits::total 14002846 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 107729 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 107729 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 107729 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 107729 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 107729 # number of overall misses
+system.cpu.icache.overall_misses::total 107729 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1994925704 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1994925704 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1994925704 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 1994925704 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 1994925704 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 1994925704 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 14110575 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 14110575 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 14110575 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 14110575 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 14110575 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 14110575 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007635 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.007635 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.007635 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.007635 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.007635 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.007635 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18518.000761 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18518.000761 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18518.000761 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18518.000761 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18518.000761 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18518.000761 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 484 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 45.400000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 23.047619 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12648 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 12648 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 12648 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 12648 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 12648 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 12648 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93261 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 93261 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 93261 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 93261 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 93261 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 93261 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1519348535 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 1519348535 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1519348535 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 1519348535 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1519348535 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 1519348535 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006710 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006710 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006710 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.006710 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006710 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.006710 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16291.360108 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16291.360108 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16291.360108 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16291.360108 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16291.360108 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16291.360108 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12756 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 12756 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 12756 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 12756 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 12756 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 12756 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94973 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 94973 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 94973 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 94973 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 94973 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 94973 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1539030293 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 1539030293 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1539030293 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 1539030293 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1539030293 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 1539030293 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006731 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006731 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006731 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.006731 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006731 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.006731 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16204.924484 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16204.924484 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16204.924484 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16204.924484 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16204.924484 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16204.924484 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 132413 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 30673.735606 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 159593 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 164480 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.970288 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 132416 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 30678.676989 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 161509 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 164481 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.981931 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26310.881210 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2113.593767 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 2249.260629 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.802944 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064502 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.068642 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.936088 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 32067 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1480 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18009 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12342 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 26301.675025 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2114.771932 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 2262.230032 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.802663 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064538 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.069038 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.936239 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32065 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1465 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18112 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12251 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978607 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 4049912 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 4049912 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 85586 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 34280 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 119866 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 168938 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 168938 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 12623 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 12623 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 85586 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 46903 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 132489 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 85586 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 46903 # number of overall hits
-system.cpu.l2cache.overall_hits::total 132489 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 7675 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 27857 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 35532 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 130793 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 130793 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 7675 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 158650 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 166325 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 7675 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 158650 # number of overall misses
-system.cpu.l2cache.overall_misses::total 166325 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 569595000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2069573000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 2639168000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13123369250 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 13123369250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 569595000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 15192942250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 15762537250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 569595000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 15192942250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 15762537250 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 93261 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 62137 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 155398 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 168938 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 168938 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 143416 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 143416 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 93261 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 205553 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 298814 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 93261 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 205553 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 298814 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082296 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448316 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.228652 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911983 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.911983 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082296 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.771820 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.556617 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082296 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.771820 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.556617 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74214.332248 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74292.745091 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74275.807723 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 100336.938903 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 100336.938903 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74214.332248 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95763.896943 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 94769.500977 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74214.332248 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95763.896943 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 94769.500977 # average overall miss latency
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978546 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 4065321 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 4065321 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 87302 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 34382 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 121684 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 169024 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 169024 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 12642 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 12642 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 87302 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 47024 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 134326 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 87302 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 47024 # number of overall hits
+system.cpu.l2cache.overall_hits::total 134326 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 7671 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 27874 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 35545 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 130782 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 130782 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 7671 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 158656 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 166327 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 7671 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 158656 # number of overall misses
+system.cpu.l2cache.overall_misses::total 166327 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 570435250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2071676250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 2642111500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13040199000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 13040199000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 570435250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 15111875250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 15682310500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 570435250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 15111875250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 15682310500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 94973 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 62256 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 157229 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 169024 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 169024 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 143424 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 143424 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 94973 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 205680 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 300653 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 94973 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 205680 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 300653 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.080770 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.447732 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.226072 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911856 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.911856 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.080770 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.771373 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.553219 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.080770 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.771373 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.553219 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74362.566810 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74322.890507 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74331.453088 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 99709.432491 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 99709.432491 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74362.566810 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95249.314555 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 94286.017904 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74362.566810 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95249.314555 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 94286.017904 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 114011 # number of writebacks
-system.cpu.l2cache.writebacks::total 114011 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7675 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27857 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 35532 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130793 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 130793 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 7675 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 158650 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 166325 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 7675 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 158650 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 166325 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 472615500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1714074500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2186690000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11513357750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11513357750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472615500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13227432250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 13700047750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472615500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13227432250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 13700047750 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082296 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448316 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228652 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911983 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911983 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082296 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771820 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.556617 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082296 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771820 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.556617 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61578.566775 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61531.195032 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61541.427446 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88027.323710 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88027.323710 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61578.566775 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83374.927513 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82369.143244 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61578.566775 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83374.927513 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82369.143244 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 114016 # number of writebacks
+system.cpu.l2cache.writebacks::total 114016 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7671 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27874 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 35545 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130782 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 130782 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 7671 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 158656 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 166327 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 7671 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 158656 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 166327 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 473528250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1715909250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2189437500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11438645000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11438645000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 473528250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13154554250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 13628082500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 473528250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13154554250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 13628082500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.080770 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.447732 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.226072 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911856 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911856 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.080770 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771373 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.553219 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.080770 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771373 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.553219 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61729.663668 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61559.490923 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61596.216064 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87463.450628 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87463.450628 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61729.663668 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82912.428462 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81935.479507 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61729.663668 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82912.428462 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81935.479507 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 201457 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4073.584909 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 34188310 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 205553 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 166.323576 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 223833000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4073.584909 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.994528 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.994528 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 201584 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4073.453777 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 34149208 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 205680 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 166.030766 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 220256000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4073.453777 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.994496 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.994496 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2926 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 1087 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2932 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 71195917 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 71195917 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 20614139 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 20614139 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 13574109 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 13574109 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 34188248 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 34188248 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 34188248 # number of overall hits
-system.cpu.dcache.overall_hits::total 34188248 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 267604 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 267604 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1039268 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1039268 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1306872 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1306872 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1306872 # number of overall misses
-system.cpu.dcache.overall_misses::total 1306872 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 16043231998 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 16043231998 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 85247557215 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 85247557215 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 101290789213 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 101290789213 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 101290789213 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 101290789213 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 20881743 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 20881743 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 71118094 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 71118094 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 20574856 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 20574856 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 13574283 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 13574283 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 69 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 69 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data 34149139 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 34149139 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 34149139 # number of overall hits
+system.cpu.dcache.overall_hits::total 34149139 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 267905 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 267905 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1039094 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1039094 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1306999 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1306999 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1306999 # number of overall misses
+system.cpu.dcache.overall_misses::total 1306999 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 16089401748 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 16089401748 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 84831675131 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 84831675131 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 100921076879 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 100921076879 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 100921076879 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 100921076879 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 20842761 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 20842761 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 35495120 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 35495120 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 35495120 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 35495120 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012815 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012815 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.036818 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.036818 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.036818 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.036818 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59951.390854 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59951.390854 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82026.539078 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 82026.539078 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 77506.281574 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 77506.281574 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 77506.281574 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 77506.281574 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 4834178 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 35456138 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 35456138 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 35456138 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 35456138 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012854 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012854 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071106 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.071106 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.036862 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.036862 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.036862 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.036862 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60056.369788 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60056.369788 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81640.039430 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81640.039430 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 77215.879185 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 77215.879185 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 77215.879185 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 77215.879185 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 5326980 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 104486 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 116355 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.266275 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.782132 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 168938 # number of writebacks
-system.cpu.dcache.writebacks::total 168938 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205464 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 205464 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895855 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 895855 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 169024 # number of writebacks
+system.cpu.dcache.writebacks::total 169024 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205645 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 205645 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895674 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 895674 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1101319 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1101319 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1101319 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1101319 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62140 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 62140 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143413 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 143413 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 205553 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 205553 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 205553 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 205553 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2476433502 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2476433502 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13394078745 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 13394078745 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15870512247 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 15870512247 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15870512247 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 15870512247 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62260 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 62260 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143420 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 143420 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 205680 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 205680 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 205680 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 205680 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2479695502 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2479695502 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13310863495 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 13310863495 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15790558997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 15790558997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15790558997 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 15790558997 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002987 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002987 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39852.486353 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39852.486353 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93395.150684 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93395.150684 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77208.857312 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77208.857312 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77208.857312 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77208.857312 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005801 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.005801 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005801 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.005801 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39828.067812 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39828.067812 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92810.371601 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92810.371601 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76772.457201 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76772.457201 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76772.457201 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76772.457201 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
warn: Sockets disabled, not accepting gdb connections
-warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:54:40
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:43:42
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5a6c340
+ 0: system.cpu.isa: ISA system set to: 0 0x62769a0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 26790388000 because target called exit()
+Exiting @ tick 25431292500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.026655 # Number of seconds simulated
-sim_ticks 26655046000 # Number of ticks simulated
-final_tick 26655046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.025431 # Number of seconds simulated
+sim_ticks 25431292500 # Number of ticks simulated
+final_tick 25431292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 108502 # Simulator instruction rate (inst/s)
-host_op_rate 153979 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40787374 # Simulator tick rate (ticks/s)
-host_mem_usage 322284 # Number of bytes of host memory used
-host_seconds 653.51 # Real time elapsed on the host
+host_inst_rate 123125 # Simulator instruction rate (inst/s)
+host_op_rate 174730 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44159257 # Simulator tick rate (ticks/s)
+host_mem_usage 270444 # Number of bytes of host memory used
+host_seconds 575.90 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 298176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8241600 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 298176 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 298176 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5372544 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5372544 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 4659 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128775 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83946 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83946 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11186475 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 298008265 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 309194739 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11186475 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11186475 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 201558234 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 201558234 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 201558234 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11186475 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 298008265 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 510752973 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128776 # Number of read requests accepted
-system.physmem.writeReqs 83946 # Number of write requests accepted
-system.physmem.readBursts 128776 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 83946 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 8241344 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5371328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 8241664 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5372544 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 300416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7942976 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8243392 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 300416 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 300416 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 4694 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 124109 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 128803 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 11812848 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 312330803 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 324143651 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 11812848 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 11812848 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 211249664 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 211249664 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 211249664 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 11812848 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 312330803 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 535393315 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 128804 # Number of read requests accepted
+system.physmem.writeReqs 83943 # Number of write requests accepted
+system.physmem.readBursts 128804 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 83943 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 8243072 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
+system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 8243456 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 5372352 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 320 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 8145 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8395 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 342 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 8140 # Per bank write bursts
+system.physmem.perBankRdBursts::1 8383 # Per bank write bursts
system.physmem.perBankRdBursts::2 8248 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8167 # Per bank write bursts
-system.physmem.perBankRdBursts::4 8288 # Per bank write bursts
-system.physmem.perBankRdBursts::5 8447 # Per bank write bursts
-system.physmem.perBankRdBursts::6 8087 # Per bank write bursts
-system.physmem.perBankRdBursts::7 7963 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8065 # Per bank write bursts
+system.physmem.perBankRdBursts::3 8172 # Per bank write bursts
+system.physmem.perBankRdBursts::4 8304 # Per bank write bursts
+system.physmem.perBankRdBursts::5 8450 # Per bank write bursts
+system.physmem.perBankRdBursts::6 8104 # Per bank write bursts
+system.physmem.perBankRdBursts::7 7960 # Per bank write bursts
+system.physmem.perBankRdBursts::8 8081 # Per bank write bursts
system.physmem.perBankRdBursts::9 7608 # Per bank write bursts
system.physmem.perBankRdBursts::10 7787 # Per bank write bursts
-system.physmem.perBankRdBursts::11 7815 # Per bank write bursts
+system.physmem.perBankRdBursts::11 7813 # Per bank write bursts
system.physmem.perBankRdBursts::12 7882 # Per bank write bursts
-system.physmem.perBankRdBursts::13 7885 # Per bank write bursts
-system.physmem.perBankRdBursts::14 7978 # Per bank write bursts
-system.physmem.perBankRdBursts::15 8011 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5180 # Per bank write bursts
-system.physmem.perBankWrBursts::1 5377 # Per bank write bursts
+system.physmem.perBankRdBursts::13 7882 # Per bank write bursts
+system.physmem.perBankRdBursts::14 7972 # Per bank write bursts
+system.physmem.perBankRdBursts::15 8012 # Per bank write bursts
+system.physmem.perBankWrBursts::0 5177 # Per bank write bursts
+system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
system.physmem.perBankWrBursts::2 5291 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5157 # Per bank write bursts
+system.physmem.perBankWrBursts::3 5156 # Per bank write bursts
system.physmem.perBankWrBursts::4 5265 # Per bank write bursts
system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5199 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5049 # Per bank write bursts
+system.physmem.perBankWrBursts::6 5200 # Per bank write bursts
+system.physmem.perBankWrBursts::7 5050 # Per bank write bursts
system.physmem.perBankWrBursts::8 5030 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5091 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5246 # Per bank write bursts
-system.physmem.perBankWrBursts::11 5144 # Per bank write bursts
-system.physmem.perBankWrBursts::12 5342 # Per bank write bursts
+system.physmem.perBankWrBursts::9 5089 # Per bank write bursts
+system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
+system.physmem.perBankWrBursts::11 5142 # Per bank write bursts
+system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
+system.physmem.perBankWrBursts::15 5223 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 26655030500 # Total gap between requests
+system.physmem.totGap 25431274000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 128776 # Read request sizes (log2)
+system.physmem.readPktSize::6 128804 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 83946 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 74138 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 53140 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 1433 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 52 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 83943 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 74268 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 52779 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1686 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 643 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 655 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2224 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4090 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4895 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5187 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 658 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2213 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3968 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5202 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5604 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5798 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6000 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5297 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5379 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5443 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5403 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5565 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 5914 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5677 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6138 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6027 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5293 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 37804 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 360.014390 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 216.175335 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 343.156707 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12089 31.98% 31.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 7874 20.83% 52.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 3781 10.00% 62.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2728 7.22% 70.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2397 6.34% 76.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1617 4.28% 80.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1220 3.23% 83.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1066 2.82% 86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5032 13.31% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 37804 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5144 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.030132 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 392.032521 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5142 99.96% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5144 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5144 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.315513 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.292869 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.917660 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4492 87.33% 87.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 6 0.12% 87.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 431 8.38% 95.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 161 3.13% 98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 33 0.64% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 11 0.21% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 6 0.12% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 1 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5144 # Writes before turning the bus around for reads
-system.physmem.totQLat 2471536000 # Total ticks spent queuing
-system.physmem.totMemAccLat 4885992250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 643855000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 19193.27 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 37764 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 360.466900 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 216.757090 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 343.203142 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 11986 31.74% 31.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 7964 21.09% 52.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 3753 9.94% 62.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2738 7.25% 70.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2422 6.41% 76.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1565 4.14% 80.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1215 3.22% 83.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1119 2.96% 86.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5002 13.25% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 37764 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5143 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 25.040249 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 360.430137 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 5140 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 5143 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5143 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.318102 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.295777 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.900493 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 4492 87.34% 87.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 9 0.17% 87.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 404 7.86% 95.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 175 3.40% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 41 0.80% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 14 0.27% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 4 0.08% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 2 0.04% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 2 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5143 # Writes before turning the bus around for reads
+system.physmem.totQLat 2477042500 # Total ticks spent queuing
+system.physmem.totMemAccLat 4892005000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 643990000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 19232.00 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 37943.27 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 309.19 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 201.51 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 309.20 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 201.56 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 37982.00 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 324.13 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 211.20 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 324.15 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 211.25 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.99 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.52 # Average write queue length when enqueuing
-system.physmem.readRowHits 112800 # Number of row buffer hits during reads
-system.physmem.writeRowHits 62083 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.96 # Row buffer hit rate for writes
-system.physmem.avgGap 125304.53 # Average gap between requests
-system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 11333884750 # Time in different power states
-system.physmem.memoryStateTime::REF 889980000 # Time in different power states
+system.physmem.busUtil 4.18 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.53 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 1.65 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 23.78 # Average write queue length when enqueuing
+system.physmem.readRowHits 112907 # Number of row buffer hits during reads
+system.physmem.writeRowHits 62042 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.66 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.91 # Row buffer hit rate for writes
+system.physmem.avgGap 119537.64 # Average gap between requests
+system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 10352020250 # Time in different power states
+system.physmem.memoryStateTime::REF 849160000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 14428773750 # Time in different power states
+system.physmem.memoryStateTime::ACT 14228986000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 510752973 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 26520 # Transaction distribution
-system.membus.trans_dist::ReadResp 26519 # Transaction distribution
-system.membus.trans_dist::Writeback 83946 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 320 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 320 # Transaction distribution
-system.membus.trans_dist::ReadExReq 102256 # Transaction distribution
-system.membus.trans_dist::ReadExResp 102256 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342137 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 342137 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 13614144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 13614144 # Total data (bytes)
+system.membus.throughput 535393315 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 26553 # Transaction distribution
+system.membus.trans_dist::ReadResp 26552 # Transaction distribution
+system.membus.trans_dist::Writeback 83943 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 342 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 342 # Transaction distribution
+system.membus.trans_dist::ReadExReq 102251 # Transaction distribution
+system.membus.trans_dist::ReadExResp 102251 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342234 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 342234 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13615744 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 13615744 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 13615744 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 932451500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 901934500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 3.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1211794930 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 4.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1187807158 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 4.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 16636502 # Number of BP lookups
-system.cpu.branchPred.condPredicted 12767541 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 605249 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 10577266 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7776939 # Number of BTB hits
+system.cpu.branchPred.lookups 17001662 # Number of BP lookups
+system.cpu.branchPred.condPredicted 13020210 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 614898 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10708539 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7958691 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 73.525039 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1824082 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 113194 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 74.320979 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1855518 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 113838 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 53310093 # number of cpu cycles simulated
+system.cpu.numCycles 50862586 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12544266 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 85245132 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16636502 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9601021 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21203621 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2373453 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 10826846 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 346 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11685368 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 181941 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46316681 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.577051 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.331362 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 12841579 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 87379296 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 17001662 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9814209 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21679126 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2704202 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 6435967 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11938705 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 201875 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 43012606 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.839331 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.389146 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 25133357 54.26% 54.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2139356 4.62% 58.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1964088 4.24% 63.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2042720 4.41% 67.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1470632 3.18% 70.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1380684 2.98% 73.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 958438 2.07% 75.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1191046 2.57% 78.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10036360 21.67% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21356489 49.65% 49.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2172665 5.05% 54.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2009321 4.67% 59.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2081413 4.84% 64.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1500240 3.49% 67.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1419840 3.30% 71.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 985272 2.29% 73.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1219233 2.83% 76.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10268133 23.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46316681 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.312070 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.599043 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 14641724 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9163742 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19491129 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1382035 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1638051 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3333190 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 105248 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 116897409 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 363517 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1638051 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16359930 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2678860 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1013546 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19105164 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5521130 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 115000815 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 16720 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4660350 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 282 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115331621 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 529914525 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 476510410 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2776 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 43012606 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.334267 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.717948 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 13769056 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5959303 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20895341 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 441693 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1947213 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3430949 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 110387 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 119589480 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 395300 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1947213 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 14636498 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 284865 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1020852 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 20468957 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4654221 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 117623188 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 544 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 181856 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 2734092 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1628680 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 1673 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 117928367 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 541896046 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 487330730 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3427 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 16198949 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 20436 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 20434 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13095384 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29625138 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 22434042 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3869725 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4362550 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 111565619 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 36058 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 107262004 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 275498 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10829281 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 25946611 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2272 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46316681 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.315840 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.990470 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 18795695 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 20563 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 20550 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 5392644 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 30100241 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 22927452 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5590192 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5698921 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 113818479 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 36102 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 108240105 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 379531 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 13068972 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 32214297 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2316 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 43012606 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.516474 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.084237 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 11030019 23.81% 23.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 8138803 17.57% 41.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7430883 16.04% 57.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7110857 15.35% 72.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5417654 11.70% 84.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3891349 8.40% 92.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1848302 3.99% 96.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 878821 1.90% 98.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 569993 1.23% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9996470 23.24% 23.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 6251950 14.54% 37.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6474591 15.05% 52.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6613067 15.37% 68.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5424130 12.61% 80.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4356381 10.13% 90.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2112627 4.91% 95.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1221535 2.84% 98.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 561855 1.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46316681 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 43012606 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 113827 4.59% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1360293 54.84% 59.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1006288 40.57% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 131486 5.24% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 1 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1416079 56.44% 61.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 961652 38.32% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 56646184 52.81% 52.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91539 0.09% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 222 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 28903042 26.95% 79.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21621010 20.16% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57280619 52.92% 52.92% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 91502 0.08% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 249 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 29070055 26.86% 79.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21797673 20.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 107262004 # Type of FU issued
-system.cpu.iq.rate 2.012039 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2480410 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023125 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263595997 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 122458930 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 105571537 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 600 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 932 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 176 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 109742111 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 303 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2179776 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 108240105 # Type of FU issued
+system.cpu.iq.rate 2.128089 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2509218 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.023182 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 262380760 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 126960554 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 106504533 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 805 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 110748938 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 385 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2726538 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2318030 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6495 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30041 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1878304 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2793133 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5994 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 39986 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2371714 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 708 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 777 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1638051 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1126663 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 45667 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 111611483 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 295320 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29625138 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 22434042 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 20138 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6203 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5120 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30041 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 394287 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 181285 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 575572 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106232062 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 28604336 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1029942 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1947213 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 83242 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 154560 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 113864521 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 271261 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 30100241 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 22927452 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 20182 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 11127 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 139253 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 39986 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 397706 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 183440 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 581146 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 107196907 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 28742416 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1043198 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9806 # number of nop insts executed
-system.cpu.iew.exec_refs 49939736 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14601830 # Number of branches executed
-system.cpu.iew.exec_stores 21335400 # Number of stores executed
-system.cpu.iew.exec_rate 1.992720 # Inst execution rate
-system.cpu.iew.wb_sent 105794271 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 105571713 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 53289529 # num instructions producing a value
-system.cpu.iew.wb_consumers 103696689 # num instructions consuming a value
+system.cpu.iew.exec_nop 9940 # number of nop insts executed
+system.cpu.iew.exec_refs 50252614 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14716112 # Number of branches executed
+system.cpu.iew.exec_stores 21510198 # Number of stores executed
+system.cpu.iew.exec_rate 2.107579 # Inst execution rate
+system.cpu.iew.wb_sent 106740577 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 106504731 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 57038202 # num instructions producing a value
+system.cpu.iew.wb_consumers 114479064 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.980333 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.513898 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.093970 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.498241 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 10980049 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 13236328 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 501819 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 44678630 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.252362 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.761359 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 506712 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 41065393 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.450541 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.921831 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 15558775 34.82% 34.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11701818 26.19% 61.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3471869 7.77% 68.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2879306 6.44% 75.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1869514 4.18% 79.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1922443 4.30% 83.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 688922 1.54% 85.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 562713 1.26% 86.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6023270 13.48% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 14078032 34.28% 34.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 10319124 25.13% 59.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 2761047 6.72% 66.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2619650 6.38% 72.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1508272 3.67% 76.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1822351 4.44% 80.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 663911 1.62% 82.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 540097 1.32% 83.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6752909 16.44% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 44678630 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 41065393 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70913181 # Number of instructions committed
system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 100632428 # Class of committed instruction
-system.cpu.commit.bw_lim_events 6023270 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6752909 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 150242538 # The number of ROB reads
-system.cpu.rob.rob_writes 224871982 # The number of ROB writes
-system.cpu.timesIdled 79510 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 6993412 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 148155941 # The number of ROB reads
+system.cpu.rob.rob_writes 229697127 # The number of ROB writes
+system.cpu.timesIdled 83826 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7849980 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.751825 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.751825 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.330098 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.330098 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 511631717 # number of integer regfile reads
-system.cpu.int_regfile_writes 103353872 # number of integer regfile writes
-system.cpu.fp_regfile_reads 846 # number of floating regfile reads
-system.cpu.fp_regfile_writes 710 # number of floating regfile writes
-system.cpu.misc_regfile_reads 49341635 # number of misc regfile reads
+system.cpu.cpi 0.717308 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.717308 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.394102 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.394102 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 515806241 # number of integer regfile reads
+system.cpu.int_regfile_writes 104262317 # number of integer regfile writes
+system.cpu.fp_regfile_reads 1054 # number of floating regfile reads
+system.cpu.fp_regfile_writes 938 # number of floating regfile writes
+system.cpu.misc_regfile_reads 49641533 # number of misc regfile reads
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 775139386 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 86625 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 86624 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 129165 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 335 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 335 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 107045 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 107045 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62039 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454624 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 516663 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1968896 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659776 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 20628672 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 20628672 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 32704 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 290752497 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 820945141 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 90021 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 90020 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 129157 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 357 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 357 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68737 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454707 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 523444 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2182208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660800 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 20843008 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 20843008 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 34688 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 292444997 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 47657477 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 52710982 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 267144007 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 261104274 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 28917 # number of replacements
-system.cpu.icache.tags.tagsinuse 1807.865134 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 11650266 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 30950 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 376.422165 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 32259 # number of replacements
+system.cpu.icache.tags.tagsinuse 1808.767041 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 11900174 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 34296 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 346.984313 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1807.865134 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.882747 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.882747 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 2033 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 1259 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.992676 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 23402009 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 23402009 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 11650274 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11650274 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11650274 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11650274 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11650274 # number of overall hits
-system.cpu.icache.overall_hits::total 11650274 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 35093 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 35093 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 35093 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 35093 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 35093 # number of overall misses
-system.cpu.icache.overall_misses::total 35093 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 796173972 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 796173972 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 796173972 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 796173972 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 796173972 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 796173972 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11685367 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11685367 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11685367 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11685367 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11685367 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11685367 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003003 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.003003 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.003003 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.003003 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.003003 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.003003 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22687.543727 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22687.543727 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22687.543727 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22687.543727 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22687.543727 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22687.543727 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1584 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1808.767041 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.883187 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.883187 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 2037 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 674 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.994629 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 23912047 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 23912047 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 11900181 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 11900181 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 11900181 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 11900181 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 11900181 # number of overall hits
+system.cpu.icache.overall_hits::total 11900181 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 38523 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 38523 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 38523 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 38523 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 38523 # number of overall misses
+system.cpu.icache.overall_misses::total 38523 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 840683730 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 840683730 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 840683730 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 840683730 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 840683730 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 840683730 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11938704 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11938704 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11938704 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11938704 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11938704 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11938704 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003227 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.003227 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.003227 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.003227 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.003227 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.003227 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21822.903979 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21822.903979 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21822.903979 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21822.903979 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21822.903979 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21822.903979 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1168 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 60.923077 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 40.275862 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3818 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 3818 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 3818 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 3818 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 3818 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 3818 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31275 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 31275 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 31275 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 31275 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 31275 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 31275 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 647196022 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 647196022 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 647196022 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 647196022 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 647196022 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 647196022 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.717730 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.717730 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.717730 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.717730 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.717730 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.717730 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3883 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 3883 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 3883 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 3883 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 3883 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 3883 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34640 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 34640 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 34640 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 34640 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 34640 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 34640 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 683348518 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 683348518 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 683348518 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 683348518 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 683348518 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 683348518 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002901 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002901 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002901 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19727.151212 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19727.151212 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19727.151212 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19727.151212 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19727.151212 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19727.151212 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 95645 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 29867.639929 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 88414 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 126758 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.697502 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 95674 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 29835.516778 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 91740 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 126786 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.723581 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26665.630532 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 1369.813019 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 1832.196377 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.813770 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041803 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.055914 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.911488 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 31113 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1847 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20513 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8219 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949493 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 2815092 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 2815092 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 26089 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 33429 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 59518 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 129165 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 129165 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 26089 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 38217 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 64306 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 26089 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 38217 # number of overall hits
-system.cpu.l2cache.overall_hits::total 64306 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 4675 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 21921 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 26596 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 319 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 319 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 4675 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 124178 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 128853 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 4675 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 124178 # number of overall misses
-system.cpu.l2cache.overall_misses::total 128853 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 354274500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1813961250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 2168235750 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8348408999 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 8348408999 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 354274500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10162370249 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 10516644749 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 354274500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10162370249 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 10516644749 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 30764 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 55350 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 86114 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 129165 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 129165 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 335 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 335 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 107045 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 107045 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 30764 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 162395 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 193159 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 30764 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 162395 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 193159 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.151963 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.396043 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.308846 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.952239 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.952239 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955271 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.955271 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.151963 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.764666 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.667083 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.151963 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.764666 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.667083 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75780.641711 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82749.931572 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 81524.881561 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.097179 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.097179 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81641.442630 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81641.442630 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75780.641711 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81837.122912 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81617.383755 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75780.641711 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81837.122912 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81617.383755 # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 26618.880266 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 1380.164406 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 1836.472106 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.812344 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042119 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.056045 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.910508 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 31112 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1913 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20923 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7751 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 387 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949463 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 2842080 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 2842080 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 29388 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 33459 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 62847 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 129157 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 129157 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 4786 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 4786 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 29388 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 38245 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 67633 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 29388 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 38245 # number of overall hits
+system.cpu.l2cache.overall_hits::total 67633 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 4710 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 21922 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 26632 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 342 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 342 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 102251 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 102251 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 4710 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 124173 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 128883 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 4710 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 124173 # number of overall misses
+system.cpu.l2cache.overall_misses::total 128883 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 353854250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1815685750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 2169540000 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8365864000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 8365864000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 353854250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10181549750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 10535404000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 353854250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10181549750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 10535404000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 34098 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 55381 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 89479 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 129157 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 129157 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 357 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 357 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 34098 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 162418 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 196516 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 34098 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 162418 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 196516 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.138131 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395840 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.297634 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.957983 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.957983 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955286 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.955286 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.138131 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.764527 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.655840 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.138131 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.764527 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.655840 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75128.290870 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82824.822097 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 81463.652749 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.959064 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.959064 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81816.940666 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81816.940666 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75128.290870 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81994.876100 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81743.938301 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75128.290870 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81994.876100 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81743.938301 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 83946 # number of writebacks
-system.cpu.l2cache.writebacks::total 83946 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4659 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 26520 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 319 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 319 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 4659 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 128777 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 4659 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 294952000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1536285750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1831237750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3196819 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3196819 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7058409501 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7058409501 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 294952000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8594695251 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 8889647251 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294952000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8594695251 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 8889647251 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394959 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.952239 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.952239 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955271 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955271 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764297 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.666689 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151443 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764297 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.666689 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63308.006010 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70275.181831 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69051.197210 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10021.376176 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10021.376176 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69026.174257 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69026.174257 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63308.006010 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69246.162934 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69031.327419 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63308.006010 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69246.162934 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69031.327419 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 83943 # number of writebacks
+system.cpu.l2cache.writebacks::total 83943 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 79 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4695 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21858 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 26553 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 342 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 342 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102251 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 102251 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 4695 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 124109 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 128804 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 4695 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 124109 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 128804 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 294197750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1539385750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1833583500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3432342 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3432342 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7104890000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7104890000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 294197750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8644275750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 8938473500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294197750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8644275750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 8938473500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.137691 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394684 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.296751 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.957983 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.957983 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955286 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955286 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.137691 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764133 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.655438 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.137691 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764133 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.655438 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62661.927583 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70426.651569 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69053.722743 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10036.087719 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10036.087719 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69484.797215 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69484.797215 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62661.927583 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69650.676019 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69395.931027 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62661.927583 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69650.676019 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69395.931027 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 158298 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4068.579596 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 44367951 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 162394 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 273.211763 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 366659250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4068.579596 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 158322 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4067.859586 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 43957323 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 162418 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 270.643174 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 358577250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4067.859586 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.993130 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.993130 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1762 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 1830 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 92310952 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 92310952 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 26067775 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 26067775 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18267649 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18267649 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 15993 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 15993 # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses 91492426 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 91492426 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 25658218 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 25658218 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18266460 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18266460 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 16005 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 16005 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 44335424 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 44335424 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 44335424 # number of overall hits
-system.cpu.dcache.overall_hits::total 44335424 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 124650 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 124650 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1582252 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1582252 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1706902 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1706902 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1706902 # number of overall misses
-system.cpu.dcache.overall_misses::total 1706902 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5082447470 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5082447470 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 124553146004 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 124553146004 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 917250 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 917250 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 129635593474 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 129635593474 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 129635593474 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 129635593474 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 26192425 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 26192425 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 43924678 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 43924678 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 43924678 # number of overall hits
+system.cpu.dcache.overall_hits::total 43924678 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 124918 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 124918 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1583441 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1583441 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1708359 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1708359 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1708359 # number of overall misses
+system.cpu.dcache.overall_misses::total 1708359 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5184955254 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5184955254 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 125206065525 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 125206065525 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 993000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 993000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 130391020779 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 130391020779 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 130391020779 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 130391020779 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 25783136 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 25783136 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16034 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 16034 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16048 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 16048 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46042326 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46042326 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46042326 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46042326 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004759 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004759 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079711 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.079711 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002557 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002557 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037072 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037072 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037072 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037072 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40773.746249 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40773.746249 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78718.905714 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 78718.905714 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22371.951220 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22371.951220 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 75947.883050 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 75947.883050 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 75947.883050 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 75947.883050 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 3831 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1303 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 134 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.589552 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 81.437500 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 45633037 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 45633037 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 45633037 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 45633037 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004845 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004845 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079771 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.079771 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002679 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002679 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037437 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.037437 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037437 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.037437 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41506.870539 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 41506.870539 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79072.138163 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 79072.138163 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23093.023256 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23093.023256 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76325.304447 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76325.304447 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76325.304447 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76325.304447 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 4253 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1744 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.597122 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 79.272727 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 129165 # number of writebacks
-system.cpu.dcache.writebacks::total 129165 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69269 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 69269 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1474904 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1474904 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1544173 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1544173 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1544173 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1544173 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55381 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55381 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107348 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107348 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 129157 # number of writebacks
+system.cpu.dcache.writebacks::total 129157 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69501 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 69501 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1476084 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1476084 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1545585 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1545585 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1545585 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1545585 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55417 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55417 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107357 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107357 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 162729 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 162729 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 162729 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 162729 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2206437312 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2206437312 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8512084920 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8512084920 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 11500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 11500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10718522232 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10718522232 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10718522232 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10718522232 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002114 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002114 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 162774 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 162774 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 162774 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 162774 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2210443817 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2210443817 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8528691900 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8528691900 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 11000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 11000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10739135717 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10739135717 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10739135717 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10739135717 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002149 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002149 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.000062 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000062 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003534 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003534 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003534 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003534 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39841.052202 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39841.052202 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79294.303760 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79294.303760 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65867.314566 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65867.314566 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65867.314566 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65867.314566 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003567 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003567 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39887.468051 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39887.468051 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79442.345632 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79442.345632 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11000 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11000 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65975.743774 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65975.743774 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65975.743774 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65975.743774 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 18:30:51
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 16:50:46
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 685386545000 because target called exit()
+Exiting @ tick 679349778000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.680209 # Number of seconds simulated
-sim_ticks 680209231000 # Number of ticks simulated
-final_tick 680209231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.679350 # Number of seconds simulated
+sim_ticks 679349778000 # Number of ticks simulated
+final_tick 679349778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134123 # Simulator instruction rate (inst/s)
-host_op_rate 134123 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52551522 # Simulator tick rate (ticks/s)
-host_mem_usage 268516 # Number of bytes of host memory used
-host_seconds 12943.66 # Real time elapsed on the host
+host_inst_rate 165098 # Simulator instruction rate (inst/s)
+host_op_rate 165098 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 64606302 # Simulator tick rate (ticks/s)
+host_mem_usage 222340 # Number of bytes of host memory used
+host_seconds 10515.22 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125794880 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125856448 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65262848 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65262848 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1965545 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1966507 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1019732 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1019732 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 90513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 184935567 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 185026081 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 90513 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 90513 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 95945255 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 95945255 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 95945255 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 90513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 184935567 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 280971335 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1966507 # Number of read requests accepted
-system.physmem.writeReqs 1019732 # Number of write requests accepted
-system.physmem.readBursts 1966507 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1019732 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 125774784 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 81664 # Total number of bytes read from write queue
-system.physmem.bytesWritten 65260864 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 125856448 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 65262848 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1276 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125814720 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125876544 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65265856 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65265856 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1965855 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1966821 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1019779 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1019779 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 91005 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 185198736 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 185289740 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 91005 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 91005 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 96071064 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 96071064 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 96071064 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 91005 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 185198736 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 281360804 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1966821 # Number of read requests accepted
+system.physmem.writeReqs 1019779 # Number of write requests accepted
+system.physmem.readBursts 1966821 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1019779 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 125795136 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 81408 # Total number of bytes read from write queue
+system.physmem.bytesWritten 65264000 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 125876544 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 65265856 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1272 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 118983 # Per bank write bursts
-system.physmem.perBankRdBursts::1 114362 # Per bank write bursts
-system.physmem.perBankRdBursts::2 116533 # Per bank write bursts
-system.physmem.perBankRdBursts::3 118021 # Per bank write bursts
-system.physmem.perBankRdBursts::4 118095 # Per bank write bursts
-system.physmem.perBankRdBursts::5 117780 # Per bank write bursts
-system.physmem.perBankRdBursts::6 120157 # Per bank write bursts
-system.physmem.perBankRdBursts::7 124901 # Per bank write bursts
-system.physmem.perBankRdBursts::8 127484 # Per bank write bursts
-system.physmem.perBankRdBursts::9 130413 # Per bank write bursts
-system.physmem.perBankRdBursts::10 129050 # Per bank write bursts
-system.physmem.perBankRdBursts::11 130729 # Per bank write bursts
-system.physmem.perBankRdBursts::12 126632 # Per bank write bursts
-system.physmem.perBankRdBursts::13 125586 # Per bank write bursts
-system.physmem.perBankRdBursts::14 122901 # Per bank write bursts
-system.physmem.perBankRdBursts::15 123604 # Per bank write bursts
-system.physmem.perBankWrBursts::0 61270 # Per bank write bursts
-system.physmem.perBankWrBursts::1 61551 # Per bank write bursts
-system.physmem.perBankWrBursts::2 60668 # Per bank write bursts
-system.physmem.perBankWrBursts::3 61328 # Per bank write bursts
-system.physmem.perBankWrBursts::4 61752 # Per bank write bursts
-system.physmem.perBankWrBursts::5 63187 # Per bank write bursts
-system.physmem.perBankWrBursts::6 64234 # Per bank write bursts
-system.physmem.perBankWrBursts::7 65693 # Per bank write bursts
-system.physmem.perBankWrBursts::8 65471 # Per bank write bursts
-system.physmem.perBankWrBursts::9 65863 # Per bank write bursts
-system.physmem.perBankWrBursts::10 65411 # Per bank write bursts
-system.physmem.perBankWrBursts::11 65720 # Per bank write bursts
-system.physmem.perBankWrBursts::12 64318 # Per bank write bursts
-system.physmem.perBankWrBursts::13 64300 # Per bank write bursts
-system.physmem.perBankWrBursts::14 64642 # Per bank write bursts
-system.physmem.perBankWrBursts::15 64293 # Per bank write bursts
+system.physmem.perBankRdBursts::0 118990 # Per bank write bursts
+system.physmem.perBankRdBursts::1 114401 # Per bank write bursts
+system.physmem.perBankRdBursts::2 116526 # Per bank write bursts
+system.physmem.perBankRdBursts::3 118038 # Per bank write bursts
+system.physmem.perBankRdBursts::4 118100 # Per bank write bursts
+system.physmem.perBankRdBursts::5 117781 # Per bank write bursts
+system.physmem.perBankRdBursts::6 120191 # Per bank write bursts
+system.physmem.perBankRdBursts::7 124916 # Per bank write bursts
+system.physmem.perBankRdBursts::8 127523 # Per bank write bursts
+system.physmem.perBankRdBursts::9 130444 # Per bank write bursts
+system.physmem.perBankRdBursts::10 129055 # Per bank write bursts
+system.physmem.perBankRdBursts::11 130769 # Per bank write bursts
+system.physmem.perBankRdBursts::12 126629 # Per bank write bursts
+system.physmem.perBankRdBursts::13 125625 # Per bank write bursts
+system.physmem.perBankRdBursts::14 122929 # Per bank write bursts
+system.physmem.perBankRdBursts::15 123632 # Per bank write bursts
+system.physmem.perBankWrBursts::0 61276 # Per bank write bursts
+system.physmem.perBankWrBursts::1 61573 # Per bank write bursts
+system.physmem.perBankWrBursts::2 60655 # Per bank write bursts
+system.physmem.perBankWrBursts::3 61329 # Per bank write bursts
+system.physmem.perBankWrBursts::4 61751 # Per bank write bursts
+system.physmem.perBankWrBursts::5 63183 # Per bank write bursts
+system.physmem.perBankWrBursts::6 64216 # Per bank write bursts
+system.physmem.perBankWrBursts::7 65714 # Per bank write bursts
+system.physmem.perBankWrBursts::8 65484 # Per bank write bursts
+system.physmem.perBankWrBursts::9 65866 # Per bank write bursts
+system.physmem.perBankWrBursts::10 65407 # Per bank write bursts
+system.physmem.perBankWrBursts::11 65735 # Per bank write bursts
+system.physmem.perBankWrBursts::12 64310 # Per bank write bursts
+system.physmem.perBankWrBursts::13 64307 # Per bank write bursts
+system.physmem.perBankWrBursts::14 64646 # Per bank write bursts
+system.physmem.perBankWrBursts::15 64298 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 680209108500 # Total gap between requests
+system.physmem.totGap 679349688500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1966507 # Read request sizes (log2)
+system.physmem.readPktSize::6 1966821 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1019732 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1643607 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 226349 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 73697 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 21571 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1019779 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1643770 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 225726 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 72200 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 23834 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 28201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 29888 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 50211 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 56677 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 59143 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 60086 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 60363 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 60607 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 60720 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 60883 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 61104 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 61463 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 63111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 63876 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 61304 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 61887 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 60350 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 59595 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 28029 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 29643 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 50000 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 56258 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 59169 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 60158 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 60388 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 60609 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 60716 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 61035 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 61226 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 61677 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 63137 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 63948 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 61422 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 62019 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 60448 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 59666 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 135 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1771936 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 107.810521 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 82.950451 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 136.949127 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1375751 77.64% 77.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 273384 15.43% 93.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 53057 2.99% 96.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 21092 1.19% 97.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 12942 0.73% 97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6638 0.37% 98.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4973 0.28% 98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3952 0.22% 98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 20147 1.14% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1771936 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 59540 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 32.963117 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 163.210264 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 59503 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1771721 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 107.836103 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 82.953832 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 137.029832 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1375665 77.65% 77.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 272762 15.40% 93.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 53440 3.02% 96.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 21316 1.20% 97.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 12827 0.72% 97.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6576 0.37% 98.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5044 0.28% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3861 0.22% 98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 20230 1.14% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1771721 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 59588 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 32.942421 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 164.012858 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 59550 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 13 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 59540 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 59540 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.126318 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.084701 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.213811 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 29197 49.04% 49.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1546 2.60% 51.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 22630 38.01% 89.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 4967 8.34% 97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 921 1.55% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 191 0.32% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 48 0.08% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 6 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 3 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 4 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 4 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 5 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 59540 # Writes before turning the bus around for reads
-system.physmem.totQLat 40008960000 # Total ticks spent queuing
-system.physmem.totMemAccLat 76857041250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 9826155000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 20358.40 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 59588 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 59588 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.113345 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.071670 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.230173 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17 30977 51.99% 51.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19 27509 46.17% 98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21 1030 1.73% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23 43 0.07% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27 4 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31 11 0.02% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-77 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 59588 # Writes before turning the bus around for reads
+system.physmem.totQLat 40014194750 # Total ticks spent queuing
+system.physmem.totMemAccLat 76868238500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 9827745000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 20357.77 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 39108.40 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 184.91 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 95.94 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 185.03 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 95.95 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 39107.77 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 185.17 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 96.07 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 185.29 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 96.07 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.19 # Data bus utilization in percentage
-system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads
+system.physmem.busUtil 2.20 # Data bus utilization in percentage
+system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing
-system.physmem.readRowHits 795143 # Number of row buffer hits during reads
-system.physmem.writeRowHits 417847 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 40.46 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 40.98 # Row buffer hit rate for writes
-system.physmem.avgGap 227781.20 # Average gap between requests
-system.physmem.pageHitRate 40.64 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 135240615750 # Time in different power states
-system.physmem.memoryStateTime::REF 22713600000 # Time in different power states
+system.physmem.avgWrQLen 25.15 # Average write queue length when enqueuing
+system.physmem.readRowHits 795833 # Number of row buffer hits during reads
+system.physmem.writeRowHits 417735 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 40.49 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 40.96 # Row buffer hit rate for writes
+system.physmem.avgGap 227465.91 # Average gap between requests
+system.physmem.pageHitRate 40.65 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 134374460000 # Time in different power states
+system.physmem.memoryStateTime::REF 22684740000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 522252858000 # Time in different power states
+system.physmem.memoryStateTime::ACT 522286376500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 280971335 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 1191350 # Transaction distribution
-system.membus.trans_dist::ReadResp 1191350 # Transaction distribution
-system.membus.trans_dist::Writeback 1019732 # Transaction distribution
-system.membus.trans_dist::ReadExReq 775157 # Transaction distribution
-system.membus.trans_dist::ReadExResp 775157 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952746 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4952746 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191119296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 191119296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 191119296 # Total data (bytes)
+system.membus.throughput 281360804 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1191893 # Transaction distribution
+system.membus.trans_dist::ReadResp 1191893 # Transaction distribution
+system.membus.trans_dist::Writeback 1019779 # Transaction distribution
+system.membus.trans_dist::ReadExReq 774928 # Transaction distribution
+system.membus.trans_dist::ReadExResp 774928 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4953421 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4953421 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191142400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 191142400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 191142400 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 11871718000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 11809306000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 18474668250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 18437139750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 381496982 # Number of BP lookups
-system.cpu.branchPred.condPredicted 296448748 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 16088801 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 262281784 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 259596653 # Number of BTB hits
+system.cpu.branchPred.lookups 390516660 # Number of BP lookups
+system.cpu.branchPred.condPredicted 303583970 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16113462 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 268537122 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 266026822 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.976242 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 24710775 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 3135 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.065194 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 25282995 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 613956448 # DTB read hits
-system.cpu.dtb.read_misses 11261576 # DTB read misses
+system.cpu.dtb.read_hits 621222786 # DTB read hits
+system.cpu.dtb.read_misses 11503040 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 625218024 # DTB read accesses
-system.cpu.dtb.write_hits 212357219 # DTB write hits
-system.cpu.dtb.write_misses 7142526 # DTB write misses
+system.cpu.dtb.read_accesses 632725826 # DTB read accesses
+system.cpu.dtb.write_hits 213831979 # DTB write hits
+system.cpu.dtb.write_misses 7254265 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 219499745 # DTB write accesses
-system.cpu.dtb.data_hits 826313667 # DTB hits
-system.cpu.dtb.data_misses 18404102 # DTB misses
+system.cpu.dtb.write_accesses 221086244 # DTB write accesses
+system.cpu.dtb.data_hits 835054765 # DTB hits
+system.cpu.dtb.data_misses 18757305 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 844717769 # DTB accesses
-system.cpu.itb.fetch_hits 391069582 # ITB hits
-system.cpu.itb.fetch_misses 39 # ITB misses
+system.cpu.dtb.data_accesses 853812070 # DTB accesses
+system.cpu.itb.fetch_hits 400046189 # ITB hits
+system.cpu.itb.fetch_misses 44 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 391069621 # ITB accesses
+system.cpu.itb.fetch_accesses 400046233 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1360418463 # number of cpu cycles simulated
+system.cpu.numCycles 1358699557 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 402539494 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3160334453 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 381496982 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 284307428 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 574405529 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 140578200 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 186557630 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1439 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 391069582 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 8066485 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1280247946 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.468533 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.146412 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 410929991 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3243314345 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 390516660 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 291309817 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 589336372 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 147340013 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 133548447 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1456 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 400046189 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 9025513 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1257254668 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.579680 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.173136 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 705842417 55.13% 55.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42672657 3.33% 58.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 21781408 1.70% 60.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 39699602 3.10% 63.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 129277672 10.10% 73.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 61541075 4.81% 78.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38576961 3.01% 81.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28126887 2.20% 83.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 212729267 16.62% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 667918296 53.13% 53.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 44267394 3.52% 56.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22207289 1.77% 58.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 40636739 3.23% 61.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 131869370 10.49% 72.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 62966774 5.01% 77.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 40227274 3.20% 80.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28245094 2.25% 82.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 218916438 17.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1280247946 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.280426 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.323061 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 434538205 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 167760960 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 542351250 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 18854501 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 116743030 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 58351365 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 885 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3087789939 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2070 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 116743030 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 457481337 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 112438612 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7413 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 535473100 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 58104454 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3005831981 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 610085 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1830591 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 51785017 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2247201366 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3898074686 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3897930349 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 144336 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1257254668 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.287419 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.387072 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 430550615 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 129659255 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 568815009 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4792365 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 123437424 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 59500767 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 917 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3153748807 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2128 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 123437424 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 446386402 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 61779163 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 6860 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 557518816 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 68126003 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3069486898 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1505727 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 6123879 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 54202488 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 8466199 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2295837862 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3983545178 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3983398130 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 147047 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 870998403 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 181 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 123645792 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 679622906 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 255441649 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 67625349 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 36837000 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2724438630 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 139 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2509429146 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3195077 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 979206212 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 415660734 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1280247946 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.960112 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.971405 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 919634899 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 203 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 202 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 44876150 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 692163471 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 260495859 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 73383628 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 38808502 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2780183806 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 184 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2536585762 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4364880 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1034533664 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 460650584 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 155 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1257254668 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.017559 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.009997 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 438364734 34.24% 34.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 203576191 15.90% 50.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 185673841 14.50% 64.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 153359678 11.98% 76.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 133007255 10.39% 87.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 80763135 6.31% 93.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 65057682 5.08% 98.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 15327988 1.20% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5117442 0.40% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 428157011 34.05% 34.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 188380197 14.98% 49.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 177998596 14.16% 63.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 153960413 12.25% 75.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 135215337 10.75% 86.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 80818226 6.43% 92.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 69593138 5.54% 98.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 17238172 1.37% 99.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5893578 0.47% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1280247946 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1257254668 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2183926 11.79% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 11926883 64.38% 76.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4416070 23.84% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2760636 13.79% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12853797 64.19% 77.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4410220 22.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1643735577 65.50% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 274 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 641577426 25.57% 91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 224115520 8.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1663143410 65.57% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 259 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 21 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 647516942 25.53% 91.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 225924828 8.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2509429146 # Type of FU issued
-system.cpu.iq.rate 1.844601 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18526879 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007383 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6318927693 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3702533179 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2413056574 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1900501 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1218976 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 851931 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2527016485 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 939540 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62611923 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2536585762 # Type of FU issued
+system.cpu.iq.rate 1.866922 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 20024653 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007894 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6352883505 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3813585390 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2440929650 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1932220 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1252073 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 864209 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2555655812 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 954603 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 64558247 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 235027243 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 263015 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 108918 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 94713147 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 247567808 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 343004 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 121628 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 99767357 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 189 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1519116 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 225 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1607198 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 116743030 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 54024400 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1298779 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2866611550 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 8938226 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 679622906 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 255441649 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 139 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 284739 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 17925 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 108918 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10360501 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8559141 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18919642 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2462113163 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 625218563 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 47315983 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 123437424 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 22713536 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 8297734 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2923674181 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 8955846 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 692163471 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 260495859 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 184 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 449856 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8304684 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 121628 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10428435 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8597760 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 19026195 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2492121408 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 632726353 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 44464354 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 142172781 # number of nop insts executed
-system.cpu.iew.exec_refs 844718328 # number of memory reference insts executed
-system.cpu.iew.exec_branches 300875979 # Number of branches executed
-system.cpu.iew.exec_stores 219499765 # Number of stores executed
-system.cpu.iew.exec_rate 1.809820 # Inst execution rate
-system.cpu.iew.wb_sent 2441867145 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2413908505 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1388259644 # num instructions producing a value
-system.cpu.iew.wb_consumers 1764197986 # num instructions consuming a value
+system.cpu.iew.exec_nop 143490191 # number of nop insts executed
+system.cpu.iew.exec_refs 853812632 # number of memory reference insts executed
+system.cpu.iew.exec_branches 304222027 # Number of branches executed
+system.cpu.iew.exec_stores 221086279 # Number of stores executed
+system.cpu.iew.exec_rate 1.834196 # Inst execution rate
+system.cpu.iew.wb_sent 2470047897 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2441793859 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1422096892 # num instructions producing a value
+system.cpu.iew.wb_consumers 1830175974 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.774387 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.797155 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.777027 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 826160079 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 873443731 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16088003 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1163504916 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.564050 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.502160 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16112643 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1133817244 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.605003 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.541695 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 649463962 55.82% 55.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 174969107 15.04% 70.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 86152065 7.40% 78.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 53532710 4.60% 82.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 34727147 2.98% 85.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 26083842 2.24% 88.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 21573250 1.85% 89.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 22881203 1.97% 91.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 94121630 8.09% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 625261340 55.15% 55.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 171314027 15.11% 70.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 86268180 7.61% 77.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 54871559 4.84% 82.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 31288205 2.76% 85.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 20767631 1.83% 87.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 23576751 2.08% 89.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22892827 2.02% 91.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 97576724 8.61% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1163504916 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1133817244 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
-system.cpu.commit.bw_lim_events 94121630 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 97576724 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3629544291 # The number of ROB reads
-system.cpu.rob.rob_writes 5408721730 # The number of ROB writes
-system.cpu.timesIdled 949757 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 80170517 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3643685177 # The number of ROB reads
+system.cpu.rob.rob_writes 5509997541 # The number of ROB writes
+system.cpu.timesIdled 1119552 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 101444889 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.783631 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.783631 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.276110 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.276110 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3317990648 # number of integer regfile reads
-system.cpu.int_regfile_writes 1931970641 # number of integer regfile writes
-system.cpu.fp_regfile_reads 30869 # number of floating regfile reads
-system.cpu.fp_regfile_writes 545 # number of floating regfile writes
+system.cpu.cpi 0.782641 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.782641 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.277725 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.277725 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3354502671 # number of integer regfile reads
+system.cpu.int_regfile_writes 1955490145 # number of integer regfile writes
+system.cpu.fp_regfile_reads 31250 # number of floating regfile reads
+system.cpu.fp_regfile_writes 519 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1214348707 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 7297685 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7297685 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 3725127 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1883613 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1883613 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1924 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085799 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 22087723 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61568 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825949632 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 826011200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 826011200 # Total data (bytes)
+system.cpu.toL2Bus.throughput 1216162152 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7299986 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7299986 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 3725797 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1883584 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1883584 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22091005 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 22092937 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826137664 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 826199488 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 826199488 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 10178394945 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 10180553427 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1603000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1609000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14072846750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 14076007750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
system.cpu.icache.tags.replacements 1 # number of replacements
-system.cpu.icache.tags.tagsinuse 772.655537 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 391068098 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 962 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 406515.694387 # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 775.530288 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 400044658 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 414124.904762 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 772.655537 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.377273 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.377273 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 961 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 902 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.469238 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 782140126 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 782140126 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 391068098 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 391068098 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 391068098 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 391068098 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 391068098 # number of overall hits
-system.cpu.icache.overall_hits::total 391068098 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses
-system.cpu.icache.overall_misses::total 1484 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 102456750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 102456750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 102456750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 102456750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 102456750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 102456750 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 391069582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 391069582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 391069582 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 391069582 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 391069582 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 391069582 # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst 775.530288 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.378677 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.378677 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 912 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 800093342 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 800093342 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 400044658 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 400044658 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 400044658 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 400044658 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 400044658 # number of overall hits
+system.cpu.icache.overall_hits::total 400044658 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1530 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1530 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1530 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1530 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1530 # number of overall misses
+system.cpu.icache.overall_misses::total 1530 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 107584749 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 107584749 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 107584749 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 107584749 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 107584749 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 107584749 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 400046188 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 400046188 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 400046188 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 400046188 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 400046188 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 400046188 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69040.936658 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69040.936658 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69040.936658 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69040.936658 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69040.936658 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69040.936658 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70316.829412 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70316.829412 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70316.829412 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70316.829412 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70316.829412 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 203.500000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 48.833333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 522 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 522 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 522 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 522 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 522 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 522 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 71417000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 71417000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 71417000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 71417000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 71417000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 71417000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 564 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 564 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 564 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 564 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 564 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73366499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 73366499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73366499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 73366499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73366499 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 73366499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74238.045738 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74238.045738 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74238.045738 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74238.045738 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74238.045738 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74238.045738 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75948.756729 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75948.756729 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75948.756729 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75948.756729 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75948.756729 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75948.756729 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 1933800 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 31420.392793 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 9058700 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1963581 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 4.613357 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 28339083250 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14569.495652 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.490666 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16824.406475 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.444626 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000808 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.513440 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.958874 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 29781 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 975 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17306 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10757 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908844 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 107098594 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 107098594 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.data 6106335 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 6106335 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 3725127 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 3725127 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 1108456 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 1108456 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data 7214791 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 7214791 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data 7214791 # number of overall hits
-system.cpu.l2cache.overall_hits::total 7214791 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 962 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1190388 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1191350 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 775157 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 775157 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 962 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1965545 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 1966507 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 962 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1965545 # number of overall misses
-system.cpu.l2cache.overall_misses::total 1966507 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 70450000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 97815753000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 97886203000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63988346750 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 63988346750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 70450000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 161804099750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 161874549750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 70450000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 161804099750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 161874549750 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 7296723 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7297685 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 3725127 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 3725127 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883613 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1883613 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 9180336 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 9181298 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 9180336 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 9181298 # number of overall (read+write) accesses
+system.cpu.l2cache.tags.replacements 1934120 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 31423.856311 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 9061358 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 1963896 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 4.613970 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 28109033750 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14558.709173 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.630498 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 16838.516639 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.444297 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000813 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.513871 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.958980 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 973 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 595 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17352 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10703 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 107122416 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 107122416 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.data 6108093 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 6108093 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 3725797 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 3725797 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1108656 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1108656 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data 7216749 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 7216749 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data 7216749 # number of overall hits
+system.cpu.l2cache.overall_hits::total 7216749 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1190927 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1191893 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 774928 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 774928 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 966 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1965855 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 1966821 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 966 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1965855 # number of overall misses
+system.cpu.l2cache.overall_misses::total 1966821 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 72391000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 97891621750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 97964012750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63926223998 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 63926223998 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 72391000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 161817845748 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 161890236748 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 72391000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 161817845748 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 161890236748 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 7299020 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7299986 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3725797 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3725797 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883584 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1883584 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 9182604 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9183570 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 9182604 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9183570 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163140 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.163250 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411527 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.411527 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163163 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.163273 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411411 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.411411 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.214104 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.214186 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.214085 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.214167 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.214104 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.214186 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73232.848233 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82171.319771 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 82164.102069 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82548.885903 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82548.885903 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73232.848233 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82320.221491 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82315.776018 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73232.848233 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82320.221491 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82315.776018 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.214085 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.214167 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74938.923395 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82197.835594 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 82191.952424 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82493.114196 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82493.114196 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74938.923395 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82314.232610 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82310.610243 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74938.923395 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82314.232610 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82310.610243 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1019732 # number of writebacks
-system.cpu.l2cache.writebacks::total 1019732 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190388 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1191350 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775157 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 775157 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1965545 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 1966507 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1965545 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1966507 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58345500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 82892612500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82950958000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54245247750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54245247750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58345500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137137860250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 137196205750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58345500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137137860250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 137196205750 # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks 1019779 # number of writebacks
+system.cpu.l2cache.writebacks::total 1019779 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190927 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1191893 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 774928 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 774928 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1965855 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1966821 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1965855 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1966821 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 60233500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 82944620750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83004854250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54243912498 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54243912498 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 60233500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137188533248 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 137248766748 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 60233500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137188533248 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 137248766748 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163140 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163250 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411527 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411527 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163163 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163273 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411411 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411411 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.214186 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.214167 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.214186 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60650.207900 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69634.953057 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69627.697990 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69979.691533 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69979.691533 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60650.207900 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69770.908450 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69766.446674 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60650.207900 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69770.908450 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69766.446674 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214085 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.214167 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62353.519669 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69647.107463 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69641.196190 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69998.648259 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69998.648259 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62353.519669 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69785.682692 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69782.032401 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 9176240 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4087.503872 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 694248122 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9180336 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 75.623389 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 5175532250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4087.503872 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.997926 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.997926 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 9178508 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4087.552800 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 699314315 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9182604 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 76.156427 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 5143328250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4087.552800 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.997938 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.997938 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 694 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2982 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 416 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 755 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 2929 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1430846728 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1430846728 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 538710092 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 538710092 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 155538028 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 155538028 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 694248120 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 694248120 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 694248120 # number of overall hits
-system.cpu.dcache.overall_hits::total 694248120 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 11394599 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 11394599 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5190474 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5190474 # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses 1441348176 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1441348176 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 543788004 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 543788004 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 155526308 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 155526308 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data 699314312 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 699314312 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 699314312 # number of overall hits
+system.cpu.dcache.overall_hits::total 699314312 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 11566276 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 11566276 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5202194 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5202194 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 16585073 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 16585073 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 16585073 # number of overall misses
-system.cpu.dcache.overall_misses::total 16585073 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 331603001250 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 331603001250 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 288972510585 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 288972510585 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 129500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 620575511835 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 620575511835 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 620575511835 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 620575511835 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 550104691 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 550104691 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 16768470 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 16768470 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 16768470 # number of overall misses
+system.cpu.dcache.overall_misses::total 16768470 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 334833749250 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 334833749250 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 287624135124 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 287624135124 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 622457884374 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 622457884374 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 622457884374 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 622457884374 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 555354280 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 555354280 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 710833193 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 710833193 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 710833193 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 710833193 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032293 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032293 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.023332 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.023332 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.023332 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.023332 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29101.770168 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 29101.770168 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55673.626452 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55673.626452 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 129500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 129500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37417.713617 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37417.713617 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37417.713617 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37417.713617 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 11561530 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 8659652 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 743678 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.546419 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 132.949290 # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 716082782 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 716082782 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 716082782 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 716082782 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020827 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.020827 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032366 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.032366 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.023417 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.023417 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.023417 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.023417 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28949.140523 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28949.140523 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55289.005970 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55289.005970 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37120.732206 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37120.732206 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37120.732206 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 11998793 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 8384809 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 779484 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 65137 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.393251 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 128.725747 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3725127 # number of writebacks
-system.cpu.dcache.writebacks::total 3725127 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097867 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 4097867 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3306871 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3306871 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7404738 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7404738 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7404738 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7404738 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296732 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7296732 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883603 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1883603 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 3725797 # number of writebacks
+system.cpu.dcache.writebacks::total 3725797 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4267247 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 4267247 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3318620 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3318620 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7585867 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7585867 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7585867 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7585867 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7299029 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7299029 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883574 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1883574 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9180335 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9180335 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9180335 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9180335 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167014367250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 167014367250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77391574454 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 77391574454 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244405941704 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 244405941704 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244405941704 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 244405941704 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9182603 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9182603 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9182603 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9182603 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167129067750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 167129067750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77336919371 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 77336919371 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244465987121 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 244465987121 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244465987121 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 244465987121 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013143 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013143 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22888.927159 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22888.927159 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41086.988317 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41086.988317 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 127500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 127500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.769398 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.769398 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.769398 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.769398 # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.012823 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012823 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.012823 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22897.438515 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22897.438515 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41058.604213 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41058.604213 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.732914 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.732914 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:05:55
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:45:58
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5017340
+ 0: system.cpu.isa: ISA system set to: 0 0x5287000
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 533761922000 because target called exit()
+Exiting @ tick 523063504500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.528386 # Number of seconds simulated
-sim_ticks 528386107000 # Number of ticks simulated
-final_tick 528386107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.523064 # Number of seconds simulated
+sim_ticks 523063504500 # Number of ticks simulated
+final_tick 523063504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123376 # Simulator instruction rate (inst/s)
-host_op_rate 137635 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42206077 # Simulator tick rate (ticks/s)
-host_mem_usage 313484 # Number of bytes of host memory used
-host_seconds 12519.20 # Real time elapsed on the host
+host_inst_rate 149016 # Simulator instruction rate (inst/s)
+host_op_rate 166238 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50463882 # Simulator tick rate (ticks/s)
+host_mem_usage 261252 # Number of bytes of host memory used
+host_seconds 10365.11 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 47936 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 143742400 # Number of bytes read from this memory
-system.physmem.bytes_read::total 143790336 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 47936 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 47936 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70434560 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70434560 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 749 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2245975 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2246724 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1100540 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1100540 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 90722 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 272040461 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 272131182 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 90722 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 90722 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 133301310 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 133301310 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 133301310 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 90722 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 272040461 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 405432492 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2246724 # Number of read requests accepted
-system.physmem.writeReqs 1100540 # Number of write requests accepted
-system.physmem.readBursts 2246724 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1100540 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 143697408 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 92928 # Total number of bytes read from write queue
-system.physmem.bytesWritten 70433344 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 143790336 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 70434560 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1452 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 143764288 # Number of bytes read from this memory
+system.physmem.bytes_read::total 143812352 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 70447616 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70447616 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2246317 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2247068 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1100744 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1100744 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 91889 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 274850543 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 274942432 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 91889 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 91889 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 134682721 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 134682721 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 134682721 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 91889 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 274850543 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 409625153 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2247068 # Number of read requests accepted
+system.physmem.writeReqs 1100744 # Number of write requests accepted
+system.physmem.readBursts 2247068 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1100744 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 143722368 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 89984 # Total number of bytes read from write queue
+system.physmem.bytesWritten 70445760 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 143812352 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 70447616 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1406 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 139707 # Per bank write bursts
-system.physmem.perBankRdBursts::1 136292 # Per bank write bursts
-system.physmem.perBankRdBursts::2 133767 # Per bank write bursts
-system.physmem.perBankRdBursts::3 136231 # Per bank write bursts
-system.physmem.perBankRdBursts::4 134692 # Per bank write bursts
-system.physmem.perBankRdBursts::5 135454 # Per bank write bursts
-system.physmem.perBankRdBursts::6 136225 # Per bank write bursts
-system.physmem.perBankRdBursts::7 136115 # Per bank write bursts
-system.physmem.perBankRdBursts::8 143769 # Per bank write bursts
-system.physmem.perBankRdBursts::9 146465 # Per bank write bursts
-system.physmem.perBankRdBursts::10 144332 # Per bank write bursts
-system.physmem.perBankRdBursts::11 146005 # Per bank write bursts
-system.physmem.perBankRdBursts::12 145798 # Per bank write bursts
-system.physmem.perBankRdBursts::13 145907 # Per bank write bursts
-system.physmem.perBankRdBursts::14 142108 # Per bank write bursts
-system.physmem.perBankRdBursts::15 142405 # Per bank write bursts
-system.physmem.perBankWrBursts::0 69150 # Per bank write bursts
-system.physmem.perBankWrBursts::1 67464 # Per bank write bursts
-system.physmem.perBankWrBursts::2 65717 # Per bank write bursts
-system.physmem.perBankWrBursts::3 66314 # Per bank write bursts
-system.physmem.perBankWrBursts::4 66158 # Per bank write bursts
-system.physmem.perBankWrBursts::5 66498 # Per bank write bursts
-system.physmem.perBankWrBursts::6 67950 # Per bank write bursts
-system.physmem.perBankWrBursts::7 68767 # Per bank write bursts
-system.physmem.perBankWrBursts::8 70393 # Per bank write bursts
-system.physmem.perBankWrBursts::9 70943 # Per bank write bursts
-system.physmem.perBankWrBursts::10 70514 # Per bank write bursts
-system.physmem.perBankWrBursts::11 70857 # Per bank write bursts
-system.physmem.perBankWrBursts::12 70359 # Per bank write bursts
-system.physmem.perBankWrBursts::13 70734 # Per bank write bursts
-system.physmem.perBankWrBursts::14 69641 # Per bank write bursts
-system.physmem.perBankWrBursts::15 69062 # Per bank write bursts
+system.physmem.perBankRdBursts::0 139750 # Per bank write bursts
+system.physmem.perBankRdBursts::1 136144 # Per bank write bursts
+system.physmem.perBankRdBursts::2 133842 # Per bank write bursts
+system.physmem.perBankRdBursts::3 136111 # Per bank write bursts
+system.physmem.perBankRdBursts::4 134906 # Per bank write bursts
+system.physmem.perBankRdBursts::5 135203 # Per bank write bursts
+system.physmem.perBankRdBursts::6 136131 # Per bank write bursts
+system.physmem.perBankRdBursts::7 136315 # Per bank write bursts
+system.physmem.perBankRdBursts::8 143809 # Per bank write bursts
+system.physmem.perBankRdBursts::9 146590 # Per bank write bursts
+system.physmem.perBankRdBursts::10 144423 # Per bank write bursts
+system.physmem.perBankRdBursts::11 146169 # Per bank write bursts
+system.physmem.perBankRdBursts::12 145711 # Per bank write bursts
+system.physmem.perBankRdBursts::13 146127 # Per bank write bursts
+system.physmem.perBankRdBursts::14 142010 # Per bank write bursts
+system.physmem.perBankRdBursts::15 142421 # Per bank write bursts
+system.physmem.perBankWrBursts::0 69157 # Per bank write bursts
+system.physmem.perBankWrBursts::1 67395 # Per bank write bursts
+system.physmem.perBankWrBursts::2 65690 # Per bank write bursts
+system.physmem.perBankWrBursts::3 66283 # Per bank write bursts
+system.physmem.perBankWrBursts::4 66211 # Per bank write bursts
+system.physmem.perBankWrBursts::5 66391 # Per bank write bursts
+system.physmem.perBankWrBursts::6 67933 # Per bank write bursts
+system.physmem.perBankWrBursts::7 68845 # Per bank write bursts
+system.physmem.perBankWrBursts::8 70389 # Per bank write bursts
+system.physmem.perBankWrBursts::9 71029 # Per bank write bursts
+system.physmem.perBankWrBursts::10 70577 # Per bank write bursts
+system.physmem.perBankWrBursts::11 70974 # Per bank write bursts
+system.physmem.perBankWrBursts::12 70326 # Per bank write bursts
+system.physmem.perBankWrBursts::13 70796 # Per bank write bursts
+system.physmem.perBankWrBursts::14 69605 # Per bank write bursts
+system.physmem.perBankWrBursts::15 69114 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 528386038000 # Total gap between requests
+system.physmem.totGap 523063435500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 2246724 # Read request sizes (log2)
+system.physmem.readPktSize::6 2247068 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1100540 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1622160 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 446140 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 134185 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 42773 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1100744 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1615066 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 449330 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 137330 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 43923 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 24008 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 25689 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 49841 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 60617 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 65166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 66484 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 66755 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 66961 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 67037 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 67317 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 67353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 67677 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 68712 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 70133 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 67405 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 67796 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 66043 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 65172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 23358 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 24975 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 49534 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 60519 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 65129 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 66570 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 66892 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 67087 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 67424 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 67533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 67827 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 68851 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 70296 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 67618 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 68033 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 66306 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 65326 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 193 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 2026945 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 105.641008 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 82.595213 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 129.312456 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1568777 77.40% 77.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 317859 15.68% 93.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 67458 3.33% 96.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 23638 1.17% 97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 14371 0.71% 98.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6663 0.33% 98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4947 0.24% 98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3635 0.18% 99.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 19597 0.97% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 2026945 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 65065 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 34.467994 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 154.943879 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 65024 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 2025915 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 105.713545 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 82.619710 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 129.565498 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1567130 77.35% 77.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 318929 15.74% 93.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 67085 3.31% 96.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 23530 1.16% 97.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 13977 0.69% 98.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6837 0.34% 98.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5148 0.25% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3637 0.18% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 19642 0.97% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 2025915 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 65189 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 34.403642 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 148.850371 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 65147 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 65065 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 65065 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.914178 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.872771 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.215883 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 38677 59.44% 59.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1561 2.40% 61.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 18560 28.53% 90.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 4956 7.62% 97.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 979 1.50% 99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 233 0.36% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 49 0.08% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 12 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 5 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 7 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 65189 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 65189 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.884981 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.844479 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.202215 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 39520 60.62% 60.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1483 2.27% 62.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 18196 27.91% 90.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 4786 7.34% 98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 898 1.38% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 207 0.32% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 54 0.08% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 9 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 3 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 10 0.02% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 3 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 65065 # Writes before turning the bus around for reads
-system.physmem.totQLat 49926066500 # Total ticks spent queuing
-system.physmem.totMemAccLat 92024916500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 11226360000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 22236.09 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 65189 # Writes before turning the bus around for reads
+system.physmem.totQLat 50228413500 # Total ticks spent queuing
+system.physmem.totMemAccLat 92334576000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 11228310000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 22366.86 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 40986.09 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 271.96 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 133.30 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 272.13 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 133.30 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 41116.86 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 274.77 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 134.68 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 274.94 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 134.68 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.17 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.12 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.15 # Average write queue length when enqueuing
-system.physmem.readRowHits 904882 # Number of row buffer hits during reads
-system.physmem.writeRowHits 413955 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 40.30 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 37.61 # Row buffer hit rate for writes
-system.physmem.avgGap 157856.10 # Average gap between requests
-system.physmem.pageHitRate 39.42 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 96247983250 # Time in different power states
-system.physmem.memoryStateTime::REF 17643860000 # Time in different power states
+system.physmem.busUtil 3.20 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.15 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 1.05 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing
+system.physmem.readRowHits 905849 # Number of row buffer hits during reads
+system.physmem.writeRowHits 414601 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 40.34 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 37.67 # Row buffer hit rate for writes
+system.physmem.avgGap 156240.38 # Average gap between requests
+system.physmem.pageHitRate 39.46 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 94741058000 # Time in different power states
+system.physmem.memoryStateTime::REF 17466020000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 414492555250 # Time in different power states
+system.physmem.memoryStateTime::ACT 410854630500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 405432371 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 1420231 # Transaction distribution
-system.membus.trans_dist::ReadResp 1420230 # Transaction distribution
-system.membus.trans_dist::Writeback 1100540 # Transaction distribution
-system.membus.trans_dist::ReadExReq 826493 # Transaction distribution
-system.membus.trans_dist::ReadExResp 826493 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593987 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5593987 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214224832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 214224832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 214224832 # Total data (bytes)
+system.membus.throughput 409625031 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1419612 # Transaction distribution
+system.membus.trans_dist::ReadResp 1419611 # Transaction distribution
+system.membus.trans_dist::Writeback 1100744 # Transaction distribution
+system.membus.trans_dist::ReadExReq 827456 # Transaction distribution
+system.membus.trans_dist::ReadExResp 827456 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5594879 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5594879 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214259904 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 214259904 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 214259904 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 12921710000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
-system.membus.respLayer1.occupancy 21064187250 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 12872956000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 21034966500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 4.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 303120066 # Number of BP lookups
-system.cpu.branchPred.condPredicted 249328718 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15217036 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 172898211 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 161402010 # Number of BTB hits
+system.cpu.branchPred.lookups 310041872 # Number of BP lookups
+system.cpu.branchPred.condPredicted 254951905 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15242132 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 177250182 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 164623168 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.350885 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 17552010 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 92.876163 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 17905906 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1056772215 # number of cpu cycles simulated
+system.cpu.numCycles 1046127010 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 298543809 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2186558852 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 303120066 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 178954020 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 435169965 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 87664150 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 162830797 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 66 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 289028116 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5928471 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 966231390 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.503805 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.207339 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 304406506 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2237155990 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 310041872 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 182529074 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 444747763 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 93800973 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 104367517 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 295060555 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6266924 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 929205544 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.663579 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.245143 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 531061564 54.96% 54.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25270109 2.62% 57.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 39059321 4.04% 61.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 48280752 5.00% 66.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 43652123 4.52% 71.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46384495 4.80% 75.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38400203 3.97% 79.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18890593 1.96% 81.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 175232230 18.14% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 484458019 52.14% 52.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25667204 2.76% 54.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 39962445 4.30% 59.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 49351933 5.31% 64.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 44527866 4.79% 69.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 47023403 5.06% 74.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 39036338 4.20% 78.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 19508250 2.10% 80.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 179670086 19.34% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 966231390 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.286836 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.069092 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 330688304 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 140707592 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 404837901 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20311495 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 69686098 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46045464 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2366336890 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2408 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 69686098 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 354035761 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 69333450 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19564 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 400161334 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 72995183 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2304279831 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 149122 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5007808 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 60068670 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 28 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2280029311 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10640069170 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 9754807461 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 523 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 929205544 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.296371 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.138513 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 323230837 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95973570 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 424273226 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 10044892 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 75683019 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46957126 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 712 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2419092576 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2470 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 75683019 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 338590369 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36235131 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 20070 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 418478079 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 60198876 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2357219159 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 486871 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 10439342 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 39865193 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 9487400 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 108 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2332621614 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10887738442 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 9980989966 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 478 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 573709381 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 838 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 160867468 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 624344109 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 220690096 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 85895596 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 71104649 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2201067148 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 872 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2018188753 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 4009836 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 473419118 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1122820623 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 702 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 966231390 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.088722 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.905985 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 626301684 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1665 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1662 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 62763220 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 637377073 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 224726985 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 97022139 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 86012676 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2244793752 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1629 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2031991177 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 6410093 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 517307509 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1273036014 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 929205544 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.186805 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.944442 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 283676122 29.36% 29.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 153451692 15.88% 45.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 160814353 16.64% 61.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 120202627 12.44% 74.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 123594762 12.79% 87.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 73761984 7.63% 94.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 38320993 3.97% 98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 9885308 1.02% 99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2523549 0.26% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 266904218 28.72% 28.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 128322549 13.81% 42.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 158977129 17.11% 59.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 117185502 12.61% 72.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 128428514 13.82% 86.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 72785870 7.83% 93.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 42669642 4.59% 98.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10960354 1.18% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2971766 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 966231390 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 929205544 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 893685 3.74% 3.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5601 0.02% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 18261914 76.52% 80.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4703701 19.71% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1285844 5.85% 5.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5675 0.03% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 18368199 83.62% 89.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2306433 10.50% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1236629707 61.27% 61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 925874 0.05% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 25 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 11 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 587570237 29.11% 90.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193062842 9.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1245462856 61.29% 61.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 947392 0.05% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 9 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 592199391 29.14% 90.48% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193381454 9.52% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2018188753 # Type of FU issued
-system.cpu.iq.rate 1.909767 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 23864901 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011825 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5030483281 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2674676202 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1957157350 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 352 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 748 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 2031991177 # Type of FU issued
+system.cpu.iq.rate 1.942394 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 21966151 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010810 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5021563817 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2762296727 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1969035141 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 660 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 139 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2042053478 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 64607819 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 2053957167 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 66315008 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 138417340 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 267938 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 192339 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 45843051 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 151450304 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 182572 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 197144 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 49879940 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4440345 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4648682 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 69686098 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 32530520 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1603302 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2201068109 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 7883109 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 624344109 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 220690096 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 810 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 479479 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 96880 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 192339 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8149711 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 9614325 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 17764036 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1987581145 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 573715440 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 30607608 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 75683019 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 13889446 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 17402817 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2244795480 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 7970371 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 637377073 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 224726985 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1567 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 551835 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 16641279 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 197144 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8164855 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 9718586 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 17883441 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2000301565 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 577561658 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 31689612 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 89 # number of nop insts executed
-system.cpu.iew.exec_refs 763896054 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238343533 # Number of branches executed
-system.cpu.iew.exec_stores 190180614 # Number of stores executed
-system.cpu.iew.exec_rate 1.880804 # Inst execution rate
-system.cpu.iew.wb_sent 1965589817 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1957157489 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1295200215 # num instructions producing a value
-system.cpu.iew.wb_consumers 2058841803 # num instructions consuming a value
+system.cpu.iew.exec_nop 99 # number of nop insts executed
+system.cpu.iew.exec_refs 768256899 # number of memory reference insts executed
+system.cpu.iew.exec_branches 239583236 # Number of branches executed
+system.cpu.iew.exec_stores 190695241 # Number of stores executed
+system.cpu.iew.exec_rate 1.912102 # Inst execution rate
+system.cpu.iew.wb_sent 1977910575 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1969035280 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1321133911 # num instructions producing a value
+system.cpu.iew.wb_consumers 2129107129 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.852015 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.629092 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.882214 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.620511 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 478093326 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 522107871 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15216382 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 896545292 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.921904 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.720119 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 15241473 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 853522525 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.018780 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.777115 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 407981027 45.51% 45.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 193272762 21.56% 67.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 72814151 8.12% 75.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35242500 3.93% 79.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18951832 2.11% 81.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30763398 3.43% 84.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19961065 2.23% 86.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11413875 1.27% 88.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106144682 11.84% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 375117315 43.95% 43.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 185477330 21.73% 65.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 70116011 8.21% 73.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 33059312 3.87% 77.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 18836055 2.21% 79.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 30683416 3.59% 83.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 20461939 2.40% 85.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11515545 1.35% 87.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 108255602 12.68% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 896545292 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 853522525 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1723073853 # Class of committed instruction
-system.cpu.commit.bw_lim_events 106144682 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 108255602 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2991567190 # The number of ROB reads
-system.cpu.rob.rob_writes 4472170576 # The number of ROB writes
-system.cpu.timesIdled 1153872 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 90540825 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2990448048 # The number of ROB reads
+system.cpu.rob.rob_writes 4566229463 # The number of ROB writes
+system.cpu.timesIdled 1335234 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 116921466 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.684188 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.684188 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.461586 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.461586 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 9954183829 # number of integer regfile reads
-system.cpu.int_regfile_writes 1937102211 # number of integer regfile writes
-system.cpu.fp_regfile_reads 137 # number of floating regfile reads
-system.cpu.fp_regfile_writes 142 # number of floating regfile writes
-system.cpu.misc_regfile_reads 737626428 # number of misc regfile reads
+system.cpu.cpi 0.677296 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.677296 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.476458 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.476458 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 10016037678 # number of integer regfile reads
+system.cpu.int_regfile_writes 1949973157 # number of integer regfile writes
+system.cpu.fp_regfile_reads 144 # number of floating regfile reads
+system.cpu.fp_regfile_writes 144 # number of floating regfile writes
+system.cpu.misc_regfile_reads 741547581 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1621046225 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 7708753 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7708752 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 3781180 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1893479 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1893479 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1556 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984087 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 22985643 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856488512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 856538304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 856538304 # Total data (bytes)
+system.cpu.toL2Bus.throughput 1637500473 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7708273 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7708272 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 3780671 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1894131 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1894131 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22983914 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 22985478 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856466688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 856516736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 10473041845 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 10472370339 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1300248 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1301749 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14753489741 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 14750464244 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%)
-system.cpu.icache.tags.replacements 20 # number of replacements
-system.cpu.icache.tags.tagsinuse 629.404083 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 289026911 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 778 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 371499.885604 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 21 # number of replacements
+system.cpu.icache.tags.tagsinuse 633.135504 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 295059337 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 377313.730179 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 629.404083 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.307326 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.307326 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 758 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 633.135504 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.309148 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.309148 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 761 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.370117 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 578057010 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 578057010 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 289026911 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 289026911 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 289026911 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 289026911 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 289026911 # number of overall hits
-system.cpu.icache.overall_hits::total 289026911 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses
-system.cpu.icache.overall_misses::total 1205 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 80982998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 80982998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 80982998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 80982998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 80982998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 80982998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 289028116 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 289028116 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 289028116 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 289028116 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 289028116 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 289028116 # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4 732 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.371582 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 590121892 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 590121892 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 295059337 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 295059337 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 295059337 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 295059337 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 295059337 # number of overall hits
+system.cpu.icache.overall_hits::total 295059337 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1218 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1218 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1218 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1218 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1218 # number of overall misses
+system.cpu.icache.overall_misses::total 1218 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 82722999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 82722999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 82722999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 82722999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 82722999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 82722999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 295060555 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 295060555 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 295060555 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 295060555 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 295060555 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 295060555 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67205.807469 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67205.807469 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67205.807469 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67205.807469 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67205.807469 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67205.807469 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67917.076355 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67917.076355 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67917.076355 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67917.076355 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67917.076355 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 48.666667 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 427 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 427 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 427 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 427 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 427 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 427 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55589252 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 55589252 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55589252 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 55589252 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55589252 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 55589252 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55396751 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 55396751 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55396751 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 55396751 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55396751 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 55396751 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71451.480720 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71451.480720 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71451.480720 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71451.480720 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71451.480720 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71451.480720 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70839.835038 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70839.835038 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70839.835038 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70839.835038 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70839.835038 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70839.835038 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 2214034 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 31529.362843 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 9245387 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 2243807 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 4.120402 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 21611639250 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14288.917834 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.667187 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 17219.777822 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.436063 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000631 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.525506 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.962200 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 29773 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1894 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23771 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3939 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908600 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 111204582 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 111204582 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 6288484 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 6288511 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 3781180 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 3781180 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 1066986 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 1066986 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 7355470 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 7355497 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 7355470 # number of overall hits
-system.cpu.l2cache.overall_hits::total 7355497 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 751 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1419491 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 1420242 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 826493 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 826493 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 751 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 2245984 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 2246735 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 751 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 2245984 # number of overall misses
-system.cpu.l2cache.overall_misses::total 2246735 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 54536250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 119001772500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 119056308750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70780259250 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 70780259250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 54536250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 189782031750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 189836568000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 54536250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 189782031750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 189836568000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 7707975 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7708753 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 3781180 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 3781180 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893479 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1893479 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 9601454 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 9602232 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 9601454 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 9602232 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965296 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184159 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.184238 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436494 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.436494 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965296 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.233921 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.233980 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965296 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.233921 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.233980 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72618.175766 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83834.115539 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 83828.184739 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85639.272504 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85639.272504 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72618.175766 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84498.389904 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 84494.418790 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72618.175766 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84498.389904 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 84494.418790 # average overall miss latency
+system.cpu.l2cache.tags.replacements 2214381 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 31528.028759 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 9244052 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 2244157 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 4.119165 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 21499673750 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14271.586690 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.657217 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 17235.784852 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.435534 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000630 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.525994 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.962159 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1924 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23845 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3832 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 111202888 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 111202888 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 6288624 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 6288654 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 3780671 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 3780671 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1066675 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1066675 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 7355299 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 7355329 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 7355299 # number of overall hits
+system.cpu.l2cache.overall_hits::total 7355329 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 752 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1418867 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1419619 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 827456 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 827456 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 752 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 2246323 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 2247075 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 752 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 2246323 # number of overall misses
+system.cpu.l2cache.overall_misses::total 2247075 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 54308250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 119156229500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 119210537750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70981342750 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 70981342750 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 54308250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 190137572250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 190191880500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 54308250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 190137572250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 190191880500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 782 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 7707491 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7708273 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 3780671 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3780671 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894131 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1894131 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 782 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 9601622 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 9602404 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 782 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 9601622 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 9602404 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961637 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184089 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.184168 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436853 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.436853 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961637 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.233952 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.234012 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961637 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.233952 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.234012 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72218.417553 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83979.844129 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 83973.613871 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85782.618955 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85782.618955 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72218.417553 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84643.914633 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 84639.756350 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72218.417553 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84643.914633 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 84639.756350 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1100540 # number of writebacks
-system.cpu.l2cache.writebacks::total 1100540 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 749 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419482 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1420231 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826493 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 826493 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 749 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2245975 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 2246724 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 749 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2245975 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 2246724 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44958250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101218844750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101263803000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60411500250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60411500250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44958250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 161630345000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 161675303250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44958250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 161630345000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 161675303250 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962725 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184158 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184236 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436494 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436494 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962725 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233920 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.233979 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962725 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233920 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.233979 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60024.365821 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71306.888534 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71300.938368 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73093.783311 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73093.783311 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60024.365821 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71964.445285 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71960.464770 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60024.365821 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71964.445285 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71960.464770 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 1100744 # number of writebacks
+system.cpu.l2cache.writebacks::total 1100744 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418861 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1419612 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 827456 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 827456 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2246317 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2247068 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2246317 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2247068 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44796750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 101386052500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 101430849250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60631607750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60631607750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44796750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162017660250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 162062457000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44796750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162017660250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 162062457000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184089 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184167 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436853 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436853 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.234011 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960358 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233952 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.234011 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59649.467377 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71455.944240 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71449.698404 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73274.721254 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73274.721254 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59649.467377 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72125.911102 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72121.741309 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 9597357 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4087.971590 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 656031329 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9601453 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 68.326255 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 3540268250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4087.971590 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.998040 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.998040 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 9597525 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4087.935639 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 657806876 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9601621 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 68.509981 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 3523864250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4087.935639 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.998031 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 640 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2362 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 1093 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 660 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 2418 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1355949467 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1355949467 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 489075849 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 489075849 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 166955354 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 166955354 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses 1359744661 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1359744661 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 490891096 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 490891096 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 166915657 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 166915657 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 656031203 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 656031203 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 656031203 # number of overall hits
-system.cpu.dcache.overall_hits::total 656031203 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 11511982 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 11511982 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5630693 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5630693 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 657806753 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 657806753 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 657806753 # number of overall hits
+system.cpu.dcache.overall_hits::total 657806753 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 11594251 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 11594251 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5670390 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5670390 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 17142675 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 17142675 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 17142675 # number of overall misses
-system.cpu.dcache.overall_misses::total 17142675 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 350608925483 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 350608925483 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 296498774019 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 296498774019 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 225500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 647107699502 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 647107699502 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 647107699502 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 647107699502 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 500587831 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 500587831 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 17264641 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 17264641 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 17264641 # number of overall misses
+system.cpu.dcache.overall_misses::total 17264641 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 353287122740 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 353287122740 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 298200381062 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 298200381062 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 243250 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 243250 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 651487503802 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 651487503802 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 651487503802 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 651487503802 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 502485347 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 502485347 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 673173878 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 673173878 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 673173878 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 673173878 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022997 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.022997 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032625 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032625 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025465 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025465 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025465 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025465 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30456.000147 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30456.000147 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52657.598988 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52657.598988 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37748.350214 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37748.350214 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37748.350214 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37748.350214 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 22019527 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 3996591 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1208409 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.221916 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 61.361405 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 675071394 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 675071394 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 675071394 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 675071394 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023074 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.023074 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032855 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.032855 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025575 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025575 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025575 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025575 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30470.887920 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30470.887920 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52589.042564 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52589.042564 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 81083.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 81083.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37735.363498 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37735.363498 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37735.363498 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 22798709 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 4000734 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1307566 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.435991 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 61.425957 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3781180 # number of writebacks
-system.cpu.dcache.writebacks::total 3781180 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3804007 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3804007 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3737214 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3737214 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 3780671 # number of writebacks
+system.cpu.dcache.writebacks::total 3780671 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3886759 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3886759 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3776260 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3776260 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7541221 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7541221 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7541221 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7541221 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707975 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7707975 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893479 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1893479 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9601454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9601454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9601454 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9601454 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191480901509 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 191480901509 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83841557570 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 83841557570 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275322459079 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 275322459079 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275322459079 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 275322459079 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015398 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015398 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24841.920415 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24841.920415 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44279.106116 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44279.106116 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28675.079741 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28675.079741 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28675.079741 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28675.079741 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 7663019 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7663019 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7663019 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7663019 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707492 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7707492 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894130 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1894130 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9601622 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9601622 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9601622 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9601622 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 191674058756 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 191674058756 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84036609462 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 84036609462 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 275710668218 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 275710668218 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 275710668218 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 275710668218 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015339 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015339 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24868.538139 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24868.538139 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.864715 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.864715 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28715.009633 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28715.009633 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:15:16
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 12:55:52
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 23461709500 because target called exit()
+122 123 124 Exiting @ tick 23058360500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023496 # Number of seconds simulated
-sim_ticks 23495860500 # Number of ticks simulated
-final_tick 23495860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.023058 # Number of seconds simulated
+sim_ticks 23058360500 # Number of ticks simulated
+final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 162171 # Simulator instruction rate (inst/s)
-host_op_rate 162171 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45264552 # Simulator tick rate (ticks/s)
-host_mem_usage 273204 # Number of bytes of host memory used
-host_seconds 519.08 # Real time elapsed on the host
+host_inst_rate 185322 # Simulator instruction rate (inst/s)
+host_op_rate 185322 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50763012 # Simulator tick rate (ticks/s)
+host_mem_usage 226392 # Number of bytes of host memory used
+host_seconds 454.24 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 196416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory
-system.physmem.bytes_read::total 334528 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 334848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 196416 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 196416 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3069 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8345981 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 5891761 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14237742 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8345981 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8345981 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8345981 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5891761 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 14237742 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5227 # Number of read requests accepted
+system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 8518212 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 6003549 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14521761 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 8518212 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 8518212 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 8518212 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 6003549 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 14521761 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5232 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 469 # Per bank write bursts
+system.physmem.perBankRdBursts::0 471 # Per bank write bursts
system.physmem.perBankRdBursts::1 291 # Per bank write bursts
system.physmem.perBankRdBursts::2 302 # Per bank write bursts
system.physmem.perBankRdBursts::3 524 # Per bank write bursts
system.physmem.perBankRdBursts::4 220 # Per bank write bursts
-system.physmem.perBankRdBursts::5 226 # Per bank write bursts
-system.physmem.perBankRdBursts::6 220 # Per bank write bursts
-system.physmem.perBankRdBursts::7 285 # Per bank write bursts
-system.physmem.perBankRdBursts::8 236 # Per bank write bursts
-system.physmem.perBankRdBursts::9 280 # Per bank write bursts
+system.physmem.perBankRdBursts::5 225 # Per bank write bursts
+system.physmem.perBankRdBursts::6 219 # Per bank write bursts
+system.physmem.perBankRdBursts::7 286 # Per bank write bursts
+system.physmem.perBankRdBursts::8 240 # Per bank write bursts
+system.physmem.perBankRdBursts::9 278 # Per bank write bursts
system.physmem.perBankRdBursts::10 248 # Per bank write bursts
-system.physmem.perBankRdBursts::11 254 # Per bank write bursts
+system.physmem.perBankRdBursts::11 253 # Per bank write bursts
system.physmem.perBankRdBursts::12 398 # Per bank write bursts
-system.physmem.perBankRdBursts::13 336 # Per bank write bursts
+system.physmem.perBankRdBursts::13 338 # Per bank write bursts
system.physmem.perBankRdBursts::14 491 # Per bank write bursts
-system.physmem.perBankRdBursts::15 447 # Per bank write bursts
+system.physmem.perBankRdBursts::15 448 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 23495733500 # Total gap between requests
+system.physmem.totGap 23058233500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 5227 # Read request sizes (log2)
+system.physmem.readPktSize::6 5232 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1191 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3262 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 633 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 867 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 383.188005 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 230.923786 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 354.572905 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 252 29.07% 29.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 197 22.72% 51.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 79 9.11% 60.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 57 6.57% 67.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 42 4.84% 72.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 41 4.73% 77.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 51 5.88% 82.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 24 2.77% 85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 124 14.30% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 867 # Bytes accessed per row activation
-system.physmem.totQLat 41053500 # Total ticks spent queuing
-system.physmem.totMemAccLat 139059750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7854.12 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 871 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 381.722158 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 229.044875 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 356.837953 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 257 29.51% 29.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 194 22.27% 51.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 84 9.64% 61.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 65 7.46% 68.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 35 4.02% 72.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 36 4.13% 77.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 31 3.56% 80.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 43 4.94% 85.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 126 14.47% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 871 # Bytes accessed per row activation
+system.physmem.totQLat 38517250 # Total ticks spent queuing
+system.physmem.totMemAccLat 136617250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 7361.86 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26604.12 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 14.24 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26111.86 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 14.52 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 14.24 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 14.52 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.11 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4351 # Number of row buffer hits during reads
+system.physmem.readRowHits 4353 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.24 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 4495070.50 # Average gap between requests
-system.physmem.pageHitRate 83.24 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 21787630000 # Time in different power states
-system.physmem.memoryStateTime::REF 784420000 # Time in different power states
+system.physmem.avgGap 4407154.72 # Average gap between requests
+system.physmem.pageHitRate 83.20 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 21416461750 # Time in different power states
+system.physmem.memoryStateTime::REF 769860000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 919340000 # Time in different power states
+system.physmem.memoryStateTime::ACT 869038750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 14237742 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 3522 # Transaction distribution
-system.membus.trans_dist::ReadResp 3522 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1705 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1705 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 334528 # Total data (bytes)
+system.membus.throughput 14521761 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3525 # Transaction distribution
+system.membus.trans_dist::ReadResp 3525 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1707 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1707 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 334848 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 6755000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 6496500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 48973500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 48985000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 14867597 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10786733 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 927657 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8507235 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6975722 # Number of BTB hits
+system.cpu.branchPred.lookups 15361032 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11166301 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 940671 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8650721 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7195754 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.997523 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1468896 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 3134 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 83.180974 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1505004 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3205 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 23141508 # DTB read hits
-system.cpu.dtb.read_misses 194908 # DTB read misses
-system.cpu.dtb.read_acv 2 # DTB read access violations
-system.cpu.dtb.read_accesses 23336416 # DTB read accesses
-system.cpu.dtb.write_hits 7073051 # DTB write hits
-system.cpu.dtb.write_misses 1111 # DTB write misses
-system.cpu.dtb.write_acv 1 # DTB write access violations
-system.cpu.dtb.write_accesses 7074162 # DTB write accesses
-system.cpu.dtb.data_hits 30214559 # DTB hits
-system.cpu.dtb.data_misses 196019 # DTB misses
-system.cpu.dtb.data_acv 3 # DTB access violations
-system.cpu.dtb.data_accesses 30410578 # DTB accesses
-system.cpu.itb.fetch_hits 14761442 # ITB hits
-system.cpu.itb.fetch_misses 106 # ITB misses
+system.cpu.dtb.read_hits 23573955 # DTB read hits
+system.cpu.dtb.read_misses 207074 # DTB read misses
+system.cpu.dtb.read_acv 4 # DTB read access violations
+system.cpu.dtb.read_accesses 23781029 # DTB read accesses
+system.cpu.dtb.write_hits 7120317 # DTB write hits
+system.cpu.dtb.write_misses 1134 # DTB write misses
+system.cpu.dtb.write_acv 4 # DTB write access violations
+system.cpu.dtb.write_accesses 7121451 # DTB write accesses
+system.cpu.dtb.data_hits 30694272 # DTB hits
+system.cpu.dtb.data_misses 208208 # DTB misses
+system.cpu.dtb.data_acv 8 # DTB access violations
+system.cpu.dtb.data_accesses 30902480 # DTB accesses
+system.cpu.itb.fetch_hits 15234213 # ITB hits
+system.cpu.itb.fetch_misses 102 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 14761548 # ITB accesses
+system.cpu.itb.fetch_accesses 15234315 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 46991722 # number of cpu cycles simulated
+system.cpu.numCycles 46116722 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15493602 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127144789 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14867597 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 8444618 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22164191 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4494518 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 5543985 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2326 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 15940932 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 131589057 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15361032 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 8700758 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22892353 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5007718 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2994752 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2134 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 14761442 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 326314 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46736650 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.720451 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.375825 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 15234213 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 364576 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 45860852 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.869311 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.407633 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24572459 52.58% 52.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2364267 5.06% 57.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1190852 2.55% 60.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1750659 3.75% 63.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2760354 5.91% 69.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1155374 2.47% 72.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1219764 2.61% 74.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 773397 1.65% 76.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10949524 23.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 22968499 50.08% 50.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2435887 5.31% 55.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1214898 2.65% 58.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1783514 3.89% 61.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2844070 6.20% 68.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1193047 2.60% 70.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1264346 2.76% 73.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 807487 1.76% 75.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 11349104 24.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46736650 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.316388 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.705685 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17320813 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4244089 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20558459 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1092640 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3520649 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2518881 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12242 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 124135665 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 32164 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3520649 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18467014 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 956444 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7682 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 20482522 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 3302339 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 121292511 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 405307 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2418029 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 89077183 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 157604141 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 150534696 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 7069444 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 45860852 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.333090 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.853391 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16942268 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2554020 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 21969696 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 376134 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4018734 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2597948 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12434 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 128314772 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 36360 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4018734 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 17696753 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 830389 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 7936 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21575239 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1731801 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 125347310 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 9609 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 982853 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 675750 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 22720 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 92019426 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 162776933 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 155390791 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 7386141 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 20649822 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 718 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 707 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 8775432 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 25394818 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 8253633 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2570331 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 907077 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 105549830 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2075 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 96657653 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 179218 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 20902238 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 15662437 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1686 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46736650 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.068134 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.876130 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 23592065 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 733 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 3333773 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26203423 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 8541215 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2901793 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1268500 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 108868755 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1841 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 97966771 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 305092 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 24205687 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 18927840 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1452 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 45860852 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.136174 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.932064 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 12165151 26.03% 26.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 9350062 20.01% 46.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8404811 17.98% 64.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6298333 13.48% 77.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4922419 10.53% 88.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2869013 6.14% 94.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1725015 3.69% 97.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 796629 1.70% 99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 205217 0.44% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 12004778 26.18% 26.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 8735781 19.05% 45.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7795942 17.00% 62.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6187579 13.49% 75.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4939987 10.77% 86.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3238381 7.06% 93.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1831298 3.99% 97.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 880120 1.92% 99.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 246986 0.54% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46736650 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 45860852 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 189767 12.10% 12.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 12.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 12.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 186 0.01% 12.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 7209 0.46% 12.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 5897 0.38% 12.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 843167 53.74% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 445094 28.37% 95.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 77619 4.95% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 202355 11.05% 11.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 107 0.01% 11.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 8618 0.47% 11.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 9498 0.52% 12.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 955023 52.14% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 532552 29.07% 93.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 123630 6.75% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58783696 60.82% 60.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 479813 0.50% 61.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2802274 2.90% 64.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 115457 0.12% 64.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2387860 2.47% 66.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 311147 0.32% 67.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 760157 0.79% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 23859982 24.69% 92.60% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 7156941 7.40% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 59518834 60.75% 60.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 484423 0.49% 61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2816502 2.87% 64.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 115449 0.12% 64.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2407923 2.46% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 312382 0.32% 67.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 763359 0.78% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 24335343 24.84% 92.64% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 7212230 7.36% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 96657653 # Type of FU issued
-system.cpu.iq.rate 2.056908 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1568939 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 226667825 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 117702286 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87133167 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15132288 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 8786528 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 7070448 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 90230128 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7996457 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1520956 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 97966771 # Type of FU issued
+system.cpu.iq.rate 2.124322 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1831783 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 228533724 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 123769088 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 88239146 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 15397545 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 9344200 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 7119957 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 91612691 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 8185856 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1667830 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5398620 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 18484 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 34785 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1752530 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6207225 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 16318 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 37199 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2040112 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 10530 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 2127 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 40236 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 2728 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3520649 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 133897 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 18217 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 115793083 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 374761 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 25394818 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 8253633 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2932 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 43 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 34785 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 541104 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 495336 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1036440 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 95417746 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 23336859 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1239907 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4018734 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 14986 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 580703 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 119442937 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 327587 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 26203423 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 8541215 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 22416 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 558101 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 37199 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 549687 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 504581 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1054268 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 96742235 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 23781507 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1224536 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 10241178 # number of nop insts executed
-system.cpu.iew.exec_refs 30411225 # number of memory reference insts executed
-system.cpu.iew.exec_branches 12030179 # Number of branches executed
-system.cpu.iew.exec_stores 7074366 # Number of stores executed
-system.cpu.iew.exec_rate 2.030522 # Inst execution rate
-system.cpu.iew.wb_sent 94727613 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 94203615 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 64511907 # num instructions producing a value
-system.cpu.iew.wb_consumers 89904657 # num instructions consuming a value
+system.cpu.iew.exec_nop 10572341 # number of nop insts executed
+system.cpu.iew.exec_refs 30903185 # number of memory reference insts executed
+system.cpu.iew.exec_branches 12219901 # Number of branches executed
+system.cpu.iew.exec_stores 7121678 # Number of stores executed
+system.cpu.iew.exec_rate 2.097769 # Inst execution rate
+system.cpu.iew.wb_sent 95961828 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 95359103 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 65705546 # num instructions producing a value
+system.cpu.iew.wb_consumers 92226364 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.004685 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.717559 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.067777 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.712438 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 23891142 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 27540320 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 915882 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 43216001 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.126598 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.743951 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 928822 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 41842118 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.196425 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.812600 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 16755601 38.77% 38.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 9919008 22.95% 61.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4484606 10.38% 72.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2269127 5.25% 77.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1610437 3.73% 81.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1128955 2.61% 83.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 722092 1.67% 85.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 821021 1.90% 87.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5505154 12.74% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 16239554 38.81% 38.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 9401519 22.47% 61.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4137637 9.89% 71.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2136234 5.11% 76.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1534088 3.67% 79.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1088589 2.60% 82.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 699410 1.67% 84.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 798893 1.91% 86.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5806194 13.88% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 43216001 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 41842118 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5505154 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5806194 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 153504004 # The number of ROB reads
-system.cpu.rob.rob_writes 235133069 # The number of ROB writes
-system.cpu.timesIdled 5418 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 255072 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 155478259 # The number of ROB reads
+system.cpu.rob.rob_writes 242937786 # The number of ROB writes
+system.cpu.timesIdled 5286 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 255870 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.558231 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.558231 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.791373 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.791373 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 129151691 # number of integer regfile reads
-system.cpu.int_regfile_writes 70572840 # number of integer regfile writes
-system.cpu.fp_regfile_reads 6193374 # number of floating regfile reads
-system.cpu.fp_regfile_writes 6052358 # number of floating regfile writes
-system.cpu.misc_regfile_reads 714605 # number of misc regfile reads
+system.cpu.cpi 0.547837 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 130779467 # number of integer regfile reads
+system.cpu.int_regfile_writes 71543363 # number of integer regfile writes
+system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads
+system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes
+system.cpu.misc_regfile_reads 718857 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 37684936 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 11995 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 11995 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22964 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4597 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 27561 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734848 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 885440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 885440 # Total data (bytes)
+system.cpu.toL2Bus.throughput 37986395 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 11847 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 11847 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1732 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1732 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22674 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4591 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 27265 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 875904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 875904 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 7026500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 17802750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 17583000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3545000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3542750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 9548 # number of replacements
-system.cpu.icache.tags.tagsinuse 1597.278061 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 14747183 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 11482 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1284.374064 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 9401 # number of replacements
+system.cpu.icache.tags.tagsinuse 1598.407560 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 15220036 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 11337 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1342.510011 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1597.278061 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.779921 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.779921 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 29534364 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 29534364 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 14747183 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 14747183 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 14747183 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 14747183 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 14747183 # number of overall hits
-system.cpu.icache.overall_hits::total 14747183 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 14258 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 14258 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 14258 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 14258 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 14258 # number of overall misses
-system.cpu.icache.overall_misses::total 14258 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 414157250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 414157250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 414157250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 414157250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 414157250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 414157250 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 14761441 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 14761441 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 14761441 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 14761441 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 14761441 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 14761441 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000966 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000966 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000966 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000966 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000966 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000966 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29047.359377 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29047.359377 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29047.359377 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29047.359377 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1598.407560 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.780472 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.780472 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 931 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 30479761 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 30479761 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 15220036 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 15220036 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 15220036 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 15220036 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 15220036 # number of overall hits
+system.cpu.icache.overall_hits::total 15220036 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 14176 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 14176 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 14176 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 14176 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 14176 # number of overall misses
+system.cpu.icache.overall_misses::total 14176 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 411369250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 411369250 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 411369250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 411369250 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 411369250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 411369250 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 15234212 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 15234212 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 15234212 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 15234212 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 15234212 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 15234212 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000931 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000931 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000931 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000931 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000931 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000931 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29018.711202 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 29018.711202 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 29018.711202 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 29018.711202 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 61.600000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2776 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2776 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2776 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2776 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2776 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2776 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11482 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 11482 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 11482 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 11482 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 11482 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 11482 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306274750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 306274750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306274750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 306274750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306274750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 306274750 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000778 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000778 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000778 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26674.338094 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26674.338094 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2839 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2839 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2839 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2839 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2839 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2839 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11337 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 11337 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 11337 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 11337 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 11337 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 11337 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302662500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 302662500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302662500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 302662500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302662500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 302662500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000744 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000744 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000744 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26696.877481 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26696.877481 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 2409.001155 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 8488 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 2.365004 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 2409.556828 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 8337 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 2.321637 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 17.673690 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.868133 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 379.459331 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061397 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.073517 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 17.688406 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2013.956930 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 377.911492 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061461 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.011533 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.073534 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 116000 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 116000 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 8418 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 8473 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 8418 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 8499 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 8418 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits
-system.cpu.l2cache.overall_hits::total 8499 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3064 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 3522 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 1705 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 1705 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3064 # number of demand (read+write) misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109589 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 114811 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 114811 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 8268 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 8322 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 8268 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 8347 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 8268 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
+system.cpu.l2cache.overall_hits::total 8347 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3069 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 456 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 3525 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 1707 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 1707 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3069 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2163 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 5227 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3064 # number of overall misses
+system.cpu.l2cache.demand_misses::total 5232 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3069 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2163 # number of overall misses
-system.cpu.l2cache.overall_misses::total 5227 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210607000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35793000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 246400000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122677500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 122677500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 210607000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 158470500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 369077500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 210607000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 158470500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 369077500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 11482 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 11995 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 11482 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 13726 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 11482 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 13726 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266852 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892788 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.293622 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266852 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.963904 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.380810 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266852 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.963904 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.380810 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68735.966057 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78150.655022 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69960.249858 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71951.612903 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71951.612903 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68735.966057 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73264.216366 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70609.814425 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68735.966057 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73264.216366 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70609.814425 # average overall miss latency
+system.cpu.l2cache.overall_misses::total 5232 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208636250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35488000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 244124250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122872750 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 122872750 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 208636250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 158360750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 366997000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 208636250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 158360750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 366997000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 11337 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 510 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 11847 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1732 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1732 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 11337 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2242 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 13579 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 11337 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2242 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 13579 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.270707 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894118 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.297544 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985566 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.985566 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.270707 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.964764 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.385301 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.270707 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.964764 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.385301 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67981.834474 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77824.561404 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69255.106383 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71981.693029 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71981.693029 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67981.834474 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73213.476653 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70144.686544 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67981.834474 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73213.476653 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70144.686544 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3064 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 3522 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3064 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3069 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 456 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3525 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1707 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1707 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3069 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3064 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5232 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3069 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171789000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30123000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201912000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101752000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101752000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171789000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131875000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 303664000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171789000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131875000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 303664000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293622 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.380810 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266852 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.380810 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56066.906005 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65770.742358 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57328.790460 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59678.592375 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59678.592375 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56066.906005 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60968.562182 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58095.274536 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56066.906005 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60968.562182 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58095.274536 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169758750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29825000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199583750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101974750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101974750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169758750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131799750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 301558500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169758750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131799750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 301558500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270707 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894118 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297544 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985566 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985566 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270707 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.385301 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270707 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.385301 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55314.027370 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65405.701754 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56619.503546 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59739.162273 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59739.162273 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55314.027370 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60933.772538 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57637.327982 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55314.027370 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60933.772538 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57637.327982 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 159 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1456.991941 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 28100018 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12522.289661 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 157 # number of replacements
+system.cpu.dcache.tags.tagsinuse 1456.621503 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 28355724 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2242 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 12647.512935 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1456.991941 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.355711 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.355711 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 1456.621503 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.355620 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.355620 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 56220748 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 56220748 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 21606921 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21606921 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 6492872 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6492872 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 225 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 225 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 28099793 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28099793 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28099793 # number of overall hits
-system.cpu.dcache.overall_hits::total 28099793 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1002 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1002 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 8231 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 8231 # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses 56732342 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 56732342 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 21862715 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 21862715 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 6492763 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6492763 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 246 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 246 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data 28355478 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 28355478 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 28355478 # number of overall hits
+system.cpu.dcache.overall_hits::total 28355478 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 985 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 985 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 8340 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 8340 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9233 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9233 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9233 # number of overall misses
-system.cpu.dcache.overall_misses::total 9233 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 62924000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 62924000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 508720531 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 508720531 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 9325 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9325 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9325 # number of overall misses
+system.cpu.dcache.overall_misses::total 9325 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 61174750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 61174750 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 507348010 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 507348010 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 571644531 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 571644531 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 571644531 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 571644531 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 21607923 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 21607923 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 568522760 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 568522760 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 568522760 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 568522760 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 21863700 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 21863700 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 226 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 226 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 28109026 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 28109026 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 28109026 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 28109026 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001266 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.001266 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004425 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004425 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62798.403194 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62798.403194 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61805.434455 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61805.434455 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 28364803 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 28364803 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 28364803 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 28364803 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001283 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.001283 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004049 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004049 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000329 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000329 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000329 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000329 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62106.345178 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62106.345178 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60833.094724 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60833.094724 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61913.195170 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61913.195170 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 23691 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60967.588204 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60967.588204 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 27950 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.069971 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.942857 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 109 # number of writebacks
-system.cpu.dcache.writebacks::total 109 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 490 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6500 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6500 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 6990 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 6990 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 6990 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 6990 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
+system.cpu.dcache.writebacks::total 107 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 476 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 476 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6608 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6608 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7084 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7084 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7084 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7084 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36779750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 36779750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124808747 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 124808747 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 2241 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2241 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2241 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2241 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36463750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 36463750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124994997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 124994997 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161588497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 161588497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161588497 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 161588497 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161458747 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 161458747 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161458747 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 161458747 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004425 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004425 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71835.449219 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71835.449219 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72102.106875 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72102.106875 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004049 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004049 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71638.015717 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71638.015717 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72168.012125 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72168.012125 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:25:13
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 21:53:28
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5949040
+ 0: system.cpu.isa: ISA system set to: 0 0x4f074c0
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 74219931000 because target called exit()
+122 123 124 Exiting @ tick 74056845500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.074209 # Number of seconds simulated
-sim_ticks 74208571000 # Number of ticks simulated
-final_tick 74208571000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.074057 # Number of seconds simulated
+sim_ticks 74056845500 # Number of ticks simulated
+final_tick 74056845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109569 # Simulator instruction rate (inst/s)
-host_op_rate 119969 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47190079 # Simulator tick rate (ticks/s)
-host_mem_usage 316768 # Number of bytes of host memory used
-host_seconds 1572.55 # Real time elapsed on the host
+host_inst_rate 115398 # Simulator instruction rate (inst/s)
+host_op_rate 126351 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 49598898 # Simulator tick rate (ticks/s)
+host_mem_usage 265028 # Number of bytes of host memory used
+host_seconds 1493.11 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 188656503 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 131456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 243264 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 131456 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 131456 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2054 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3801 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1771440 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1506672 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3278112 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1771440 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1771440 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1771440 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1506672 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3278112 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3802 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 131840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory
+system.physmem.bytes_read::total 244032 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 131840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 131840 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2060 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3813 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1780254 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1514944 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3295198 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1780254 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1780254 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1780254 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1514944 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3295198 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 3814 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 3802 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 3814 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 243328 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 244096 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 243328 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 244096 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 306 # Per bank write bursts
-system.physmem.perBankRdBursts::1 216 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 307 # Per bank write bursts
+system.physmem.perBankRdBursts::1 215 # Per bank write bursts
system.physmem.perBankRdBursts::2 134 # Per bank write bursts
-system.physmem.perBankRdBursts::3 308 # Per bank write bursts
-system.physmem.perBankRdBursts::4 298 # Per bank write bursts
+system.physmem.perBankRdBursts::3 310 # Per bank write bursts
+system.physmem.perBankRdBursts::4 299 # Per bank write bursts
system.physmem.perBankRdBursts::5 300 # Per bank write bursts
system.physmem.perBankRdBursts::6 265 # Per bank write bursts
-system.physmem.perBankRdBursts::7 217 # Per bank write bursts
+system.physmem.perBankRdBursts::7 223 # Per bank write bursts
system.physmem.perBankRdBursts::8 246 # Per bank write bursts
-system.physmem.perBankRdBursts::9 215 # Per bank write bursts
+system.physmem.perBankRdBursts::9 213 # Per bank write bursts
system.physmem.perBankRdBursts::10 289 # Per bank write bursts
-system.physmem.perBankRdBursts::11 192 # Per bank write bursts
+system.physmem.perBankRdBursts::11 196 # Per bank write bursts
system.physmem.perBankRdBursts::12 190 # Per bank write bursts
-system.physmem.perBankRdBursts::13 208 # Per bank write bursts
-system.physmem.perBankRdBursts::14 218 # Per bank write bursts
-system.physmem.perBankRdBursts::15 200 # Per bank write bursts
+system.physmem.perBankRdBursts::13 207 # Per bank write bursts
+system.physmem.perBankRdBursts::14 219 # Per bank write bursts
+system.physmem.perBankRdBursts::15 201 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 74208552500 # Total gap between requests
+system.physmem.totGap 74056827000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 3802 # Read request sizes (log2)
+system.physmem.readPktSize::6 3814 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 2914 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 704 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 139 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 2889 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 752 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 765 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 315.649673 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 194.993895 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 311.806865 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 244 31.90% 31.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 208 27.19% 59.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 73 9.54% 68.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 46 6.01% 74.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 29 3.79% 78.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 70 9.15% 87.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 12 1.57% 89.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 15 1.96% 91.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 68 8.89% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 765 # Bytes accessed per row activation
-system.physmem.totQLat 30320750 # Total ticks spent queuing
-system.physmem.totMemAccLat 101608250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 19010000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7974.95 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 775 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 313.641290 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 192.687696 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 311.293227 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 258 33.29% 33.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 189 24.39% 57.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 87 11.23% 68.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 51 6.58% 75.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 41 5.29% 80.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 31 4.00% 84.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 43 5.55% 90.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 10 1.29% 91.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 65 8.39% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 775 # Bytes accessed per row activation
+system.physmem.totQLat 30109750 # Total ticks spent queuing
+system.physmem.totMemAccLat 101622250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 19070000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 7894.53 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26724.95 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26644.53 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.30 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.30 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 3030 # Number of row buffer hits during reads
+system.physmem.readRowHits 3033 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.69 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 79.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 19518293.66 # Average gap between requests
-system.physmem.pageHitRate 79.69 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 70857777500 # Time in different power states
-system.physmem.memoryStateTime::REF 2477800000 # Time in different power states
+system.physmem.avgGap 19417101.99 # Average gap between requests
+system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 70721348250 # Time in different power states
+system.physmem.memoryStateTime::REF 2472860000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 867720500 # Time in different power states
+system.physmem.memoryStateTime::ACT 861203250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 3278112 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 2731 # Transaction distribution
-system.membus.trans_dist::ReadResp 2730 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1071 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1071 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7603 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 7603 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243264 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 243264 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 243264 # Total data (bytes)
+system.membus.throughput 3295198 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 2737 # Transaction distribution
+system.membus.trans_dist::ReadResp 2736 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1077 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1077 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7631 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 7631 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 244032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 244032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 244032 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 4541000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 35718000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 35636248 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 94830067 # Number of BP lookups
-system.cpu.branchPred.condPredicted 74823235 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6280063 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 44671635 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 43055955 # Number of BTB hits
+system.cpu.branchPred.lookups 95688557 # Number of BP lookups
+system.cpu.branchPred.condPredicted 75485372 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6295432 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 45268261 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 43530249 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 96.383208 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 4354004 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 88575 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 96.160639 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 4420185 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 89338 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 148417143 # number of cpu cycles simulated
+system.cpu.numCycles 148113692 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 39654365 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 380231735 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 94830067 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 47409959 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 80369944 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 27285630 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7202415 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 5794 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 40192835 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 385592009 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 95688557 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 47950434 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 81543775 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 28012255 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 4465673 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 36851066 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1832690 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 148222429 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.802512 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.153204 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 37392446 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1863811 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 147907378 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.849949 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.160123 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 68020985 45.89% 45.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5256509 3.55% 49.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 10534999 7.11% 56.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10284828 6.94% 63.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8666572 5.85% 69.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6537070 4.41% 73.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6246175 4.21% 77.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8016813 5.41% 83.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 24658478 16.64% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 66535735 44.98% 44.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5361707 3.63% 48.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 10726789 7.25% 55.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10405351 7.04% 62.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8725871 5.90% 68.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 6634741 4.49% 73.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 6328592 4.28% 77.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 8060301 5.45% 83.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 25128291 16.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 148222429 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.638943 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.561913 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45507597 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5871716 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 74805608 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1201041 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 20836467 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 14340186 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164591 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 392845308 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 733522 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 20836467 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 50894479 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 722812 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 602318 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 70557272 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4609081 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 371354915 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 338748 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3656059 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 631764461 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1588652531 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1506975247 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3198470 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 147907378 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.646048 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.603352 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 45234948 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 3964725 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 76674416 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 488435 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 21544854 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 14463585 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 165860 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 398867240 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 776962 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 21544854 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 49978288 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 80802 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 634035 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 72417632 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 3251767 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 377266574 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 64 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 883323 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 2242172 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 19804 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 7460 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 639899653 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1616068029 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1531504010 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3330597 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 333720322 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 25119 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 25116 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13019783 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 43012506 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16421309 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 5620383 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3639856 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 329245944 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 47173 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 249482695 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 793526 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 139565421 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 362544222 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1957 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 148222429 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.683164 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.761970 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 341855514 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 25341 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25337 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 6011835 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 44415560 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16956234 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 6645157 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4213095 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 334591306 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 47320 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 251099486 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1072213 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 144899766 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 380484892 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2104 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 147907378 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.697681 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.790678 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56049781 37.81% 37.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 22646407 15.28% 53.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 24808421 16.74% 69.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 20317592 13.71% 83.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12547069 8.47% 92.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6521251 4.40% 96.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4032352 2.72% 99.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1118421 0.75% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 181135 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56583019 38.26% 38.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 21897324 14.80% 53.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 24121591 16.31% 69.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 20330444 13.75% 83.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12466477 8.43% 91.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 6673732 4.51% 96.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4321605 2.92% 98.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1302038 0.88% 99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 211148 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 148222429 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 147907378 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 964061 38.35% 38.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5595 0.22% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 96 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1168003 46.46% 85.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 376162 14.96% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1040958 39.39% 39.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5589 0.21% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 97 0.00% 39.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 356 0.01% 39.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 45 0.00% 39.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1222208 46.25% 85.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 373303 14.13% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 194908316 78.12% 78.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 978999 0.39% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 164299 0.07% 78.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 255151 0.10% 78.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76428 0.03% 78.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 465968 0.19% 78.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 206368 0.08% 79.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 71868 0.03% 79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 38371220 15.38% 94.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 13950685 5.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 195834645 77.99% 77.99% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 981127 0.39% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 33203 0.01% 78.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 259909 0.10% 78.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 76654 0.03% 78.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 470113 0.19% 78.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 206582 0.08% 78.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 71910 0.03% 78.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.89% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 38922233 15.50% 94.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 14078361 5.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 249482695 # Type of FU issued
-system.cpu.iq.rate 1.680956 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2513965 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010077 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 646755779 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 466684925 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 237894917 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3739531 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2191886 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1842592 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 250120414 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1876246 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2009109 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 251099486 # Type of FU issued
+system.cpu.iq.rate 1.695316 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2642556 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010524 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 650051417 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 477257433 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 239511768 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3769702 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2301296 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1862518 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 251853224 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1888818 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2264941 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 13163022 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11141 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18733 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3776675 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 14566076 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14946 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 20827 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 4311600 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 115 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 20836467 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 18579 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 909 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 329310121 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 781513 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 43012506 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16421309 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 24765 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 190 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 272 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18733 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3888765 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3761308 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7650073 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 242977304 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 36862847 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6505391 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 21544854 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1947 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2849 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 334655682 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 756589 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 44415560 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16956234 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 24912 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 319 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2632 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 20827 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3907560 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3770350 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 7677910 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 244706645 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 37396904 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 6392841 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 17004 # number of nop insts executed
-system.cpu.iew.exec_refs 50511963 # number of memory reference insts executed
-system.cpu.iew.exec_branches 53432662 # Number of branches executed
-system.cpu.iew.exec_stores 13649116 # Number of stores executed
-system.cpu.iew.exec_rate 1.637124 # Inst execution rate
-system.cpu.iew.wb_sent 240796428 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 239737509 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 148472463 # num instructions producing a value
-system.cpu.iew.wb_consumers 267293668 # num instructions consuming a value
+system.cpu.iew.exec_nop 17056 # number of nop insts executed
+system.cpu.iew.exec_refs 51162912 # number of memory reference insts executed
+system.cpu.iew.exec_branches 53733408 # Number of branches executed
+system.cpu.iew.exec_stores 13766008 # Number of stores executed
+system.cpu.iew.exec_rate 1.652154 # Inst execution rate
+system.cpu.iew.wb_sent 242463171 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 241374286 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 150213875 # num instructions producing a value
+system.cpu.iew.wb_consumers 271770811 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.615295 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.555466 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.629655 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.552723 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 140639228 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 145985060 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6126680 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 127385962 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.481096 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.186061 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 6141058 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 126362524 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.493092 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.207919 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 57702305 45.30% 45.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 31675528 24.87% 70.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13782422 10.82% 80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 7634808 5.99% 86.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4379316 3.44% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1319569 1.04% 91.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1705598 1.34% 92.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1313930 1.03% 93.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7872486 6.18% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 57333838 45.37% 45.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 31277146 24.75% 70.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13531640 10.71% 80.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 7550408 5.98% 86.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4276360 3.38% 90.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1325331 1.05% 91.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1692872 1.34% 92.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1209518 0.96% 93.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 8165411 6.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 127385962 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 126362524 # Number of insts commited each cycle
system.cpu.commit.committedInsts 172317409 # Number of instructions committed
system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction
-system.cpu.commit.bw_lim_events 7872486 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 8165411 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 448818394 # The number of ROB reads
-system.cpu.rob.rob_writes 679565858 # The number of ROB writes
-system.cpu.timesIdled 2789 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 194714 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 452847863 # The number of ROB reads
+system.cpu.rob.rob_writes 690972129 # The number of ROB writes
+system.cpu.timesIdled 2844 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 206314 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172303021 # Number of Instructions Simulated
system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.861373 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.861373 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.160937 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.160937 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1079497274 # number of integer regfile reads
-system.cpu.int_regfile_writes 384888160 # number of integer regfile writes
-system.cpu.fp_regfile_reads 2912753 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2499155 # number of floating regfile writes
-system.cpu.misc_regfile_reads 64874393 # number of misc regfile reads
+system.cpu.cpi 0.859612 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.859612 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.163316 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.163316 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1087499674 # number of integer regfile reads
+system.cpu.int_regfile_writes 386673292 # number of integer regfile writes
+system.cpu.fp_regfile_reads 2922602 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2532629 # number of floating regfile writes
+system.cpu.misc_regfile_reads 65625361 # number of misc regfile reads
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 5170292 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 4896 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 4895 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 19 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1081 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1081 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8239 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3733 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 11972 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.throughput 5184342 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1084 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1084 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8245 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3740 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 11985 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263744 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 383808 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 383808 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 6548996 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 6552747 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3099487 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3102991 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 2388 # number of replacements
-system.cpu.icache.tags.tagsinuse 1346.753946 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 36845676 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 4119 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 8945.296431 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 2387 # number of replacements
+system.cpu.icache.tags.tagsinuse 1349.069671 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 37387126 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 4121 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 9072.343121 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1346.753946 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.657595 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.657595 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 1349.069671 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.658725 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.658725 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1734 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 73706251 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 73706251 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 36845676 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 36845676 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 36845676 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 36845676 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 36845676 # number of overall hits
-system.cpu.icache.overall_hits::total 36845676 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5390 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5390 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5390 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5390 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5390 # number of overall misses
-system.cpu.icache.overall_misses::total 5390 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 228751995 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 228751995 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 228751995 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 228751995 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 228751995 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 228751995 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 36851066 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 36851066 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 36851066 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 36851066 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 36851066 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 36851066 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42440.073284 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42440.073284 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1596 # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 547 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.846680 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 74789015 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 74789015 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 37387126 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 37387126 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 37387126 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 37387126 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 37387126 # number of overall hits
+system.cpu.icache.overall_hits::total 37387126 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 5320 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 5320 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 5320 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 5320 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 5320 # number of overall misses
+system.cpu.icache.overall_misses::total 5320 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 224799997 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 224799997 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 224799997 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 224799997 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 224799997 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 224799997 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 37392446 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 37392446 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 37392446 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 37392446 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 37392446 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 37392446 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42255.638534 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42255.638534 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42255.638534 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42255.638534 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1071 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1270 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1270 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1270 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1270 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1270 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1270 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4120 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 4120 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 4120 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 4120 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 4120 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 4120 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167326504 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 167326504 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167326504 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 167326504 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167326504 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 167326504 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40613.229126 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40613.229126 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1196 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1196 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1196 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1196 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1196 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1196 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168596253 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 168596253 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168596253 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 168596253 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168596253 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 168596253 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000110 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000110 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000110 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40881.729631 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40881.729631 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 1966.490721 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2149 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 2739 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.784593 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 1967.769315 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 2148 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 2745 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.782514 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 4.023907 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 1424.627361 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839452 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 4.017679 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 1427.875766 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 535.875870 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043476 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.016414 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.060013 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 2739 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 607 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1969 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083588 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 51788 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 51788 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 2061 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2148 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 19 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 19 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 2061 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2158 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 2061 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2158 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 2059 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 2748 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2059 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 3819 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2059 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses
-system.cpu.l2cache.overall_misses::total 3819 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 142590000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50403250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 192993250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74281750 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 74281750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 142590000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 124685000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 267275000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 142590000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 124685000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 267275000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 4120 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043575 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.016354 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.060052 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 2745 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 608 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083771 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 51829 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 51829 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 2058 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 89 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2147 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 2058 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2154 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 2058 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2154 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2064 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 687 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 2751 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 1077 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 1077 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2064 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1764 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 3828 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2064 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1764 # number of overall misses
+system.cpu.l2cache.overall_misses::total 3828 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143880250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49531000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 193411250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74080000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 74080000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 143880250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 123611000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 267491250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 143880250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 123611000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 267491250 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 4122 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 776 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 4896 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 19 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 19 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1081 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1081 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 4120 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1857 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 5977 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 4120 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1857 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 5977 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.499757 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887887 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.561275 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990749 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.990749 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.499757 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.947765 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.638949 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.499757 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.947765 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.638949 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69252.064109 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73154.208999 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70230.440320 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69357.376284 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69357.376284 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69985.598324 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69985.598324 # average overall miss latency
+system.cpu.l2cache.ReadReq_accesses::total 4898 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1084 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1084 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 4122 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1860 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 5982 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 4122 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1860 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 5982 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.500728 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.885309 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.561658 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993542 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.993542 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.500728 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.948387 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.639920 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.500728 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.948387 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.639920 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69709.423450 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72097.525473 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70305.797892 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68783.658310 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68783.658310 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69709.423450 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70074.263039 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69877.547022 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69709.423450 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70074.263039 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69877.547022 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2055 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2061 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 676 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 2731 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1747 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 3802 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1747 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 3802 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116514500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41206750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 157721250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60687250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60687250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116514500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101894000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 218408500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116514500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101894000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 218408500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2737 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1077 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1077 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2061 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3814 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2061 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3814 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117822250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40424500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 158246750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60589000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60589000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117822250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101013500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 218835750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117822250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101013500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 218835750 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.557802 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990749 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990749 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.636105 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.636105 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56698.053528 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60956.730769 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57752.196997 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56664.098973 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56664.098973 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.558800 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993542 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993542 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942473 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.637579 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.500000 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942473 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.637579 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57167.515769 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59799.556213 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57817.592254 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56257.195915 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56257.195915 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 60 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1407.063073 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 46801066 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1857 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 25202.512655 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 56 # number of replacements
+system.cpu.dcache.tags.tagsinuse 1410.171492 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 47073011 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1860 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 25308.070430 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1407.063073 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.343521 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.343521 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 1410.171492 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.344280 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.344280 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 1804 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 93623269 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 93623269 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 34399630 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 34399630 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12356556 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12356556 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.440430 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 94167216 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 94167216 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 34671591 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 34671591 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12356534 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12356534 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 22477 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 22477 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 46756186 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 46756186 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 46756186 # number of overall hits
-system.cpu.dcache.overall_hits::total 46756186 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1907 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1907 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 7731 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 7731 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 47028125 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 47028125 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 47028125 # number of overall hits
+system.cpu.dcache.overall_hits::total 47028125 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1914 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1914 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 7753 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 7753 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9638 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9638 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9638 # number of overall misses
-system.cpu.dcache.overall_misses::total 9638 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 121525225 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 121525225 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 489452496 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 489452496 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 9667 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9667 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9667 # number of overall misses
+system.cpu.dcache.overall_misses::total 9667 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 120679977 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 120679977 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 501616998 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 501616998 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 610977721 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 610977721 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 610977721 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 610977721 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 34401537 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 34401537 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 622296975 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 622296975 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 622296975 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 622296975 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 34673505 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 34673505 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22479 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 22479 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46765824 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46765824 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46765824 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46765824 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 47037792 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 47037792 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 47037792 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 47037792 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63392.583627 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63392.583627 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.545455 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64373.329368 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64373.329368 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 99 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.428571 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 99 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 19 # number of writebacks
-system.cpu.dcache.writebacks::total 19 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1130 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1130 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6651 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6651 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
+system.cpu.dcache.writebacks::total 16 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6668 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6668 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7781 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7781 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7781 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7781 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7805 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7805 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7805 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7805 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1080 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1080 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52119013 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 52119013 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75404498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 75404498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 127523511 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 127523511 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 127523511 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 127523511 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1862 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1862 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1862 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1862 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51275761 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 51275761 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75222996 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 75222996 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126498757 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 126498757 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126498757 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 126498757 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/cpu2000/binaries/x86/linux/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 21:43:52
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+gem5 compiled Jun 21 2014 11:13:07
+gem5 started Jun 21 2014 22:44:43
+gem5 executing on phenom
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 144463317000 because target called exit()
+122 123 124 Exiting @ tick 145782984000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.144620 # Number of seconds simulated
-sim_ticks 144620050000 # Number of ticks simulated
-final_tick 144620050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.145783 # Number of seconds simulated
+sim_ticks 145782984000 # Number of ticks simulated
+final_tick 145782984000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 65513 # Simulator instruction rate (inst/s)
-host_op_rate 109805 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 71737347 # Simulator tick rate (ticks/s)
-host_mem_usage 319696 # Number of bytes of host memory used
-host_seconds 2015.97 # Real time elapsed on the host
+host_inst_rate 75578 # Simulator instruction rate (inst/s)
+host_op_rate 126676 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 83424852 # Simulator tick rate (ticks/s)
+host_mem_usage 276072 # Number of bytes of host memory used
+host_seconds 1747.48 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory
-system.physmem.bytes_read::total 342656 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1501977 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 867376 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2369353 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1501977 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1501977 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1501977 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 867376 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2369353 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5356 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 219712 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125824 # Number of bytes read from this memory
+system.physmem.bytes_read::total 345536 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 219712 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 219712 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3433 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1966 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5399 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1507117 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 863091 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2370208 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1507117 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1507117 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1507117 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 863091 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2370208 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5399 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 5356 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 5399 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 342784 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 345536 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 342784 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 345536 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 131 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 288 # Per bank write bursts
-system.physmem.perBankRdBursts::1 358 # Per bank write bursts
-system.physmem.perBankRdBursts::2 449 # Per bank write bursts
-system.physmem.perBankRdBursts::3 356 # Per bank write bursts
-system.physmem.perBankRdBursts::4 330 # Per bank write bursts
-system.physmem.perBankRdBursts::5 328 # Per bank write bursts
-system.physmem.perBankRdBursts::6 400 # Per bank write bursts
-system.physmem.perBankRdBursts::7 378 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 225 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 296 # Per bank write bursts
+system.physmem.perBankRdBursts::1 360 # Per bank write bursts
+system.physmem.perBankRdBursts::2 450 # Per bank write bursts
+system.physmem.perBankRdBursts::3 362 # Per bank write bursts
+system.physmem.perBankRdBursts::4 334 # Per bank write bursts
+system.physmem.perBankRdBursts::5 327 # Per bank write bursts
+system.physmem.perBankRdBursts::6 402 # Per bank write bursts
+system.physmem.perBankRdBursts::7 379 # Per bank write bursts
system.physmem.perBankRdBursts::8 340 # Per bank write bursts
-system.physmem.perBankRdBursts::9 277 # Per bank write bursts
-system.physmem.perBankRdBursts::10 231 # Per bank write bursts
-system.physmem.perBankRdBursts::11 276 # Per bank write bursts
-system.physmem.perBankRdBursts::12 208 # Per bank write bursts
-system.physmem.perBankRdBursts::13 466 # Per bank write bursts
-system.physmem.perBankRdBursts::14 385 # Per bank write bursts
-system.physmem.perBankRdBursts::15 286 # Per bank write bursts
+system.physmem.perBankRdBursts::9 280 # Per bank write bursts
+system.physmem.perBankRdBursts::10 232 # Per bank write bursts
+system.physmem.perBankRdBursts::11 283 # Per bank write bursts
+system.physmem.perBankRdBursts::12 213 # Per bank write bursts
+system.physmem.perBankRdBursts::13 468 # Per bank write bursts
+system.physmem.perBankRdBursts::14 388 # Per bank write bursts
+system.physmem.perBankRdBursts::15 285 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 144620007000 # Total gap between requests
+system.physmem.totGap 145782934000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 5356 # Read request sizes (log2)
+system.physmem.readPktSize::6 5399 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 4298 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 873 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 161 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4350 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 862 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1043 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 326.933845 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 193.223116 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 334.208962 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 368 35.28% 35.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 248 23.78% 59.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 102 9.78% 68.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 58 5.56% 74.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 42 4.03% 78.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 59 5.66% 84.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 17 1.63% 85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 23 2.21% 87.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 126 12.08% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1043 # Bytes accessed per row activation
-system.physmem.totQLat 35519000 # Total ticks spent queuing
-system.physmem.totMemAccLat 135944000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 26780000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6631.63 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 313.768881 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 183.938334 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 327.481688 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 421 38.31% 38.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 241 21.93% 60.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 100 9.10% 69.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 65 5.91% 75.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 56 5.10% 80.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 54 4.91% 85.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 19 1.73% 86.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 20 1.82% 88.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 123 11.19% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation
+system.physmem.totQLat 41267750 # Total ticks spent queuing
+system.physmem.totMemAccLat 142499000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 26995000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 7643.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25381.63 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 26393.59 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4304 # Number of row buffer hits during reads
+system.physmem.readRowHits 4296 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 79.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 27001494.96 # Average gap between requests
-system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 138334279250 # Time in different power states
-system.physmem.memoryStateTime::REF 4828980000 # Time in different power states
+system.physmem.avgGap 27001839.97 # Average gap between requests
+system.physmem.pageHitRate 79.57 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 139294402000 # Time in different power states
+system.physmem.memoryStateTime::REF 4867980000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1451861250 # Time in different power states
+system.physmem.memoryStateTime::ACT 1619857750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 2368911 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 3823 # Transaction distribution
-system.membus.trans_dist::ReadResp 3820 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 131 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 131 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1533 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1533 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10971 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10971 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10971 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 342592 # Total data (bytes)
+system.membus.throughput 2370208 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3862 # Transaction distribution
+system.membus.trans_dist::ReadResp 3862 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 225 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 225 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1537 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1537 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11248 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11248 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 11248 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 345536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 345536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 345536 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 6960500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 6776000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 50659869 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 50906775 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 18663045 # Number of BP lookups
-system.cpu.branchPred.condPredicted 18663045 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1489785 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11444584 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 10797822 # Number of BTB hits
+system.cpu.branchPred.lookups 19251245 # Number of BP lookups
+system.cpu.branchPred.condPredicted 19251245 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1503864 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11794147 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 11185323 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.348750 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1319901 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 22895 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.837914 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1363914 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 22896 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 289523031 # number of cpu cycles simulated
+system.cpu.numCycles 291881234 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 23473938 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 206858197 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 18663045 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 12117723 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 54247835 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 15552938 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 178336695 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 7706 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 22368694 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 223698 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 269869756 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.267902 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.756065 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 24212208 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 214052436 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 19251245 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 12549237 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 55985392 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 16840264 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 177008858 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 1283 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 7024 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 65 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 23136044 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 282405 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 272277792 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.296795 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.780007 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 217061517 80.43% 80.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2847740 1.06% 81.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2315002 0.86% 82.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2640494 0.98% 83.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3217056 1.19% 84.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3387561 1.26% 85.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3839682 1.42% 87.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2560696 0.95% 88.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 32000008 11.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 217778926 79.98% 79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2920418 1.07% 81.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2383762 0.88% 81.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2729411 1.00% 82.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3335214 1.22% 84.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 3498463 1.28% 85.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4001053 1.47% 86.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2671434 0.98% 87.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 32959111 12.10% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 269869756 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.064461 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.714479 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 36939117 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 167279649 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 41594778 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 10253994 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 13802218 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 336245393 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 13802218 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 45020160 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 116775107 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 31642 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 42714880 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 51525749 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 329872428 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 11092 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 26167242 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 22759273 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 382595093 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 918331708 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 606342575 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4133173 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 272277792 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.065956 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.733355 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35864450 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 167881983 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 44786392 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8682005 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 15062962 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 346567500 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 15062962 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 42671339 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 116778023 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 37081 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 45654825 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 52073562 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 340013592 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 22387 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 45742154 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 5966467 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 137065 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 393960742 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 945391670 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 624205941 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4453971 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 123165643 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2073 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2073 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 105277588 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 84554246 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 30134710 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 58533931 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 19035455 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 322937953 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4364 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 260608849 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 112553 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 101196304 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 210593531 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3119 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 269869756 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.965684 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.342187 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 134531292 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2243 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2238 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 90830827 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 87006444 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 31074157 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 61167406 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 20316475 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 332092429 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4572 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 263265541 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 182587 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 110344895 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 231927910 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3327 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 272277792 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.966901 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.357293 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 143519297 53.18% 53.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 55647203 20.62% 73.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 34229884 12.68% 86.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 19073202 7.07% 93.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 10874136 4.03% 97.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4113724 1.52% 99.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1802263 0.67% 99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 476846 0.18% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 133201 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 146114169 53.66% 53.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 54798888 20.13% 73.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 34241976 12.58% 86.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18986540 6.97% 93.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 11181244 4.11% 97.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4283756 1.57% 99.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1956251 0.72% 99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 577925 0.21% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 137043 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 269869756 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 272277792 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 125646 4.63% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2288183 84.39% 89.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 297636 10.98% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 142962 5.08% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2337044 83.10% 88.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 332186 11.81% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1210826 0.46% 0.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 162119129 62.21% 62.67% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 788294 0.30% 62.97% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 7035677 2.70% 65.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1444684 0.55% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 65441941 25.11% 91.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 22568298 8.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 1210901 0.46% 0.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 164273729 62.40% 62.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 789732 0.30% 63.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 7035869 2.67% 65.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1461918 0.56% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 65849141 25.01% 91.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 22644251 8.60% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 260608849 # Type of FU issued
-system.cpu.iq.rate 0.900132 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2711465 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010404 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 789025856 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 420800342 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 255248449 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 4885616 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 3622403 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2349194 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 259650836 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2458652 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 18874838 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 263265541 # Type of FU issued
+system.cpu.iq.rate 0.901961 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2812192 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010682 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 796857032 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 438700759 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 257701720 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 4946621 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 4039797 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 2377852 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 262377827 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2489005 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 18800853 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 27904659 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 26471 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 289699 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 9618993 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 30356857 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 18134 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 304082 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 10558440 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 49872 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 13802218 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 85051562 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 5443180 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 322942317 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 133815 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 84554246 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 30134710 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2043 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2682047 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 14716 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 289699 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 640019 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 900364 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1540383 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 258834349 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 64663337 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1774500 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 15062962 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 84436601 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 5827541 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 332097001 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 93155 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 87006444 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 31074157 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2159 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 2868922 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 287074 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 304082 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 649398 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 907392 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1556790 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 261390422 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 65051182 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1875119 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 87028906 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14271418 # Number of branches executed
-system.cpu.iew.exec_stores 22365569 # Number of stores executed
-system.cpu.iew.exec_rate 0.894003 # Inst execution rate
-system.cpu.iew.wb_sent 258197839 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 257597643 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 206027195 # num instructions producing a value
-system.cpu.iew.wb_consumers 369217293 # num instructions consuming a value
+system.cpu.iew.exec_refs 87491108 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14410736 # Number of branches executed
+system.cpu.iew.exec_stores 22439926 # Number of stores executed
+system.cpu.iew.exec_rate 0.895537 # Inst execution rate
+system.cpu.iew.wb_sent 260730148 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 260079572 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 208603284 # num instructions producing a value
+system.cpu.iew.wb_consumers 373821854 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.889731 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.558011 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.891046 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.558029 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 101647922 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 110904752 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1490935 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 256067538 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.864473 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.651889 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1504927 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 257214830 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.860617 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.643182 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 156617936 61.16% 61.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57255270 22.36% 83.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 14082261 5.50% 89.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 12088609 4.72% 93.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4189643 1.64% 95.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2964480 1.16% 96.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 903129 0.35% 96.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1051661 0.41% 97.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6914549 2.70% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 157256344 61.14% 61.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57715541 22.44% 83.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 14223073 5.53% 89.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12060500 4.69% 93.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4224463 1.64% 95.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2956145 1.15% 96.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 920096 0.36% 96.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1048300 0.41% 97.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6810368 2.65% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 256067538 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 257214830 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
-system.cpu.commit.bw_lim_events 6914549 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6810368 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 572164295 # The number of ROB reads
-system.cpu.rob.rob_writes 659850863 # The number of ROB writes
-system.cpu.timesIdled 5930649 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 19653275 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 582672598 # The number of ROB reads
+system.cpu.rob.rob_writes 679632792 # The number of ROB writes
+system.cpu.timesIdled 5976195 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 19603442 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.192174 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.192174 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.456168 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.456168 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 451375343 # number of integer regfile reads
-system.cpu.int_regfile_writes 234032598 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3213912 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2009037 # number of floating regfile writes
-system.cpu.cc_regfile_reads 102846049 # number of cc regfile reads
-system.cpu.cc_regfile_writes 59805449 # number of cc regfile writes
-system.cpu.misc_regfile_reads 133386978 # number of misc regfile reads
+system.cpu.cpi 2.210030 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.210030 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.452483 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.452483 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 453366407 # number of integer regfile reads
+system.cpu.int_regfile_writes 236319036 # number of integer regfile writes
+system.cpu.fp_regfile_reads 3248620 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2037591 # number of floating regfile writes
+system.cpu.cc_regfile_reads 102911292 # number of cc regfile reads
+system.cpu.cc_regfile_writes 59928663 # number of cc regfile writes
+system.cpu.misc_regfile_reads 134914047 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 3852301 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 7156 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7153 # Transaction distribution
+system.cpu.toL2Bus.throughput 4027905 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7620 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7618 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 132 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13245 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4286 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 17531 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 419584 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129024 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 548608 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 548608 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 8512 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4433000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::UpgradeReq 226 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 226 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1544 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1544 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14075 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4490 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 18565 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 443136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129600 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 572736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 572736 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 14464 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 4714500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 10626750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 11320000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3450631 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3508475 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 4592 # number of replacements
-system.cpu.icache.tags.tagsinuse 1628.049417 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 22359876 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 6557 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 3410.077169 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 4955 # number of replacements
+system.cpu.icache.tags.tagsinuse 1627.815791 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 23126816 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 6924 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 3340.094743 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1628.049417 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.794946 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.794946 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 124 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 44744077 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 44744077 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 22359876 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 22359876 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 22359876 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 22359876 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 22359876 # number of overall hits
-system.cpu.icache.overall_hits::total 22359876 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 8818 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 8818 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 8818 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 8818 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 8818 # number of overall misses
-system.cpu.icache.overall_misses::total 8818 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 365022750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 365022750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 365022750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 365022750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 365022750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 365022750 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 22368694 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 22368694 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 22368694 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 22368694 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 22368694 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 22368694 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000394 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000394 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000394 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000394 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000394 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000394 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41395.185983 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 41395.185983 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 41395.185983 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 41395.185983 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 701 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1627.815791 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.794832 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.794832 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1969 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 748 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.961426 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 46279236 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 46279236 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 23126816 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 23126816 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 23126816 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 23126816 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 23126816 # number of overall hits
+system.cpu.icache.overall_hits::total 23126816 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 9227 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 9227 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 9227 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 9227 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 9227 # number of overall misses
+system.cpu.icache.overall_misses::total 9227 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 376330999 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 376330999 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 376330999 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 376330999 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 376330999 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 376330999 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 23136043 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 23136043 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 23136043 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 23136043 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 23136043 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 23136043 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40785.845779 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 40785.845779 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 40785.845779 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 40785.845779 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 40785.845779 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 40785.845779 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1569 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 46.733333 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 98.062500 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2129 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2129 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2129 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2129 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2129 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2129 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6689 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 6689 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 6689 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 6689 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 6689 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 6689 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 269490250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 269490250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 269490250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 269490250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 269490250 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 269490250 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40288.570788 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40288.570788 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2076 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2076 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2076 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2076 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2076 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2076 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7151 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 7151 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 7151 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 7151 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 7151 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 7151 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279771249 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 279771249 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 279771249 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 279771249 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 279771249 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 279771249 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000309 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000309 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000309 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39123.374213 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39123.374213 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39123.374213 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 39123.374213 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39123.374213 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 39123.374213 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 2549.629926 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3205 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 3824 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.838128 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 2580.073748 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3536 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 3865 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.914877 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 1.731773 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2236.346523 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 311.551630 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068248 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.009508 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.077809 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 3824 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2568 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116699 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 75020 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 75020 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 3162 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 3200 # number of ReadReq hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 1.848072 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2267.439437 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 310.786239 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000056 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069197 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.009484 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.078738 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 3865 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 868 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2602 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.117950 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 78826 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 78826 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 3491 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 40 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 3531 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 3162 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 44 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 3206 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 3162 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 44 # number of overall hits
-system.cpu.l2cache.overall_hits::total 3206 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3394 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 3491 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 47 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 3538 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 3491 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 47 # number of overall hits
+system.cpu.l2cache.overall_hits::total 3538 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3434 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 429 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 3823 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 131 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 131 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3394 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 5356 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3394 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses
-system.cpu.l2cache.overall_misses::total 5356 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 231042500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32071000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 263113500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 103820500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 103820500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 231042500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 135891500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 366934000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 231042500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 135891500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 366934000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 6556 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 467 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 7023 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_misses::total 3863 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 225 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 225 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 1537 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 1537 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3434 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1966 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 5400 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3434 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1966 # number of overall misses
+system.cpu.l2cache.overall_misses::total 5400 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 237479500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33236000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 270715500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104554500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 104554500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 237479500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 137790500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 375270000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 237479500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 137790500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 375270000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 6925 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 469 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 7394 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 132 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 132 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1539 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 6556 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2006 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 8562 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 6556 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2006 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 8562 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.517694 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.918630 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.544354 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992424 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992424 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996101 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.996101 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.517694 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.978066 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.625555 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.517694 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.978066 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.625555 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68073.806718 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74757.575758 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68823.829453 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67723.744292 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67723.744292 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68073.806718 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69261.722732 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68508.961912 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68073.806718 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69261.722732 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68508.961912 # average overall miss latency
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 226 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 226 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1544 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1544 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 6925 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2013 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 8938 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 6925 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2013 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 8938 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.495884 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.914712 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.522451 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.995575 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.995575 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995466 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.995466 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.495884 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.976652 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.604162 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.495884 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.976652 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.604162 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69155.358183 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77473.193473 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70079.083614 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68025.048796 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68025.048796 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69155.358183 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70086.724313 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69494.444444 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69155.358183 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70086.724313 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69494.444444 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3394 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3434 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 429 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 3823 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 131 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 131 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3394 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 5356 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3394 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 5356 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 188477000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26778500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 215255500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1310131 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1310131 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84218500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84218500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 188477000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110997000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 299474000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 188477000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110997000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 299474000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.918630 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.544354 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992424 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992424 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996101 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996101 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978066 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.625555 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.517694 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978066 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.625555 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55532.410136 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62420.745921 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56305.388438 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::total 3863 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 225 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 225 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1537 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1537 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3434 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1966 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5400 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3434 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1966 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 5400 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 194452000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27908500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222360500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2250225 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2250225 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85239500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85239500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 194452000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 113148000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 307600000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 194452000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 113148000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 307600000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.495884 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.914712 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.522451 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.995575 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.995575 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995466 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995466 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.495884 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.976652 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.604162 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.495884 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.976652 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.604162 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56625.509610 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65054.778555 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57561.610148 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54937.051533 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54937.051533 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55458.360442 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55458.360442 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56625.509610 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57552.390641 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56962.962963 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56625.509610 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57552.390641 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56962.962963 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 59 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1435.036669 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 66148000 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2003 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 33024.463305 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 57 # number of replacements
+system.cpu.dcache.tags.tagsinuse 1441.863444 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 66606870 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 33104.806163 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1435.036669 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.350351 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.350351 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 430 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 132302857 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 132302857 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 45633758 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 45633758 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20514059 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20514059 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 66147817 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 66147817 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 66147817 # number of overall hits
-system.cpu.dcache.overall_hits::total 66147817 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1672 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1672 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses
-system.cpu.dcache.overall_misses::total 2610 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 59941301 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 59941301 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 112492631 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 112492631 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 172433932 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 172433932 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 172433932 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 172433932 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 45634696 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 45634696 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data 1441.863444 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.352017 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.352017 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 1955 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.477295 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 133220616 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 133220616 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 46092554 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 46092554 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20513960 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20513960 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 66606514 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 66606514 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 66606514 # number of overall hits
+system.cpu.dcache.overall_hits::total 66606514 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1017 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1017 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1771 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1771 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2788 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2788 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2788 # number of overall misses
+system.cpu.dcache.overall_misses::total 2788 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 61229380 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 61229380 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 115680725 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 115680725 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 176910105 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 176910105 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 176910105 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 176910105 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 46093571 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 46093571 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 66150427 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 66150427 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 66150427 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 66150427 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63903.305970 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63903.305970 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67280.281699 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 67280.281699 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66066.640613 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66066.640613 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 66609302 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 66609302 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 66609302 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 66609302 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000086 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60205.880039 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60205.880039 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65319.438171 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65319.438171 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63454.126614 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63454.126614 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63454.126614 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63454.126614 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 94 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.500000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
system.cpu.dcache.writebacks::total 13 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 470 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 547 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 547 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 472 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 472 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 472 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1670 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1670 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2138 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32985750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 32985750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108417619 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 108417619 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141403369 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 141403369 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 141403369 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 141403369 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 549 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 549 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 549 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 549 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 470 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 470 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1769 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1769 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2239 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2239 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2239 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2239 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34113000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 34113000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111361525 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 111361525 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145474525 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 145474525 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145474525 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 145474525 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000081 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000081 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70482.371795 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70482.371795 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64920.729940 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64920.729940 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000086 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72580.851064 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72580.851064 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62951.681741 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62951.681741 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64972.990174 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 64972.990174 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64972.990174 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 64972.990174 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:24:08
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 10:37:19
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 21065000 because target called exit()
+Exiting @ tick 21025000 because target called exit()
sim_ticks 21025000 # Number of ticks simulated
final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 72274 # Simulator instruction rate (inst/s)
-host_op_rate 72262 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 238397605 # Simulator tick rate (ticks/s)
-host_mem_usage 265716 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 63804 # Simulator instruction rate (inst/s)
+host_op_rate 63793 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 210460029 # Simulator tick rate (ticks/s)
+host_mem_usage 221600 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 222.888418 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 329.838248 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22 27.85% 27.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18 22.78% 50.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
-system.physmem.totQLat 4394750 # Total ticks spent queuing
-system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 4169250 # Total ticks spent queuing
+system.physmem.totMemAccLat 13319250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8543.55 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 27293.55 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s
system.physmem.memoryStateTime::ACT 15304250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 1482425684 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 415 # Transaction distribution
-system.membus.trans_dist::ReadResp 414 # Transaction distribution
-system.membus.trans_dist::ReadExReq 73 # Transaction distribution
-system.membus.trans_dist::ReadExResp 73 # Transaction distribution
+system.membus.trans_dist::ReadReq 416 # Transaction distribution
+system.membus.trans_dist::ReadResp 415 # Transaction distribution
+system.membus.trans_dist::ReadExReq 72 # Transaction distribution
+system.membus.trans_dist::ReadExResp 72 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 31168 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4554750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 21.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 2894 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 2922 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1714 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 512 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2209 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 756 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 2236 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 763 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 34.223631 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 34.123435 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 417 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 2077 # DTB read hits
+system.cpu.dtb.read_hits 2080 # DTB read hits
system.cpu.dtb.read_misses 47 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2124 # DTB read accesses
-system.cpu.dtb.write_hits 1062 # DTB write hits
+system.cpu.dtb.read_accesses 2127 # DTB read accesses
+system.cpu.dtb.write_hits 1064 # DTB write hits
system.cpu.dtb.write_misses 31 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1093 # DTB write accesses
-system.cpu.dtb.data_hits 3139 # DTB hits
+system.cpu.dtb.write_accesses 1095 # DTB write accesses
+system.cpu.dtb.data_hits 3144 # DTB hits
system.cpu.dtb.data_misses 78 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3217 # DTB accesses
-system.cpu.itb.fetch_hits 2387 # ITB hits
+system.cpu.dtb.data_accesses 3222 # DTB accesses
+system.cpu.itb.fetch_hits 2403 # ITB hits
system.cpu.itb.fetch_misses 39 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2426 # ITB accesses
+system.cpu.itb.fetch_accesses 2442 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.numCycles 42051 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 8528 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 16754 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2922 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2995 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1927 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1100 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 2403 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 389 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14718 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.138334 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.533627 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11723 79.65% 79.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 324 2.20% 81.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 234 1.59% 83.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 214 1.45% 84.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 255 1.73% 86.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 243 1.65% 88.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 264 1.79% 90.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 187 1.27% 91.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1274 8.66% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2769 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 14718 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.069487 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.398421 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9297 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1311 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2827 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1242 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 247 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 15491 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2627 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups
+system.cpu.rename.SquashCycles 1242 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9496 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 220 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2672 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 534 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 14802 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 4 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 481 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 11114 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 18470 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 18461 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 6544 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 484 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1358 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 13092 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 10822 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 61 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6316 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3704 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 14718 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.735290 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.419888 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10506 71.38% 71.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1362 9.25% 80.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 966 6.56% 87.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 797 5.42% 92.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 583 3.96% 96.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 288 1.96% 98.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 161 1.09% 99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 41 0.28% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14718 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 18 15.38% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 61 52.14% 67.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 38 32.48% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7283 67.30% 67.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2401 22.19% 89.53% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1133 10.47% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10779 # Type of FU issued
-system.cpu.iq.rate 0.256332 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 112 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 10822 # Type of FU issued
+system.cpu.iq.rate 0.257354 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 117 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010811 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 36519 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 19441 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9646 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10926 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 74 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1607 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 493 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 138 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 1242 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 105 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 13210 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1358 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 383 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 506 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 10117 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2138 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 705 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 89 # number of nop insts executed
-system.cpu.iew.exec_refs 3230 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1589 # Number of branches executed
-system.cpu.iew.exec_stores 1095 # Number of stores executed
-system.cpu.iew.exec_rate 0.239495 # Inst execution rate
-system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9612 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5069 # num instructions producing a value
-system.cpu.iew.wb_consumers 6811 # num instructions consuming a value
+system.cpu.iew.exec_refs 3235 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1594 # Number of branches executed
+system.cpu.iew.exec_stores 1097 # Number of stores executed
+system.cpu.iew.exec_rate 0.240589 # Inst execution rate
+system.cpu.iew.wb_sent 9800 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9656 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5168 # num instructions producing a value
+system.cpu.iew.wb_consumers 7004 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.229626 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.737864 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6822 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 13476 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.474102 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.366169 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10977 81.46% 81.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1202 8.92% 90.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 500 3.71% 94.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 222 1.65% 95.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 141 1.05% 96.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 79 0.59% 97.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 99 0.73% 98.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 80 0.59% 98.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 176 1.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13476 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
-system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 176 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 26369 # The number of ROB reads
-system.cpu.rob.rob_writes 27413 # The number of ROB writes
-system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 26160 # The number of ROB reads
+system.cpu.rob.rob_writes 27673 # The number of ROB writes
+system.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 27333 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads
system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12784 # number of integer regfile reads
-system.cpu.int_regfile_writes 7268 # number of integer regfile writes
+system.cpu.int_regfile_reads 12844 # number of integer regfile reads
+system.cpu.int_regfile_writes 7306 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 417 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 276750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 159.493349 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1913 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 6.092357 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 159.493349 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.077878 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.077878 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 5088 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits
-system.cpu.icache.overall_hits::total 1898 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses
-system.cpu.icache.overall_misses::total 489 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency
+system.cpu.icache.tags.tag_accesses 5120 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 5120 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1913 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1913 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1913 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1913 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1913 # number of overall hits
+system.cpu.icache.overall_hits::total 1913 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses
+system.cpu.icache.overall_misses::total 490 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 31404750 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 31404750 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 31404750 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 31404750 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 31404750 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 31404750 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2403 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2403 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 2403 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2403 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 2403 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2403 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.203912 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.203912 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.203912 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.203912 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.203912 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.203912 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64091.326531 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64091.326531 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64091.326531 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 64091.326531 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64091.326531 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64091.326531 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 174 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 174 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 174 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 174 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22044500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 22044500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22044500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 22044500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22044500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 22044500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131086 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.131086 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.131086 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69982.539683 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69982.539683 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69982.539683 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69982.539683 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69982.539683 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69982.539683 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 219.991091 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006691 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.576725 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 60.414366 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004870 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.006714 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4399 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4399 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses
system.cpu.l2cache.overall_misses::total 488 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21690000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 29408000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 21690000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 13435750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 35125750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 21690000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 13435750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 35125750 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21718500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7799500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 29518000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5388750 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5388750 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 21718500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 13188250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 34906750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 21718500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 13188250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 34906750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69167.197452 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76465.686275 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70956.730769 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74843.750000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74843.750000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71530.225410 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71530.225410 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17737500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6477000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24214500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4818250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4818250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17737500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11295250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 29032750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17737500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11295250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 29032750 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17765000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6546500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24311500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4505750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4505750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17765000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11052250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 28817250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17765000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11052250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 28817250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56576.433121 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64181.372549 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58441.105769 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62579.861111 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62579.861111 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56576.433121 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63518.678161 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59051.741803 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56576.433121 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63518.678161 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59051.741803 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 107.231811 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2229 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 107.281632 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2231 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.810345 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 12.821839 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 107.231811 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.026180 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 107.281632 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.026192 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.026192 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 5696 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5696 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1725 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1725 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2229 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2229 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2229 # number of overall hits
-system.cpu.dcache.overall_hits::total 2229 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 2231 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2231 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2231 # number of overall hits
+system.cpu.dcache.overall_hits::total 2231 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses
system.cpu.dcache.overall_misses::total 530 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11460500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11460500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 25449978 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 25449978 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 36910478 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 36910478 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 36910478 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 36910478 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11477000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11477000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 23139722 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 23139722 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 34616722 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 34616722 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 34616722 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 34616722 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1896 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1896 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2761 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2761 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2761 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2761 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090190 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.090190 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.191959 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.191959 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.191959 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.191959 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67116.959064 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67116.959064 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64456.050139 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64456.050139 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65314.569811 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65314.569811 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65314.569811 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65314.569811 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 1676 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.900000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7909000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7909000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5463750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5463750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13372750 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 13372750 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13372750 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 13372750 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053797 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053797 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.063021 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.063021 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77539.215686 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77539.215686 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75885.416667 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75885.416667 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/alpha/tru64/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 17:24:20
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 10:38:16
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 11990500 because target called exit()
+Exiting @ tick 11975500 because target called exit()
sim_ticks 11975500 # Number of ticks simulated
final_tick 11975500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56599 # Simulator instruction rate (inst/s)
-host_op_rate 56579 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 283759448 # Simulator tick rate (ticks/s)
-host_mem_usage 265424 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 28986 # Simulator instruction rate (inst/s)
+host_op_rate 28981 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 145369893 # Simulator tick rate (ticks/s)
+host_mem_usage 220536 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.tot_pkt_size::total 17472 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 17472 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 344500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2556250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2554750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 21.3 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 1176 # Number of BP lookups
-system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 1179 # Number of BP lookups
+system.cpu.branchPred.condPredicted 620 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 253 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 254 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 31.467662 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 31.513648 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 710 # DTB read hits
+system.cpu.dtb.read_hits 712 # DTB read hits
system.cpu.dtb.read_misses 31 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 741 # DTB read accesses
+system.cpu.dtb.read_accesses 743 # DTB read accesses
system.cpu.dtb.write_hits 368 # DTB write hits
system.cpu.dtb.write_misses 20 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 388 # DTB write accesses
-system.cpu.dtb.data_hits 1078 # DTB hits
+system.cpu.dtb.data_hits 1080 # DTB hits
system.cpu.dtb.data_misses 51 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 1129 # DTB accesses
-system.cpu.itb.fetch_hits 1065 # ITB hits
+system.cpu.dtb.data_accesses 1131 # DTB accesses
+system.cpu.itb.fetch_hits 1070 # ITB hits
system.cpu.itb.fetch_misses 30 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 1095 # ITB accesses
+system.cpu.itb.fetch_accesses 1100 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.numCycles 23952 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 4342 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 7011 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 1176 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1209 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 531 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 7041 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 1179 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 466 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1215 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 516 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1065 # Number of cache lines fetched
+system.cpu.fetch.CacheLines 1070 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 7705 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.909929 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.316850 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 7706 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.913704 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.320621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 6496 84.31% 84.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 53 0.69% 85.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 115 1.49% 86.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 95 1.23% 87.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 176 2.28% 90.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 76 0.99% 90.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 64 0.83% 91.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 65 0.84% 92.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 565 7.33% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 6491 84.23% 84.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 53 0.69% 84.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 117 1.52% 86.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 96 1.25% 87.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 176 2.28% 89.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 76 0.99% 90.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 64 0.83% 91.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 66 0.86% 92.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 567 7.36% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 7705 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.049098 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.292710 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5480 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 569 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 1153 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 7706 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.049223 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.293963 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5479 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 562 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 1164 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 497 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 6199 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 6225 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 5578 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles 497 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 5576 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 257 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1063 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 5900 # Number of instructions processed by rename
+system.cpu.rename.RunCycles 1068 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 28 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 5913 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 4279 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 6674 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 6667 # Number of integer rename lookups
+system.cpu.rename.IQFullEvents 20 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RenamedOperands 4287 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 6690 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 6683 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 2511 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 2519 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 956 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 469 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 93 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 4966 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 4974 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 4045 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 4048 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2341 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1389 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined 2349 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1396 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 7705 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.524984 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.239779 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 7706 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.525305 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.241065 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 6081 78.92% 78.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 6082 78.93% 78.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 565 7.33% 86.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 401 5.20% 91.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 263 3.41% 94.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 200 2.60% 97.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 120 1.56% 99.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 47 0.61% 99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 198 2.57% 97.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 121 1.57% 99.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 48 0.62% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 7705 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 7706 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 2864 70.80% 70.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 2866 70.80% 70.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.83% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 785 19.41% 90.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 395 9.77% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 786 19.42% 90.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 395 9.76% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 4045 # Type of FU issued
-system.cpu.iq.rate 0.168879 # Inst issue rate
+system.cpu.iq.FU_type_0::total 4048 # Type of FU issued
+system.cpu.iq.rate 0.169005 # Inst issue rate
system.cpu.iq.fu_busy_cnt 44 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010878 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 15880 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 7311 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 3652 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.010870 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 15887 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 7327 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 4082 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 4085 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 541 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 175 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 176 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 5308 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 497 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 231 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 5316 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 956 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 469 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 742 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 190 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 3860 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 744 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 188 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 336 # number of nop insts executed
-system.cpu.iew.exec_refs 1130 # number of memory reference insts executed
+system.cpu.iew.exec_refs 1132 # number of memory reference insts executed
system.cpu.iew.exec_branches 644 # Number of branches executed
system.cpu.iew.exec_stores 388 # Number of stores executed
-system.cpu.iew.exec_rate 0.160947 # Inst execution rate
-system.cpu.iew.wb_sent 3738 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 3658 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1710 # num instructions producing a value
-system.cpu.iew.wb_consumers 2211 # num instructions consuming a value
+system.cpu.iew.exec_rate 0.161156 # Inst execution rate
+system.cpu.iew.wb_sent 3742 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 3661 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1713 # num instructions producing a value
+system.cpu.iew.wb_consumers 2215 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.152722 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.773406 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.152847 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.773363 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 2726 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 2734 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 7211 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.357232 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.199732 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 7209 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.357331 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.199884 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 6342 87.95% 87.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 6340 87.95% 87.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 204 2.83% 90.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 308 4.27% 95.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 114 1.58% 96.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 7211 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 7209 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 12203 # The number of ROB reads
-system.cpu.rob.rob_writes 11111 # The number of ROB writes
+system.cpu.rob.rob_reads 12209 # The number of ROB reads
+system.cpu.rob.rob_writes 11130 # The number of ROB writes
system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 16247 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 16246 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 10.034353 # CPI: Cycles Per Instruction
system.cpu.cpi_total 10.034353 # CPI: Total CPI of All Threads
system.cpu.ipc 0.099658 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.099658 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 4672 # number of integer regfile reads
-system.cpu.int_regfile_writes 2825 # number of integer regfile writes
+system.cpu.int_regfile_reads 4676 # number of integer regfile reads
+system.cpu.int_regfile_writes 2829 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.respLayer1.occupancy 133500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 93.052511 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 815 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 93.052678 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 820 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 188 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 4.335106 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 4.361702 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 93.052511 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 93.052678 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.045436 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.045436 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.091797 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 2318 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 2318 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 815 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 815 # number of overall hits
-system.cpu.icache.overall_hits::total 815 # number of overall hits
+system.cpu.icache.tags.tag_accesses 2328 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 2328 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 820 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 820 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 820 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 820 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 820 # number of overall hits
+system.cpu.icache.overall_hits::total 820 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses
system.cpu.icache.overall_misses::total 250 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17506249 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17506249 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17506249 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17506249 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17506249 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17506249 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1065 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1065 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1065 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1065 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1065 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1065 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234742 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.234742 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.234742 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.234742 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.234742 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.234742 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70024.996000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70024.996000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70024.996000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70024.996000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70024.996000 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17505249 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17505249 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17505249 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17505249 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17505249 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 17505249 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1070 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1070 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1070 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1070 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1070 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1070 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233645 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.233645 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.233645 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.233645 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.233645 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.233645 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70020.996000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70020.996000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70020.996000 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70020.996000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70020.996000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70020.996000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13110499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 13110499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13110499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 13110499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13110499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 13110499 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176526 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.176526 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176526 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.176526 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69736.696809 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69736.696809 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69736.696809 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69736.696809 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13109499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 13109499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13109499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 13109499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13109499 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 13109499 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175701 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.175701 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175701 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.175701 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69731.377660 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69731.377660 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69731.377660 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69731.377660 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69731.377660 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69731.377660 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 121.888429 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 121.888470 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 249 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250749 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637680 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 93.250833 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 28.637638 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.003720 # Average percentage of cache occupancy
system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
system.cpu.l2cache.overall_misses::total 273 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12921750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 17574250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12920750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4652000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 17572750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1688000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1688000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 12921750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6340500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 19262250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 12921750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6340500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 19262250 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 12920750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6340000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 19260750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 12920750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6340000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 19260750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68732.712766 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76270.491803 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70579.317269 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68727.393617 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76262.295082 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70573.293173 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70333.333333 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70333.333333 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70557.692308 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68732.712766 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74594.117647 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70557.692308 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68727.393617 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74588.235294 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70552.197802 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68727.393617 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74588.235294 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70552.197802 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 45.583444 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 759 # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 761 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 8.929412 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 8.952941 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 45.583444 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.011129 # Average percentage of cache occupancy
system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1995 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1995 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 546 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 546 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 1999 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1999 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 548 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 548 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 759 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 759 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 759 # number of overall hits
-system.cpu.dcache.overall_hits::total 759 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 761 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 761 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 761 # number of overall hits
+system.cpu.dcache.overall_hits::total 761 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 13179000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13179000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13179000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 661 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 661 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 955 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 955 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 955 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 955 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173979 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.173979 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 957 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 957 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 957 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 957 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173454 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.173454 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.205236 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.205236 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.205236 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.205236 # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.204807 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.204807 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.204807 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.204807 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68493.478261 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 68493.478261 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65459.876543 # average WriteReq miss latency
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4713000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4713000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6427000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6427000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6427000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6427000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092284 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092284 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6426500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6426500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092006 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.089005 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089005 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.089005 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77270.491803 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77270.491803 # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088819 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.088819 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088819 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.088819 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77262.295082 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77262.295082 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71395.833333 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71395.833333 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75611.764706 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75611.764706 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75605.882353 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75605.882353 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75605.882353 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75605.882353 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
profile=0
progress_interval=0
simpoint_start_insts=
+socket_id=0
switched_out=false
system=system
tracer=system.cpu.checker.tracer
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/arm/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:05:52
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 11:25:19
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.checker.isa: ISA system set to: 0 0x5d826c0
- 0: system.cpu.isa: ISA system set to: 0 0x5d826c0
+ 0: system.cpu.checker.isa: ISA system set to: 0 0x54ee6d0
+ 0: system.cpu.isa: ISA system set to: 0 0x54ee6d0
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 16981000 because target called exit()
+Exiting @ tick 16786000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 16955000 # Number of ticks simulated
-final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 16786000 # Number of ticks simulated
+final_tick 16786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 43189 # Simulator instruction rate (inst/s)
-host_op_rate 53887 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 159459409 # Simulator tick rate (ticks/s)
-host_mem_usage 309444 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 36444 # Simulator instruction rate (inst/s)
+host_op_rate 45472 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 133219523 # Simulator tick rate (ticks/s)
+host_mem_usage 259336 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 392 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1029429286 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 465149529 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1494578816 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1029429286 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1029429286 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1029429286 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 465149529 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1494578816 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 392 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankRdBursts::2 20 # Per bank write bursts
system.physmem.perBankRdBursts::3 42 # Per bank write bursts
system.physmem.perBankRdBursts::4 17 # Per bank write bursts
-system.physmem.perBankRdBursts::5 34 # Per bank write bursts
+system.physmem.perBankRdBursts::5 33 # Per bank write bursts
system.physmem.perBankRdBursts::6 35 # Per bank write bursts
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
-system.physmem.perBankRdBursts::9 7 # Per bank write bursts
+system.physmem.perBankRdBursts::9 8 # Per bank write bursts
system.physmem.perBankRdBursts::10 28 # Per bank write bursts
system.physmem.perBankRdBursts::11 42 # Per bank write bursts
system.physmem.perBankRdBursts::12 9 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 16897500 # Total gap between requests
+system.physmem.totGap 16721500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 396.387097 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 264.062800 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 334.835382 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17 27.42% 45.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8 12.90% 58.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7 11.29% 69.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2 3.23% 72.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5 8.06% 85.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 1.61% 87.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
-system.physmem.totQLat 3795000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3300000 # Total ticks spent queuing
+system.physmem.totMemAccLat 10650000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8418.37 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27168.37 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1494.58 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1494.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.56 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.68 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 326 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 43105.87 # Average gap between requests
+system.physmem.avgGap 42656.89 # Average gap between requests
system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 15324750 # Time in different power states
+system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1475906812 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 351 # Transaction distribution
+system.membus.throughput 1494578816 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 350 # Transaction distribution
system.membus.trans_dist::ReadResp 350 # Transaction distribution
-system.membus.trans_dist::ReadExReq 41 # Transaction distribution
-system.membus.trans_dist::ReadExResp 41 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 25024 # Total data (bytes)
+system.membus.trans_dist::ReadExReq 42 # Transaction distribution
+system.membus.trans_dist::ReadExResp 42 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 784 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 25088 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 479500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3655500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 21.8 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 2481 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 2517 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1805 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 697 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 2002 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 714 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 35.664336 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 294 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 33911 # number of cpu cycles simulated
+system.cpu.numCycles 33573 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6921 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12073 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1008 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2659 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2378 # Number of cycles fetch has spent blocked
+system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13089 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.162808 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.572483 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10430 79.69% 79.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 226 1.73% 81.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 203 1.55% 82.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 238 1.82% 84.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 231 1.76% 86.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 269 2.06% 88.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 93 0.71% 89.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 145 1.11% 90.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1254 9.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2426 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 13089 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.074971 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.359604 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6910 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2688 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2492 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 31 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 385 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13358 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 539 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7139 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 151 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2277 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2296 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 258 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12614 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 195 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 12625 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57590 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 52228 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 47 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6952 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 329 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2826 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1583 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11316 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8961 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 149 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5288 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14803 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 13089 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.684621 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.402607 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9594 73.30% 73.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1210 9.24% 82.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 823 6.29% 88.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 494 3.77% 92.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 479 3.66% 96.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 298 2.28% 98.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 131 1.00% 99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 49 0.37% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13089 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 2.71% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 138 62.44% 65.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 77 34.84% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5369 59.92% 59.92% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2357 26.30% 86.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1223 13.65% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
-system.cpu.iq.rate 0.263071 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8961 # Type of FU issued
+system.cpu.iq.rate 0.266911 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 221 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31345 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16624 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8077 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9162 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1626 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 645 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11366 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2826 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1583 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 266 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 376 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8568 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 393 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1437 # Number of branches executed
-system.cpu.iew.exec_stores 1160 # Number of stores executed
-system.cpu.iew.exec_rate 0.251364 # Inst execution rate
-system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3883 # num instructions producing a value
-system.cpu.iew.wb_consumers 7789 # num instructions consuming a value
+system.cpu.iew.exec_nop 1 # number of nop insts executed
+system.cpu.iew.exec_refs 3332 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1443 # Number of branches executed
+system.cpu.iew.exec_stores 1172 # Number of stores executed
+system.cpu.iew.exec_rate 0.255205 # Inst execution rate
+system.cpu.iew.wb_sent 8256 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8093 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3919 # num instructions producing a value
+system.cpu.iew.wb_consumers 8062 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.241057 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.486108 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5642 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 326 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 12121 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.472651 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.325156 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9924 81.87% 81.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 978 8.07% 89.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 402 3.32% 93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 224 1.85% 95.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 175 1.44% 96.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 212 1.75% 98.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 50 0.41% 98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 33 0.27% 98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 123 1.01% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12121 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4591 # Number of instructions committed
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5729 # Class of committed instruction
-system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 123 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23248 # The number of ROB reads
-system.cpu.rob.rob_writes 23415 # The number of ROB writes
-system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 23212 # The number of ROB reads
+system.cpu.rob.rob_writes 23723 # The number of ROB writes
+system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 20484 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4591 # Number of Instructions Simulated
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39214 # number of integer regfile reads
-system.cpu.int_regfile_writes 7985 # number of integer regfile writes
+system.cpu.cpi 7.312786 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.312786 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.136747 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.136747 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39407 # number of integer regfile reads
+system.cpu.int_regfile_writes 7992 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
+system.cpu.misc_regfile_reads 3253 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.throughput 1662337662 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 395 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 394 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 577 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 870 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 27712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 27712 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 480500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 4 # number of replacements
-system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks.
+system.cpu.icache.tags.replacements 1 # number of replacements
+system.cpu.icache.tags.tagsinuse 148.488883 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1601 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 5.520690 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4184 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits
-system.cpu.icache.overall_hits::total 1584 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses
-system.cpu.icache.overall_misses::total 363 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 148.488883 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.072504 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.072504 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.141113 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 4226 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 4226 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
+system.cpu.icache.overall_hits::total 1601 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses
+system.cpu.icache.overall_misses::total 367 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 23960000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 23960000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 23960000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 23960000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 23960000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 23960000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186484 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.186484 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.186484 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.186484 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.186484 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.186484 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65286.103542 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 65286.103542 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 65286.103542 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 65286.103542 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 53.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19152500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 19152500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19152500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 19152500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19152500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 19152500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147358 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.147358 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.147358 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66043.103448 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66043.103448 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66043.103448 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66043.103448 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66043.103448 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66043.103448 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 185.364644 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 37 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.105714 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.907401 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 46.457243 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004239 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001418 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005657 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses 3864 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 3864 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
+system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
+system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
-system.cpu.l2cache.overall_hits::total 40 # number of overall hits
+system.cpu.l2cache.overall_hits::total 37 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 355 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
system.cpu.l2cache.overall_misses::total 397 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18683000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6637250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 25320250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3108750 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3108750 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 18683000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9746000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 28429000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 18683000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9746000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 28429000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 287 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 392 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 287 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 434 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 287 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total 434 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.940767 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.905612 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.940767 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.914747 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.940767 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.914747 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69196.296296 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78085.294118 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71324.647887 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74017.857143 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74017.857143 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71609.571788 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71609.571788 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15291000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5345250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20636250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2596250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2596250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15291000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7941500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23232500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15291000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7941500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23232500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892857 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.903226 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.903226 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56633.333333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66815.625000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58960.714286 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61815.476190 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61815.476190 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 87.019573 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 16.438356 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 87.019573 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.021245 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.021245 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 5964 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5964 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1782 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1782 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
-system.cpu.dcache.overall_hits::total 2373 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 2378 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2378 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2378 # number of overall hits
+system.cpu.dcache.overall_hits::total 2378 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
-system.cpu.dcache.overall_misses::total 496 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 507 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 507 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 507 # number of overall misses
+system.cpu.dcache.overall_misses::total 507 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613493 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11613493 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 20684250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 20684250 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 32297743 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 32297743 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 32297743 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 32297743 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1972 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2885 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2885 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2885 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2885 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096349 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.096349 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.175737 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.175737 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.175737 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.175737 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65250 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65250 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63703.635108 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63703.635108 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 118 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6871755 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6871755 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3151750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3151750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023505 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10023505 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023505 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10023505 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.050953 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.050953 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/arm/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:05:41
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 11:25:21
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x578c380
+ 0: system.cpu.isa: ISA system set to: 0 0x4e56660
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 16981000 because target called exit()
+Exiting @ tick 16786000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 16955000 # Number of ticks simulated
-final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 16786000 # Number of ticks simulated
+final_tick 16786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 52426 # Simulator instruction rate (inst/s)
-host_op_rate 65410 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 193552438 # Simulator tick rate (ticks/s)
-host_mem_usage 308400 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 42967 # Simulator instruction rate (inst/s)
+host_op_rate 53611 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 157060125 # Simulator tick rate (ticks/s)
+host_mem_usage 258920 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
system.physmem.num_reads::total 392 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1029429286 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 465149529 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1494578816 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1029429286 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1029429286 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1029429286 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 465149529 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1494578816 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 392 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankRdBursts::2 20 # Per bank write bursts
system.physmem.perBankRdBursts::3 42 # Per bank write bursts
system.physmem.perBankRdBursts::4 17 # Per bank write bursts
-system.physmem.perBankRdBursts::5 34 # Per bank write bursts
+system.physmem.perBankRdBursts::5 33 # Per bank write bursts
system.physmem.perBankRdBursts::6 35 # Per bank write bursts
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
-system.physmem.perBankRdBursts::9 7 # Per bank write bursts
+system.physmem.perBankRdBursts::9 8 # Per bank write bursts
system.physmem.perBankRdBursts::10 28 # Per bank write bursts
system.physmem.perBankRdBursts::11 42 # Per bank write bursts
system.physmem.perBankRdBursts::12 9 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 16897500 # Total gap between requests
+system.physmem.totGap 16721500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 396.387097 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 264.062800 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 334.835382 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17 27.42% 45.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 8 12.90% 58.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7 11.29% 69.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2 3.23% 72.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5 8.06% 85.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 1.61% 87.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
-system.physmem.totQLat 3795000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3300000 # Total ticks spent queuing
+system.physmem.totMemAccLat 10650000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8418.37 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27168.37 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1494.58 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1494.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 11.56 # Data bus utilization in percentage
-system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads
+system.physmem.busUtil 11.68 # Data bus utilization in percentage
+system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 326 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 43105.87 # Average gap between requests
+system.physmem.avgGap 42656.89 # Average gap between requests
system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 15324750 # Time in different power states
+system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1475906812 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 351 # Transaction distribution
+system.membus.throughput 1494578816 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 350 # Transaction distribution
system.membus.trans_dist::ReadResp 350 # Transaction distribution
-system.membus.trans_dist::ReadExReq 41 # Transaction distribution
-system.membus.trans_dist::ReadExResp 41 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 25024 # Total data (bytes)
+system.membus.trans_dist::ReadExReq 42 # Transaction distribution
+system.membus.trans_dist::ReadExResp 42 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 784 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 25088 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 479500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3655500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 21.8 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 2481 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 2517 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1805 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 697 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 2002 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 714 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 35.664336 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 294 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 33911 # number of cpu cycles simulated
+system.cpu.numCycles 33573 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6921 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12073 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1008 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2659 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2378 # Number of cycles fetch has spent blocked
+system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13089 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.162808 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.572483 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10430 79.69% 79.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 226 1.73% 81.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 203 1.55% 82.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 238 1.82% 84.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 231 1.76% 86.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 269 2.06% 88.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 93 0.71% 89.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 145 1.11% 90.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1254 9.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2426 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 13089 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.074971 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.359604 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6910 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2688 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2492 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 31 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 385 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13358 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 539 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7139 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 151 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2277 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2296 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 258 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12614 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 195 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 12625 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57590 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 52228 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 47 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6952 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 329 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2826 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1583 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11316 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8961 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 149 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5288 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14803 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 13089 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.684621 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.402607 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9594 73.30% 73.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1210 9.24% 82.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 823 6.29% 88.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 494 3.77% 92.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 479 3.66% 96.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 298 2.28% 98.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 131 1.00% 99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 49 0.37% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13089 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 2.71% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 138 62.44% 65.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 77 34.84% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5369 59.92% 59.92% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2357 26.30% 86.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1223 13.65% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
-system.cpu.iq.rate 0.263071 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8961 # Type of FU issued
+system.cpu.iq.rate 0.266911 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 221 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31345 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16624 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8077 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9162 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1626 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 645 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11366 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2826 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1583 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 266 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 376 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8568 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 393 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1437 # Number of branches executed
-system.cpu.iew.exec_stores 1160 # Number of stores executed
-system.cpu.iew.exec_rate 0.251364 # Inst execution rate
-system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3883 # num instructions producing a value
-system.cpu.iew.wb_consumers 7789 # num instructions consuming a value
+system.cpu.iew.exec_nop 1 # number of nop insts executed
+system.cpu.iew.exec_refs 3332 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1443 # Number of branches executed
+system.cpu.iew.exec_stores 1172 # Number of stores executed
+system.cpu.iew.exec_rate 0.255205 # Inst execution rate
+system.cpu.iew.wb_sent 8256 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8093 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3919 # num instructions producing a value
+system.cpu.iew.wb_consumers 8062 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.241057 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.486108 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5642 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 326 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 12121 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.472651 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.325156 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9924 81.87% 81.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 978 8.07% 89.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 402 3.32% 93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 224 1.85% 95.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 175 1.44% 96.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 212 1.75% 98.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 50 0.41% 98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 33 0.27% 98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 123 1.01% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12121 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4591 # Number of instructions committed
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5729 # Class of committed instruction
-system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 123 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23248 # The number of ROB reads
-system.cpu.rob.rob_writes 23415 # The number of ROB writes
-system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 23212 # The number of ROB reads
+system.cpu.rob.rob_writes 23723 # The number of ROB writes
+system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 20484 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4591 # Number of Instructions Simulated
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39214 # number of integer regfile reads
-system.cpu.int_regfile_writes 7985 # number of integer regfile writes
+system.cpu.cpi 7.312786 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.312786 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.136747 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.136747 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39407 # number of integer regfile reads
+system.cpu.int_regfile_writes 7992 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
+system.cpu.misc_regfile_reads 3253 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.throughput 1662337662 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 395 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 394 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 577 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 870 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 27712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 27712 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 480500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 4 # number of replacements
-system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks.
+system.cpu.icache.tags.replacements 1 # number of replacements
+system.cpu.icache.tags.tagsinuse 148.488883 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1601 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 5.520690 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4184 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits
-system.cpu.icache.overall_hits::total 1584 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses
-system.cpu.icache.overall_misses::total 363 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 148.488883 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.072504 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.072504 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.141113 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 4226 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 4226 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
+system.cpu.icache.overall_hits::total 1601 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses
+system.cpu.icache.overall_misses::total 367 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 23960000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 23960000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 23960000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 23960000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 23960000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 23960000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186484 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.186484 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.186484 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.186484 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.186484 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.186484 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65286.103542 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 65286.103542 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 65286.103542 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 65286.103542 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 53.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19152500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 19152500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19152500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 19152500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19152500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 19152500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147358 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.147358 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.147358 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66043.103448 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66043.103448 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66043.103448 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66043.103448 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66043.103448 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66043.103448 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 185.364644 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 37 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.105714 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.907401 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 46.457243 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004239 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001418 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005657 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses 3864 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 3864 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
+system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
+system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
-system.cpu.l2cache.overall_hits::total 40 # number of overall hits
+system.cpu.l2cache.overall_hits::total 37 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 355 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
system.cpu.l2cache.overall_misses::total 397 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18683000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6637250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 25320250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3108750 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3108750 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 18683000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9746000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 28429000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 18683000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9746000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 28429000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 287 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 392 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 287 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 434 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 287 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total 434 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.940767 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.905612 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.940767 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.914747 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.940767 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.914747 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69196.296296 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78085.294118 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71324.647887 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74017.857143 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74017.857143 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71609.571788 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71609.571788 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15291000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5345250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20636250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2596250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2596250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15291000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7941500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23232500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15291000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7941500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23232500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892857 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.903226 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.903226 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56633.333333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66815.625000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58960.714286 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61815.476190 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61815.476190 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 87.019573 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 16.438356 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 87.019573 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.021245 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.021245 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 5964 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5964 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1782 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1782 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
-system.cpu.dcache.overall_hits::total 2373 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 2378 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2378 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2378 # number of overall hits
+system.cpu.dcache.overall_hits::total 2378 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
-system.cpu.dcache.overall_misses::total 496 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 507 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 507 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 507 # number of overall misses
+system.cpu.dcache.overall_misses::total 507 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613493 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11613493 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 20684250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 20684250 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 32297743 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 32297743 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 32297743 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 32297743 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1972 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2885 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2885 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2885 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2885 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096349 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.096349 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.175737 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.175737 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.175737 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.175737 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65250 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65250 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63703.635108 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63703.635108 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 118 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6871755 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6871755 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3151750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3151750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023505 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10023505 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023505 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10023505 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.050953 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.050953 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/mips/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:53:01
-gem5 started Jan 22 2014 17:28:02
-gem5 executing on u200540-lin
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
+gem5 compiled Jun 21 2014 10:59:13
+gem5 started Jun 21 2014 10:59:41
+gem5 executing on phenom
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 21898500 because target called exit()
+Exiting @ tick 21842500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21843500 # Number of ticks simulated
-final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 21842500 # Number of ticks simulated
+final_tick 21842500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 63396 # Simulator instruction rate (inst/s)
-host_op_rate 63384 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 268482897 # Simulator tick rate (ticks/s)
-host_mem_usage 267540 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 54203 # Simulator instruction rate (inst/s)
+host_op_rate 54195 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 229554116 # Simulator tick rate (ticks/s)
+host_mem_usage 222444 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30464 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 477 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 477 # Number of read requests accepted
+system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 476 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 981572622 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 413139522 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1394712144 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 981572622 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 981572622 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 981572622 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 413139522 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1394712144 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 476 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 476 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 30464 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 30464 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdBursts::12 51 # Per bank write bursts
system.physmem.perBankRdBursts::13 29 # Per bank write bursts
system.physmem.perBankRdBursts::14 77 # Per bank write bursts
-system.physmem.perBankRdBursts::15 8 # Per bank write bursts
+system.physmem.perBankRdBursts::15 7 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 21764000 # Total gap between requests
+system.physmem.totGap 21770000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 477 # Read request sizes (log2)
+system.physmem.readPktSize::6 476 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation
-system.physmem.totQLat 4715500 # Total ticks spent queuing
-system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 108 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 255.407407 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 175.497802 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 250.634672 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 31 28.70% 28.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39 36.11% 64.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 16 14.81% 79.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8 7.41% 87.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 3.70% 90.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1 0.93% 91.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3 2.78% 94.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 0.93% 95.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5 4.63% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 108 # Bytes accessed per row activation
+system.physmem.totQLat 4718000 # Total ticks spent queuing
+system.physmem.totMemAccLat 13643000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2380000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9911.76 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28661.76 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1394.71 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1394.71 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.92 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.90 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 357 # Number of row buffer hits during reads
+system.physmem.readRowHits 358 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 75.21 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45626.83 # Average gap between requests
-system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 45735.29 # Average gap between requests
+system.physmem.pageHitRate 75.21 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 15319000 # Time in different power states
+system.physmem.memoryStateTime::ACT 15316000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1397578227 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 426 # Transaction distribution
-system.membus.trans_dist::ReadResp 426 # Transaction distribution
+system.membus.throughput 1394712144 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 425 # Transaction distribution
+system.membus.trans_dist::ReadResp 425 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 30528 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 952 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 30464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 30464 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 20.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4464750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 2174 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 2178 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1497 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 492 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 491 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 29.596142 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 43688 # number of cpu cycles simulated
+system.cpu.numCycles 43686 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 8839 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13190 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2178 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 749 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3214 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1378 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1314 # Number of cycles fetch has spent blocked
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14424 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.914448 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.226738 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11210 77.72% 77.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1316 9.12% 86.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 106 0.73% 87.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 131 0.91% 88.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 113 0.78% 91.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 150 1.04% 92.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 160 1.11% 93.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 933 6.47% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3025 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 14424 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.049856 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.301927 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8852 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1624 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3059 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 872 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 12284 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles 872 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9006 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 365 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2898 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups
+system.cpu.rename.RunCycles 2923 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 285 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11879 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents 266 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14112 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13884 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 151 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 9223 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8300 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 3436 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2075 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 14424 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.575430 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.252383 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10895 75.53% 75.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1375 9.53% 85.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 844 5.85% 90.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 571 3.96% 94.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 375 2.60% 97.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 225 1.56% 99.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 91 0.63% 99.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14424 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 5 3.09% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 102 62.96% 66.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 55 33.95% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4936 59.47% 59.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2249 27.10% 86.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1106 13.33% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8293 # Type of FU issued
-system.cpu.iq.rate 0.189823 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 160 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8300 # Type of FU issued
+system.cpu.iq.rate 0.189992 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 162 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019518 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31229 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 12679 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8460 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1305 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 270 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 872 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 287 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10750 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 365 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7921 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 379 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1512 # number of nop insts executed
-system.cpu.iew.exec_refs 3186 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1344 # Number of branches executed
-system.cpu.iew.exec_stores 1079 # Number of stores executed
-system.cpu.iew.exec_rate 0.181102 # Inst execution rate
-system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7455 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2921 # num instructions producing a value
-system.cpu.iew.wb_consumers 4197 # num instructions consuming a value
+system.cpu.iew.exec_nop 1515 # number of nop insts executed
+system.cpu.iew.exec_refs 3187 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1350 # Number of branches executed
+system.cpu.iew.exec_stores 1077 # Number of stores executed
+system.cpu.iew.exec_rate 0.181317 # Inst execution rate
+system.cpu.iew.wb_sent 7554 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7469 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2985 # num instructions producing a value
+system.cpu.iew.wb_consumers 4341 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.170970 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.687630 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4930 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 13552 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.428940 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.213640 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11200 82.64% 82.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 943 6.96% 89.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 594 4.38% 93.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 344 2.54% 96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 162 1.20% 97.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 97 0.72% 98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 69 0.51% 98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 41 0.30% 99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13552 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5813 # Number of instructions committed
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5813 # Class of committed instruction
-system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 24239 # The number of ROB reads
-system.cpu.rob.rob_writes 22333 # The number of ROB writes
-system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 24180 # The number of ROB reads
+system.cpu.rob.rob_writes 22370 # The number of ROB writes
+system.cpu.timesIdled 295 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 29262 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5156 # Number of Instructions Simulated
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10743 # number of integer regfile reads
-system.cpu.int_regfile_writes 5234 # number of integer regfile writes
+system.cpu.cpi 8.472847 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 8.472847 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.118024 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.118024 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 10764 # number of integer regfile reads
+system.cpu.int_regfile_writes 5241 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 148 # number of misc regfile reads
-system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution
+system.cpu.toL2Bus.throughput 1403502346 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 428 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 958 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 30656 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 571750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 226500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 17 # number of replacements
-system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 161.396825 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1520 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 4.497041 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 161.396825 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.078807 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.078807 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4268 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits
-system.cpu.icache.overall_hits::total 1514 # number of overall hits
+system.cpu.icache.tags.tag_accesses 4280 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 4280 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1520 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1520 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1520 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1520 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1520 # number of overall hits
+system.cpu.icache.overall_hits::total 1520 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses
system.cpu.icache.overall_misses::total 451 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 31166000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 31166000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 31166000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 31166000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 31166000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 31166000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228818 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.228818 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.228818 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.228818 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.228818 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.228818 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69104.212860 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69104.212860 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69104.212860 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69104.212860 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24162750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 24162750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24162750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 24162750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24162750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 24162750 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.171487 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.171487 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.171487 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71487.426036 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71487.426036 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 221.498533 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 425 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.007059 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.688333 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810199 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 425 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012970 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 4308 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 4308 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 425 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
-system.cpu.l2cache.overall_misses::total 477 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
+system.cpu.l2cache.overall_misses::total 476 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23794750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6985750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 30780500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 23794750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10762000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 34556750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 23794750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10762000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 34556750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 479 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 480 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.993007 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71029.104478 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77619.444444 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72424.705882 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71029.104478 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76326.241135 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72598.214286 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71029.104478 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76326.241135 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72598.214286 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19559250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5880750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19559250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9025000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 28584250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19559250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9025000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 28584250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58385.820896 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65341.666667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59858.823529 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58385.820896 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64007.092199 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60050.945378 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58385.820896 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64007.092199 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60050.945378 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 91.608220 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 91.608220 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.022365 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.022365 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 5965 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5965 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
-system.cpu.dcache.overall_hits::total 2395 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits
+system.cpu.dcache.overall_hits::total 2400 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 150 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 150 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
-system.cpu.dcache.overall_misses::total 510 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses
+system.cpu.dcache.overall_misses::total 512 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 10436500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 10436500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 22532249 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 22532249 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 32968749 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 32968749 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 32968749 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 32968749 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1987 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1987 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2912 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2912 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2912 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2912 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075491 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.075491 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.175824 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.175824 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.175824 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.175824 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69576.666667 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69576.666667 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62243.781768 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62243.781768 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64392.087891 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64392.087891 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64392.087891 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64392.087891 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7079250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7079250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10907499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10907499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10907499 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10907499 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045294 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045294 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.048420 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.048420 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78658.333333 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78658.333333 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/power/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout
+Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:58:44
-gem5 started Jan 22 2014 17:29:11
-gem5 executing on u200540-lin
-command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
+gem5 compiled Jun 21 2014 11:03:15
+gem5 started Jun 21 2014 11:03:43
+gem5 executing on phenom
+command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 18905500 because target called exit()
+Exiting @ tick 19030500 because target called exit()
sim_ticks 19030500 # Number of ticks simulated
final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 79159 # Simulator instruction rate (inst/s)
-host_op_rate 79144 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 259986612 # Simulator tick rate (ticks/s)
-host_mem_usage 262500 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 17395 # Simulator instruction rate (inst/s)
+host_op_rate 17394 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57147442 # Simulator tick rate (ticks/s)
+host_mem_usage 218304 # Number of bytes of host memory used
+host_seconds 0.33 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 199.719469 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 351.121005 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 27 35.06% 35.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18 23.38% 58.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation
-system.physmem.totQLat 3599250 # Total ticks spent queuing
-system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3354000 # Total ticks spent queuing
+system.physmem.totMemAccLat 11716500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 7520.18 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 26270.18 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 11.72 # Data bus utilization in percentage
system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 358 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 28544 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 22.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 2235 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 2252 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1816 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1850 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 602 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1865 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 610 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 32.540541 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 32.707775 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.numCycles 38062 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 7462 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13226 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2252 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 809 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2276 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1296 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 871 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1823 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 11476 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.152492 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.564431 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9200 80.17% 80.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 178 1.55% 81.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 178 1.55% 83.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 145 1.26% 84.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 228 1.99% 86.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 133 1.16% 87.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 261 2.27% 89.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 110 0.96% 90.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1043 9.09% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2089 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 11476 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.059167 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.347486 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 7479 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1089 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2174 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 714 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1980 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename
+system.cpu.decode.DecodedInsts 11804 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 714 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7660 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2016 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 428 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11368 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups
+system.cpu.rename.LQFullEvents 165 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 241 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 9753 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 18286 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 18260 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 4755 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
+system.cpu.rename.skidInsts 259 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2025 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1841 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 10356 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8901 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 8929 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined 4296 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3542 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 11476 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.778059 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.545863 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8265 72.02% 72.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1011 8.81% 80.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 683 5.95% 86.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 469 4.09% 90.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 473 4.12% 94.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 313 2.73% 97.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 182 1.59% 99.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 44 0.38% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 11476 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 73 42.20% 46.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 92 53.18% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11 6.21% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 75 42.37% 48.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 91 51.41% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5476 61.52% 61.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1796 20.18% 81.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5495 61.54% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1798 20.14% 81.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1634 18.30% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8901 # Type of FU issued
-system.cpu.iq.rate 0.233855 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8929 # Type of FU issued
+system.cpu.iq.rate 0.234591 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019823 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 29690 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 14680 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9072 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1064 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 795 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 714 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 160 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10413 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2025 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1841 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8500 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 8526 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1682 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3201 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1350 # Number of branches executed
-system.cpu.iew.exec_stores 1523 # Number of stores executed
-system.cpu.iew.exec_rate 0.223320 # Inst execution rate
-system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8155 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 4187 # num instructions producing a value
-system.cpu.iew.wb_consumers 6623 # num instructions consuming a value
+system.cpu.iew.exec_refs 3211 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1353 # Number of branches executed
+system.cpu.iew.exec_stores 1529 # Number of stores executed
+system.cpu.iew.exec_rate 0.224003 # Inst execution rate
+system.cpu.iew.wb_sent 8294 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8178 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 4388 # num instructions producing a value
+system.cpu.iew.wb_consumers 6958 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.214860 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.630641 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4620 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 10762 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.538190 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.389247 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 8538 79.33% 79.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 887 8.24% 87.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 552 5.13% 92.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 240 2.23% 94.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 177 1.64% 96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 96 0.89% 97.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 118 1.10% 98.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 47 0.44% 99.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 107 0.99% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 10762 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
-system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 21428 # The number of ROB reads
-system.cpu.rob.rob_writes 21442 # The number of ROB writes
-system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 21067 # The number of ROB reads
+system.cpu.rob.rob_writes 21539 # The number of ROB writes
+system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 26586 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads
system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 13470 # number of integer regfile reads
-system.cpu.int_regfile_writes 7047 # number of integer regfile writes
+system.cpu.int_regfile_reads 13502 # number of integer regfile reads
+system.cpu.int_regfile_writes 7065 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 588250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 162000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 169.076059 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1380 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 3.931624 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 169.076059 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.082557 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.082557 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 3971 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 3971 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1369 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1369 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1369 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1369 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1369 # number of overall hits
-system.cpu.icache.overall_hits::total 1369 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses
-system.cpu.icache.overall_misses::total 441 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1810 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1810 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1810 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243646 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.243646 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency
+system.cpu.icache.tags.tag_accesses 3997 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 3997 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1380 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1380 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1380 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1380 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1380 # number of overall hits
+system.cpu.icache.overall_hits::total 1380 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 443 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 443 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 443 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 443 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 443 # number of overall misses
+system.cpu.icache.overall_misses::total 443 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 29586250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 29586250 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 29586250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 29586250 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 29586250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 29586250 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1823 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1823 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1823 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1823 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1823 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1823 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243006 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.243006 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.243006 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.243006 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.243006 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.243006 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66786.117381 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 66786.117381 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 66786.117381 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 66786.117381 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24098750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 24098750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24098750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 24098750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24098750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 24098750 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192540 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.192540 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.192540 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68657.407407 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68657.407407 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 199.437860 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.936913 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31.500947 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005125 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.006086 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 215 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses
system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23687250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4073750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 27761000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3627250 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 23687250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7701000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 31388250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 23687250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7701000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 31388250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68658.695652 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75439.814815 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69576.441103 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77175.531915 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77175.531915 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70377.242152 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70377.242152 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19339750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3409250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22749000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3052750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3052750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19339750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6462000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 25801750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19339750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6462000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 25801750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56057.246377 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63134.259259 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57015.037594 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64952.127660 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64952.127660 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 63.722947 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2180 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 21.372549 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 63.722947 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.015557 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.015557 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5348 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5348 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 5332 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5332 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1465 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1465 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits
-system.cpu.dcache.overall_hits::total 2188 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 2180 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2180 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2180 # number of overall hits
+system.cpu.dcache.overall_hits::total 2180 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses
system.cpu.dcache.overall_misses::total 435 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 7380250 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 7380250 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 21128996 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 21128996 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 28509246 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 28509246 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 28509246 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 28509246 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2623 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2623 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2623 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066284 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.066284 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.166348 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.166348 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.166348 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.166348 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70963.942308 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70963.942308 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63833.824773 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63833.824773 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65538.496552 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65538.496552 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4139250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4139250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3677248 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3677248 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7816498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7816498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816498 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7816498 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035054 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035054 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.039006 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.039006 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75259.090909 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75259.090909 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78239.319149 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78239.319149 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/x86/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 17:29:56
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
+gem5 compiled Jun 21 2014 11:13:07
+gem5 started Jun 21 2014 11:13:51
+gem5 executing on phenom
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 19970500 because target called exit()
+Exiting @ tick 19813000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 20011500 # Number of ticks simulated
-final_tick 20011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 19813000 # Number of ticks simulated
+final_tick 19813000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 41048 # Simulator instruction rate (inst/s)
-host_op_rate 74359 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 152650007 # Simulator tick rate (ticks/s)
-host_mem_usage 284392 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 35950 # Simulator instruction rate (inst/s)
+host_op_rate 65125 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 132368943 # Simulator tick rate (ticks/s)
+host_mem_usage 240140 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26496 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 414 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 873097969 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 450940709 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1324038678 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 873097969 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 873097969 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 873097969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 450940709 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1324038678 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 415 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 885075456 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 458688740 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1343764195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 885075456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 885075456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 885075456 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 458688740 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1343764195 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 417 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 33 # Per bank write bursts
+system.physmem.perBankRdBursts::0 34 # Per bank write bursts
system.physmem.perBankRdBursts::1 1 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5 # Per bank write bursts
+system.physmem.perBankRdBursts::2 6 # Per bank write bursts
system.physmem.perBankRdBursts::3 8 # Per bank write bursts
system.physmem.perBankRdBursts::4 50 # Per bank write bursts
system.physmem.perBankRdBursts::5 44 # Per bank write bursts
-system.physmem.perBankRdBursts::6 20 # Per bank write bursts
+system.physmem.perBankRdBursts::6 21 # Per bank write bursts
system.physmem.perBankRdBursts::7 36 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23 # Per bank write bursts
+system.physmem.perBankRdBursts::8 22 # Per bank write bursts
system.physmem.perBankRdBursts::9 73 # Per bank write bursts
system.physmem.perBankRdBursts::10 63 # Per bank write bursts
system.physmem.perBankRdBursts::11 17 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 19963000 # Total gap between requests
+system.physmem.totGap 19764000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 415 # Read request sizes (log2)
+system.physmem.readPktSize::6 417 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 161.697208 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 270.249471 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 163.075563 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 270.532528 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 33 34.02% 34.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 34 35.05% 69.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13 13.40% 82.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 36 37.11% 71.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 9 9.28% 80.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 5 5.15% 85.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 6 6.19% 91.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 3.09% 94.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation
-system.physmem.totQLat 4234000 # Total ticks spent queuing
-system.physmem.totMemAccLat 12015250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10202.41 # Average queueing delay per DRAM burst
+system.physmem.totQLat 3851250 # Total ticks spent queuing
+system.physmem.totMemAccLat 11670000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9235.61 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28952.41 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1327.24 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27985.61 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1346.99 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1327.24 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1346.99 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.37 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.37 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.52 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.52 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 307 # Number of row buffer hits during reads
+system.physmem.readRowHits 310 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.98 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 74.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 48103.61 # Average gap between requests
-system.physmem.pageHitRate 73.98 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 47395.68 # Average gap between requests
+system.physmem.pageHitRate 74.34 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 15333750 # Time in different power states
+system.physmem.memoryStateTime::ACT 15315750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1324038678 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 338 # Transaction distribution
-system.membus.trans_dist::ReadResp 337 # Transaction distribution
+system.membus.throughput 1343764195 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 340 # Transaction distribution
+system.membus.trans_dist::ReadResp 339 # Transaction distribution
system.membus.trans_dist::ReadExReq 77 # Transaction distribution
system.membus.trans_dist::ReadExResp 77 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 26496 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 26624 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 501000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3873250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 19.4 # Layer utilization (%)
+system.membus.reqLayer0.occupancy 508000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3892500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 19.6 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 3083 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3083 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2281 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 725 # Number of BTB hits
+system.cpu.branchPred.lookups 3151 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3151 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 538 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2362 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 784 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 31.784305 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 33.192210 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 213 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 80 # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 40024 # number of cpu cycles simulated
+system.cpu.numCycles 39627 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 10292 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14141 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3083 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3942 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2472 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 5349 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 21900 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.150913 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.666787 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 10249 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 14342 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3151 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 997 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4009 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2516 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 5030 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 499 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 21739 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.176503 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.686230 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 18059 82.46% 82.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 217 0.99% 83.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 142 0.65% 84.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 224 1.02% 85.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 180 0.82% 85.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 201 0.92% 86.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 275 1.26% 88.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 159 0.73% 88.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2443 11.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 17828 82.01% 82.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 213 0.98% 82.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 156 0.72% 83.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 227 1.04% 84.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 194 0.89% 85.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 208 0.96% 86.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 291 1.34% 87.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 168 0.77% 88.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2454 11.29% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 21900 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.077029 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.353313 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 11088 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5242 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3583 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1856 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 24179 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1856 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 11454 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3886 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 592 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3330 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 782 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 22657 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 37 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 664 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 25254 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 55037 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 21739 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.079516 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.361925 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 11168 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4895 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3648 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1891 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 24503 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1891 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 11399 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 477 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 595 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 3548 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 3829 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 23145 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 51 # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents 3750 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 25950 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 56380 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 31990 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 14191 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2053 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 20246 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 17025 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 298 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 9739 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 13977 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 21900 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.777397 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.653011 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 14887 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 1258 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 20529 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 17116 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 311 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10025 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14683 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 21739 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.787341 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.689074 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 16414 74.95% 74.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1544 7.05% 82.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1087 4.96% 86.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 722 3.30% 90.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 701 3.20% 93.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 573 2.62% 96.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 583 2.66% 98.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 16539 76.08% 76.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1246 5.73% 81.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 983 4.52% 86.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 694 3.19% 89.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 782 3.60% 93.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 618 2.84% 95.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 580 2.67% 98.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 252 1.16% 99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 45 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 21900 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 21739 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 136 76.40% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 26 14.61% 91.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 16 8.99% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 13665 80.26% 80.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 13738 80.26% 80.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5 0.03% 80.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1970 11.51% 91.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1393 8.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 17025 # Type of FU issued
-system.cpu.iq.rate 0.425370 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 181 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010631 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 56421 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 30018 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 17116 # Type of FU issued
+system.cpu.iq.rate 0.431928 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010400 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 56452 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 30591 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 15728 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 17199 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 17287 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 197 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1240 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 684 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3085 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 20272 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 1891 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 262 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 20557 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 31 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 571 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 687 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 16122 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 697 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 16214 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1838 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 902 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3126 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1623 # Number of branches executed
-system.cpu.iew.exec_stores 1273 # Number of stores executed
-system.cpu.iew.exec_rate 0.402808 # Inst execution rate
-system.cpu.iew.wb_sent 15864 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 15645 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 10128 # num instructions producing a value
-system.cpu.iew.wb_consumers 15590 # num instructions consuming a value
+system.cpu.iew.exec_refs 3129 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1636 # Number of branches executed
+system.cpu.iew.exec_stores 1291 # Number of stores executed
+system.cpu.iew.exec_rate 0.409165 # Inst execution rate
+system.cpu.iew.wb_sent 15955 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 15732 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 10485 # num instructions producing a value
+system.cpu.iew.wb_consumers 16294 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.390890 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.649647 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.397002 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.643488 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 10536 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 10809 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 20044 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.486280 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.342641 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 19848 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.491082 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.377621 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 16476 82.20% 82.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1360 6.79% 88.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 589 2.94% 91.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 713 3.56% 95.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 364 1.82% 97.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 16557 83.42% 83.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1016 5.12% 88.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 561 2.83% 91.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 767 3.86% 95.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 387 1.95% 97.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 137 0.69% 97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 118 0.59% 98.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 73 0.37% 98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 232 1.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 20044 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 19848 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
-system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 40115 # The number of ROB reads
-system.cpu.rob.rob_writes 42444 # The number of ROB writes
-system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 18124 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 40172 # The number of ROB reads
+system.cpu.rob.rob_writes 43025 # The number of ROB writes
+system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 17888 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 7.439405 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.439405 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.134419 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.134419 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 20731 # number of integer regfile reads
-system.cpu.int_regfile_writes 12356 # number of integer regfile writes
+system.cpu.cpi 7.365613 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.365613 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.135766 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.135766 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 20766 # number of integer regfile reads
+system.cpu.int_regfile_writes 12432 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
-system.cpu.cc_regfile_reads 8007 # number of cc regfile reads
-system.cpu.cc_regfile_writes 4854 # number of cc regfile writes
-system.cpu.misc_regfile_reads 7133 # number of misc regfile reads
+system.cpu.cc_regfile_reads 8051 # number of cc regfile reads
+system.cpu.cc_regfile_writes 4869 # number of cc regfile writes
+system.cpu.misc_regfile_reads 7177 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1330435000 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
+system.cpu.toL2Bus.throughput 1346994398 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 341 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 340 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 459500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 461000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 236250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 130.942440 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 5.875912 # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 131.410773 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 5.967273 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 130.942440 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.063937 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.063937 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4236 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4236 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits
-system.cpu.icache.overall_hits::total 1610 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses
-system.cpu.icache.overall_misses::total 371 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 25106250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 25106250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 25106250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 25106250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 25106250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 25106250 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187279 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.187279 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.187279 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.187279 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.187279 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.187279 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67671.832884 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67671.832884 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67671.832884 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67671.832884 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67671.832884 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 131.410773 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.064165 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.064165 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 275 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.134277 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 4301 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 4301 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1641 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1641 # number of overall hits
+system.cpu.icache.overall_hits::total 1641 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses
+system.cpu.icache.overall_misses::total 372 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25012250 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25012250 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 25012250 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25012250 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 25012250 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 25012250 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184799 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.184799 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.184799 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.184799 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.184799 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.184799 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67237.231183 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67237.231183 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67237.231183 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67237.231183 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67237.231183 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67237.231183 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19660000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 19660000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19660000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 19660000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19660000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 19660000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71751.824818 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71751.824818 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71751.824818 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71751.824818 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 275 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 275 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19562000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 19562000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19562000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 19562000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19562000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 19562000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136612 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.136612 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136612 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.136612 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71134.545455 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71134.545455 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71134.545455 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71134.545455 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71134.545455 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71134.545455 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 163.759335 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 164.472388 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 339 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.002950 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.011600 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 32.747734 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.481156 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 32.991232 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004012 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001007 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005019 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010345 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 338 # number of ReadReq misses
+system.cpu.l2cache.overall_hits::total 1 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 66 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 340 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
-system.cpu.l2cache.overall_misses::total 415 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19374500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5212250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 24586750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5445500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5445500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 19374500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10657750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 30032250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 19374500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10657750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 30032250 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses
+system.cpu.l2cache.overall_misses::total 417 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19276500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5050250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 24326750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5454250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5454250 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 19276500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10504500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 29781000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 19276500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10504500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 29781000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 275 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 341 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 275 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 274 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 275 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996350 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.984848 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.994118 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996364 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.997067 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70968.864469 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80188.461538 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72741.863905 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70720.779221 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70720.779221 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72366.867470 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70968.864469 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75054.577465 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72366.867470 # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996364 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996364 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70352.189781 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76518.939394 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71549.264706 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70834.415584 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70834.415584 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70352.189781 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73458.041958 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71417.266187 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70352.189781 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73458.041958 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71417.266187 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15946000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4413250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20359250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4486000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4486000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15946000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8899250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 24845250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15946000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8899250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 24845250 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15837000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4238250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20075250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4493750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4493750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15837000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8732000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 24569000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15837000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8732000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 24569000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997067 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58410.256410 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67896.153846 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60234.467456 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58259.740260 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58259.740260 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58410.256410 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62670.774648 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59868.072289 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57799.270073 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64215.909091 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59044.852941 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58360.389610 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58360.389610 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57799.270073 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61062.937063 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58918.465228 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57799.270073 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61062.937063 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58918.465228 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 83.261165 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2335 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 83.263820 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2308 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 16.443662 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 16.253521 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 83.261165 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.020327 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.020327 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 83.263820 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.020328 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.020328 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5232 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5232 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 5178 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5178 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1450 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1450 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2335 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2335 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2335 # number of overall hits
-system.cpu.dcache.overall_hits::total 2335 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 2308 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2308 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2308 # number of overall hits
+system.cpu.dcache.overall_hits::total 2308 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 210 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 210 # number of overall misses
system.cpu.dcache.overall_misses::total 210 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9645750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9645750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5703500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5703500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 15349250 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 15349250 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 15349250 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 15349250 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1610 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1610 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9474500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9474500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5711750 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5711750 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 15186250 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 15186250 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 15186250 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 15186250 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1583 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1583 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2545 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2545 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2545 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2545 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082609 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.082609 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2518 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2518 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2518 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2518 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084018 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.084018 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.082515 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.082515 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.082515 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.082515 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72524.436090 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 72524.436090 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74071.428571 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74071.428571 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73091.666667 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73091.666667 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73091.666667 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.083400 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.083400 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.083400 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.083400 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71236.842105 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71236.842105 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74178.571429 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 74178.571429 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72315.476190 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72315.476190 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72315.476190 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72315.476190 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5522500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5522500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10809750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10809750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10809750 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10809750 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040994 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040994 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5115250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5115250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5531250 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5531250 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10646500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10646500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10646500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10646500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041693 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041693 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.056189 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056189 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.056189 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80109.848485 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80109.848485 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71720.779221 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71720.779221 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75592.657343 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75592.657343 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056791 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.056791 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056791 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.056791 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77503.787879 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77503.787879 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71834.415584 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71834.415584 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74451.048951 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74451.048951 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74451.048951 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74451.048951 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
errout=cerr
euid=100
eventq_index=0
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
+tXAW=30000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 17 2014 14:58:40
-gem5 started Apr 17 2014 20:39:31
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
+gem5 compiled Jun 21 2014 10:36:29
+gem5 started Jun 21 2014 10:38:01
+gem5 executing on phenom
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Hello world!
Hello world!
-Exiting @ tick 24279500 because target called exit()
+Exiting @ tick 24521000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated
-sim_ticks 24520500 # Number of ticks simulated
-final_tick 24520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 24521000 # Number of ticks simulated
+final_tick 24521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 60032 # Simulator instruction rate (inst/s)
-host_op_rate 60027 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 115480799 # Simulator tick rate (ticks/s)
-host_mem_usage 266308 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 36221 # Simulator instruction rate (inst/s)
+host_op_rate 36219 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69681363 # Simulator tick rate (ticks/s)
+host_mem_usage 222160 # Number of bytes of host memory used
+host_seconds 0.35 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 40128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22656 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62528 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 40128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 40128 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 627 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 354 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 981 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1636508228 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 923961583 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2560469811 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1636508228 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1636508228 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1636508228 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 923961583 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2560469811 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 981 # Number of read requests accepted
+system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 977 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1636474858 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 913502712 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2549977570 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1636474858 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1636474858 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1636474858 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 913502712 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2549977570 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 977 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 981 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 977 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 62784 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 62528 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 62784 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 62528 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 83 # Per bank write bursts
-system.physmem.perBankRdBursts::1 156 # Per bank write bursts
+system.physmem.perBankRdBursts::1 153 # Per bank write bursts
system.physmem.perBankRdBursts::2 77 # Per bank write bursts
system.physmem.perBankRdBursts::3 59 # Per bank write bursts
system.physmem.perBankRdBursts::4 87 # Per bank write bursts
system.physmem.perBankRdBursts::5 49 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
-system.physmem.perBankRdBursts::7 51 # Per bank write bursts
+system.physmem.perBankRdBursts::7 50 # Per bank write bursts
system.physmem.perBankRdBursts::8 42 # Per bank write bursts
-system.physmem.perBankRdBursts::9 38 # Per bank write bursts
+system.physmem.perBankRdBursts::9 39 # Per bank write bursts
system.physmem.perBankRdBursts::10 31 # Per bank write bursts
system.physmem.perBankRdBursts::11 33 # Per bank write bursts
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
-system.physmem.perBankRdBursts::13 123 # Per bank write bursts
-system.physmem.perBankRdBursts::14 69 # Per bank write bursts
+system.physmem.perBankRdBursts::13 121 # Per bank write bursts
+system.physmem.perBankRdBursts::14 70 # Per bank write bursts
system.physmem.perBankRdBursts::15 36 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 24372500 # Total gap between requests
+system.physmem.totGap 24370500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 981 # Read request sizes (log2)
+system.physmem.readPktSize::6 977 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 352 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 195 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 65 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 339 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 353 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 70 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 218 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 281.541284 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 177.445911 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 284.903946 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 77 35.32% 35.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 55 25.23% 60.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 27 12.39% 72.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 16 7.34% 80.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 7 3.21% 83.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 13 5.96% 89.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7 3.21% 92.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 4 1.83% 94.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 12 5.50% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 218 # Bytes accessed per row activation
-system.physmem.totQLat 12385000 # Total ticks spent queuing
-system.physmem.totMemAccLat 30778750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4905000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12624.87 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 216 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 282.666667 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 175.603788 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 291.640046 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 78 36.11% 36.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 56 25.93% 62.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 23 10.65% 72.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 15 6.94% 79.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 8 3.70% 83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 13 6.02% 89.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4 1.85% 91.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 6 2.78% 93.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 13 6.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 216 # Bytes accessed per row activation
+system.physmem.totQLat 13158000 # Total ticks spent queuing
+system.physmem.totMemAccLat 31476750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4885000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13467.76 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31374.87 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2560.47 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 32217.76 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2549.98 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2560.47 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2549.98 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 20.00 # Data bus utilization in percentage
-system.physmem.busUtilRead 20.00 # Data bus utilization in percentage for reads
+system.physmem.busUtil 19.92 # Data bus utilization in percentage
+system.physmem.busUtilRead 19.92 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 2.35 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 2.45 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 755 # Number of row buffer hits during reads
+system.physmem.readRowHits 752 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.96 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 76.97 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 24844.55 # Average gap between requests
-system.physmem.pageHitRate 76.96 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 24944.22 # Average gap between requests
+system.physmem.pageHitRate 76.97 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 22000 # Time in different power states
system.physmem.memoryStateTime::REF 780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22830500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 2560469811 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 835 # Transaction distribution
-system.membus.trans_dist::ReadResp 835 # Transaction distribution
-system.membus.trans_dist::ReadExReq 146 # Transaction distribution
-system.membus.trans_dist::ReadExResp 146 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1962 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1962 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62784 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 62784 # Total data (bytes)
+system.membus.throughput 2549977570 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 832 # Transaction distribution
+system.membus.trans_dist::ReadResp 832 # Transaction distribution
+system.membus.trans_dist::ReadExReq 145 # Transaction distribution
+system.membus.trans_dist::ReadExResp 145 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1954 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1954 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 62528 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1242500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 5.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 9118000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 37.2 # Layer utilization (%)
+system.membus.reqLayer0.occupancy 1224000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 5.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 9060500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 36.9 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 6989 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3925 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1533 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 5035 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 984 # Number of BTB hits
+system.cpu.branchPred.lookups 7716 # Number of BP lookups
+system.cpu.branchPred.condPredicted 4270 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1557 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 5587 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 1032 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 19.543198 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 915 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 192 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 18.471452 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 986 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 191 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4762 # DTB read hits
-system.cpu.dtb.read_misses 100 # DTB read misses
+system.cpu.dtb.read_hits 4952 # DTB read hits
+system.cpu.dtb.read_misses 97 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4862 # DTB read accesses
-system.cpu.dtb.write_hits 2071 # DTB write hits
-system.cpu.dtb.write_misses 87 # DTB write misses
+system.cpu.dtb.read_accesses 5049 # DTB read accesses
+system.cpu.dtb.write_hits 2131 # DTB write hits
+system.cpu.dtb.write_misses 85 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2158 # DTB write accesses
-system.cpu.dtb.data_hits 6833 # DTB hits
-system.cpu.dtb.data_misses 187 # DTB misses
+system.cpu.dtb.write_accesses 2216 # DTB write accesses
+system.cpu.dtb.data_hits 7083 # DTB hits
+system.cpu.dtb.data_misses 182 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 7020 # DTB accesses
-system.cpu.itb.fetch_hits 5544 # ITB hits
-system.cpu.itb.fetch_misses 61 # ITB misses
+system.cpu.dtb.data_accesses 7265 # DTB accesses
+system.cpu.itb.fetch_hits 5823 # ITB hits
+system.cpu.itb.fetch_misses 63 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5605 # ITB accesses
+system.cpu.itb.fetch_accesses 5886 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 49042 # number of cpu cycles simulated
+system.cpu.numCycles 49043 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 1654 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 38433 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6989 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1899 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 6450 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1925 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 460 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5544 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 915 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 29475 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.303919 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.725203 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 1643 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 42292 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 7716 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 2018 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 7014 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1937 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5823 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 939 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 28717 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.472717 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.866777 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 23025 78.12% 78.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 583 1.98% 80.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 359 1.22% 81.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 471 1.60% 82.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 462 1.57% 84.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 415 1.41% 85.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 502 1.70% 87.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 480 1.63% 89.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 3178 10.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21703 75.58% 75.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 628 2.19% 77.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 370 1.29% 79.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 488 1.70% 80.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 478 1.66% 82.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 438 1.53% 83.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 544 1.89% 85.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 450 1.57% 87.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 3618 12.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 29475 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.142511 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.783675 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 40916 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9080 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5548 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 476 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2800 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 645 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 409 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 33474 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 772 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2800 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 41622 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 5416 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1578 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 5169 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2235 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 30891 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 88 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2140 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 23128 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 38063 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 38045 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 28717 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.157331 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.862345 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 40485 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 6963 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 6425 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 184 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3240 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 753 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 442 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 37312 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 851 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3240 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 41162 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2710 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1573 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 5916 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2696 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 34656 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 211 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 347 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1943 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 26052 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 42763 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 42745 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 13988 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 50 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 5886 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 3185 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 16912 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 53 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 1929 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 3424 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1551 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2945 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1353 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 17 # Number of conflicting loads.
-system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 26844 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 22133 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 13088 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 8205 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 29475 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.750908 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.340856 # Number of insts issued each cycle
+system.cpu.memDep1.insertedLoads 3264 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1487 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 43 # Number of conflicting loads.
+system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 29904 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 80 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 23616 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 291 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 16167 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 10244 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 28717 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.822370 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.487550 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 19871 67.42% 67.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3550 12.04% 79.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2637 8.95% 88.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1555 5.28% 93.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1051 3.57% 97.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 510 1.73% 98.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 229 0.78% 99.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 60 0.20% 99.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 12 0.04% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 19680 68.53% 68.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 2792 9.72% 78.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2104 7.33% 85.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1715 5.97% 91.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1290 4.49% 96.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 654 2.28% 98.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 354 1.23% 99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 107 0.37% 99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 21 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 29475 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 28717 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7 3.80% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 112 60.87% 64.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 65 35.33% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 15 7.43% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 116 57.43% 64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 71 35.15% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7355 65.30% 65.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2746 24.38% 89.73% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1157 10.27% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7921 66.06% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2841 23.69% 89.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1223 10.20% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 11263 # Type of FU issued
+system.cpu.iq.FU_type_0::total 11990 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7126 65.56% 65.57% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.58% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.58% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.60% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2577 23.71% 89.31% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1162 10.69% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 7753 66.69% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.71% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.71% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.73% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead 2675 23.01% 89.74% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1193 10.26% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 10870 # Type of FU issued
-system.cpu.iq.FU_type::total 22133 0.00% 0.00% # Type of FU issued
-system.cpu.iq.rate 0.451307 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 101 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 184 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.003750 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.004563 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.008313 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 74007 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 40020 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19098 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total 11626 # Type of FU issued
+system.cpu.iq.FU_type::total 23616 0.00% 0.00% # Type of FU issued
+system.cpu.iq.rate 0.481537 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 102 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 202 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.004319 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.004234 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.008554 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 76400 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 46161 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 20401 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 22291 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 23792 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 93 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2002 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 585 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2241 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 686 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 438 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 66 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 422 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 68 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1762 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.squashedLoads 2081 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 488 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedStores 622 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 324 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 310 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2800 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2321 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 27123 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 657 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 6130 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 244 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1350 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20610 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2500 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2378 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4878 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1523 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3240 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 485 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 30193 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 6688 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 3038 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 461 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 265 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1140 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1405 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 21973 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0 2613 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1 2460 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 5073 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1643 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 111 # number of nop insts executed
-system.cpu.iew.exec_nop::1 89 # number of nop insts executed
-system.cpu.iew.exec_nop::total 200 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3609 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3448 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 7057 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1643 # Number of branches executed
-system.cpu.iew.exec_branches::1 1628 # Number of branches executed
-system.cpu.iew.exec_branches::total 3271 # Number of branches executed
-system.cpu.iew.exec_stores::0 1109 # Number of stores executed
-system.cpu.iew.exec_stores::1 1070 # Number of stores executed
-system.cpu.iew.exec_stores::total 2179 # Number of stores executed
-system.cpu.iew.exec_rate 0.420252 # Inst execution rate
-system.cpu.iew.wb_sent::0 9814 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9602 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 19416 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9666 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9452 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19118 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 4886 # num instructions producing a value
-system.cpu.iew.wb_producers::1 4825 # num instructions producing a value
-system.cpu.iew.wb_producers::total 9711 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6421 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6315 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 12736 # num instructions consuming a value
+system.cpu.iew.exec_nop::0 117 # number of nop insts executed
+system.cpu.iew.exec_nop::1 92 # number of nop insts executed
+system.cpu.iew.exec_nop::total 209 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3756 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3554 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 7310 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1740 # Number of branches executed
+system.cpu.iew.exec_branches::1 1743 # Number of branches executed
+system.cpu.iew.exec_branches::total 3483 # Number of branches executed
+system.cpu.iew.exec_stores::0 1143 # Number of stores executed
+system.cpu.iew.exec_stores::1 1094 # Number of stores executed
+system.cpu.iew.exec_stores::total 2237 # Number of stores executed
+system.cpu.iew.exec_rate 0.448035 # Inst execution rate
+system.cpu.iew.wb_sent::0 10504 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 10265 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 20769 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 10336 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 10085 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 20421 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 5409 # num instructions producing a value
+system.cpu.iew.wb_producers::1 5311 # num instructions producing a value
+system.cpu.iew.wb_producers::total 10720 # num instructions producing a value
+system.cpu.iew.wb_consumers::0 7242 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 7116 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 14358 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0 0.197096 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.192733 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.389829 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.760941 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.764054 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.762484 # average fanout of values written-back
+system.cpu.iew.wb_rate::0 0.210754 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.205636 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.416390 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.746893 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.746346 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.746622 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 14324 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 17385 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1153 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 29419 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.434379 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.208273 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1147 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 28645 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.446116 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.297173 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23668 80.45% 80.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 3132 10.65% 91.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1070 3.64% 94.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 465 1.58% 96.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 341 1.16% 97.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 243 0.83% 98.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 188 0.64% 98.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 91 0.31% 99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 221 0.75% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 23444 81.84% 81.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 2590 9.04% 90.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1028 3.59% 94.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 428 1.49% 95.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 310 1.08% 97.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 198 0.69% 97.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 191 0.67% 98.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 175 0.61% 99.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 281 0.98% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 29419 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 28645 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::total 6390 # Class of committed instruction
system.cpu.commit.op_class::total 12779 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 281 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 133441 # The number of ROB reads
-system.cpu.rob.rob_writes 57026 # The number of ROB writes
-system.cpu.timesIdled 384 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 19567 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 140714 # The number of ROB reads
+system.cpu.rob.rob_writes 63601 # The number of ROB writes
+system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 20326 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
system.cpu.committedInsts::total 12745 # Number of Instructions Simulated
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12745 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0 7.696485 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 7.695277 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.847940 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.129929 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.129950 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.259879 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 25834 # number of integer regfile reads
-system.cpu.int_regfile_writes 14427 # number of integer regfile writes
+system.cpu.cpi::0 7.696642 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 7.695434 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.848019 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.129927 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.129947 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.259874 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 27593 # number of integer regfile reads
+system.cpu.int_regfile_writes 15533 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 2565689933 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 837 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 837 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
+system.cpu.toL2Bus.throughput 2555197586 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 834 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 834 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1258 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 708 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1966 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1958 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40256 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22656 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 62912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 62912 # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22400 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 62656 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 489500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1033500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1029000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 567500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 559500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
-system.cpu.icache.tags.replacements::0 6 # number of replacements
+system.cpu.icache.tags.replacements::0 8 # number of replacements
system.cpu.icache.tags.replacements::1 0 # number of replacements
-system.cpu.icache.tags.replacements::total 6 # number of replacements
-system.cpu.icache.tags.tagsinuse 315.418856 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 4518 # Total number of references to valid blocks.
+system.cpu.icache.tags.replacements::total 8 # number of replacements
+system.cpu.icache.tags.tagsinuse 316.348744 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 4766 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 629 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 7.182830 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 7.577107 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 315.418856 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.154013 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.154013 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 623 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 316.348744 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.154467 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.154467 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.304199 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 11703 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 11703 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 4518 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 4518 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 4518 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 4518 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 4518 # number of overall hits
-system.cpu.icache.overall_hits::total 4518 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses
-system.cpu.icache.overall_misses::total 1019 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 68389495 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 68389495 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 68389495 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 68389495 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 68389495 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 68389495 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5537 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5537 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5537 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5537 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5537 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5537 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184035 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.184035 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.184035 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.184035 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.184035 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.184035 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67114.322866 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67114.322866 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67114.322866 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67114.322866 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67114.322866 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67114.322866 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 2439 # number of cycles access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 12259 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 12259 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 4766 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 4766 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 4766 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 4766 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 4766 # number of overall hits
+system.cpu.icache.overall_hits::total 4766 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses
+system.cpu.icache.overall_misses::total 1049 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 70831996 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 70831996 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 70831996 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 70831996 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 70831996 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 70831996 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5815 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5815 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5815 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5815 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5815 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5815 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180396 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.180396 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.180396 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.180396 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.180396 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.180396 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67523.351764 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67523.351764 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67523.351764 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67523.351764 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67523.351764 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67523.351764 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 2854 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 69 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 42.051724 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 41.362319 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 390 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 390 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 390 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 390 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 390 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 420 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 420 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 420 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 420 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 420 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 629 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 629 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 629 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 629 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 629 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 629 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46962248 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 46962248 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46962248 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 46962248 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46962248 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 46962248 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113599 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113599 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113599 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.113599 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113599 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.113599 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74661.761526 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74661.761526 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74661.761526 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74661.761526 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74661.761526 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74661.761526 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47492998 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 47492998 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47492998 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 47492998 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47492998 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 47492998 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108169 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108169 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108169 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.108169 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108169 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.108169 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75505.561208 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75505.561208 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75505.561208 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75505.561208 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75505.561208 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75505.561208 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 437.810879 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 437.665813 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 835 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.002395 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 832 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.002404 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 315.920365 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 121.890513 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009641 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.003720 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.013361 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 835 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 507 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025482 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 8845 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 8845 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.125803 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 120.540010 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009678 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.003679 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.013357 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 832 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 324 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 508 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 8809 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 8809 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 627 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 208 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 835 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 205 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 832 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 627 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 354 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 981 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 977 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 627 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 354 # number of overall misses
-system.cpu.l2cache.overall_misses::total 981 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46310000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17053750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 63363750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11492750 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 11492750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 46310000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 28546500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 74856500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 46310000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 28546500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 74856500 # number of overall miss cycles
+system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses
+system.cpu.l2cache.overall_misses::total 977 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46839000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17030000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 63869000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11685500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 11685500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 46839000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 28715500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 75554500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 46839000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 28715500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 75554500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 629 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 208 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 205 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 834 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 629 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 354 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 983 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 350 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 979 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 629 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 354 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 983 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 979 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996820 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.997611 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996820 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.997965 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.997957 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996820 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.997965 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73859.649123 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81989.182692 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75884.730539 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78717.465753 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78717.465753 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73859.649123 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80639.830508 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76306.320082 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73859.649123 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80639.830508 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76306.320082 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.997957 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74703.349282 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83073.170732 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 76765.625000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80589.655172 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80589.655172 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74703.349282 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82044.285714 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77333.162743 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74703.349282 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82044.285714 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77333.162743 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 208 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 835 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 832 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 354 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 977 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 354 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 981 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38486500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14492750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52979250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9689750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9689750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38486500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24182500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 62669000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38486500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24182500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 62669000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 977 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39039000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14504000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53543000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9900000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9900000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39039000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24404000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 63443000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39039000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24404000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 63443000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996820 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997611 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996820 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997965 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997957 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996820 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997965 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61381.977671 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69676.682692 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63448.203593 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66368.150685 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66368.150685 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61381.977671 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68312.146893 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63882.772681 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61381.977671 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68312.146893 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63882.772681 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997957 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62263.157895 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70751.219512 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64354.567308 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68275.862069 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68275.862069 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62263.157895 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69725.714286 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64936.540430 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62263.157895 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69725.714286 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64936.540430 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 215.425119 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 4587 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 354 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.957627 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 213.554041 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 4807 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 350 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.734286 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 215.425119 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.052594 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.052594 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.086426 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 11596 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 11596 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 3561 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3561 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1026 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1026 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 4587 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 4587 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 4587 # number of overall hits
-system.cpu.dcache.overall_hits::total 4587 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 330 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 330 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 704 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 704 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1034 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1034 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1034 # number of overall misses
-system.cpu.dcache.overall_misses::total 1034 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 24450500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 24450500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 50450459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 50450459 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 74900959 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 74900959 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 74900959 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 74900959 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 3891 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 3891 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data 213.554041 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.052137 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.052137 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.085449 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 12052 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 12052 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 3785 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 3785 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 4807 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 4807 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 4807 # number of overall hits
+system.cpu.dcache.overall_hits::total 4807 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 336 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 336 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1044 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1044 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1044 # number of overall misses
+system.cpu.dcache.overall_misses::total 1044 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 24770500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 24770500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 51632692 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 51632692 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 76403192 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 76403192 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 76403192 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 76403192 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 4121 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 4121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 5621 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 5621 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 5621 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 5621 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084811 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.084811 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.406936 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.406936 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.183953 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.183953 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.183953 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.183953 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74092.424242 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 74092.424242 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71662.583807 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 71662.583807 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.064797 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72438.064797 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72438.064797 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72438.064797 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 4010 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 5851 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 5851 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 5851 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 5851 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081534 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.081534 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.178431 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.178431 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.178431 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.178431 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73721.726190 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 73721.726190 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72927.531073 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72927.531073 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73183.134100 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73183.134100 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73183.134100 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73183.134100 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 4134 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 101 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 118 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.702970 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.033898 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 122 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 122 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 558 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 558 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 208 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 208 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 354 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 354 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 354 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 354 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17272750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17272750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11640746 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11640746 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28913496 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 28913496 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28913496 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 28913496 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053457 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053457 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062978 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.062978 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062978 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.062978 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83042.067308 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83042.067308 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79731.136986 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79731.136986 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81676.542373 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 81676.542373 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81676.542373 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 81676.542373 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 131 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 131 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 694 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 694 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 694 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 694 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17244500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 17244500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11834247 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11834247 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29078747 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 29078747 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29078747 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 29078747 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.049745 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.049745 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059819 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.059819 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059819 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.059819 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84119.512195 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84119.512195 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81615.496552 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81615.496552 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83082.134286 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 83082.134286 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83082.134286 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 83082.134286 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 17:29:34
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
+gem5 compiled Jun 21 2014 11:07:38
+gem5 started Jun 21 2014 11:08:19
+gem5 executing on phenom
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 26616500 because target called exit()
+Exiting @ tick 26706500 because target called exit()
sim_ticks 26706500 # Number of ticks simulated
final_tick 26706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64712 # Simulator instruction rate (inst/s)
-host_op_rate 64708 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 119701044 # Simulator tick rate (ticks/s)
-host_mem_usage 272800 # Number of bytes of host memory used
-host_seconds 0.22 # Real time elapsed on the host
+host_inst_rate 22395 # Simulator instruction rate (inst/s)
+host_op_rate 22394 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41428038 # Simulator tick rate (ticks/s)
+host_mem_usage 228784 # Number of bytes of host memory used
+host_seconds 0.64 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 802800816 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 805197237 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 352273791 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1155074607 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 802800816 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 802800816 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 802800816 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 1157471028 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 805197237 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 805197237 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 805197237 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 352273791 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1155074607 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 482 # Number of read requests accepted
+system.physmem.bw_total::total 1157471028 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 483 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 483 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 30912 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 30912 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 102 # Per bank write bursts
system.physmem.perBankRdBursts::1 29 # Per bank write bursts
-system.physmem.perBankRdBursts::2 50 # Per bank write bursts
+system.physmem.perBankRdBursts::2 51 # Per bank write bursts
system.physmem.perBankRdBursts::3 24 # Per bank write bursts
system.physmem.perBankRdBursts::4 19 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 482 # Read request sizes (log2)
+system.physmem.readPktSize::6 483 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 403.200000 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 265.551535 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 347.027861 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 404.114286 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 265.832819 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 348.256092 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 22 31.43% 48.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9 12.86% 61.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3 4.29% 65.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 5.71% 71.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 4.29% 75.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 6 8.57% 84.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 1.43% 85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5 7.14% 82.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2 2.86% 85.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 14.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation
-system.physmem.totQLat 2602000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11639500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5398.34 # Average queueing delay per DRAM burst
+system.physmem.totQLat 2649500 # Total ticks spent queuing
+system.physmem.totMemAccLat 11705750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2415000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5485.51 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24148.34 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1155.07 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24235.51 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1157.47 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1155.07 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1157.47 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 9.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 9.02 # Data bus utilization in percentage for reads
+system.physmem.busUtil 9.04 # Data bus utilization in percentage
+system.physmem.busUtilRead 9.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 403 # Number of row buffer hits during reads
+system.physmem.readRowHits 404 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 55073.65 # Average gap between requests
-system.physmem.pageHitRate 83.61 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 54959.63 # Average gap between requests
+system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1553250 # Time in different power states
system.physmem.memoryStateTime::REF 780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 21299250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1155074607 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 399 # Transaction distribution
-system.membus.trans_dist::ReadResp 399 # Transaction distribution
+system.membus.throughput 1157471028 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 400 # Transaction distribution
+system.membus.trans_dist::ReadResp 400 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 30848 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 966 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 966 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 30912 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 606500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4499500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 16.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4506000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 16.9 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 6716 # Number of BP lookups
-system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 6723 # Number of BP lookups
+system.cpu.branchPred.condPredicted 4462 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 2432 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 5029 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 2435 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 48.419169 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 53414 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12411 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 31121 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9132 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 9191 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 12428 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 31151 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6723 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 2879 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 9139 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3047 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8960 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 33531 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.928126 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.121319 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 33327 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.934708 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.127415 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24399 72.77% 72.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4510 13.45% 86.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 474 1.41% 87.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 392 1.17% 88.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 680 2.03% 90.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 706 2.11% 92.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 235 0.70% 93.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 253 0.75% 94.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1882 5.61% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24188 72.58% 72.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4512 13.54% 86.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 474 1.42% 87.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 392 1.18% 88.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 683 2.05% 90.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 706 2.12% 92.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 235 0.71% 93.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 253 0.76% 94.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1884 5.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 33531 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.125735 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.582638 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12927 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 10191 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 8340 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 201 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13569 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 456 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9204 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 7948 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 482 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 33327 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.125866 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.583199 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 12851 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 10052 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 8399 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 150 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1875 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 29050 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1875 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13476 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 163 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9186 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 7977 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 650 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 26689 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 152 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups
+system.cpu.rename.SQFullEvents 339 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 23975 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 49504 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 40958 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 10156 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2747 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 2667 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2291 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 22517 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 22544 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21121 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 21140 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 7903 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined 7925 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 5519 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 33531 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.629895 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.256216 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 33327 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.634321 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.264898 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24281 72.41% 72.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3570 10.65% 83.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2315 6.90% 89.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1704 5.08% 95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 886 2.64% 97.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 470 1.40% 99.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 240 0.72% 99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 45 0.13% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24173 72.53% 72.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3454 10.36% 82.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2274 6.82% 89.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1733 5.20% 94.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 917 2.75% 97.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 470 1.41% 99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 241 0.72% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 33531 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 33327 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 15650 74.10% 74.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 15664 74.10% 74.10% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2109 9.99% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 3362 15.90% 90.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2114 10.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 21121 # Type of FU issued
-system.cpu.iq.rate 0.395421 # Inst issue rate
+system.cpu.iq.FU_type_0::total 21140 # Type of FU issued
+system.cpu.iq.rate 0.395776 # Inst issue rate
system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 76017 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 31101 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.006954 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 75851 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 31150 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19533 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21268 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21287 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 843 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 300 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 24306 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 403 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewSquashCycles 1875 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 24333 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions
+system.cpu.iew.iewDispStoreInsts 2291 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions
+system.cpu.iew.predictedNotTakenIncorrect 947 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1211 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20085 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1047 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 1055 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1134 # number of nop insts executed
-system.cpu.iew.exec_refs 5224 # number of memory reference insts executed
-system.cpu.iew.exec_branches 4239 # Number of branches executed
-system.cpu.iew.exec_stores 2022 # Number of stores executed
-system.cpu.iew.exec_rate 0.375819 # Inst execution rate
-system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 19522 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 9116 # num instructions producing a value
-system.cpu.iew.wb_consumers 11226 # num instructions consuming a value
+system.cpu.iew.exec_refs 5227 # number of memory reference insts executed
+system.cpu.iew.exec_branches 4240 # Number of branches executed
+system.cpu.iew.exec_stores 2025 # Number of stores executed
+system.cpu.iew.exec_rate 0.376025 # Inst execution rate
+system.cpu.iew.wb_sent 19760 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 19533 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 9201 # num instructions producing a value
+system.cpu.iew.wb_consumers 11404 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.365485 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.812043 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.365691 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.806822 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9046 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9073 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 31659 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.478916 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.176623 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 31452 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.482068 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.184176 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 24337 76.87% 76.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 4081 12.89% 89.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1353 4.27% 94.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 763 2.41% 96.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 348 1.10% 97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 270 0.85% 98.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 322 1.02% 99.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 68 0.21% 99.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 24226 77.03% 77.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 3950 12.56% 89.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1330 4.23% 93.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 819 2.60% 96.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 349 1.11% 97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 271 0.86% 98.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 322 1.02% 99.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 31659 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 31452 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 54927 # The number of ROB reads
-system.cpu.rob.rob_writes 50296 # The number of ROB writes
-system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 19883 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 54747 # The number of ROB reads
+system.cpu.rob.rob_writes 50353 # The number of ROB writes
+system.cpu.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 20087 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 3.700055 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.700055 # CPI: Total CPI of All Threads
system.cpu.ipc 0.270266 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.270266 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 32043 # number of integer regfile reads
-system.cpu.int_regfile_writes 17841 # number of integer regfile writes
-system.cpu.misc_regfile_reads 6919 # number of misc regfile reads
+system.cpu.int_regfile_reads 32058 # number of integer regfile reads
+system.cpu.int_regfile_writes 17849 # number of integer regfile writes
+system.cpu.misc_regfile_reads 6922 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 1159867448 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
+system.cpu.toL2Bus.throughput 1162263868 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 31040 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 564000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 566000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 235000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 187.422918 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 188.199882 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 14.414201 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 187.422918 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.091515 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.091515 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst 188.199882 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.091894 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.091894 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.164551 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 11095 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 11095 # Number of data accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.165039 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 11098 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 11098 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits
system.cpu.icache.overall_hits::total 4872 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses
-system.cpu.icache.overall_misses::total 507 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 31638750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 31638750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 31638750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 31638750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 31638750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 31638750 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62403.846154 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62403.846154 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62403.846154 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62403.846154 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62403.846154 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62403.846154 # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst 508 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 508 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 508 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 508 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 508 # number of overall misses
+system.cpu.icache.overall_misses::total 508 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 31702750 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 31702750 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 31702750 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 31702750 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 31702750 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 31702750 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094424 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.094424 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.094424 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.094424 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.094424 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.094424 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62406.988189 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62406.988189 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62406.988189 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 62406.988189 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62406.988189 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62406.988189 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22516000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 22516000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22516000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 22516000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22516000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 22516000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66813.056380 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66813.056380 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66813.056380 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66813.056380 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66813.056380 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66813.056380 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22584000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 22584000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22584000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 22584000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22584000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 22584000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062825 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.062825 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.062825 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66816.568047 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66816.568047 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66816.568047 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66816.568047 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66816.568047 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66816.568047 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 221.271055 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 222.048188 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.815406 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 34.455649 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005701 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006753 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.592876 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 34.455312 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005725 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001051 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.006776 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 4354 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 4354 # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012207 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 4363 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 4363 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 482 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
+system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
-system.cpu.l2cache.overall_misses::total 482 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22159000 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::total 483 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22226000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4637250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 26796250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6037250 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6037250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 22159000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10674500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 32833500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 22159000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10674500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 32833500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::total 26863250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6075250 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6075250 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 22226000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10712500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 32938500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 22226000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10712500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 32938500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 337 # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994065 # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994083 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.995012 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66146.268657 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66148.809524 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72457.031250 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.521303 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72737.951807 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72737.951807 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66146.268657 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72615.646259 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68119.294606 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66146.268657 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72615.646259 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68119.294606 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.125000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73195.783133 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73195.783133 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66148.809524 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72874.149660 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68195.652174 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66148.809524 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72874.149660 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68195.652174 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17946500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18000000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3851750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21798250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5016750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5016750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17946500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8868500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 26815000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17946500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8868500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 26815000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21851750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5060250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5060250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 26912000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 26912000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.641791 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.428571 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60183.593750 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54632.205514 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60442.771084 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60442.771084 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.641791 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60329.931973 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55632.780083 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.641791 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60329.931973 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55632.780083 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54629.375000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60966.867470 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60966.867470 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.428571 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60625.850340 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55718.426501 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.428571 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60625.850340 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55718.426501 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 99.054052 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 99.055513 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 99.054052 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 99.055513 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.024183 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024183 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses
system.cpu.dcache.overall_misses::total 535 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 7967250 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7967250 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 25697977 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 25697977 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 33665227 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 33665227 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 33665227 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 33665227 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 7969250 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 7969250 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 25782224 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 25782224 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 33751474 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 33751474 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 33751474 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 33751474 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63232.142857 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63232.142857 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62831.239609 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62831.239609 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62925.657944 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62925.657944 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62925.657944 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62925.657944 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 776 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63248.015873 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63248.015873 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63037.222494 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63037.222494 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63086.867290 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63086.867290 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63086.867290 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63086.867290 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 851 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 25 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.040000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.392857 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4701750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4701750 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6121250 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6121250 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10823000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10823000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10823000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10823000 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6159250 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 6159250 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10861000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10861000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73464.843750 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73464.843750 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73750 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73750 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73625.850340 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73625.850340 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73625.850340 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73625.850340 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74207.831325 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74207.831325 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73884.353741 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73884.353741 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73884.353741 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73884.353741 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
slave=system.system_port system.l2c.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.toL2Bus]
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 17:29:46
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Jun 21 2014 11:07:38
+gem5 started Jun 21 2014 11:08:21
+gem5 executing on phenom
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
[Iteration 1, Thread 2] Got lock
[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
Iteration 1 completed
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
Iteration 2 completed
[Iteration 3, Thread 3] Got lock
[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 3, Thread 2] Got lock
[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
Iteration 3 completed
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 4, Thread 2] Got lock
[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
Iteration 4 completed
[Iteration 5, Thread 2] Got lock
[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
Iteration 5 completed
[Iteration 6, Thread 3] Got lock
[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
Iteration 6 completed
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
Iteration 7 completed
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
Iteration 8 completed
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 9, Thread 2] Got lock
[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
Iteration 9 completed
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
Iteration 10 completed
PASSED :-)
-Exiting @ tick 111025500 because target called exit()
+Exiting @ tick 110970500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000111 # Number of seconds simulated
-sim_ticks 110872500 # Number of ticks simulated
-final_tick 110872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 110970500 # Number of ticks simulated
+final_tick 110970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 118027 # Simulator instruction rate (inst/s)
-host_op_rate 118027 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12557410 # Simulator tick rate (ticks/s)
-host_mem_usage 289008 # Number of bytes of host memory used
-host_seconds 8.83 # Real time elapsed on the host
-sim_insts 1042088 # Number of instructions simulated
-sim_ops 1042088 # Number of ops (including micro ops) simulated
+host_inst_rate 128659 # Simulator instruction rate (inst/s)
+host_op_rate 128659 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 13699808 # Simulator tick rate (ticks/s)
+host_mem_usage 244656 # Number of bytes of host memory used
+host_seconds 8.10 # Real time elapsed on the host
+sim_insts 1042156 # Number of instructions simulated
+sim_ops 1042156 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 42176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 4608 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 659 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 205497305 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 96976257 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 5772396 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 7504115 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 41561253 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 11544792 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 4040677 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7504115 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 380400911 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 205497305 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 5772396 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 41561253 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 4040677 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 256871632 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 205497305 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 96976257 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 5772396 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 7504115 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 41561253 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 11544792 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 4040677 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7504115 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 380400911 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 205315827 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 96890615 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 7497488 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 7497488 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 41524549 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 11534597 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 2306919 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7497488 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 380064972 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 205315827 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 7497488 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 41524549 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 2306919 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 256644784 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 205315827 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 96890615 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 7497488 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 7497488 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 41524549 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 11534597 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 2306919 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7497488 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 380064972 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 660 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 110844500 # Total gap between requests
+system.physmem.totGap 110942500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 403 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 400 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 275.027027 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 186.656156 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 254.302887 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 45 30.41% 30.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 43 29.05% 59.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 21 14.19% 73.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 274.594595 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 184.768834 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 255.591879 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 47 31.76% 31.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39 26.35% 58.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 23 15.54% 73.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation
-system.physmem.totQLat 5597750 # Total ticks spent queuing
-system.physmem.totMemAccLat 17972750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 5904750 # Total ticks spent queuing
+system.physmem.totMemAccLat 18279750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8481.44 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8946.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27231.44 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 380.98 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27696.59 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 380.64 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 380.98 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.98 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
+system.physmem.busUtil 2.97 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 505 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 167946.21 # Average gap between requests
+system.physmem.avgGap 168094.70 # Average gap between requests
system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 48028250 # Time in different power states
+system.physmem.memoryStateTime::IDLE 48408000 # Time in different power states
system.physmem.memoryStateTime::REF 3640000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 57613000 # Time in different power states
+system.physmem.memoryStateTime::ACT 57233250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 380400911 # Throughput (bytes/s)
+system.membus.throughput 380064972 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 529 # Transaction distribution
system.membus.trans_dist::ReadResp 528 # Transaction distribution
system.membus.trans_dist::UpgradeReq 287 # Transaction distribution
system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
-system.membus.trans_dist::ReadExReq 163 # Transaction distribution
+system.membus.trans_dist::ReadExReq 162 # Transaction distribution
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1715 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1715 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 42176 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 925500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 921500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 6302174 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 6294424 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 5.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 417.213115 # Cycle average of tags in use
-system.l2c.tags.total_refs 1443 # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse 416.952741 # Cycle average of tags in use
+system.l2c.tags.total_refs 1442 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks.
+system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 0.799585 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 285.091922 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 58.421534 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 7.040102 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 0.695019 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 55.399606 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 5.410902 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 3.621924 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 0.732522 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks 0.799591 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 285.006820 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 58.406933 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 8.706163 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 0.731992 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 54.635838 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 5.407858 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst 2.562888 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data 0.694658 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.004349 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.000107 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.000133 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.000845 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.000834 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.000055 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst 0.000039 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.006366 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.006362 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 18244 # Number of tag accesses
-system.l2c.tags.data_accesses 18244 # Number of data accesses
+system.l2c.tags.tag_accesses 18236 # Number of tag accesses
+system.l2c.tags.data_accesses 18236 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 413 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 409 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst 423 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1442 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 413 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst 423 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1443 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1442 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 229 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 413 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 409 # number of overall hits
system.l2c.overall_hits::cpu1.data 11 # number of overall hits
system.l2c.overall_hits::cpu2.inst 349 # number of overall hits
system.l2c.overall_hits::cpu2.data 5 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 420 # number of overall hits
+system.l2c.overall_hits::cpu3.inst 423 # number of overall hits
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
-system.l2c.overall_hits::total 1443 # number of overall hits
+system.l2c.overall_hits::total 1442 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 19 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 75 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst 10 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 543 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 19 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 75 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 674 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 359 # number of overall misses
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 15 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 19 # number of overall misses
system.l2c.overall_misses::cpu1.data 13 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 76 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 75 # number of overall misses
system.l2c.overall_misses::cpu2.data 20 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 10 # number of overall misses
+system.l2c.overall_misses::cpu3.inst 7 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 674 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 24533250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 5569000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 1122250 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 24479500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 5371500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 1394250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 5286500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst 658250 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 5296000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 494750 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst 438500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 37813500 # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 6780000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data 943000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 9662250 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 24533250 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 12349000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 1122250 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 5286500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst 658250 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data 1017500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 47475750 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 24533250 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 12349000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 1122250 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 5286500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst 658250 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data 1017500 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 47475750 # number of overall miss cycles
+system.l2c.ReadReq_miss_latency::total 37623500 # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 7056000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 894000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 1355500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data 863500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 10169000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 24479500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 12427500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 1394250 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 968500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 5296000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 1850250 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst 438500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data 938000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 47792500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 24479500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 12427500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 1394250 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 968500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 5296000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 1850250 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst 438500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data 938000 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 47792500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 424 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 424 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2116 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 424 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2116 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.035047 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.044393 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.176887 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst 0.023256 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst 0.016279 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.273552 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.035047 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.044393 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.176887 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.023256 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.016279 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.318526 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.035047 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.044393 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.176887 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.023256 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.016279 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68337.743733 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 75256.756757 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74816.666667 # average ReadReq miss latency
+system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68188.022284 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 72587.837838 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73381.578947 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69559.210526 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65825 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70613.333333 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 70678.571429 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst 62642.857143 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 69638.121547 # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72127.659574 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78583.333333 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 73757.633588 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 65825 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 70438.798220 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 65825 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 70438.798220 # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::total 69288.213628 # average ReadReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 75063.829787 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74500 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 104269.230769 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 71958.333333 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 77625.954198 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 68188.022284 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 73973.214286 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 73381.578947 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 74500 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 70613.333333 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 92512.500000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 62642.857143 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 72153.846154 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 70908.753709 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 68188.022284 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 73973.214286 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 73381.578947 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 74500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 70613.333333 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 92512.500000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 62642.857143 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 72153.846154 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 70908.753709 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.inst 4 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 10 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 13 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 72 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst 7 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 72 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst 7 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 72 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst 7 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19962500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4657000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 698750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19908750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4459500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 858750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4160750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4235250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 431250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 258500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 30444000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 30254500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 199518 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 160016 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 779576 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5606500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 792500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 8028750 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 19962500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 10263500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 698750 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 4160750 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst 431250 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data 855000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 38472750 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 19962500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 10263500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 698750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 4160750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst 431250 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data 855000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 38472750 # number of overall MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 218520 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 170017 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 170017 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 778576 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5892000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 743000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1197000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 713000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 8545000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 19908750 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 10351500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 858750 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 805500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 4235250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 1605750 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst 258500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data 775500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 38799500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 19908750 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 10351500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 858750 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 805500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 4235250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 1605750 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst 258500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data 775500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 38799500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.030374 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.169811 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009302 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.266499 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.030374 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.169811 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009302 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.311909 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.030374 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.169811 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009302 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62932.432432 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69875 # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::total 0.311909 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60263.513514 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 64625 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 57550.094518 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 57191.871456 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10405.714286 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59643.617021 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 66041.666667 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61288.167939 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.376623 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62680.851064 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61916.666667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 92076.923077 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 59416.666667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 65229.007634 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61616.071429 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61961.538462 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80287.500000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 64625 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59653.846154 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 58787.121212 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55766.806723 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61616.071429 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66057.692308 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61961.538462 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58822.916667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80287.500000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 64625 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59653.846154 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 58787.121212 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.toL2Bus.throughput 1690157613 # Throughput (bytes/s)
+system.toL2Bus.throughput 1688665006 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 587 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 356 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 358 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5414 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27136 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 135488 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 51904 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 1624477 # Layer occupancy (ticks)
+system.toL2Bus.tot_pkt_size::total 135424 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 135424 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 1625975 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2708498 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2708248 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1467012 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1463019 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 1928746 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 1929745 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 1148249 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 1153498 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 1927493 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 1921995 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 1209237 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 1183735 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 1936745 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 1936494 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 1133003 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 1159999 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%)
-system.cpu0.branchPred.lookups 82981 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 80783 # Number of conditional branches predicted
+system.cpu0.branchPred.lookups 83070 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 80870 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 80310 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 78265 # Number of BTB hits
+system.cpu0.branchPred.BTBLookups 80399 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 78350 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 97.453617 # BTB Hit Percentage
+system.cpu0.branchPred.BTBHitPct 97.451461 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 221746 # number of cpu cycles simulated
+system.cpu0.numCycles 221942 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 17234 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 492474 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 82981 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 78777 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 161662 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3811 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 13862 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles 17233 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 493008 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 83070 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 78862 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 161826 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3812 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 13755 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingTrapStallCycles 1482 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 492 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 196720 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.503426 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.215057 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.IcacheSquashes 491 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 196747 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.505797 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.214858 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 35058 17.82% 17.82% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 80078 40.71% 58.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 578 0.29% 58.82% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 76182 38.73% 98.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 34921 17.75% 17.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 80152 40.74% 58.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 578 0.29% 58.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 974 0.50% 59.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 477 0.24% 59.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 76267 38.76% 98.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2455 1.25% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2459 1.25% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 196720 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.374216 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.220892 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 17819 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 15483 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 160693 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 280 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2445 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 489648 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 2445 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 18474 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 866 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 14003 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 160341 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 591 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 486805 # Number of instructions processed by rename
-system.cpu0.rename.LSQFullEvents 216 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 332880 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 970801 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 733282 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 319911 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 12969 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 866 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 886 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 3624 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 155743 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 78707 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 75959 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 75775 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 407094 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 910 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 404367 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10771 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 9755 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 351 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 196720 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.055546 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.097437 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 196747 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.374287 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.221337 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 17711 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 15452 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 160920 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 218 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2446 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 490118 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 2446 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 18323 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 441 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 14289 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 160585 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 663 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 487271 # Number of instructions processed by rename
+system.cpu0.rename.SQFullEvents 294 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 333181 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 971741 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 733988 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 320207 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 12974 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 868 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 890 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 3239 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 155891 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 78785 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 76033 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 75852 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 407472 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 912 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 404753 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 136 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10781 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 9726 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 353 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 196747 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.057226 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.098946 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 34036 17.30% 17.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4955 2.52% 19.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 77877 39.59% 59.41% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 77259 39.27% 98.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1573 0.80% 99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 652 0.33% 99.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 34174 17.37% 17.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4673 2.38% 19.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 77781 39.53% 59.28% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 77469 39.37% 98.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1629 0.83% 99.48% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 654 0.33% 99.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 260 0.13% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 91 0.05% 99.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 196720 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 196747 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 57 25.79% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 52 23.53% 49.32% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 60 26.43% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 55 24.23% 50.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 112 49.34% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 170970 42.28% 42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 171127 42.28% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 155279 38.40% 80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 78118 19.32% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 155427 38.40% 80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 78199 19.32% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 404367 # Type of FU issued
-system.cpu0.iq.rate 1.823559 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000547 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1005807 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 418829 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 402541 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total 404753 # Type of FU issued
+system.cpu0.iq.rate 1.823688 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 227 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1006616 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 419219 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 402934 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 404588 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 404980 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 75486 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 75562 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1428 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2445 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 400 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 484514 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 155743 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 78707 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 397 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 484968 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 314 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 155891 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 78785 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 800 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 403298 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 154949 # Number of load instructions executed
+system.cpu0.iew.iewExecutedInsts 403684 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 155095 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 76510 # number of nop insts executed
-system.cpu0.iew.exec_refs 232965 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 80120 # Number of branches executed
-system.cpu0.iew.exec_stores 78016 # Number of stores executed
-system.cpu0.iew.exec_rate 1.818739 # Inst execution rate
-system.cpu0.iew.wb_sent 402871 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 402541 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 238524 # num instructions producing a value
-system.cpu0.iew.wb_consumers 240975 # num instructions consuming a value
+system.cpu0.iew.exec_nop 76584 # number of nop insts executed
+system.cpu0.iew.exec_refs 233191 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 80195 # Number of branches executed
+system.cpu0.iew.exec_stores 78096 # Number of stores executed
+system.cpu0.iew.exec_rate 1.818872 # Inst execution rate
+system.cpu0.iew.wb_sent 403263 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 402934 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 238926 # num instructions producing a value
+system.cpu0.iew.wb_consumers 241439 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.815325 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.989829 # average fanout of values written-back
+system.cpu0.iew.wb_rate 1.815492 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.989592 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 12269 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts 12279 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 194275 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.430668 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.136401 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::samples 194301 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.432628 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.139595 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 34469 17.74% 17.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 79913 41.13% 58.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2377 1.22% 60.10% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 686 0.35% 60.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 75283 38.75% 99.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 305 0.16% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 34596 17.81% 17.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 79813 41.08% 58.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2261 1.16% 60.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 671 0.35% 60.39% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 526 0.27% 60.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 75370 38.79% 99.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 456 0.23% 99.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 240 0.12% 99.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 368 0.19% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 194275 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 472218 # Number of instructions committed
-system.cpu0.commit.committedOps 472218 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 194301 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 472662 # Number of instructions committed
+system.cpu0.commit.committedOps 472662 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 230824 # Number of memory references committed
-system.cpu0.commit.loads 153545 # Number of loads committed
+system.cpu0.commit.refs 231046 # Number of memory references committed
+system.cpu0.commit.loads 153693 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 79166 # Number of branches committed
+system.cpu0.commit.branches 79240 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 318242 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 318538 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 75898 16.07% 16.07% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 165412 35.03% 51.10% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass 75972 16.07% 16.07% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 165560 35.03% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 153629 32.53% 83.63% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 77279 16.37% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 153777 32.53% 83.63% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 77353 16.37% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 472218 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 472662 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 368 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 677296 # The number of ROB reads
-system.cpu0.rob.rob_writes 971436 # The number of ROB writes
-system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 25026 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 396236 # Number of Instructions Simulated
-system.cpu0.committedOps 396236 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 0.559631 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.559631 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.786891 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.786891 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 721496 # number of integer regfile reads
-system.cpu0.int_regfile_writes 325166 # number of integer regfile writes
+system.cpu0.rob.rob_reads 677713 # The number of ROB reads
+system.cpu0.rob.rob_writes 972345 # The number of ROB writes
+system.cpu0.timesIdled 334 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 25195 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 396606 # Number of Instructions Simulated
+system.cpu0.committedOps 396606 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 0.559603 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.559603 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.786980 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.786980 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 722190 # number of integer regfile reads
+system.cpu0.int_regfile_writes 325483 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 234788 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 235015 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.icache.tags.replacements 297 # number of replacements
-system.cpu0.icache.tags.tagsinuse 241.323737 # Cycle average of tags in use
+system.cpu0.icache.tags.tagsinuse 241.252317 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.323737 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471335 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.471335 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.252317 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471196 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.471196 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses
system.cpu0.icache.overall_misses::total 756 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35655495 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 35655495 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 35655495 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 35655495 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 35655495 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 35655495 # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35519995 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 35519995 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 35519995 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 35519995 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 35519995 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 35519995 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses
system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47163.353175 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 47163.353175 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 47163.353175 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 47163.353175 # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46984.120370 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 46984.120370 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46984.120370 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 46984.120370 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46984.120370 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 46984.120370 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27420002 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 27420002 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27420002 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 27420002 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27420002 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 27420002 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27366252 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 27366252 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27366252 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 27366252 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27366252 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 27366252 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46632.656463 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46541.244898 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 46541.244898 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46541.244898 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 46541.244898 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 2 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 142.026535 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 155594 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse 141.985956 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 155741 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 915.258824 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 916.123529 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026535 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.985956 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277316 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.277316 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 627036 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 627036 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 78986 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 78986 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 76692 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 76692 # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses 627612 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 627612 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 79059 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 79059 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 76768 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 76768 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 155678 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 155678 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 155678 # number of overall hits
-system.cpu0.dcache.overall_hits::total 155678 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 416 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 416 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
+system.cpu0.dcache.demand_hits::cpu0.data 155827 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 155827 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 155827 # number of overall hits
+system.cpu0.dcache.overall_hits::total 155827 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 413 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 413 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 961 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 961 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 961 # number of overall misses
-system.cpu0.dcache.overall_misses::total 961 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13375931 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 13375931 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32683256 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 32683256 # number of WriteReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data 956 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 956 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 956 # number of overall misses
+system.cpu0.dcache.overall_misses::total 956 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 12955987 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 12955987 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33432506 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 33432506 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 46059187 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 46059187 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 46059187 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 46059187 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 79402 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 79402 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 77237 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 77237 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu0.data 46388493 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 46388493 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 46388493 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 46388493 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 79472 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 79472 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 77311 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 77311 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 156639 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 156639 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 156639 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 156639 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005239 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.005239 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007056 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.007056 # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 156783 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 156783 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 156783 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 156783 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005197 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.005197 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007024 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.007024 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006135 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.006135 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006135 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.006135 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32153.680288 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 32153.680288 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59969.277064 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 59969.277064 # average WriteReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006098 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.006098 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006098 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.006098 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31370.428571 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 31370.428571 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 61569.992634 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 61569.992634 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 47928.394381 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 47928.394381 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 512 # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48523.528243 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 48523.528243 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48523.528243 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 48523.528243 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.380952 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.833333 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 228 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 598 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 598 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 598 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 226 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 594 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 594 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 363 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 363 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 363 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 363 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6192510 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6192510 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7258228 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7258228 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5995003 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5995003 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7531728 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7531728 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13450738 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 13450738 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13450738 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 13450738 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002368 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002368 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002266 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002266 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13526731 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 13526731 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13526731 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 13526731 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002353 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002353 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002264 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.002317 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.002317 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32938.882979 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32938.882979 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41475.588571 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41475.588571 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32058.839572 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32058.839572 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43038.445714 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43038.445714 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37366.660221 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37366.660221 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37366.660221 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37366.660221 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 49222 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 46474 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 1275 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 43117 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 42310 # Number of BTB hits
+system.cpu1.branchPred.lookups 52187 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 49510 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1259 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 46153 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 45385 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 98.128348 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 644 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct 98.335969 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 643 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu1.numCycles 177641 # number of cpu cycles simulated
+system.cpu1.numCycles 177799 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 30689 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 271480 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 49222 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 42954 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 98036 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3712 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 35816 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles 28925 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 291186 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 52187 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 46028 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 103264 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3653 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 32544 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 7751 # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 22336 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 175432 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.547494 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.089471 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.NoActiveThreadStallCycles 7803 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines 20583 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 175643 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.657829 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.130344 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 77396 44.12% 44.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 50499 28.79% 72.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 7414 4.23% 77.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3189 1.82% 78.95% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 704 0.40% 79.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 30975 17.66% 97.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1193 0.68% 97.68% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 759 0.43% 98.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3303 1.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 72379 41.21% 41.21% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 52711 30.01% 71.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 6570 3.74% 74.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3206 1.83% 76.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 681 0.39% 77.17% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 34861 19.85% 97.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1219 0.69% 97.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 754 0.43% 98.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3262 1.86% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 175432 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.277087 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.528251 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 37161 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 30981 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 90858 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 6321 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2360 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 267812 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 2360 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 37844 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 18525 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 11702 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 84806 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 12444 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 265497 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 184374 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 502466 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 391647 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 171546 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 12828 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 15168 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 73767 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 34233 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 35724 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 29188 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 218285 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 7630 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 221655 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10737 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 10712 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 175432 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.263481 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.299438 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 175643 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.293517 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.637726 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 34549 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 28563 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 96884 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 5527 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2317 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 287488 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 2317 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 35238 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 16093 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 11725 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 91623 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 10844 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 285400 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RenamedOperands 199084 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 545686 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 424083 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 186368 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 12716 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1090 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1211 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 13408 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 80706 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 38119 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 38742 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 33075 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 236041 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 6768 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 238678 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10581 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 10451 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 175643 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.358881 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.308073 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 74808 42.64% 42.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 26276 14.98% 57.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 34476 19.65% 77.27% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 35104 20.01% 97.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3248 1.85% 99.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1161 0.66% 99.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 252 0.14% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 69713 39.69% 39.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 23816 13.56% 53.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 38346 21.83% 75.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 38982 22.19% 97.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1165 0.66% 99.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 266 0.15% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 175432 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 175643 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 17 6.42% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 38 14.34% 20.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 210 79.25% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 108760 49.07% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 79356 35.80% 84.87% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 33539 15.13% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 115728 48.49% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 85517 35.83% 84.32% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 37433 15.68% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 221655 # Type of FU issued
-system.cpu1.iq.rate 1.247769 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001200 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 619107 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 236695 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 219827 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 238678 # Type of FU issued
+system.cpu1.iq.rate 1.342404 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 265 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001110 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 653323 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 253430 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 236861 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 221921 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 238943 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 28930 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 32850 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2336 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1444 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1422 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2360 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 686 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 262565 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 73767 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 34233 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1056 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 2317 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 666 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 282498 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 80706 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 38119 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1050 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 918 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 220479 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 72759 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 907 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 237512 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 79760 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 36650 # number of nop insts executed
-system.cpu1.iew.exec_refs 106217 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 45894 # Number of branches executed
-system.cpu1.iew.exec_stores 33458 # Number of stores executed
-system.cpu1.iew.exec_rate 1.241149 # Inst execution rate
-system.cpu1.iew.wb_sent 220112 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 219827 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 122951 # num instructions producing a value
-system.cpu1.iew.wb_consumers 127610 # num instructions consuming a value
+system.cpu1.iew.exec_nop 39689 # number of nop insts executed
+system.cpu1.iew.exec_refs 117113 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 48963 # Number of branches executed
+system.cpu1.iew.exec_stores 37353 # Number of stores executed
+system.cpu1.iew.exec_rate 1.335846 # Inst execution rate
+system.cpu1.iew.wb_sent 237151 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 236861 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 133843 # num instructions producing a value
+system.cpu1.iew.wb_consumers 138503 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.237479 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.963490 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.332184 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.966355 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 12326 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1275 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 165321 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.513546 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.970448 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 12124 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 6196 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1259 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 165523 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.633344 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.016153 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 73866 44.68% 44.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 44045 26.64% 71.32% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 7953 4.81% 79.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 29501 17.84% 98.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 477 0.29% 98.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 1008 0.61% 99.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 804 0.49% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 67946 41.05% 41.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 47096 28.45% 69.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6082 3.67% 73.18% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 7142 4.31% 77.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1575 0.95% 78.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 33355 20.15% 98.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 510 0.31% 98.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 1001 0.60% 99.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 165321 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 250221 # Number of instructions committed
-system.cpu1.commit.committedOps 250221 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 165523 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 270356 # Number of instructions committed
+system.cpu1.commit.committedOps 270356 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 104162 # Number of memory references committed
-system.cpu1.commit.loads 71373 # Number of loads committed
-system.cpu1.commit.membars 6322 # Number of memory barriers committed
-system.cpu1.commit.branches 45072 # Number of branches committed
+system.cpu1.commit.refs 115067 # Number of memory references committed
+system.cpu1.commit.loads 78370 # Number of loads committed
+system.cpu1.commit.membars 5484 # Number of memory barriers committed
+system.cpu1.commit.branches 48146 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 171353 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 185335 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 35859 14.33% 14.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 103878 41.51% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 77695 31.05% 86.90% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 32789 13.10% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass 38938 14.40% 14.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 110867 41.01% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 83854 31.02% 86.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 36697 13.57% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 250221 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 804 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 270356 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 426477 # The number of ROB reads
-system.cpu1.rob.rob_writes 527460 # The number of ROB writes
-system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 2209 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 44103 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 208040 # Number of Instructions Simulated
-system.cpu1.committedOps 208040 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 0.853879 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.853879 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.171126 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.171126 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 377205 # number of integer regfile reads
-system.cpu1.int_regfile_writes 176304 # number of integer regfile writes
+system.cpu1.rob.rob_reads 446600 # The number of ROB reads
+system.cpu1.rob.rob_writes 567283 # The number of ROB writes
+system.cpu1.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 2156 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 44141 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 225934 # Number of Instructions Simulated
+system.cpu1.committedOps 225934 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 0.786951 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.786951 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.270727 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.270727 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 409872 # number of integer regfile reads
+system.cpu1.int_regfile_writes 191136 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 107775 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 118682 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.tags.replacements 318 # number of replacements
-system.cpu1.icache.tags.tagsinuse 76.769709 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 21861 # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse 79.885573 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 20107 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 51.077103 # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 46.978972 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.769709 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149941 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.149941 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.885573 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156027 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.156027 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 22764 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 22764 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 21861 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 21861 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 21861 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 21861 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 21861 # number of overall hits
-system.cpu1.icache.overall_hits::total 21861 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 475 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 475 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 475 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 475 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 475 # number of overall misses
-system.cpu1.icache.overall_misses::total 475 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7146245 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 7146245 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 7146245 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 7146245 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 7146245 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 7146245 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 22336 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 22336 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 22336 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 22336 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 22336 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 22336 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021266 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.021266 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021266 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.021266 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021266 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.021266 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15044.726316 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15044.726316 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15044.726316 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15044.726316 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 21011 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 21011 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 20107 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 20107 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 20107 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 20107 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 20107 # number of overall hits
+system.cpu1.icache.overall_hits::total 20107 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 476 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 476 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 476 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses
+system.cpu1.icache.overall_misses::total 476 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7353244 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 7353244 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 7353244 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 7353244 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 7353244 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 7353244 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 20583 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 20583 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 20583 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 20583 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 20583 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 20583 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023126 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.023126 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023126 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.023126 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023126 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.023126 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15447.991597 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15447.991597 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15447.991597 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15447.991597 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15447.991597 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15447.991597 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 47 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 47 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 47 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 48 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 48 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5694254 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5694254 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5694254 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5694254 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5694254 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5694254 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019162 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.019162 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.019162 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13304.331776 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5927255 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 5927255 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5927255 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 5927255 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5927255 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 5927255 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020794 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.020794 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020794 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.020794 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13848.726636 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13848.726636 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13848.726636 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13848.726636 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 0 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 23.645460 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 38791 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse 24.706566 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 42694 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 1385.392857 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 1524.785714 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.645460 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046183 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.046183 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.706566 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048255 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 306653 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 306653 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 43477 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 43477 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 32586 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 32586 # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 76063 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 76063 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 76063 # number of overall hits
-system.cpu1.dcache.overall_hits::total 76063 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 336 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 336 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 468 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 468 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 468 # number of overall misses
-system.cpu1.dcache.overall_misses::total 468 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4177635 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 4177635 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2763761 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2763761 # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 521507 # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total 521507 # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 6941396 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 6941396 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 6941396 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 6941396 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 43813 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 43813 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 32718 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 32718 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 76531 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 76531 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 76531 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 76531 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007669 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.007669 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004034 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.004034 # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006115 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.006115 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006115 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.006115 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12433.437500 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12433.437500 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333 # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9149.245614 # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 9149.245614 # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14832.042735 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14832.042735 # average overall miss latency
+system.cpu1.dcache.tags.tag_accesses 334614 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 334614 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 46543 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 46543 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 36491 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 36491 # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 83034 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 83034 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 83034 # number of overall hits
+system.cpu1.dcache.overall_hits::total 83034 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 352 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 352 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 492 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 492 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 492 # number of overall misses
+system.cpu1.dcache.overall_misses::total 492 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4522597 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 4522597 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3033762 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 3033762 # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 535508 # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total 535508 # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 7556359 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 7556359 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 7556359 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 7556359 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 46895 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 46895 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 36631 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 36631 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 83526 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 83526 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 83526 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 83526 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007506 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.007506 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003822 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.003822 # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.818182 # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005890 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.005890 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005890 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.005890 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12848.286932 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12848.286932 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21669.728571 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21669.728571 # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9916.814815 # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 9916.814815 # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15358.453252 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15358.453252 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15358.453252 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15358.453252 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 178 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 30 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 208 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 208 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1076519 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1076519 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1313739 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1313739 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 407493 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total 407493 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2390258 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 2390258 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2390258 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 2390258 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003606 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003606 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003118 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003118 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.003397 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.003397 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6813.411392 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6813.411392 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7149 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7149 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 195 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 227 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 227 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 157 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1099522 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1099522 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1387488 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1387488 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 427492 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 427492 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2487010 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2487010 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2487010 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2487010 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003348 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002948 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002948 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.818182 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.818182 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003173 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.003173 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003173 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.003173 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7003.324841 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7003.324841 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12847.111111 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12847.111111 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7916.518519 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7916.518519 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9384.943396 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9384.943396 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9384.943396 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9384.943396 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups 47728 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 45021 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 1300 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 41568 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 40861 # Number of BTB hits
+system.cpu2.branchPred.lookups 51191 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 48468 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 44993 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 44297 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 98.299172 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 682 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct 98.453093 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 177276 # number of cpu cycles simulated
+system.cpu2.numCycles 177434 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 30843 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 263204 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 47728 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 41543 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 94904 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 3824 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 35041 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles 28865 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 285908 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 51191 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 44981 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 100768 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 3816 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 31184 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 807 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 21784 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 171794 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.532091 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.088011 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.NoActiveThreadStallCycles 7805 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles 1366 # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines 19788 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 172424 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.658168 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.138146 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 76890 44.76% 44.76% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 48833 28.43% 73.18% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 7151 4.16% 77.34% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3183 1.85% 79.20% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 686 0.40% 79.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 29845 17.37% 96.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1160 0.68% 97.64% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 777 0.45% 98.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3269 1.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 71656 41.56% 41.56% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 51257 29.73% 71.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 6128 3.55% 74.84% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3186 1.85% 76.69% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 695 0.40% 77.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 34284 19.88% 96.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1167 0.68% 97.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 773 0.45% 98.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3278 1.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 171794 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.269230 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.484713 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 36742 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 30806 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 88081 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5970 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 2446 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 259729 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 2446 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 37466 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 17718 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 12322 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 82351 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 11742 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 257457 # Number of instructions processed by rename
-system.cpu2.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 179534 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 487570 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 380512 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 166403 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 13131 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1114 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1238 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 14439 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 71183 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 33053 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 34319 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 28008 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 212034 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 7370 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 214866 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 11214 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 11199 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 171794 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.250719 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.303691 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 172424 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.288507 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.611348 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 34386 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 27902 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 94859 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5040 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 2432 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 282267 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 2432 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 35111 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 14773 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 12374 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 90050 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 9879 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 280008 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.RenamedOperands 196247 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 536665 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 417354 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 183125 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 13122 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1115 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 12503 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 79020 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 37489 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 37725 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 32426 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 232155 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 6357 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 234096 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 11107 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 11056 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 607 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 172424 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.357676 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.313193 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 74486 43.36% 43.36% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 25336 14.75% 58.11% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 33280 19.37% 77.48% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 33902 19.73% 97.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3243 1.89% 99.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1160 0.68% 99.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 274 0.16% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 69134 40.10% 40.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 22467 13.03% 53.13% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 37714 21.87% 75.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 38330 22.23% 97.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3239 1.88% 99.11% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1151 0.67% 99.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 171794 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 172424 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 17 6.18% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 48 17.45% 23.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 210 76.36% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 12 4.40% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 51 18.68% 23.08% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 210 76.92% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 106150 49.40% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 76361 35.54% 84.94% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 32355 15.06% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 114033 48.71% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 83276 35.57% 84.29% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 36787 15.71% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 214866 # Type of FU issued
-system.cpu2.iq.rate 1.212042 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 275 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001280 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 601907 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 230666 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 213047 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 234096 # Type of FU issued
+system.cpu2.iq.rate 1.319341 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 273 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001166 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 640996 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 249665 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 232273 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 215141 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 234369 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 27720 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 32149 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2543 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2502 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 48 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 1485 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 916 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 254607 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewSquashCycles 2432 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 787 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 277138 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 71183 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 33053 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1074 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewDispLoadInsts 79020 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 37489 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1072 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 48 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 458 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 967 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1425 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 213716 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 70082 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1150 # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 971 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1435 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 232944 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 77967 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1152 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 35203 # number of nop insts executed
-system.cpu2.iew.exec_refs 102354 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 44387 # Number of branches executed
-system.cpu2.iew.exec_stores 32272 # Number of stores executed
-system.cpu2.iew.exec_rate 1.205555 # Inst execution rate
-system.cpu2.iew.wb_sent 213334 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 213047 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 119124 # num instructions producing a value
-system.cpu2.iew.wb_consumers 123829 # num instructions consuming a value
+system.cpu2.iew.exec_nop 38626 # number of nop insts executed
+system.cpu2.iew.exec_refs 114664 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 47841 # Number of branches executed
+system.cpu2.iew.exec_stores 36697 # Number of stores executed
+system.cpu2.iew.exec_rate 1.312849 # Inst execution rate
+system.cpu2.iew.wb_sent 232563 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 232273 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 131430 # num instructions producing a value
+system.cpu2.iew.wb_consumers 136123 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.201781 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.962004 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.309067 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.965524 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 12897 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 6722 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1300 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 161599 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.495727 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.966465 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 12771 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 5750 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 162187 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.630001 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.017893 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 73205 45.30% 45.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 42525 26.32% 71.62% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 6095 3.77% 75.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.11% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1558 0.96% 81.07% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 28296 17.51% 98.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 469 0.29% 98.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 66847 41.22% 41.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 46010 28.37% 69.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 6109 3.77% 73.35% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 6666 4.11% 77.46% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1557 0.96% 78.42% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 32708 20.17% 98.59% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 471 0.29% 98.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 1007 0.62% 99.50% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 161599 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 241708 # Number of instructions committed
-system.cpu2.commit.committedOps 241708 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 162187 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 264365 # Number of instructions committed
+system.cpu2.commit.committedOps 264365 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 100224 # Number of memory references committed
-system.cpu2.commit.loads 68640 # Number of loads committed
-system.cpu2.commit.membars 6003 # Number of memory barriers committed
-system.cpu2.commit.branches 43548 # Number of branches committed
+system.cpu2.commit.refs 112522 # Number of memory references committed
+system.cpu2.commit.loads 76518 # Number of loads committed
+system.cpu2.commit.membars 5033 # Number of memory barriers committed
+system.cpu2.commit.branches 47000 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 165890 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 181641 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 34333 14.20% 14.20% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 101148 41.85% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 74643 30.88% 86.93% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 31584 13.07% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass 37787 14.29% 14.29% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 109023 41.24% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 81551 30.85% 86.38% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 36004 13.62% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 241708 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 264365 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 414795 # The number of ROB reads
-system.cpu2.rob.rob_writes 511661 # The number of ROB writes
-system.cpu2.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 5482 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 44468 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 201372 # Number of Instructions Simulated
-system.cpu2.committedOps 201372 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 0.880341 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.880341 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.135924 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.135924 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 365782 # number of integer regfile reads
-system.cpu2.int_regfile_writes 171355 # number of integer regfile writes
+system.cpu2.rob.rob_reads 437924 # The number of ROB reads
+system.cpu2.rob.rob_writes 556709 # The number of ROB writes
+system.cpu2.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 5010 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 44506 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 221545 # Number of Instructions Simulated
+system.cpu2.committedOps 221545 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 0.800894 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.800894 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.248605 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.248605 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 402715 # number of integer regfile reads
+system.cpu2.int_regfile_writes 188101 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 103916 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 116228 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.icache.tags.replacements 317 # number of replacements
-system.cpu2.icache.tags.tagsinuse 82.236907 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 21297 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 50.110588 # Average number of references to valid blocks.
+system.cpu2.icache.tags.tagsinuse 81.450670 # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs 19300 # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs 424 # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs 45.518868 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236907 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160619 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.160619 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id
+system.cpu2.icache.tags.occ_blocks::cpu2.inst 81.450670 # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst 0.159083 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total 0.159083 # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024 107 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 22209 # Number of tag accesses
-system.cpu2.icache.tags.data_accesses 22209 # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst 21297 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 21297 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 21297 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 21297 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 21297 # number of overall hits
-system.cpu2.icache.overall_hits::total 21297 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 487 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 487 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 487 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 487 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 487 # number of overall misses
-system.cpu2.icache.overall_misses::total 487 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521239 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 11521239 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 11521239 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 11521239 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 11521239 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 11521239 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 21784 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 21784 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 21784 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 21784 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 21784 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 21784 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.022356 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.022356 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.022356 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.022356 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.022356 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.022356 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23657.574949 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 23657.574949 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 23657.574949 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 23657.574949 # average overall miss latency
+system.cpu2.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024 0.208984 # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses 20212 # Number of tag accesses
+system.cpu2.icache.tags.data_accesses 20212 # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst 19300 # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total 19300 # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst 19300 # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total 19300 # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst 19300 # number of overall hits
+system.cpu2.icache.overall_hits::total 19300 # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst 488 # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total 488 # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst 488 # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total 488 # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst 488 # number of overall misses
+system.cpu2.icache.overall_misses::total 488 # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11534741 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total 11534741 # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst 11534741 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total 11534741 # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst 11534741 # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total 11534741 # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst 19788 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total 19788 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst 19788 # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total 19788 # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst 19788 # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total 19788 # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024661 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total 0.024661 # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024661 # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total 0.024661 # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024661 # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total 0.024661 # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23636.764344 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 23636.764344 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23636.764344 # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 23636.764344 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23636.764344 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 23636.764344 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 62 # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst 62 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst 62 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9226007 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 9226007 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9226007 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 9226007 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9226007 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 9226007 # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019510 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total 0.019510 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total 0.019510 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21708.251765 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 64 # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst 64 # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst 64 # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total 64 # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 424 # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst 424 # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total 424 # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst 424 # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total 424 # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9234505 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total 9234505 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9234505 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 9234505 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9234505 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 9234505 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021427 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021427 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021427 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total 0.021427 # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021427 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total 0.021427 # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21779.492925 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21779.492925 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21779.492925 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 21779.492925 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21779.492925 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 21779.492925 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.tags.replacements 0 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 26.169210 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 37730 # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 1301.034483 # Average number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse 26.136002 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 42041 # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs 1501.464286 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.169210 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051112 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.051112 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.136002 # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051047 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total 0.051047 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 295974 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 295974 # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data 42003 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 42003 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 31371 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 31371 # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 73374 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 73374 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 73374 # number of overall hits
-system.cpu2.dcache.overall_hits::total 73374 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 342 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 342 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 140 # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 482 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 482 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 482 # number of overall misses
-system.cpu2.dcache.overall_misses::total 482 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5435581 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 5435581 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3139010 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 3139010 # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 574505 # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total 574505 # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 8574591 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 8574591 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 8574591 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 8574591 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 42345 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 42345 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 31511 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 31511 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 73856 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 73856 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 73856 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 73856 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008077 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004443 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total 0.004443 # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.808219 # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total 0.808219 # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006526 # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total 0.006526 # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006526 # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total 0.006526 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15893.511696 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 15893.511696 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000 # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9737.372881 # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 9737.372881 # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 17789.607884 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17789.607884 # average overall miss latency
+system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses 327476 # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses 327476 # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data 45457 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total 45457 # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data 35794 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total 35794 # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data 81251 # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total 81251 # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data 81251 # number of overall hits
+system.cpu2.dcache.overall_hits::total 81251 # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data 345 # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total 345 # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data 484 # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total 484 # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data 484 # number of overall misses
+system.cpu2.dcache.overall_misses::total 484 # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5375808 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total 5375808 # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3387510 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total 3387510 # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 561006 # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total 561006 # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data 8763318 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total 8763318 # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data 8763318 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total 8763318 # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data 45802 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total 45802 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data 35933 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total 35933 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data 81735 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total 81735 # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data 81735 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total 81735 # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007532 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total 0.007532 # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003868 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total 0.003868 # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005922 # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total 0.005922 # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005922 # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total 0.005922 # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15582.052174 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 15582.052174 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24370.575540 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 24370.575540 # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9672.517241 # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 9672.517241 # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18106.028926 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 18106.028926 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18106.028926 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 18106.028926 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 177 # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total 177 # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data 211 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total 211 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data 211 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total 211 # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 165 # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 184 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data 217 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data 217 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1515278 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1515278 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1527990 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1527990 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456495 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456495 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3043268 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 3043268 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3043268 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 3043268 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003897 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003897 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003364 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003364 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.808219 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.808219 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.003669 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.003669 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9183.503030 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9183.503030 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14415 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14415 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7737.203390 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7737.203390 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1467781 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1467781 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1796490 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1796490 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 444994 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 444994 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3264271 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 3264271 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3264271 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 3264271 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003515 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003515 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002950 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002950 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003267 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total 0.003267 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003267 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.003267 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9116.652174 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9116.652174 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16948.018868 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16948.018868 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7672.310345 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7672.310345 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12225.734082 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12225.734082 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12225.734082 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12225.734082 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups 53964 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 51232 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 1265 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 47874 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 47117 # Number of BTB hits
+system.cpu3.branchPred.lookups 47572 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 44838 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1269 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 41556 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 40675 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 98.418766 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 645 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct 97.879969 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 650 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu3.numCycles 176930 # number of cpu cycles simulated
+system.cpu3.numCycles 177088 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 27837 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 302665 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 53964 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 47762 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 106222 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 3643 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles 30631 # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles 31611 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 260615 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 47572 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 41325 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 95272 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 3721 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles 37783 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 19577 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 175543 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.724164 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.153360 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.NoActiveThreadStallCycles 7803 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 23344 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 257 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 175638 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.483819 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.061741 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 69321 39.49% 39.49% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 53950 30.73% 70.22% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 6031 3.44% 73.66% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3206 1.83% 75.48% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 696 0.40% 75.88% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 37091 21.13% 97.01% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1217 0.69% 97.70% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 754 0.43% 98.13% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3277 1.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 80366 45.76% 45.76% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 49379 28.11% 73.87% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 7947 4.52% 78.40% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3182 1.81% 80.21% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 669 0.38% 80.59% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 28809 16.40% 96.99% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1228 0.70% 97.69% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 757 0.43% 98.12% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3301 1.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 175543 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.305002 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.710648 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 32973 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 27130 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 100348 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 5043 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2300 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 299109 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 2300 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 33648 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 14616 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 11766 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 95589 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 9875 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 296992 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands 207702 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 570845 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 442935 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 195079 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 12623 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1224 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 12490 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 84722 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 40383 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 40455 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 35338 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 246413 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 6255 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 248738 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 58 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 10413 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 9948 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 566 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 175543 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.416963 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.309147 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 175638 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.268635 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.471669 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 38601 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 32457 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 87595 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 6808 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2374 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 256826 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 2374 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 39299 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 20012 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 11695 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 81034 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 13421 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 254587 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.RenamedOperands 176229 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 478476 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 373673 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 163264 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 12965 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1216 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 16061 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 69948 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 32037 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 34088 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 26994 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 208399 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 8161 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 212159 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 10835 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 11026 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 608 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 175638 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.207933 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.292111 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 66501 37.88% 37.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 22275 12.69% 50.57% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 40683 23.18% 73.75% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 41300 23.53% 97.27% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 77942 44.38% 44.38% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 27771 15.81% 60.19% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 32234 18.35% 78.54% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 32910 18.74% 97.28% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1166 0.66% 99.79% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 47 0.03% 99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1156 0.66% 99.79% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 263 0.15% 99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 175543 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 175638 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 17 6.44% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 37 14.02% 20.45% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 12 4.44% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 48 17.78% 22.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 210 77.78% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 119912 48.21% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.21% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 89101 35.82% 84.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 39725 15.97% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 104799 49.40% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 76027 35.83% 85.23% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 31333 14.77% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 248738 # Type of FU issued
-system.cpu3.iq.rate 1.405855 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 264 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001061 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 673341 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 263119 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 246940 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 212159 # Type of FU issued
+system.cpu3.iq.rate 1.198043 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 270 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001273 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 600350 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 227441 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 210302 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 249002 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 212429 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 35155 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 26730 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2247 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2459 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1447 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2300 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 643 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 294126 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 84722 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 40383 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1060 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 2374 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 705 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 44 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 251552 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 69948 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 32037 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1046 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1378 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 247584 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 83851 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 464 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 910 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1374 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 210966 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 68906 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1193 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 41458 # number of nop insts executed
-system.cpu3.iew.exec_refs 123507 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 50799 # Number of branches executed
-system.cpu3.iew.exec_stores 39656 # Number of stores executed
-system.cpu3.iew.exec_rate 1.399333 # Inst execution rate
-system.cpu3.iew.wb_sent 247229 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 246940 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 140247 # num instructions producing a value
-system.cpu3.iew.wb_consumers 144914 # num instructions consuming a value
+system.cpu3.iew.exec_nop 34992 # number of nop insts executed
+system.cpu3.iew.exec_refs 100151 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 44184 # Number of branches executed
+system.cpu3.iew.exec_stores 31245 # Number of stores executed
+system.cpu3.iew.exec_rate 1.191306 # Inst execution rate
+system.cpu3.iew.wb_sent 210604 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 210302 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 116846 # num instructions producing a value
+system.cpu3.iew.wb_consumers 121503 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.395693 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.967795 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.187556 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.961672 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 11951 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 5689 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1265 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 165494 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.704926 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 2.039126 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 12453 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 7553 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 1269 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 165461 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.444927 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.940782 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 64312 38.86% 38.86% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 48901 29.55% 68.41% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.09% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 6636 4.01% 76.10% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.05% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 35663 21.55% 98.60% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 504 0.30% 98.90% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 999 0.60% 99.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 818 0.49% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 77418 46.79% 46.79% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 42307 25.57% 72.36% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 6087 3.68% 76.04% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 8486 5.13% 81.17% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1577 0.95% 82.12% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 27301 16.50% 98.62% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 474 0.29% 98.91% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 1005 0.61% 99.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 165494 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 282155 # Number of instructions committed
-system.cpu3.commit.committedOps 282155 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 165461 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 239079 # Number of instructions committed
+system.cpu3.commit.committedOps 239079 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 121473 # Number of memory references committed
-system.cpu3.commit.loads 82475 # Number of loads committed
-system.cpu3.commit.membars 4979 # Number of memory barriers committed
-system.cpu3.commit.branches 49942 # Number of branches committed
+system.cpu3.commit.refs 98079 # Number of memory references committed
+system.cpu3.commit.loads 67489 # Number of loads committed
+system.cpu3.commit.membars 6836 # Number of memory barriers committed
+system.cpu3.commit.branches 43385 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 193540 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 163585 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass 40736 14.44% 14.44% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 114967 40.75% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 87454 31.00% 86.18% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 38998 13.82% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass 34172 14.29% 14.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 99992 41.82% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.12% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead 74325 31.09% 87.21% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite 30590 12.79% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total 282155 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 818 # number cycles where commit BW limit reached
+system.cpu3.commit.op_class_0::total 239079 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads 458195 # The number of ROB reads
-system.cpu3.rob.rob_writes 590518 # The number of ROB writes
-system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1387 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 44814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 236440 # Number of Instructions Simulated
-system.cpu3.committedOps 236440 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 0.748308 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.748308 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.336348 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.336348 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 429141 # number of integer regfile reads
-system.cpu3.int_regfile_writes 199912 # number of integer regfile writes
+system.cpu3.rob.rob_reads 415600 # The number of ROB reads
+system.cpu3.rob.rob_writes 505444 # The number of ROB writes
+system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1450 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 44852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 198071 # Number of Instructions Simulated
+system.cpu3.committedOps 198071 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 0.894063 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 0.894063 # CPI: Total CPI of All Threads
+system.cpu3.ipc 1.118489 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 1.118489 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 358875 # number of integer regfile reads
+system.cpu3.int_regfile_writes 168004 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 125101 # number of misc regfile reads
+system.cpu3.misc_regfile_reads 101700 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
system.cpu3.icache.tags.replacements 319 # number of replacements
-system.cpu3.icache.tags.tagsinuse 80.524551 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 19102 # Total number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse 77.082229 # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs 22869 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 44.423256 # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs 53.183721 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.524551 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157275 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.157275 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.082229 # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst 0.150551 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total 0.150551 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 20007 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 20007 # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst 19102 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 19102 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 19102 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 19102 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 19102 # number of overall hits
-system.cpu3.icache.overall_hits::total 19102 # number of overall hits
+system.cpu3.icache.tags.tag_accesses 23774 # Number of tag accesses
+system.cpu3.icache.tags.data_accesses 23774 # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst 22869 # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total 22869 # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst 22869 # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total 22869 # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst 22869 # number of overall hits
+system.cpu3.icache.overall_hits::total 22869 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses
system.cpu3.icache.overall_misses::total 475 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6525745 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 6525745 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 6525745 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 6525745 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst 6525745 # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total 6525745 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 19577 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 19577 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 19577 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 19577 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 19577 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 19577 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024263 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total 0.024263 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024263 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.024263 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024263 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.024263 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13738.410526 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13738.410526 # average overall miss latency
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6365994 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total 6365994 # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst 6365994 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total 6365994 # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst 6365994 # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total 6365994 # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 23344 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 23344 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst 23344 # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total 23344 # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst 23344 # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total 23344 # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020348 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total 0.020348 # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020348 # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total 0.020348 # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020348 # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total 0.020348 # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13402.092632 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 13402.092632 # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13402.092632 # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 13402.092632 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13402.092632 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 13402.092632 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5298255 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 5298255 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5298255 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 5298255 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5298255 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 5298255 # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021965 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total 0.021965 # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total 0.021965 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5107006 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total 5107006 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5107006 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total 5107006 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5107006 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total 5107006 # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018420 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total 0.018420 # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018420 # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total 0.018420 # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11876.758140 # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 11876.758140 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11876.758140 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 11876.758140 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements 0 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 24.706550 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 44992 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 1606.857143 # Average number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse 23.636588 # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs 36715 # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs 1266.034483 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.706550 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048255 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.636588 # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046165 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total 0.046165 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 350946 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 350946 # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data 48327 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 48327 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 38795 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 38795 # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 87122 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 87122 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 87122 # number of overall hits
-system.cpu3.dcache.overall_hits::total 87122 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 351 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 351 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses
-system.cpu3.dcache.overall_misses::total 490 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4621144 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 4621144 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3311512 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 3311512 # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 513008 # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total 513008 # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data 7932656 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total 7932656 # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data 7932656 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total 7932656 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 48678 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 48678 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 38934 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 38934 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 87612 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 87612 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 87612 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 87612 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007211 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total 0.007211 # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003570 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total 0.003570 # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005593 # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total 0.005593 # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005593 # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total 0.005593 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13165.652422 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 13165.652422 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23823.827338 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 23823.827338 # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9865.538462 # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 9865.538462 # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 16189.093878 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 16189.093878 # average overall miss latency
+system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses 291244 # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses 291244 # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data 41825 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total 41825 # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data 30388 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total 30388 # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data 72213 # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total 72213 # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data 72213 # number of overall hits
+system.cpu3.dcache.overall_hits::total 72213 # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data 334 # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total 334 # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data 131 # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total 131 # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data 465 # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total 465 # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data 465 # number of overall misses
+system.cpu3.dcache.overall_misses::total 465 # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4213650 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total 4213650 # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2829011 # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total 2829011 # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 511006 # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total 511006 # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data 7042661 # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total 7042661 # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data 7042661 # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total 7042661 # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data 42159 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total 42159 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data 30519 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total 30519 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data 72678 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total 72678 # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data 72678 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total 72678 # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007922 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total 0.007922 # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004292 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total 0.004292 # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.788732 # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006398 # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total 0.006398 # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006398 # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total 0.006398 # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12615.718563 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 12615.718563 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21595.503817 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 21595.503817 # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9125.107143 # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 9125.107143 # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15145.507527 # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 15145.507527 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15145.507527 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 15145.507527 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 197 # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data 230 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total 230 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data 230 # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total 230 # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 154 # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1052517 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1052517 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1403488 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1403488 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 408992 # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total 408992 # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2456005 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total 2456005 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2456005 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total 2456005 # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003164 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002723 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002723 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.812500 # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.812500 # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total 0.002968 # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total 0.002968 # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6834.525974 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6834.525974 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13240.452830 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13240.452830 # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7865.230769 # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7865.230769 # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 173 # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 31 # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data 204 # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data 204 # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data 261 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data 261 # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1077518 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1077518 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1290489 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1290489 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 398994 # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total 398994 # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2368007 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total 2368007 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2368007 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total 2368007 # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003819 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003819 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003277 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.788732 # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6692.658385 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6692.658385 # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12904.890000 # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12904.890000 # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7124.892857 # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7124.892857 # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9072.823755 # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9072.823755 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9072.823755 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9072.823755 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff