radeon->texture_rect_row_align = 512;
radeon->texture_compressed_row_align = 512;
} else {
- radeon->texture_row_align = 256;
- radeon->texture_rect_row_align = 256;
- radeon->texture_compressed_row_align = 256;
+ radeon->texture_row_align = radeon->radeonScreen->group_bytes;
+ radeon->texture_rect_row_align = radeon->radeonScreen->group_bytes;
+ radeon->texture_compressed_row_align = radeon->radeonScreen->group_bytes;
}
} else if (IS_R200_CLASS(radeon->radeonScreen) ||
IS_R100_CLASS(radeon->radeonScreen)) {
else
screen->chip_flags |= RADEON_CLASS_R600;
+ /* set group bytes for r6xx+ */
+ screen->group_bytes = 256;
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
else
screen->chip_flags |= RADEON_CLASS_R600;
- /* r6xx+ tiling */
+ /* r6xx+ tiling, default to 256 group bytes */
+ screen->group_bytes = 256;
if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)