2014-09-21 Segher Boessenkool <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (ashr<mode>3, *ashr<mode>3, *ashrsi3_64,
	*ashr<mode>3_dot, *ashr<mode>3_dot2): Clobber CA_REGNO.
	(floatdisf2_internal2): Ditto.
	(ashrdi3_no_power): Ditto.  Fix formatting.

From-SVN: r215436

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fbbf00fd045ca88fc82da2406b83c0062f41cfea..96e5094f3364da4e15d8b885a207979e0b90a24f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2014-09-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/rs6000.md (ashr<mode>3, *ashr<mode>3, *ashrsi3_64,
+       *ashr<mode>3_dot, *ashr<mode>3_dot2): Clobber CA_REGNO.
+       (floatdisf2_internal2): Ditto.
+       (ashrdi3_no_power): Ditto.  Fix formatting.
+
 2014-09-21  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/rs6000.md (ctz<mode>2, ffs<mode>2, popcount<mode>2,

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 059dd99a5721811cd69783a973b68e761ad1e4aa..91bdb7d9d286bfcb38f93fc66d0e327b00c0a937 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4634,9 +4634,10 @@
 
 
 (define_expand "ashr<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
-       (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
-                     (match_operand:SI 2 "reg_or_cint_operand" "")))]
+  [(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+                  (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+                                (match_operand:SI 2 "reg_or_cint_operand" "")))
+             (clobber (reg:GPR CA_REGNO))])]
   ""
 {
   /* The generic code does not generate optimal code for the low word
@@ -4658,7 +4659,8 @@
 (define_insn "*ashr<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
        (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-                     (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
+                     (match_operand:SI 2 "reg_or_cint_operand" "rn")))
+   (clobber (reg:GPR CA_REGNO))]
   ""
   "sra<wd>%I2 %0,%1,%<hH>2"
   [(set_attr "type" "shift")
@@ -4668,7 +4670,8 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
        (sign_extend:DI
            (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                        (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
+                        (match_operand:SI 2 "reg_or_cint_operand" "rn"))))
+   (clobber (reg:SI CA_REGNO))]
   "TARGET_POWERPC64"
   "sraw%I2 %0,%1,%h2"
   [(set_attr "type" "shift")
@@ -4679,15 +4682,17 @@
        (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
                                  (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
                    (const_int 0)))
-   (clobber (match_scratch:GPR 0 "=r,r"))]
+   (clobber (match_scratch:GPR 0 "=r,r"))
+   (clobber (reg:GPR CA_REGNO))]
   "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
    sra<wd>%I2. %0,%1,%<hH>2
    #"
   "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-       (ashiftrt:GPR (match_dup 1)
-                     (match_dup 2)))
+  [(parallel [(set (match_dup 0)
+                  (ashiftrt:GPR (match_dup 1)
+                                (match_dup 2)))
+             (clobber (reg:GPR CA_REGNO))])
    (set (match_dup 3)
        (compare:CC (match_dup 0)
                    (const_int 0)))]
@@ -4704,15 +4709,17 @@
                    (const_int 0)))
    (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
        (ashiftrt:GPR (match_dup 1)
-                     (match_dup 2)))]
+                     (match_dup 2)))
+   (clobber (reg:GPR CA_REGNO))]
   "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
    sra<wd>%I2. %0,%1,%<hH>2
    #"
   "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-       (ashiftrt:GPR (match_dup 1)
-                     (match_dup 2)))
+  [(parallel [(set (match_dup 0)
+                  (ashiftrt:GPR (match_dup 1)
+                                (match_dup 2)))
+             (clobber (reg:GPR CA_REGNO))])
    (set (match_dup 3)
        (compare:CC (match_dup 0)
                    (const_int 0)))]
@@ -6153,8 +6160,9 @@
 ;; by a bit that won't be lost at that stage, but is below the SFmode
 ;; rounding position.
 (define_expand "floatdisf2_internal2"
-  [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
-                                  (const_int 53)))
+  [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
+                                             (const_int 53)))
+             (clobber (reg:DI CA_REGNO))])
    (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
                                           (const_int 2047)))
    (set (match_dup 3) (plus:DI (match_dup 3)
@@ -6317,9 +6325,9 @@
 (define_insn "ashrdi3_no_power"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-                    (match_operand:SI 2 "const_int_operand" "M,i")))]
+                    (match_operand:SI 2 "const_int_operand" "M,i")))
+   (clobber (reg:SI CA_REGNO))]
   "!TARGET_POWERPC64"
-  "*
 {
   switch (which_alternative)
     {
@@ -6336,7 +6344,7 @@
       else
        return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
     }
-}"
+}
   [(set_attr "type" "two,three")
    (set_attr "length" "8,12")])