Allow $anyconst, etc. in non-formal SV mode

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 60b1ecffd13a370b3eb002371ef2015f87ab0807..e842501463802f6cb666f5d42f08fcc441628284 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1319,7 +1319,7 @@ rvalue:
                $$ = new AstNode(AST_IDENTIFIER, $2);
                $$->str = *$1;
                delete $1;
-               if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$anyseq"))
+               if ($2 == nullptr && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$anyseq"))
                        $$->type = AST_FCALL;
        } |
        hierarchical_id non_opt_multirange {