radv: add tess ctrl stage barrier workaround for SI.

This just ports the workaround from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index cb7469168cd840e101233bf835d2ce6784fc6364..8f56fbf1eb003135f97a05b6c7c1ed143eb5e294 100644 (file)
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2917,9 +2917,17 @@ static void emit_waitcnt(struct nir_to_llvm_context *ctx,
 
 static void emit_barrier(struct nir_to_llvm_context *ctx)
 {
-       // TODO tess
+       /* SI only (thanks to a hw bug workaround):
+        * The real barrier instruction isn’t needed, because an entire patch
+        * always fits into a single wave.
+        */
+       if (ctx->options->chip_class == SI &&
+           ctx->stage == MESA_SHADER_TESS_CTRL) {
+               emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
+               return;
+       }
        ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
-                          ctx->voidt, NULL, 0, 0);
+                          ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
 }
 
 static void emit_discard_if(struct nir_to_llvm_context *ctx,