Update mul test to DSP48E1

diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
index ec30c9c2c0a309d6ad7aabb12a42d6f8ae04b792..f5306e848efa8d563258f13919325f6288ed3c6d 100644 (file)
--- a/tests/xilinx/mul.ys
+++ b/tests/xilinx/mul.ys
@@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 12 t:LUT2
-select -assert-count 1  t:LUT3
-select -assert-count 6  t:LUT4
-select -assert-count 1  t:LUT5
-select -assert-count 33 t:LUT6
-select -assert-count 11 t:MUXCY
-select -assert-count 1  t:MUXF7
-select -assert-count 12 t:XORCY
-select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
+select -assert-count 1 t:DSP48E1
+select -assert-none t:DSP48E1 %% t:* %D