* as.h (POISON_BFD_BOOLEAN): Define.
* as.c, * as.h, * atof-generic.c, * config/atof-ieee.c,
* config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c,
* config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c,
* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
* config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h,
* config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c,
* config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c,
* config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c,
* config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h,
* config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c,
* config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h,
* config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c,
* config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c,
* config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c,
* config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h,
* config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c,
* config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h,
* config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c,
* config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h,
* config/tc-metag.c, * config/tc-metag.h,
* config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h,
* config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c,
* config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c,
* config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h,
* config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c,
* config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h,
* config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c,
* config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h,
* config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c,
* config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c,
* config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c,
* config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c,
* config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c,
* config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h,
* config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c,
* config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c,
* config/tc-xstormy16.c, * config/tc-xstormy16.h,
* config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c,
* config/tc-z8k.c, * config/xtensa-istack.h,
* config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c,
* dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c,
* frags.h, * listing.c, * macro.c, * output-file.c, * read.c,
* read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean
with bool, FALSE with false, and TRUE with true.
+2021-03-31 Alan Modra <amodra@gmail.com>
+
+ * as.h (POISON_BFD_BOOLEAN): Define.
+ * as.c, * as.h, * atof-generic.c, * config/atof-ieee.c,
+ * config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c,
+ * config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c,
+ * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
+ * config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h,
+ * config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c,
+ * config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c,
+ * config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c,
+ * config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h,
+ * config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c,
+ * config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h,
+ * config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c,
+ * config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c,
+ * config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c,
+ * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h,
+ * config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c,
+ * config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h,
+ * config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c,
+ * config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h,
+ * config/tc-metag.c, * config/tc-metag.h,
+ * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h,
+ * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c,
+ * config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c,
+ * config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h,
+ * config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c,
+ * config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h,
+ * config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c,
+ * config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h,
+ * config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c,
+ * config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c,
+ * config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c,
+ * config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c,
+ * config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c,
+ * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h,
+ * config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c,
+ * config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c,
+ * config/tc-xstormy16.c, * config/tc-xstormy16.h,
+ * config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c,
+ * config/tc-z8k.c, * config/xtensa-istack.h,
+ * config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c,
+ * dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c,
+ * frags.h, * listing.c, * macro.c, * output-file.c, * read.c,
+ * read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean
+ with bool, FALSE with false, and TRUE with true.
+
2021-03-31 Alan Modra <amodra@gmail.com>
* config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h.
#if defined OBJ_ELF || defined OBJ_MAYBE_ELF
int flag_use_elf_stt_common = DEFAULT_GENERATE_ELF_STT_COMMON;
-bfd_boolean flag_generate_build_notes = DEFAULT_GENERATE_BUILD_NOTES;
+bool flag_generate_build_notes = DEFAULT_GENERATE_BUILD_NOTES;
#endif
/* Keep the output file. */
break;
case OPTION_GDWARF_SECTIONS:
- flag_dwarf_sections = TRUE;
+ flag_dwarf_sections = true;
break;
case OPTION_GDWARF_CIE_VERSION:
case OPTION_SIZE_CHECK:
if (strcasecmp (optarg, "error") == 0)
- flag_allow_nonconst_size = FALSE;
+ flag_allow_nonconst_size = false;
else if (strcasecmp (optarg, "warning") == 0)
- flag_allow_nonconst_size = TRUE;
+ flag_allow_nonconst_size = true;
else
as_fatal (_("Invalid --size-check= option: `%s'"), optarg);
break;
case OPTION_ELF_BUILD_NOTES:
if (strcasecmp (optarg, "no") == 0)
- flag_generate_build_notes = FALSE;
+ flag_generate_build_notes = false;
else if (strcasecmp (optarg, "yes") == 0)
- flag_generate_build_notes = TRUE;
+ flag_generate_build_notes = true;
else
as_fatal (_("Invalid --generate-missing-build-notes option: `%s'"),
optarg);
extern enum debug_info_type debug_type;
extern int use_gnu_debug_info_extensions;
-COMMON bfd_boolean flag_dwarf_sections;
+COMMON bool flag_dwarf_sections;
extern int flag_dwarf_cie_version;
extern unsigned int dwarf_level;
\f
char * atof_ieee (char *, int, LITTLENUM_TYPE *);
char * atof_ieee_detail (char *, int, int, LITTLENUM_TYPE *, FLONUM_TYPE *);
-const char * ieee_md_atof (int, char *, int *, bfd_boolean);
+const char * ieee_md_atof (int, char *, int *, bool);
const char * vax_md_atof (int, char *, int *);
char * input_scrub_include_file (const char *, char *);
void input_scrub_insert_line (const char *);
/* TRUE iff GNU Build attribute notes should
be generated if none are in the input files. */
-extern bfd_boolean flag_generate_build_notes;
+extern bool flag_generate_build_notes;
/* If section name substitution sequences should be honored */
COMMON int flag_sectname_subst;
#define SEC_OCTETS 0
#endif
+#define POISON_BFD_BOOLEAN 1
+
#endif /* GAS */
if ( /* seen_significant_digit || */ c > '0')
{
- seen_significant_digit = TRUE;
+ seen_significant_digit = true;
}
}
else
ieee_md_atof (int type,
char *litP,
int *sizeP,
- bfd_boolean big_wordian)
+ bool big_wordian)
{
LITTLENUM_TYPE words[MAX_LITTLENUMS];
LITTLENUM_TYPE *wordP;
INSTR_T bfin_gen_pseudodbg (int, int, int);
INSTR_T bfin_gen_pseudodbg_assert (int, REG_T, int);
INSTR_T bfin_gen_pseudochr (int);
-bfd_boolean bfin_resource_conflict (INSTR_T, INSTR_T, INSTR_T);
+bool bfin_resource_conflict (INSTR_T, INSTR_T, INSTR_T);
INSTR_T bfin_gen_multi_instr (INSTR_T, INSTR_T, INSTR_T);
memset (s, 0, sz);
coffsymbol (symbol_get_bfdsym (symbolP))->native = (combined_entry_type *) s;
- coffsymbol (symbol_get_bfdsym (symbolP))->native->is_sym = TRUE;
+ coffsymbol (symbol_get_bfdsym (symbolP))->native->is_sym = true;
S_SET_DATA_TYPE (symbolP, T_NULL);
S_SET_STORAGE_CLASS (symbolP, 0);
unsigned int exp;
flagword flags, oldflags;
asection *sec;
- bfd_boolean is_bss = FALSE;
+ bool is_bss = false;
if (flag_mri)
{
/* Uninitialised data section. */
flags |= SEC_ALLOC;
flags &=~ SEC_LOAD;
- is_bss = TRUE;
+ is_bss = true;
break;
case 'n':
memset (p, 0, 12);
file = as_where ((unsigned int *) NULL);
stabstr_name = concat (seg->name, "str", (char *) NULL);
- stroff = get_stab_string_offset (file, stabstr_name, TRUE);
+ stroff = get_stab_string_offset (file, stabstr_name, true);
know (stroff == 1);
md_number_to_chars (p, stroff, 4);
}
know (bfd_asymbol_flavour (symbol_get_bfdsym (sym))
== bfd_target_ecoff_flavour);
esym = ecoffsymbol (symbol_get_bfdsym (sym));
- esym->local = FALSE;
+ esym->local = false;
esym->native = xmalloc (debug_swap->external_ext_size);
(*debug_swap->swap_ext_out) (stdoutput, ext, esym->native);
}
/* Return TRUE iff SEC matches the section info INF. */
-static bfd_boolean
+static bool
get_section_by_match (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
{
struct elf_section_match *match = (struct elf_section_match *) inf;
if (ssect != NULL)
{
- bfd_boolean override = FALSE;
+ bool override = false;
if (type == SHT_NULL)
type = ssect->type;
&& (strcmp (name, ".interp") == 0
|| strcmp (name, ".strtab") == 0
|| strcmp (name, ".symtab") == 0))
- override = TRUE;
+ override = true;
/* .note.GNU-stack can have SHF_EXECINSTR. */
else if (generic_attr == SHF_EXECINSTR
&& strcmp (name, ".note.GNU-stack") == 0)
- override = TRUE;
+ override = true;
#ifdef TC_ALPHA
/* A section on Alpha may have SHF_ALPHA_GPREL. */
else if ((generic_attr & ~ssect->attr) == SHF_ALPHA_GPREL)
- override = TRUE;
+ override = true;
#endif
#ifdef TC_RX
else if (generic_attr == (SHF_EXECINSTR | SHF_WRITE | SHF_ALLOC)
if (match_p->group_name == NULL)
as_warn (_("setting incorrect section attributes for %s"),
name);
- override = TRUE;
+ override = true;
}
}
static bfd_vma
obj_elf_parse_section_letters (char *str, size_t len,
- bfd_boolean *is_clone, bfd_vma *gnu_attr)
+ bool *is_clone, bfd_vma *gnu_attr)
{
bfd_vma attr = 0;
- *is_clone = FALSE;
+ *is_clone = false;
while (len > 0)
{
*gnu_attr |= SHF_GNU_RETAIN;
break;
case '?':
- *is_clone = TRUE;
+ *is_clone = true;
break;
/* Compatibility. */
case 'm':
}
static int
-obj_elf_section_type (char *str, size_t len, bfd_boolean warn)
+obj_elf_section_type (char *str, size_t len, bool warn)
{
if (len == 8 && strncmp (str, "progbits", 8) == 0)
return SHT_PROGBITS;
}
#endif
- ret = obj_elf_section_type (str, len, FALSE);
+ ret = obj_elf_section_type (str, len, false);
if (ret != 0)
*type = ret;
else
if (*input_line_pointer == '"')
{
- bfd_boolean is_clone;
+ bool is_clone;
beg = demand_copy_C_string (&dummy);
if (beg == NULL)
ignore_rest_of_line ();
return;
}
- type = obj_elf_section_type (beg, strlen (beg), TRUE);
+ type = obj_elf_section_type (beg, strlen (beg), true);
}
else if (c == '@' || c == '%')
{
(void) restore_line_pointer (c);
type = obj_elf_section_type (beg,
input_line_pointer - beg,
- TRUE);
+ true);
}
}
else
if ((attr & SHF_GROUP) != 0 && is_clone)
{
as_warn (_("? section flag ignored with G present"));
- is_clone = FALSE;
+ is_clone = false;
}
if ((attr & SHF_GROUP) != 0 && *input_line_pointer == ',')
if (ISDIGIT (* input_line_pointer))
{
bfd_vma id;
- bfd_boolean overflow;
+ bool overflow;
char *t = input_line_pointer;
if (sizeof (bfd_vma) <= sizeof (unsigned long))
{
if ((gnu_attr & (SHF_GNU_MBIND | SHF_GNU_RETAIN)) != 0)
{
const struct elf_backend_data *bed;
- bfd_boolean mbind_p = (gnu_attr & SHF_GNU_MBIND) != 0;
+ bool mbind_p = (gnu_attr & SHF_GNU_MBIND) != 0;
if (mbind_p && (attr & SHF_ALLOC) == 0)
as_bad (_("SHF_ALLOC isn't set for GNU_MBIND section: %s"), name);
return NULL;
}
}
- sy_obj->rename = TRUE;
+ sy_obj->rename = true;
break;
default:
as_bad (_("invalid version name '%s' for symbol `%s'"),
if (obj_elf_find_and_add_versioned_name (name, sym_name,
p, sy_obj) == NULL)
{
- sy_obj->bad_version = TRUE;
+ sy_obj->bad_version = true;
ignore_rest_of_line ();
return;
}
/* Return true if we have seen an explicit specification of attribute TAG
for vendor VENDOR. */
-bfd_boolean
+bool
obj_elf_seen_attribute (int vendor, unsigned int tag)
{
unsigned int base;
for (rai = recorded_attributes; rai; rai = rai->next)
if (rai->vendor == vendor && rai->base == base)
return (rai->mask & mask) != 0;
- return FALSE;
+ return false;
}
/* Parse an attribute directive for VENDOR.
memset (p, 0, 12);
file = remap_debug_filename (as_where (NULL));
stabstr_name = concat (segment_name (seg), "str", (char *) NULL);
- stroff = get_stab_string_offset (file, stabstr_name, TRUE);
+ stroff = get_stab_string_offset (file, stabstr_name, true);
know (stroff == 1 || (stroff == 0 && file[0] == '\0'));
md_number_to_chars (p, stroff, 4);
seg_info (seg)->stabu.p = p;
supposed to *EXT to the external symbol information, and return
whether the symbol should be used at all. */
-static bfd_boolean
+static bool
elf_get_extr (asymbol *sym, EXTR *ext)
{
if (sym->udata.p == NULL)
- return FALSE;
+ return false;
*ext = *(EXTR *) sym->udata.p;
- return TRUE;
+ return true;
}
/* This function is called by bfd_ecoff_debug_externals. It has
/* We will have already reported an version error. */
if (sy_obj->bad_version)
- *puntp = TRUE;
+ *puntp = true;
/* elf_frob_file_before_adjust only allows one version symbol for
renamed symbol. */
else if (sy_obj->rename)
{
as_bad (_("`%s' can't be versioned to common symbol '%s'"),
versioned_name->name, S_GET_NAME (symp));
- *puntp = TRUE;
+ *puntp = true;
}
else
{
return;
}
- sy_obj->rename = TRUE;
+ sy_obj->rename = true;
}
}
/* Set up the external symbols. */
debug.ssext = debug.ssext_end = NULL;
debug.external_ext = debug.external_ext_end = NULL;
- if (! bfd_ecoff_debug_externals (stdoutput, &debug, debug_swap, TRUE,
+ if (! bfd_ecoff_debug_externals (stdoutput, &debug, debug_swap, true,
elf_get_extr, elf_set_index))
as_fatal (_("failed to set up debugging information: %s"),
bfd_errmsg (bfd_get_error ()));
extern void obj_elf_vtable_entry (int);
extern struct fix * obj_elf_get_vtable_inherit (void);
extern struct fix * obj_elf_get_vtable_entry (void);
-extern bfd_boolean obj_elf_seen_attribute
+extern bool obj_elf_seen_attribute
(int, unsigned int);
extern int obj_elf_vendor_attribute (int);
p = frag_more (12);
memset (p, 0, 12);
file = as_where ((unsigned int *) NULL);
- stroff = get_stab_string_offset (file, "$GDB_STRINGS$", FALSE);
+ stroff = get_stab_string_offset (file, "$GDB_STRINGS$", false);
know (stroff == 1);
md_number_to_chars (p, stroff, 4);
seg_info (seg)->stabu.p = p;
static aarch64_instruction inst;
-static bfd_boolean parse_operands (char *, const aarch64_opcode *);
-static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
+static bool parse_operands (char *, const aarch64_opcode *);
+static bool programmer_friendly_fixup (aarch64_instruction *);
#ifdef OBJ_ELF
# define now_instr_sequence seg_info \
inst.parsing_error.error = NULL;
}
-static inline bfd_boolean
+static inline bool
error_p (void)
{
return inst.parsing_error.kind != AARCH64_OPDE_NIL;
#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
-static inline bfd_boolean
+static inline bool
skip_past_char (char **str, char c)
{
if (**str == c)
{
(*str)++;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
#define skip_past_comma(str) skip_past_char (str, ',')
/* Arithmetic expressions (possibly involving symbols). */
-static bfd_boolean in_my_get_expression_p = FALSE;
+static bool in_my_get_expression_p = false;
/* Third argument to my_get_expression. */
#define GE_NO_PREFIX 0
as an valid expression; *EP will be filled with the information of
such an expression. Otherwise return FALSE. */
-static bfd_boolean
+static bool
my_get_expression (expressionS * ep, char **str, int prefix_mode,
int reject_absent)
{
save_in = input_line_pointer;
input_line_pointer = *str;
- in_my_get_expression_p = TRUE;
+ in_my_get_expression_p = true;
seg = expression (ep);
- in_my_get_expression_p = FALSE;
+ in_my_get_expression_p = false;
if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
{
set_fatal_syntax_error (_("bad expression"));
else
set_first_syntax_error (_("bad expression"));
- return FALSE;
+ return false;
}
#ifdef OBJ_AOUT
set_syntax_error (_("bad segment"));
*str = input_line_pointer;
input_line_pointer = save_in;
- return FALSE;
+ return false;
}
#else
(void) seg;
*str = input_line_pointer;
input_line_pointer = save_in;
- return TRUE;
+ return true;
}
/* Turn a string in input_line_pointer into a floating point constant
/* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
return FALSE. */
-static bfd_boolean
+static bool
aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
{
return (reg_type_masks[type] & (1 << reg->type)) != 0;
Accept only one occurrence of:
4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
b h s d q */
-static bfd_boolean
+static bool
parse_vector_type_for_operand (aarch64_reg_type reg_type,
struct vector_type_el *parsed_type, char **str)
{
if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
{
first_error_fmt (_("bad size %d in vector width specifier"), width);
- return FALSE;
+ return false;
}
elt_size:
first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
else
first_error (_("missing element size"));
- return FALSE;
+ return false;
}
if (width != 0 && width * element_size != 64
&& width * element_size != 128
first_error_fmt (_
("invalid element size %d and vector size combination %c"),
width, *ptr);
- return FALSE;
+ return false;
}
ptr++;
*str = ptr;
- return TRUE;
+ return true;
}
/* *STR contains an SVE zero/merge predication suffix. Parse it into
*PARSED_TYPE and point *STR at the end of the suffix. */
-static bfd_boolean
+static bool
parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
{
char *ptr = *str;
*ptr);
else
first_error (_("missing predication type"));
- return FALSE;
+ return false;
}
parsed_type->width = 0;
*str = ptr + 1;
- return TRUE;
+ return true;
}
/* Parse a register of the type TYPE.
static int
parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
- struct vector_type_el *typeinfo, bfd_boolean in_reg_list)
+ struct vector_type_el *typeinfo, bool in_reg_list)
{
char *str = *ccp;
const reg_entry *reg = parse_reg (&str);
struct vector_type_el atype;
struct vector_type_el parsetype;
- bfd_boolean is_typed_vecreg = FALSE;
+ bool is_typed_vecreg = false;
atype.defined = 0;
atype.type = NT_invtype;
}
/* Register if of the form Vn.[bhsdq]. */
- is_typed_vecreg = TRUE;
+ is_typed_vecreg = true;
if (type == REG_TYPE_ZN || type == REG_TYPE_PN)
{
struct vector_type_el atype;
char *str = *ccp;
int reg = parse_typed_reg (&str, type, rtype, &atype,
- /*in_reg_list= */ FALSE);
+ /*in_reg_list= */ false);
if (reg == PARSE_FAIL)
return PARSE_FAIL;
return reg;
}
-static inline bfd_boolean
+static inline bool
eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2)
{
return
int in_range;
int ret_val;
int i;
- bfd_boolean error = FALSE;
- bfd_boolean expect_index = FALSE;
+ bool error = false;
+ bool expect_index = false;
if (*str != '{')
{
val_range = val;
}
val = parse_typed_reg (&str, type, NULL, &typeinfo,
- /*in_reg_list= */ TRUE);
+ /*in_reg_list= */ true);
if (val == PARSE_FAIL)
{
set_first_syntax_error (_("invalid vector register in list"));
- error = TRUE;
+ error = true;
continue;
}
/* reject [bhsd]n */
if (type == REG_TYPE_VN && typeinfo.defined == 0)
{
set_first_syntax_error (_("invalid scalar register in list"));
- error = TRUE;
+ error = true;
continue;
}
if (typeinfo.defined & NTA_HASINDEX)
- expect_index = TRUE;
+ expect_index = true;
if (in_range)
{
{
set_first_syntax_error
(_("invalid range in vector register list"));
- error = TRUE;
+ error = true;
}
val_range++;
}
{
set_first_syntax_error
(_("type mismatch in vector register list"));
- error = TRUE;
+ error = true;
}
}
if (! error)
if (*str != '}')
{
set_first_syntax_error (_("end of vector register list not found"));
- error = TRUE;
+ error = true;
}
str++;
if (exp.X_op != O_constant)
{
set_first_syntax_error (_("constant expression required."));
- error = TRUE;
+ error = true;
}
if (! skip_past_char (&str, ']'))
- error = TRUE;
+ error = true;
else
typeinfo_first.index = exp.X_add_number;
}
else
{
set_first_syntax_error (_("expected index"));
- error = TRUE;
+ error = true;
}
}
if (nb_regs > 4)
{
set_first_syntax_error (_("too many registers in vector register list"));
- error = TRUE;
+ error = true;
}
else if (nb_regs == 0)
{
set_first_syntax_error (_("empty vector register list"));
- error = TRUE;
+ error = true;
}
*ccp = str;
new->name = name;
new->number = number;
new->type = type;
- new->builtin = FALSE;
+ new->builtin = false;
str_hash_insert (aarch64_reg_hsh, name, new, 0);
If we find one, or if it looks sufficiently like one that we want to
handle any error here, return TRUE. Otherwise return FALSE. */
-static bfd_boolean
+static bool
create_register_alias (char *newname, char *p)
{
const reg_entry *old;
collapsed to single spaces. */
oldname = p;
if (strncmp (oldname, " .req ", 6) != 0)
- return FALSE;
+ return false;
oldname += 6;
if (*oldname == '\0')
- return FALSE;
+ return false;
old = str_hash_find (aarch64_reg_hsh, oldname);
if (!old)
{
as_warn (_("unknown register '%s' -- .req ignored"), oldname);
- return TRUE;
+ return true;
}
/* If TC_CASE_SENSITIVE is defined, then newname already points to
if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
{
free (nbuf);
- return TRUE;
+ return true;
}
}
}
free (nbuf);
- return TRUE;
+ return true;
}
/* Should never be called, as .req goes between the alias and the
/* Add the literal of size SIZE in *EXP to the relevant literal pool.
Return TRUE on success, otherwise return FALSE. */
-static bfd_boolean
+static bool
add_to_lit_pool (expressionS *exp, int size)
{
literal_pool *pool;
if (entry >= MAX_LITERAL_POOL_SIZE)
{
set_syntax_error (_("literal pool overflow"));
- return FALSE;
+ return false;
}
pool->literals[entry].exp = *exp;
exp->X_add_number = ((int) entry) * size;
exp->X_add_symbol = pool->symbol;
- return TRUE;
+ return true;
}
/* Can't use symbol_new here, so have to create a symbol and then at
state from being spoiled.
The function currently serves parse_constant_immediate and
parse_big_immediate only. */
-static bfd_boolean
+static bool
reg_name_p (char *str, aarch64_reg_type reg_type)
{
int reg;
/* Prevent the diagnostics state from being spoiled. */
if (error_p ())
- return FALSE;
+ return false;
reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
clear_error ();
if (reg == PARSE_FAIL)
- return FALSE;
+ return false;
skip_whitespace (str);
if (*str == ',' || is_end_of_line[(unsigned char) *str])
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Parser functions used exclusively in instruction operands. */
done to find out whether STR is a register of type REG_TYPE followed
by a comma or the end of line. Return FALSE if STR is such a string. */
-static bfd_boolean
+static bool
parse_immediate_expression (char **str, expressionS *exp,
aarch64_reg_type reg_type)
{
if (reg_name_p (*str, reg_type))
{
set_recoverable_error (_("immediate operand required"));
- return FALSE;
+ return false;
}
my_get_expression (exp, str, GE_OPT_PREFIX, 1);
if (exp->X_op == O_absent)
{
set_fatal_syntax_error (_("missing immediate expression"));
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Constant immediate-value read function for use in insn parsing.
Return TRUE on success; otherwise return FALSE. */
-static bfd_boolean
+static bool
parse_constant_immediate (char **str, int64_t *val, aarch64_reg_type reg_type)
{
expressionS exp;
if (! parse_immediate_expression (str, &exp, reg_type))
- return FALSE;
+ return false;
if (exp.X_op != O_constant)
{
set_syntax_error (_("constant expression required"));
- return FALSE;
+ return false;
}
*val = exp.X_add_number;
- return TRUE;
+ return true;
}
static uint32_t
(+/-) n / 16 * power (2, r)
where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
-static bfd_boolean
+static bool
aarch64_imm_float_p (uint32_t imm)
{
/* If a single-precision floating-point value has the following bit
as an IEEE float without any loss of precision. Store the value in
*FPWORD if so. */
-static bfd_boolean
+static bool
can_convert_double_to_float (uint64_t imm, uint32_t *fpword)
{
/* If a double-precision floating-point value has the following bit
/* Lower 29 bits need to be 0s. */
if ((imm & 0x1fffffff) != 0)
- return FALSE;
+ return false;
/* Prepare the pattern for 'Eeeeeeeee'. */
if (((high32 >> 30) & 0x1) == 0)
/* Check E~~~. */
if ((high32 & 0x78000000) != pattern)
- return FALSE;
+ return false;
/* Check Eeee_eeee != 1111_1111. */
if ((high32 & 0x7ff00000) == 0x47f00000)
- return FALSE;
+ return false;
*fpword = ((high32 & 0xc0000000) /* 1 n bit and 1 E bit. */
| ((high32 << 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
| (low32 >> 29)); /* 3 S bits. */
- return TRUE;
+ return true;
}
/* Return true if we should treat OPERAND as a double-precision
floating-point operand rather than a single-precision one. */
-static bfd_boolean
+static bool
double_precision_operand_p (const aarch64_opnd_info *operand)
{
/* Check for unsuffixed SVE registers, which are allowed
This routine accepts any IEEE float; it is up to the callers to reject
invalid ones. */
-static bfd_boolean
-parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p,
+static bool
+parse_aarch64_imm_float (char **ccp, int *immed, bool dp_p,
aarch64_reg_type reg_type)
{
char *str = *ccp;
LITTLENUM_TYPE words[MAX_LITTLENUMS];
int64_t val = 0;
unsigned fpword = 0;
- bfd_boolean hex_p = FALSE;
+ bool hex_p = false;
skip_past_char (&str, '#');
else
fpword = val;
- hex_p = TRUE;
+ hex_p = true;
}
else if (reg_name_p (str, reg_type))
{
set_recoverable_error (_("immediate operand required"));
- return FALSE;
+ return false;
}
if (! hex_p)
*immed = fpword;
*ccp = str;
- return TRUE;
+ return true;
invalid_fp:
set_fatal_syntax_error (_("invalid floating-point constant"));
- return FALSE;
+ return false;
}
/* Less-generic immediate-value read function with the possibility of loading
out whether STR is a register of type REG_TYPE followed by a comma or
the end of line. Return FALSE if STR is such a register. */
-static bfd_boolean
+static bool
parse_big_immediate (char **str, int64_t *imm, aarch64_reg_type reg_type)
{
char *ptr = *str;
if (reg_name_p (ptr, reg_type))
{
set_syntax_error (_("immediate operand required"));
- return FALSE;
+ return false;
}
my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
*str = ptr;
- return TRUE;
+ return true;
}
/* Set operand IDX of the *INSTR that needs a GAS internal fixup.
/* Return TRUE if the instruction needs to be fixed up later internally by
the GAS; otherwise return FALSE. */
-static inline bfd_boolean
+static inline bool
aarch64_gas_internal_fixup_p (void)
{
return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
/* Parse a <shift> operator on an AArch64 data processing instruction.
Return TRUE on success; otherwise return FALSE. */
-static bfd_boolean
+static bool
parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
{
const struct aarch64_name_value_pair *shift_op;
if (p == *str)
{
set_syntax_error (_("shift expression expected"));
- return FALSE;
+ return false;
}
shift_op = str_hash_find_n (aarch64_shift_hsh, *str, p - *str);
if (shift_op == NULL)
{
set_syntax_error (_("shift operator expected"));
- return FALSE;
+ return false;
}
kind = aarch64_get_operand_modifier (shift_op);
if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
{
set_syntax_error (_("invalid use of 'MSL'"));
- return FALSE;
+ return false;
}
if (kind == AARCH64_MOD_MUL
&& mode != SHIFTED_MUL_VL)
{
set_syntax_error (_("invalid use of 'MUL'"));
- return FALSE;
+ return false;
}
switch (mode)
if (aarch64_extend_operator_p (kind))
{
set_syntax_error (_("extending shift is not permitted"));
- return FALSE;
+ return false;
}
break;
if (kind == AARCH64_MOD_ROR)
{
set_syntax_error (_("'ROR' shift is not permitted"));
- return FALSE;
+ return false;
}
break;
if (kind != AARCH64_MOD_LSL)
{
set_syntax_error (_("only 'LSL' shift is permitted"));
- return FALSE;
+ return false;
}
break;
if (kind != AARCH64_MOD_MUL)
{
set_syntax_error (_("only 'MUL' is permitted"));
- return FALSE;
+ return false;
}
break;
}
}
set_syntax_error (_("only 'MUL VL' is permitted"));
- return FALSE;
+ return false;
case SHIFTED_REG_OFFSET:
if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
{
set_fatal_syntax_error
(_("invalid shift for the register offset addressing mode"));
- return FALSE;
+ return false;
}
break;
if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
{
set_syntax_error (_("invalid shift operator"));
- return FALSE;
+ return false;
}
break;
if (!aarch64_extend_operator_p (kind) || exp_has_prefix)
{
set_syntax_error (_("missing shift amount"));
- return FALSE;
+ return false;
}
operand->shifter.amount = 0;
}
else if (exp.X_op != O_constant)
{
set_syntax_error (_("constant shift amount required"));
- return FALSE;
+ return false;
}
/* For parsing purposes, MUL #n has no inherent range. The range
depends on the operand and will be checked by operand-specific
&& (exp.X_add_number < 0 || exp.X_add_number > 63))
{
set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
- return FALSE;
+ return false;
}
else
{
operand->shifter.kind = kind;
*str = p;
- return TRUE;
+ return true;
}
/* Parse a <shifter_operand> for a data processing instruction:
Return TRUE on success; otherwise return FALSE. */
-static bfd_boolean
+static bool
parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
enum parse_shift_mode mode)
{
char *p;
if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
- return FALSE;
+ return false;
p = *str;
/* Accept an immediate expression. */
if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
- return FALSE;
+ return false;
/* Accept optional LSL for arithmetic immediate values. */
if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
if (! parse_shift (&p, operand, SHIFTED_LSL))
- return FALSE;
+ return false;
/* Not accept any shifter for logical immediate values. */
if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
&& parse_shift (&p, operand, mode))
{
set_syntax_error (_("unexpected shift operator"));
- return FALSE;
+ return false;
}
*str = p;
- return TRUE;
+ return true;
}
/* Parse a <shifter_operand> for a data processing instruction:
Return TRUE on success; otherwise return FALSE. */
-static bfd_boolean
+static bool
parse_shifter_operand (char **str, aarch64_opnd_info *operand,
enum parse_shift_mode mode)
{
if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
{
set_syntax_error (_("unexpected register in the immediate operand"));
- return FALSE;
+ return false;
}
if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
{
set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
- return FALSE;
+ return false;
}
operand->reg.regno = reg->number;
/* Accept optional shift operation on register. */
if (! skip_past_comma (str))
- return TRUE;
+ return true;
if (! parse_shift (str, operand, mode))
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
{
set_syntax_error
(_("integer register expected in the extended/shifted operand "
"register"));
- return FALSE;
+ return false;
}
/* We have a shifted immediate variable. */
/* Return TRUE on success; return FALSE otherwise. */
-static bfd_boolean
+static bool
parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
enum parse_shift_mode mode)
{
if (!(entry = find_reloc_table_entry (str)))
{
set_syntax_error (_("unknown relocation modifier"));
- return FALSE;
+ return false;
}
if (entry->add_type == 0)
{
set_syntax_error
(_("this relocation modifier is not allowed on this instruction"));
- return FALSE;
+ return false;
}
/* Save str before we decompose it. */
/* Next, we parse the expression. */
if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
- return FALSE;
+ return false;
/* Record the relocation type (use the ADD variant here). */
inst.reloc.type = entry->add_type;
/* If str is empty, we've reached the end, stop here. */
if (**str == '\0')
- return TRUE;
+ return true;
/* Otherwise, we have a shifted reloc modifier, so rewind to
recover the variable name and continue parsing for the shifter. */
for addressing modes not supported by the instruction, and to set
inst.reloc.type. */
-static bfd_boolean
+static bool
parse_address_main (char **str, aarch64_opnd_info *operand,
aarch64_opnd_qualifier_t *base_qualifier,
aarch64_opnd_qualifier_t *offset_qualifier,
if (! entry)
{
set_syntax_error (_("unknown relocation modifier"));
- return FALSE;
+ return false;
}
switch (operand->type)
set_syntax_error
(_("this relocation modifier is not allowed on this "
"instruction"));
- return FALSE;
+ return false;
}
/* #:<reloc_op>: */
if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
{
set_syntax_error (_("invalid relocation expression"));
- return FALSE;
+ return false;
}
/* #:<reloc_op>:<expr> */
if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
{
set_syntax_error (_("invalid address"));
- return FALSE;
+ return false;
}
}
*str = p;
- return TRUE;
+ return true;
}
/* [ */
if (!reg || !aarch64_check_reg_type (reg, base_type))
{
set_syntax_error (_(get_reg_expected_msg (base_type)));
- return FALSE;
+ return false;
}
operand->addr.base_regno = reg->number;
if (!aarch64_check_reg_type (reg, offset_type))
{
set_syntax_error (_(get_reg_expected_msg (offset_type)));
- return FALSE;
+ return false;
}
/* [Xn,Rm */
if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
/* Use the diagnostics set in parse_shift, so not set new
error message here. */
- return FALSE;
+ return false;
}
/* We only accept:
[base,Xm] # For vector plus scalar SVE2 indexing.
if (*offset_qualifier == AARCH64_OPND_QLF_W)
{
set_syntax_error (_("invalid use of 32-bit register offset"));
- return FALSE;
+ return false;
}
if (aarch64_get_qualifier_esize (*base_qualifier)
!= aarch64_get_qualifier_esize (*offset_qualifier)
|| *offset_qualifier != AARCH64_OPND_QLF_X))
{
set_syntax_error (_("offset has different size from base"));
- return FALSE;
+ return false;
}
}
else if (*offset_qualifier == AARCH64_OPND_QLF_X)
{
set_syntax_error (_("invalid use of 64-bit register offset"));
- return FALSE;
+ return false;
}
}
else
if (!(entry = find_reloc_table_entry (&p)))
{
set_syntax_error (_("unknown relocation modifier"));
- return FALSE;
+ return false;
}
if (entry->ldst_type == 0)
set_syntax_error
(_("this relocation modifier is not allowed on this "
"instruction"));
- return FALSE;
+ return false;
}
/* [Xn,#:<reloc_op>: */
if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
{
set_syntax_error (_("invalid relocation expression"));
- return FALSE;
+ return false;
}
/* [Xn,#:<reloc_op>:<expr> */
if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
{
set_syntax_error (_("invalid expression in the address"));
- return FALSE;
+ return false;
}
/* [Xn,<expr> */
if (imm_shift_mode != SHIFTED_NONE && skip_past_comma (&p))
/* [Xn,<expr>,<shifter> */
if (! parse_shift (&p, operand, imm_shift_mode))
- return FALSE;
+ return false;
}
}
}
if (! skip_past_char (&p, ']'))
{
set_syntax_error (_("']' expected"));
- return FALSE;
+ return false;
}
if (skip_past_char (&p, '!'))
{
set_syntax_error (_("register offset not allowed in pre-indexed "
"addressing mode"));
- return FALSE;
+ return false;
}
/* [Xn]! */
operand->addr.writeback = 1;
if (operand->addr.preind)
{
set_syntax_error (_("cannot combine pre- and post-indexing"));
- return FALSE;
+ return false;
}
reg = aarch64_reg_parse_32_64 (&p, offset_qualifier);
if (!aarch64_check_reg_type (reg, REG_TYPE_R_64))
{
set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
- return FALSE;
+ return false;
}
operand->addr.offset.regno = reg->number;
{
/* [Xn],#expr */
set_syntax_error (_("invalid expression in the address"));
- return FALSE;
+ return false;
}
}
{
/* Reject [Rn]! */
set_syntax_error (_("missing offset in the pre-indexed address"));
- return FALSE;
+ return false;
}
}
else
}
*str = p;
- return TRUE;
+ return true;
}
/* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
on success. */
-static bfd_boolean
+static bool
parse_address (char **str, aarch64_opnd_info *operand)
{
aarch64_opnd_qualifier_t base_qualifier, offset_qualifier;
/* Parse an address in which SVE vector registers and MUL VL are allowed.
The arguments have the same meaning as for parse_address_main.
Return TRUE on success. */
-static bfd_boolean
+static bool
parse_sve_address (char **str, aarch64_opnd_info *operand,
aarch64_opnd_qualifier_t *base_qualifier,
aarch64_opnd_qualifier_t *offset_qualifier)
/* Parse an operand for a MOVZ, MOVN or MOVK instruction.
Return TRUE on success; otherwise return FALSE. */
-static bfd_boolean
+static bool
parse_half (char **str, int *internal_fixup_p)
{
char *p = *str;
if (!(entry = find_reloc_table_entry (&p)))
{
set_syntax_error (_("unknown relocation modifier"));
- return FALSE;
+ return false;
}
if (entry->movw_type == 0)
{
set_syntax_error
(_("this relocation modifier is not allowed on this instruction"));
- return FALSE;
+ return false;
}
inst.reloc.type = entry->movw_type;
*internal_fixup_p = 1;
if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
- return FALSE;
+ return false;
*str = p;
- return TRUE;
+ return true;
}
/* Parse an operand for an ADRP instruction:
ADRP <Xd>, <label>
Return TRUE on success; otherwise return FALSE. */
-static bfd_boolean
+static bool
parse_adrp (char **str)
{
char *p;
if (!(entry = find_reloc_table_entry (&p)))
{
set_syntax_error (_("unknown relocation modifier"));
- return FALSE;
+ return false;
}
if (entry->adrp_type == 0)
{
set_syntax_error
(_("this relocation modifier is not allowed on this instruction"));
- return FALSE;
+ return false;
}
inst.reloc.type = entry->adrp_type;
inst.reloc.pc_rel = 1;
if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
- return FALSE;
+ return false;
*str = p;
- return TRUE;
+ return true;
}
/* Miscellaneous. */
{
*val = i;
*str = q;
- return TRUE;
+ return true;
}
if (!parse_immediate_expression (&p, &exp, reg_type))
- return FALSE;
+ return false;
if (exp.X_op == O_constant
&& (uint64_t) exp.X_add_number < size)
{
*val = exp.X_add_number;
*str = p;
- return TRUE;
+ return true;
}
/* Use the default error for this operand. */
- return FALSE;
+ return false;
}
/* Parse an option for a preload instruction. Returns the encoding for the
line, only the error of the highest severity will be picked up for
issuing the diagnostics. */
-static inline bfd_boolean
+static inline bool
operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
enum aarch64_operand_error_kind rhs)
{
/* Return TRUE if some operand error has been recorded during the
parsing of the current assembly line using the opcode *OPCODE;
otherwise return FALSE. */
-static inline bfd_boolean
+static inline bool
opcode_has_operand_error_p (const aarch64_opcode *opcode)
{
operand_error_record *record = operand_error_report.head;
info.index = idx;
info.kind = kind;
info.error = error;
- info.non_fatal = FALSE;
+ info.non_fatal = false;
record_operand_error_info (opcode, &info);
}
info.data[0] = extra_data[0];
info.data[1] = extra_data[1];
info.data[2] = extra_data[2];
- info.non_fatal = FALSE;
+ info.non_fatal = false;
record_operand_error_info (opcode, &info);
}
which is still not right. */
size_t len = strlen (get_mnemonic_name (str));
int i, qlf_idx;
- bfd_boolean result;
+ bool result;
char buf[2048];
aarch64_inst *inst_base = &inst.base;
const aarch64_opnd_qualifier_seq_t *qualifiers_list;
print due to the different instruction templates. */
static void
-output_operand_error_report (char *str, bfd_boolean non_fatal_only)
+output_operand_error_report (char *str, bool non_fatal_only)
{
int largest_error_pos;
const char *msg = NULL;
/* Process the relocation type for move wide instructions.
Return TRUE on success; otherwise return FALSE. */
-static bfd_boolean
+static bool
process_movw_reloc_info (void)
{
int is32;
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
set_syntax_error
(_("the specified relocation type is not allowed for MOVK"));
- return FALSE;
+ return false;
default:
break;
}
set_fatal_syntax_error
(_("the specified relocation type is not allowed for 32-bit "
"register"));
- return FALSE;
+ return false;
}
shift = 32;
break;
set_fatal_syntax_error
(_("the specified relocation type is not allowed for 32-bit "
"register"));
- return FALSE;
+ return false;
}
shift = 48;
break;
are supported in GAS. */
gas_assert (aarch64_gas_internal_fixup_p ());
/* The shift amount should have already been set by the parser. */
- return TRUE;
+ return true;
}
inst.base.operands[1].shifter.amount = shift;
- return TRUE;
+ return true;
}
/* A primitive log calculator. */
Return FALSE if such a register list is invalid, otherwise return TRUE. */
-static bfd_boolean
+static bool
reg_list_valid_p (uint32_t reginfo, int accept_alternate)
{
uint32_t i, nb_regs, prev_regno, incr;
reginfo >>= 5;
curr_regno = reginfo & 0x1f;
if (curr_regno != ((prev_regno + incr) & 0x1f))
- return FALSE;
+ return false;
prev_regno = curr_regno;
}
- return TRUE;
+ return true;
}
/* Generic instruction operand parser. This does no encoding and no
structure. Returns TRUE or FALSE depending on whether the
specified grammar matched. */
-static bfd_boolean
+static bool
parse_operands (char *str, const aarch64_opcode *opcode)
{
int i;
case AARCH64_OPND_FPIMM0:
{
int qfloat;
- bfd_boolean res1 = FALSE, res2 = FALSE;
+ bool res1 = false, res2 = false;
/* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
it is probably not worth the effort to support it. */
- if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE,
+ if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, false,
imm_reg_type))
&& (error_p ()
|| !(res2 = parse_constant_immediate (&str, &val,
case AARCH64_OPND_SVE_FPIMM8:
{
int qfloat;
- bfd_boolean dp_p;
+ bool dp_p;
dp_p = double_precision_operand_p (&inst.base.operands[0]);
if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type)
case AARCH64_OPND_SVE_I1_ZERO_ONE:
{
int qfloat;
- bfd_boolean dp_p;
+ bool dp_p;
dp_p = double_precision_operand_p (&inst.base.operands[0]);
if (!parse_aarch64_imm_float (&str, &qfloat, dp_p, imm_reg_type))
the problem. */
record_operand_error (opcode, i, get_error_kind (),
get_error_message ());
- return FALSE;
+ return false;
}
else
{
DEBUG_TRACE ("parsing SUCCESS");
- return TRUE;
+ return true;
}
}
the preferred architectural syntax.
Return FALSE if there is any failure; otherwise return TRUE. */
-static bfd_boolean
+static bool
programmer_friendly_fixup (aarch64_instruction *instr)
{
aarch64_inst *base = &instr->base;
{
record_operand_out_of_range_error (opcode, 1, _("immediate value"),
0, 31);
- return FALSE;
+ return false;
}
operands[0].qualifier = AARCH64_OPND_QLF_X;
}
record_operand_error (opcode, 1,
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
_("constant expression expected"));
- return FALSE;
+ return false;
}
if (! add_to_lit_pool (&instr->reloc.exp, size))
{
record_operand_error (opcode, 1,
AARCH64_OPDE_OTHER_ERROR,
_("literal pool insertion failed"));
- return FALSE;
+ return false;
}
}
break;
}
DEBUG_TRACE ("exit with SUCCESS");
- return TRUE;
+ return true;
}
/* Check for loads and stores that will cause unpredictable behavior. */
Return TRUE on success; otherwise return FALSE. */
-static bfd_boolean
+static bool
do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
aarch64_insn *code)
{
error_info.kind = AARCH64_OPDE_NIL;
if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info, insn_sequence)
&& !error_info.non_fatal)
- return TRUE;
+ return true;
gas_assert (error_info.kind != AARCH64_OPDE_NIL);
record_operand_error_info (opcode, &error_info);
}
/* Issue non-fatal messages if any. */
- output_operand_error_report (str, TRUE);
+ output_operand_error_report (str, true);
return;
}
while (template != NULL);
/* Issue the error messages if any. */
- output_operand_error_report (str, FALSE);
+ output_operand_error_report (str, false);
}
/* Various frobbings of labels and their addresses. */
should appear in both upper and lowercase variants. Some registers
also have mixed-case names. */
-#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
-#define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
+#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true }
+#define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false}
#define REGNUM(p,n,t) REGDEF(p##n, n, t)
#define REGSET16(p,t) \
REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
range expressible by a unsigned number with the indicated number of
BITS. */
-static bfd_boolean
+static bool
unsigned_overflow (valueT value, unsigned bits)
{
valueT lim;
if (bits >= sizeof (valueT) * 8)
- return FALSE;
+ return false;
lim = (valueT) 1 << bits;
return (value >= lim);
}
range expressible by an signed number with the indicated number of
BITS. */
-static bfd_boolean
+static bool
signed_overflow (offsetT value, unsigned bits)
{
offsetT lim;
if (bits >= sizeof (offsetT) * 8)
- return FALSE;
+ return false;
lim = (offsetT) 1 << (bits - 1);
return (value < -lim || value >= lim);
}
in response to the standard LDR/STR mnemonics when the immediate offset is
unambiguous, i.e. when it is negative or unaligned. */
-static bfd_boolean
+static bool
try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
{
int idx;
}
if (new_op == OP_NIL)
- return FALSE;
+ return false;
new_opcode = aarch64_get_opcode (new_op);
gas_assert (new_opcode != NULL);
if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL,
insn_sequence))
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Called by fix_insn to fix a MOV immediate alias instruction.
static int
aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
- bfd_boolean ext_only)
+ bool ext_only)
{
/* We insist on extensions being added before being removed. We achieve
this by using the ADDING_VALUE variable to indicate whether we are
{
as_bad (_("must specify extensions to add before specifying "
"those to remove"));
- return FALSE;
+ return false;
}
}
{
mcpu_cpu_opt = &opt->value;
if (ext != NULL)
- return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE);
+ return aarch64_parse_features (ext, &mcpu_cpu_opt, false);
return 1;
}
{
march_cpu_opt = &opt->value;
if (ext != NULL)
- return aarch64_parse_features (ext, &march_cpu_opt, FALSE);
+ return aarch64_parse_features (ext, &march_cpu_opt, false);
return 1;
}
{
mcpu_cpu_opt = &opt->value;
if (ext != NULL)
- if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
+ if (!aarch64_parse_features (ext, &mcpu_cpu_opt, false))
return;
cpu_variant = *mcpu_cpu_opt;
{
mcpu_cpu_opt = &opt->value;
if (ext != NULL)
- if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
+ if (!aarch64_parse_features (ext, &mcpu_cpu_opt, false))
return;
cpu_variant = *mcpu_cpu_opt;
saved_char = *input_line_pointer;
*input_line_pointer = 0;
- if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE))
+ if (!aarch64_parse_features (ext, &mcpu_cpu_opt, true))
return;
cpu_variant = *mcpu_cpu_opt;
return vax_md_atof (type, litP, sizeP);
default:
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
}
unsigned char pcrel;
/* TRUE if this fixup is for LIMM operand. */
- bfd_boolean islong;
+ bool islong;
};
struct arc_insn
int nfixups;
struct arc_fixup fixups[MAX_INSN_FIXUPS];
long limm;
- unsigned int len; /* Length of instruction in bytes. */
- bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
- valid. */
- bfd_boolean relax; /* Boolean value: TRUE if needs
- relaxation. */
+ unsigned int len; /* Length of instruction in bytes. */
+ bool has_limm; /* Boolean value: TRUE if limm field is valid. */
+ bool relax; /* Boolean value: TRUE if needs relaxation. */
};
/* Structure to hold any last two instructions. */
const struct arc_opcode *opcode;
/* Boolean value: TRUE if current insn is short. */
- bfd_boolean has_limm;
+ bool has_limm;
/* Boolean value: TRUE if current insn has delay slot. */
- bfd_boolean has_delay_slot;
+ bool has_delay_slot;
} arc_last_insns[2];
/* Extension instruction suffix classes. */
static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
/* TRUE if current assembly code uses RF16 only registers. */
-static bfd_boolean rf16_only = TRUE;
+static bool rf16_only = true;
/* MPY option. */
static unsigned mpy_option = 0;
symbolS * GOT_symbol = 0;
/* Set to TRUE when we assemble instructions. */
-static bfd_boolean assembling_insn = FALSE;
+static bool assembling_insn = false;
/* List with attributes set explicitly. */
-static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
+static bool attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
/* Functions implementation. */
0, /* size: 1, 2, or 4 usually. */
sym, /* X_add_symbol. */
0, /* X_add_number. */
- FALSE, /* TRUE if PC-relative relocation. */
+ false, /* TRUE if PC-relative relocation. */
r_type /* Relocation type. */);
fixP->fx_subsy = lab;
}
int ntok)
{
char *old_input_line_pointer;
- bfd_boolean saw_comma = FALSE;
- bfd_boolean saw_arg = FALSE;
+ bool saw_comma = false;
+ bool saw_arg = false;
int brk_lvl = 0;
int num_args = 0;
input_line_pointer++;
if (saw_comma || !saw_arg)
goto err;
- saw_comma = TRUE;
+ saw_comma = true;
break;
case '}':
if (!saw_arg || num_args == ntok)
goto err;
tok->X_op = O_colon;
- saw_arg = FALSE;
+ saw_arg = false;
++tok;
++num_args;
break;
|| num_args == ntok)
goto err;
- saw_comma = FALSE;
- saw_arg = TRUE;
+ saw_comma = false;
+ saw_arg = true;
tok++;
num_args++;
break;
|| num_args == ntok)
goto err;
- saw_comma = FALSE;
- saw_arg = TRUE;
+ saw_comma = false;
+ saw_arg = true;
tok++;
num_args++;
break;
int nflg)
{
char *old_input_line_pointer;
- bfd_boolean saw_flg = FALSE;
- bfd_boolean saw_dot = FALSE;
+ bool saw_flg = false;
+ bool saw_dot = false;
int num_flags = 0;
size_t flgnamelen;
input_line_pointer++;
if (saw_dot)
goto err;
- saw_dot = TRUE;
- saw_flg = FALSE;
+ saw_dot = true;
+ saw_flg = false;
break;
default:
input_line_pointer += flgnamelen;
flags++;
- saw_dot = FALSE;
- saw_flg = TRUE;
+ saw_dot = false;
+ saw_flg = true;
num_flags++;
break;
}
/* Actually output an instruction with its fixup. */
static void
-emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
+emit_insn0 (struct arc_insn *insn, char *where, bool relax)
{
char *f = where;
size_t total_len;
if (insn->relax)
emit_insn1 (insn);
else
- emit_insn0 (insn, NULL, FALSE);
+ emit_insn0 (insn, NULL, false);
}
/* Check whether a symbol involves a register. */
-static bfd_boolean
+static bool
contains_register (symbolS *sym)
{
if (sym)
&& !contains_register (ex->X_op_symbol));
}
- return FALSE;
+ return false;
}
/* Returns the register number within a symbol. */
/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
-static bfd_boolean
+static bool
generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
{
if (!reloc)
- return FALSE;
+ return false;
switch (reloc)
{
case BFD_RELOC_ARC_SDA16_LD2:
case BFD_RELOC_ARC_SDA16_ST2:
case BFD_RELOC_ARC_SDA32_ME:
- return FALSE;
+ return false;
default:
- return TRUE;
+ return true;
}
}
/* Check if an particular ARC feature is enabled. */
-static bfd_boolean
+static bool
check_cpu_feature (insn_subclass_t sc)
{
if (is_code_density_p (sc) && !(selected_cpu.features & CD))
- return FALSE;
+ return false;
if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
- return FALSE;
+ return false;
if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
- return FALSE;
+ return false;
if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
- return FALSE;
+ return false;
if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
returns FALSE, in which case the FIRST_PFLAG array may have been
modified. */
-static bfd_boolean
+static bool
parse_opcode_flags (const struct arc_opcode *opcode,
int nflgs,
struct arc_flags *first_pflag)
if (!strcmp (pf->name, pflag->name))
{
if (pflag->flgp != NULL)
- return FALSE;
+ return false;
/* Found it. */
cl_matches++;
pflag->flgp = pf;
if (!strcmp (flg_operand->name, pflag->name))
{
if (pflag->flgp != NULL)
- return FALSE;
+ return false;
cl_matches++;
pflag->flgp = flg_operand;
lnflg--;
}
if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
- return FALSE;
+ return false;
if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
- return FALSE;
+ return false;
}
/* Did I check all the parsed flags? */
/* Check if *op matches *tok type.
Returns FALSE if they don't match, TRUE if they match. */
-static bfd_boolean
+static bool
pseudo_operand_match (const expressionS *tok,
const struct arc_operand_operation *op)
{
offsetT min, max, val;
- bfd_boolean ret;
+ bool ret;
const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
- ret = FALSE;
+ ret = false;
switch (tok->X_op)
{
case O_constant:
min = 0;
}
if (min <= val && val <= max)
- ret = TRUE;
+ ret = true;
}
break;
if (operand_real->flags & ARC_OPERAND_LIMM
|| ((operand_real->flags & ARC_OPERAND_SIGNED)
&& operand_real->bits == 9))
- ret = TRUE;
+ ret = true;
break;
case O_register:
if (operand_real->flags & ARC_OPERAND_IR)
- ret = TRUE;
+ ret = true;
break;
case O_bracket:
if (operand_real->flags & ARC_OPERAND_BRAKET)
- ret = TRUE;
+ ret = true;
break;
default:
case O_register:
if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
|| (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
- rf16_only = FALSE;
+ rf16_only = false;
break;
default:
break;
struct arc_flags *pflags,
int nflgs)
{
- bfd_boolean found_something = FALSE;
+ bool found_something = false;
const struct arc_opcode_hash_entry *entry;
int cpumatch = 1;
const char *errmsg = NULL;
pr_debug ("%s:%d: assemble_tokens: %s\n",
frag_now->fr_file, frag_now->fr_line, opname);
- found_something = TRUE;
+ found_something = true;
opcode = find_opcode_match (entry, tok, &ntok, pflags,
nflgs, &cpumatch, &errmsg);
if (opcode != NULL)
opname = xmemdup0 (str, opnamelen);
/* Signalize we are assembling the instructions. */
- assembling_insn = TRUE;
+ assembling_insn = true;
/* Tokenize the flags. */
if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
/* Finish it off. */
assemble_tokens (opname, tok, ntok, flags, nflg);
- assembling_insn = FALSE;
+ assembling_insn = false;
}
/* Callback to insert a register into the hash table. */
value += S_GET_VALUE (fx_addsy);
value -= md_pcrel_from_section (fixP, seg);
fx_addsy = NULL;
- fixP->fx_pcrel = FALSE;
+ fixP->fx_pcrel = false;
}
else if (add_symbol_segment == absolute_section)
{
value = fixP->fx_offset;
fx_offset += S_GET_VALUE (fixP->fx_addsy);
fx_addsy = NULL;
- fixP->fx_pcrel = FALSE;
+ fixP->fx_pcrel = false;
}
}
if (!fx_addsy)
- fixP->fx_done = TRUE;
+ fixP->fx_done = true;
if (fixP->fx_pcrel)
{
size = insn.len + (insn.has_limm ? 4 : 0);
gas_assert (table_entry->rlx_length == size);
- emit_insn0 (&insn, dest, TRUE);
+ emit_insn0 (&insn, dest, true);
fragP->fr_fix += table_entry->rlx_length;
fragP->fr_var = 0;
the expression with the identified register. It returns TRUE if
it is a register and FALSE otherwise. */
-bfd_boolean
+bool
arc_parse_name (const char *name,
struct expressionS *e)
{
struct symbol *sym;
if (!assembling_insn)
- return FALSE;
+ return false;
if (e->X_op == O_symbol
&& e->X_md == O_absent)
- return FALSE;
+ return false;
sym = str_hash_find (arc_reg_hash, name);
if (sym)
{
e->X_op = O_register;
e->X_add_number = S_GET_VALUE (sym);
- return TRUE;
+ return true;
}
sym = str_hash_find (arc_addrtype_hash, name);
{
e->X_op = O_addrtype;
e->X_add_number = S_GET_VALUE (sym);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* md_parse_option
offset = strlen (space_buf);
for (i = 0; cpu_types[i].name != NULL; ++i)
{
- bfd_boolean last = (cpu_types[i + 1].name == NULL);
+ bool last = (cpu_types[i + 1].name == NULL);
/* If displaying the new cpu name string, and the ', ' (for all
but the last one) will take us past a target width of 80
{
unsigned int i;
int j;
- bfd_boolean found_flag, tmp;
+ bool found_flag, tmp;
extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
for (i = 0; i < arc_num_equiv_tab; i++)
{
if (!nflg)
continue;
- found_flag = FALSE;
+ found_flag = false;
unsigned * psflg = (unsigned *)r->flags;
do
{
- tmp = FALSE;
+ tmp = false;
for (j = 0; j < nflg; j++)
if (!strcmp (pflags[j].name,
arc_flag_operands[*psflg].name))
{
- tmp = TRUE;
+ tmp = true;
break;
}
if (!tmp)
{
- found_flag = FALSE;
+ found_flag = false;
break;
}
else
{
- found_flag = TRUE;
+ found_flag = true;
}
++ psflg;
} while (*psflg);
/* All the symbol types that are allowed to be used for
relaxation. */
-static bfd_boolean
+static bool
may_relax_expr (expressionS tok)
{
/* Check if we have unrelaxable relocs. */
default:
break;
case O_plt:
- return FALSE;
+ return false;
}
switch (tok.X_op)
break;
default:
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Checks if flags are in line with relaxable insn. */
-static bfd_boolean
+static bool
relaxable_flag (const struct arc_relaxable_ins *ins,
const struct arc_flags *pflags,
int nflgs)
/* Checks if operands are in line with relaxable insn. */
-static bfd_boolean
+static bool
relaxable_operand (const struct arc_relaxable_ins *ins,
const expressionS *tok,
int ntok)
const expressionS *epr = &tok[i];
if (i != 0 && i >= ntok)
- return FALSE;
+ return false;
switch (*operand)
{
|| epr->X_op == O_add
|| epr->X_op == O_subtract
|| epr->X_op == O_symbol))
- return FALSE;
+ return false;
break;
case REGISTER_DUP:
if ((i <= 0)
|| (epr->X_add_number != tok[i - 1].X_add_number))
- return FALSE;
+ return false;
/* Fall through. */
case REGISTER:
if (epr->X_op != O_register)
- return FALSE;
+ return false;
break;
case REGISTER_S:
if (epr->X_op != O_register)
- return FALSE;
+ return false;
switch (epr->X_add_number)
{
case 12: case 13: case 14: case 15:
break;
default:
- return FALSE;
+ return false;
}
break;
case REGISTER_NO_GP:
if ((epr->X_op != O_register)
|| (epr->X_add_number == 26)) /* 26 is the gp register. */
- return FALSE;
+ return false;
break;
case BRACKET:
if (epr->X_op != O_bracket)
- return FALSE;
+ return false;
break;
default:
/* Don't understand, bail out. */
- return FALSE;
+ return false;
break;
}
/* Return TRUE if this OPDCODE is a candidate for relaxation. */
-static bfd_boolean
+static bool
relax_insn_p (const struct arc_opcode *opcode,
const expressionS *tok,
int ntok,
int nflg)
{
unsigned i;
- bfd_boolean rv = FALSE;
+ bool rv = false;
/* Check the relaxation table. */
for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
&& relaxable_operand (arc_rlx_ins, tok, ntok)
&& relaxable_flag (arc_rlx_ins, pflags, nflg))
{
- rv = TRUE;
+ rv = true;
frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
memcpy (&frag_now->tc_frag_data.tok, tok,
sizeof (expressionS) * ntok);
int i;
int tokidx = 0;
unsigned char pcrel = 0;
- bfd_boolean needGOTSymbol;
- bfd_boolean has_delay_slot = FALSE;
+ bool needGOTSymbol;
+ bool has_delay_slot = false;
extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
memset (insn, 0, sizeof (*insn));
/* Regardless if we have a reloc or not mark the instruction
limm if it is the case. */
if (operand->flags & ARC_OPERAND_LIMM)
- insn->has_limm = TRUE;
+ insn->has_limm = true;
switch (t->X_op)
{
default:
/* This operand needs a relocation. */
- needGOTSymbol = FALSE;
+ needGOTSymbol = false;
switch (t->X_md)
{
if (opcode->insn_class == JUMP)
as_bad (_("Unable to use @plt relocation for insn %s"),
opcode->name);
- needGOTSymbol = TRUE;
+ needGOTSymbol = true;
reloc = find_reloc ("plt", opcode->name,
pflags, nflg,
operand->default_reloc);
case O_gotoff:
case O_gotpc:
- needGOTSymbol = TRUE;
+ needGOTSymbol = true;
reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
break;
case O_pcl:
break;
case O_tlsgd:
case O_tlsie:
- needGOTSymbol = TRUE;
+ needGOTSymbol = true;
/* Fall-through. */
case O_tpoff:
/* Check if the instruction has a delay slot. */
if (!strcmp (flg_operand->name, "d"))
- has_delay_slot = TRUE;
+ has_delay_slot = true;
/* There is an exceptional case when we cannot insert a flag just as
it is. On ARCv2 the '.t' and '.nt' flags must be handled in
fixup->exp = *reloc_exp;
fixup->reloc = -bitYoperand;
fixup->pcrel = pcrel;
- fixup->islong = FALSE;
+ fixup->islong = false;
}
}
else
create_extinst_section (&einsn);
}
-static bfd_boolean
+static bool
tokenize_extregister (extRegister_t *ereg, int opertype)
{
char *name;
char c;
char *p;
int number, imode = 0;
- bfd_boolean isCore_p = opertype == EXT_CORE_REGISTER;
- bfd_boolean isReg_p = opertype == EXT_CORE_REGISTER || opertype == EXT_AUX_REGISTER;
+ bool isCore_p = opertype == EXT_CORE_REGISTER;
+ bool isReg_p = opertype == EXT_CORE_REGISTER || opertype == EXT_AUX_REGISTER;
/* 1st: get register name. */
SKIP_WHITESPACE ();
as_bad (_("expected comma after name"));
ignore_rest_of_line ();
free (name);
- return FALSE;
+ return false;
}
input_line_pointer++;
number = get_absolute_expression ();
number);
ignore_rest_of_line ();
free (name);
- return FALSE;
+ return false;
}
if (isReg_p)
as_bad (_("expected comma after register number"));
ignore_rest_of_line ();
free (name);
- return FALSE;
+ return false;
}
input_line_pointer++;
as_bad (_("invalid mode"));
ignore_rest_of_line ();
free (name);
- return FALSE;
+ return false;
}
else
{
as_bad (_("expected comma after register mode"));
ignore_rest_of_line ();
free (name);
- return FALSE;
+ return false;
}
input_line_pointer++;
as_bad (_("shortcut designator invalid"));
ignore_rest_of_line ();
free (name);
- return FALSE;
+ return false;
}
else
{
ereg->name = name;
ereg->number = number;
ereg->imode = imode;
- return TRUE;
+ return true;
}
/* Create an extension register/condition description in the arc
int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
- attributes_set_explicitly[tag] = TRUE;
+ attributes_set_explicitly[tag] = true;
}
/* Set an attribute if it has not already been set by the user. */
extern void arc_md_end (void);
extern void arc_adjust_symtab (void);
extern int arc_pcrel_adjust (fragS *);
-extern bfd_boolean arc_parse_name (const char *, struct expressionS *);
+extern bool arc_parse_name (const char *, struct expressionS *);
extern int tc_arc_fix_adjustable (struct fix *);
extern void arc_handle_align (fragS *);
extern void arc_cons_fix_new (fragS *, int, int, expressionS *,
/* Perform range checks on positive and negative overflows by checking if the
VALUE given fits within the range of an BITS sized immediate. */
-static bfd_boolean out_of_range_p (offsetT value, offsetT bits)
+static bool out_of_range_p (offsetT value, offsetT bits)
{
gas_assert (bits < (offsetT)(sizeof (value) * 8));
return (value & ~((1 << bits)-1))
static arm_feature_set thumb_arch_used;
/* Flags stored in private area of BFD structure. */
-static int uses_apcs_26 = FALSE;
-static int atpcs = FALSE;
-static int support_interwork = FALSE;
-static int uses_apcs_float = FALSE;
-static int pic_code = FALSE;
-static int fix_v4bx = FALSE;
+static int uses_apcs_26 = false;
+static int atpcs = false;
+static int support_interwork = false;
+static int uses_apcs_float = false;
+static int pic_code = false;
+static int fix_v4bx = false;
/* Warn on using deprecated features. */
-static int warn_on_deprecated = TRUE;
-static int warn_on_restrict_it = FALSE;
+static int warn_on_deprecated = true;
+static int warn_on_restrict_it = false;
/* Understand CodeComposer Studio assembly syntax. */
-bfd_boolean codecomposer_syntax = FALSE;
+bool codecomposer_syntax = false;
/* Variables that we set while parsing command-line options. Once all
options have been read we re-process these values to set the real
extern FLONUM_TYPE generic_floating_point_number;
/* Return if no cpu was selected on command-line. */
-static bfd_boolean
+static bool
no_cpu_selected (void)
{
return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
-bfd_boolean
+bool
arm_is_eabi (void)
{
return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
preceding IT instructions. Unlike ARM mode, you cannot use a
conditional affix except in the scope of an IT instruction. */
-static bfd_boolean unified_syntax = FALSE;
+static bool unified_syntax = false;
/* An immediate operand can start with #, and ld*, st*, pld operands
can contain [ and ]. We need to tell APP not to elide whitespace
<insn> */
symbolS * last_label_seen;
-static int label_is_thumb_function_name = FALSE;
+static int label_is_thumb_function_name = false;
/* Literal pool structure. Held on a per-section
and per-sub-section basis. */
/* Return TRUE if anything in the expression is a bignum. */
-static bfd_boolean
+static bool
walk_no_bignums (symbolS * sp)
{
if (symbol_get_value_expression (sp)->X_op == O_big)
- return TRUE;
+ return true;
if (symbol_get_value_expression (sp)->X_add_symbol)
{
&& walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
}
- return FALSE;
+ return false;
}
-static bfd_boolean in_my_get_expression = FALSE;
+static bool in_my_get_expression = false;
/* Third argument to my_get_expression. */
#define GE_NO_PREFIX 0
save_in = input_line_pointer;
input_line_pointer = *str;
- in_my_get_expression = TRUE;
+ in_my_get_expression = true;
expression (ep);
- in_my_get_expression = FALSE;
+ in_my_get_expression = false;
if (ep->X_op == O_illegal || ep->X_op == O_absent)
{
/* If the given feature available in the selected CPU, mark it as used.
Returns TRUE iff feature is available. */
-static bfd_boolean
+static bool
mark_feature_used (const arm_feature_set *feature)
{
&& ARM_CPU_IS_ANY (cpu_variant))
{
first_error (BAD_MVE_AUTO);
- return FALSE;
+ return false;
}
/* Ensure the option is valid on the current architecture. */
if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
- return FALSE;
+ return false;
/* Add the appropriate architecture feature for the barrier option used.
*/
record_feature_use (feature);
- return TRUE;
+ return true;
}
/* Parse either a register or a scalar, with an optional type. Return the
static int
parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
- bfd_boolean *partial_match)
+ bool *partial_match)
{
char *str = *ccp;
int base_reg;
int warned = 0;
unsigned long mask = 0;
int i;
- bfd_boolean vpr_seen = FALSE;
- bfd_boolean expect_vpr =
+ bool vpr_seen = false;
+ bool expect_vpr =
(etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
if (skip_past_char (&str, '{') == FAIL)
}
base_reg = max_regs;
- *partial_match = FALSE;
+ *partial_match = false;
do
{
&& !ISALPHA (*(str + vpr_str_len))
&& !vpr_seen)
{
- vpr_seen = TRUE;
+ vpr_seen = true;
str += vpr_str_len;
if (count == 0)
base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
return FAIL;
}
- *partial_match = TRUE;
+ *partial_match = true;
if (vpr_seen)
continue;
/* True if two alias types are the same. */
-static bfd_boolean
+static bool
neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
{
if (!a && !b)
- return TRUE;
+ return true;
if (!a || !b)
- return FALSE;
+ return false;
if (a->defined != b->defined)
- return FALSE;
+ return false;
if ((a->defined & NTA_HASTYPE) != 0
&& (a->eltype.type != b->eltype.type
|| a->eltype.size != b->eltype.size))
- return FALSE;
+ return false;
if ((a->defined & NTA_HASINDEX) != 0
&& (a->index != b->index))
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
new_reg->name = name;
new_reg->number = number;
new_reg->type = type;
- new_reg->builtin = FALSE;
+ new_reg->builtin = false;
new_reg->neon = NULL;
str_hash_insert (arm_reg_hsh, name, new_reg, 0);
If we find one, or if it looks sufficiently like one that we want to
handle any error here, return TRUE. Otherwise return FALSE. */
-static bfd_boolean
+static bool
create_register_alias (char * newname, char *p)
{
struct reg_entry *old;
collapsed to single spaces. */
oldname = p;
if (strncmp (oldname, " .req ", 6) != 0)
- return FALSE;
+ return false;
oldname += 6;
if (*oldname == '\0')
- return FALSE;
+ return false;
old = (struct reg_entry *) str_hash_find (arm_reg_hsh, oldname);
if (!old)
{
as_warn (_("unknown register '%s' -- .req ignored"), oldname);
- return TRUE;
+ return true;
}
/* If TC_CASE_SENSITIVE is defined, then newname already points to
if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
{
free (nbuf);
- return TRUE;
+ return true;
}
}
}
free (nbuf);
- return TRUE;
+ return true;
}
/* Create a Neon typed/indexed register alias using directives, e.g.:
specified directly, e.g.:
vadd d0.s32, d1.s32, d2.s32 */
-static bfd_boolean
+static bool
create_neon_reg_alias (char *newname, char *p)
{
enum arm_reg_type basetype;
else if (strncmp (p, " .qn ", 5) == 0)
basetype = REG_TYPE_NQ;
else
- return FALSE;
+ return false;
p += 5;
if (*p == '\0')
- return FALSE;
+ return false;
basereg = arm_reg_parse_multi (&p);
if (basereg && basereg->type != basetype)
{
as_bad (_("bad type for register"));
- return FALSE;
+ return false;
}
if (basereg == NULL)
if (exp.X_op != O_constant)
{
as_bad (_("expression must be constant"));
- return FALSE;
+ return false;
}
basereg = &mybasereg;
basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
if (typeinfo.defined & NTA_HASTYPE)
{
as_bad (_("can't redefine the type of a register alias"));
- return FALSE;
+ return false;
}
typeinfo.defined |= NTA_HASTYPE;
if (ntype.elems != 1)
{
as_bad (_("you must specify a single type only"));
- return FALSE;
+ return false;
}
typeinfo.eltype = ntype.el[0];
}
if (typeinfo.defined & NTA_HASINDEX)
{
as_bad (_("can't redefine the index of a scalar alias"));
- return FALSE;
+ return false;
}
my_get_expression (&exp, &p, GE_NO_PREFIX);
if (exp.X_op != O_constant)
{
as_bad (_("scalar index must be constant"));
- return FALSE;
+ return false;
}
typeinfo.defined |= NTA_HASINDEX;
if (skip_past_char (&p, ']') == FAIL)
{
as_bad (_("expecting ]"));
- return FALSE;
+ return false;
}
}
typeinfo.defined != 0 ? &typeinfo : NULL);
free (namebuf);
- return TRUE;
+ return true;
}
/* Should never be called, as .req goes between the alias and the
/* The following label is the name/address of the start of a Thumb function.
We need to know this for the interworking support. */
- label_is_thumb_function_name = TRUE;
+ label_is_thumb_function_name = true;
}
/* Perform a .set directive, but also mark the alias as
delim = get_symbol_name (& name);
if (!strcasecmp (name, "unified"))
- unified_syntax = TRUE;
+ unified_syntax = true;
else if (!strcasecmp (name, "divided"))
- unified_syntax = FALSE;
+ unified_syntax = false;
else
{
as_bad (_("unrecognized syntax mode \"%s\""), name);
#define LIT_ENTRY_SIZE_MASK 0xFF
literal_pool * pool;
unsigned int entry, pool_size = 0;
- bfd_boolean padding_slot_p = FALSE;
+ bool padding_slot_p = false;
unsigned imm1 = 0;
unsigned imm2 = 0;
return SUCCESS;
}
-bfd_boolean
+bool
tc_start_label_without_colon (void)
{
- bfd_boolean ret = TRUE;
+ bool ret = true;
if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
{
if (*label == '.')
{
as_bad (_("Invalid label '%s'"), label);
- ret = FALSE;
+ ret = false;
}
asmfunc_debug (label);
return 0;
}
-static bfd_boolean
+static bool
emit_insn (expressionS *exp, int nbytes)
{
int size = 0;
valueT op;
int num_vfpv3_regs = 0;
int num_regs_below_16;
- bfd_boolean partial_match;
+ bool partial_match;
count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
&partial_match);
int count;
unsigned int reg;
valueT op;
- bfd_boolean partial_match;
+ bool partial_match;
count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D,
&partial_match);
{
char *peek;
struct reg_entry *reg;
- bfd_boolean had_brace = FALSE;
+ bool had_brace = false;
if (!unwind.proc_start)
as_bad (MISSING_FNSTART);
if (*peek == '{')
{
- had_brace = TRUE;
+ had_brace = true;
peek++;
}
static int
parse_immediate (char **str, int *val, int min, int max,
- bfd_boolean prefix_opt)
+ bool prefix_opt)
{
expressionS exp;
static int
parse_big_immediate (char **str, int i, expressionS *in_exp,
- bfd_boolean allow_symbol_p)
+ bool allow_symbol_p)
{
expressionS exp;
expressionS *exp_p = in_exp ? in_exp : &exp;
/* Detect the presence of a floating point or integer zero constant,
i.e. #0.0 or #0. */
-static bfd_boolean
+static bool
parse_ifimm_zero (char **in)
{
int error_code;
{
/* In unified syntax, all prefixes are optional. */
if (!unified_syntax)
- return FALSE;
+ return false;
}
else
++*in;
if (strncmp (*in, "0x", 2) == 0)
{
int val;
- if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
- return FALSE;
- return TRUE;
+ if (parse_immediate (in, &val, 0, 0, true) == FAIL)
+ return false;
+ return true;
}
error_code = atof_generic (in, ".", EXP_CHARS,
&& generic_floating_point_number.sign == '+'
&& (generic_floating_point_number.low
> generic_floating_point_number.leader))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Parse an 8-bit "quarter-precision" floating point number of the form:
return PARSE_OPERAND_FAIL;
}
else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
- /*allow_symbol_p=*/TRUE))
+ /*allow_symbol_p=*/true))
return PARSE_OPERAND_FAIL;
*str = p;
{
/* [Rn], {expr} - unindexed, with option */
if (parse_immediate (&p, &inst.operands[i].imm,
- 0, 255, TRUE) == FAIL)
+ 0, 255, true) == FAIL)
return PARSE_OPERAND_FAIL;
if (skip_past_char (&p, '}') == FAIL)
/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
or a bitmask suitable to be or-ed into the ARM msr instruction. */
static int
-parse_psr (char **str, bfd_boolean lhs)
+parse_psr (char **str, bool lhs)
{
char *p;
unsigned long psr_field;
const struct asm_psr *psr;
char *start;
- bfd_boolean is_apsr = FALSE;
- bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
+ bool is_apsr = false;
+ bool m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
/* PR gas/12698: If the user has specified -march=all then m_profile will
be TRUE, but we want to ignore it in this case as we are building for any
CPU type, including non-m variants. */
if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
- m_profile = FALSE;
+ m_profile = false;
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
{
/* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
and ARMv7-R architecture CPUs. */
- is_apsr = TRUE;
+ is_apsr = true;
psr_field = 0;
}
else if (m_profile)
if (psr->field <= 3)
{
psr_field = psr->field;
- is_apsr = TRUE;
+ is_apsr = true;
goto check_suffix;
}
return FAIL;
}
- if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
+ if (parse_immediate (&s, &rot, 0, 24, false) == FAIL)
return FAIL;
switch (rot)
Case 10: VMOV.F32 <Sd>, #<imm>
Case 11: VMOV.F64 <Dd>, #<imm> */
inst.operands[i].immisfloat = 1;
- else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
+ else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/false)
== SUCCESS)
/* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
structure. Returns SUCCESS or FAIL depending on whether the
specified grammar matched. */
static int
-parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
+parse_operands (char *str, const unsigned int *pattern, bool thumb)
{
unsigned const int *upat = pattern;
char *backtrack_pos = 0;
enum arm_reg_type rtype;
parse_operand_result result;
unsigned int op_parse_code;
- bfd_boolean partial_match;
+ bool partial_match;
#define po_char_or_fail(chr) \
do \
po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
break;
try_imm0:
- po_imm_or_fail (0, 0, TRUE);
+ po_imm_or_fail (0, 0, true);
}
break;
try_immbig:
/* There's a possibility of getting a 64-bit immediate here, so
we need special handling. */
- if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
+ if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/false)
== FAIL)
{
inst.error = _("immediate value is out of range");
po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
break;
try_shimm:
- po_imm_or_fail (0, 63, TRUE);
+ po_imm_or_fail (0, 63, true);
}
break;
break;
/* Immediates */
- case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
- case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
- case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
- case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
- case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
- case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
- case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
- case OP_I48_I64: po_imm1_or_imm2_or_fail (48, 64, FALSE); break;
- case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
- case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
- case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
- case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
- case OP_I127: po_imm_or_fail ( 0, 127, FALSE); break;
- case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
- case OP_I511: po_imm_or_fail ( 0, 511, FALSE); break;
- case OP_I4095: po_imm_or_fail ( 0, 4095, FALSE); break;
- case OP_I8191: po_imm_or_fail ( 0, 8191, FALSE); break;
- case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
+ case OP_I7: po_imm_or_fail ( 0, 7, false); break;
+ case OP_I15: po_imm_or_fail ( 0, 15, false); break;
+ case OP_I16: po_imm_or_fail ( 1, 16, false); break;
+ case OP_I16z: po_imm_or_fail ( 0, 16, false); break;
+ case OP_I31: po_imm_or_fail ( 0, 31, false); break;
+ case OP_I32: po_imm_or_fail ( 1, 32, false); break;
+ case OP_I32z: po_imm_or_fail ( 0, 32, false); break;
+ case OP_I48_I64: po_imm1_or_imm2_or_fail (48, 64, false); break;
+ case OP_I63s: po_imm_or_fail (-64, 63, false); break;
+ case OP_I63: po_imm_or_fail ( 0, 63, false); break;
+ case OP_I64: po_imm_or_fail ( 1, 64, false); break;
+ case OP_I64z: po_imm_or_fail ( 0, 64, false); break;
+ case OP_I127: po_imm_or_fail ( 0, 127, false); break;
+ case OP_I255: po_imm_or_fail ( 0, 255, false); break;
+ case OP_I511: po_imm_or_fail ( 0, 511, false); break;
+ case OP_I4095: po_imm_or_fail ( 0, 4095, false); break;
+ case OP_I8191: po_imm_or_fail ( 0, 8191, false); break;
+ case OP_I4b: po_imm_or_fail ( 1, 4, true); break;
case OP_oI7b:
- case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
- case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
+ case OP_I7b: po_imm_or_fail ( 0, 7, true); break;
+ case OP_I15b: po_imm_or_fail ( 0, 15, true); break;
case OP_oI31b:
- case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
- case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
- case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
- case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
+ case OP_I31b: po_imm_or_fail ( 0, 31, true); break;
+ case OP_oI32b: po_imm_or_fail ( 1, 32, true); break;
+ case OP_oI32z: po_imm_or_fail ( 0, 32, true); break;
+ case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, true); break;
/* Immediate variants */
case OP_oI255c:
po_char_or_fail ('{');
- po_imm_or_fail (0, 255, TRUE);
+ po_imm_or_fail (0, 255, true);
po_char_or_fail ('}');
break;
s[-1] = '\0';
inst.operands[i].writeback = 1;
}
- po_imm_or_fail (0, 31, TRUE);
+ po_imm_or_fail (0, 31, true);
if (str == s - 1)
str = s;
}
/* Register or immediate. */
case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
- I0: po_imm_or_fail (0, 0, FALSE); break;
+ I0: po_imm_or_fail (0, 0, false); break;
case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break;
- I32: po_imm_or_fail (1, 32, FALSE); break;
+ I32: po_imm_or_fail (1, 32, false); break;
case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
IF:
break;
case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
- I32z: po_imm_or_fail (0, 32, FALSE); break;
+ I32z: po_imm_or_fail (0, 32, false); break;
/* Two kinds of register. */
case OP_RIWR_RIWC:
case OP_oBARRIER_I15:
po_barrier_or_imm (str); break;
immediate:
- if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
+ if (parse_immediate (&str, &val, 0, 15, true) == FAIL)
goto failure;
break;
/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
static void
-encode_arm_addr_mode_common (int i, bfd_boolean is_t)
+encode_arm_addr_mode_common (int i, bool is_t)
{
/* PR 14260:
Generate an error if the operand is not a register. */
reject forms that cannot be used with a T instruction (i.e. not
post-indexed). */
static void
-encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
+encode_arm_addr_mode_2 (int i, bool is_t)
{
- const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
+ const bool is_pc = (inst.operands[i].reg == REG_PC);
encode_arm_addr_mode_common (i, is_t);
{
if (is_pc && !inst.relocs[0].pc_rel)
{
- const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
+ const bool is_load = ((inst.instruction & LOAD_BIT) != 0);
/* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
cannot use PC in addressing.
forms that cannot be used with a T instruction (i.e. not
post-indexed). */
static void
-encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
+encode_arm_addr_mode_3 (int i, bool is_t)
{
if (inst.operands[i].immisreg && inst.operands[i].shifted)
{
/* Returns TRUE if double precision value V may be cast
to single precision without loss of accuracy. */
-static bfd_boolean
+static bool
is_double_a_single (bfd_uint64_t v)
{
int exp = (v >> 52) & 0x7FF;
/* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
Determine whether it can be performed with a move instruction; if
it can, convert inst.instruction to that move instruction and
- return TRUE; if it can't, convert inst.instruction to a literal-pool
+ return true; if it can't, convert inst.instruction to a literal-pool
load and return FALSE. If this is not a valid thing to do in the
current context, set inst.error and return TRUE.
inst.operands[i] describes the destination register. */
-static bfd_boolean
-move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
+static bool
+move_or_literal_pool (int i, enum lit_type t, bool mode_3)
{
unsigned long tbit;
- bfd_boolean thumb_p = (t == CONST_THUMB);
- bfd_boolean arm_p = (t == CONST_ARM);
+ bool thumb_p = (t == CONST_THUMB);
+ bool arm_p = (t == CONST_ARM);
if (thumb_p)
tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
if ((inst.instruction & tbit) == 0)
{
inst.error = _("invalid pseudo operation");
- return TRUE;
+ return true;
}
if (inst.relocs[0].exp.X_op != O_constant
&& inst.relocs[0].exp.X_op != O_big)
{
inst.error = _("constant expression expected");
- return TRUE;
+ return true;
}
if (inst.relocs[0].exp.X_op == O_constant
/* Check if on thumb2 it can be done with a mov.w, mvn or
movw instruction. */
unsigned int newimm;
- bfd_boolean isNegated = FALSE;
+ bool isNegated = false;
newimm = encode_thumb32_immediate (v);
if (newimm == (unsigned int) FAIL)
{
newimm = encode_thumb32_immediate (~v);
- isNegated = TRUE;
+ isNegated = true;
}
/* The number can be loaded with a mov.w or mvn
inst.instruction |= (newimm & 0x800) << 15;
inst.instruction |= (newimm & 0x700) << 4;
inst.instruction |= (newimm & 0x0ff);
- return TRUE;
+ return true;
}
/* The number can be loaded with a movw instruction. */
else if ((v & ~0xFFFF) == 0
instruction size check, as otherwise GAS will reject
the use of this T32 instruction. */
inst.size_req = 0;
- return TRUE;
+ return true;
}
}
}
inst.instruction &= LITERAL_MASK;
inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
inst.instruction |= value & 0xfff;
- return TRUE;
+ return true;
}
value = encode_arm_immediate (~ v);
inst.instruction &= LITERAL_MASK;
inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
inst.instruction |= value & 0xfff;
- return TRUE;
+ return true;
}
}
else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
: inst.relocs[0].exp.X_unsigned
? 0
: ((bfd_int64_t)((int) immlo)) >> 32;
- int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
+ int cmode = neon_cmode_for_move_imm (immlo, immhi, false, &immbits,
&op, 64, NT_invtype);
if (cmode == FAIL)
{
neon_invert_size (&immlo, &immhi, 64);
op = !op;
- cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
+ cmode = neon_cmode_for_move_imm (immlo, immhi, false, &immbits,
&op, 64, NT_invtype);
}
else
inst.instruction |= (0xFU << 28) | (0x1 << 25);
neon_write_immbits (immbits);
- return TRUE;
+ return true;
}
}
}
inst.operands[1].imm =
neon_qfloat_bits (v);
do_vfp_nsyn_opcode ("fconsts");
- return TRUE;
+ return true;
}
/* If our host does not support a 64-bit type then we cannot perform
inst.operands[1].imm =
neon_qfloat_bits (double_to_single (v));
do_vfp_nsyn_opcode ("fconstd");
- return TRUE;
+ return true;
}
}
#endif
if (add_to_lit_pool ((!inst.operands[i].isvec
|| inst.operands[i].issingle) ? 4 : 8) == FAIL)
- return TRUE;
+ return true;
inst.operands[1].reg = REG_PC;
inst.operands[1].isreg = 1;
: (mode_3
? BFD_RELOC_ARM_HWLITERAL
: BFD_RELOC_ARM_LITERAL));
- return FALSE;
+ return false;
}
/* inst.operands[i] was set up by parse_address. Encode it into an
inst.error = _("invalid co-processor operand");
return FAIL;
}
- if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/false))
return SUCCESS;
}
inst.instruction |= inst.operands[1].reg << 16;
}
-static bfd_boolean
+static bool
check_obsolete (const arm_feature_set *feature, const char *msg)
{
if (ARM_CPU_IS_ANY (cpu_variant))
{
as_tsktsk ("%s", msg);
- return TRUE;
+ return true;
}
else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
{
as_bad ("%s", msg);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
static void
do_rd_cpaddr (void)
{
inst.instruction |= inst.operands[0].reg << 12;
- encode_arm_cp_address (1, TRUE, TRUE, 0);
+ encode_arm_cp_address (1, true, true, 0);
}
/* ARM instructions, in alphabetical order by function name (except
static void
do_bx (void)
{
- bfd_boolean want_reloc;
+ bool want_reloc;
if (inst.operands[0].reg == REG_PC)
as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
if (!ARM_FEATURE_ZERO (selected_object_arch)
&& !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
- want_reloc = TRUE;
+ want_reloc = true;
#ifdef OBJ_ELF
if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
#endif
- want_reloc = FALSE;
+ want_reloc = false;
if (want_reloc)
inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
static void
do_ldmstm (void)
{
- encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
+ encode_ldmstm (/*from_push_pop_mnem=*/false);
}
/* ARMv5TE load-consecutive (argument parse)
as_warn (_("index register overlaps transfer register"));
}
inst.instruction |= inst.operands[0].reg << 12;
- encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
+ encode_arm_addr_mode_3 (2, /*is_t=*/false);
}
static void
{
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/false))
return;
- encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
+ encode_arm_addr_mode_2 (1, /*is_t=*/false);
check_ldr_r15_aligned ();
}
inst.operands[1].writeback = 1;
}
inst.instruction |= inst.operands[0].reg << 12;
- encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
+ encode_arm_addr_mode_2 (1, /*is_t=*/true);
}
/* Halfword and signed-byte load/store operations. */
constraint (inst.operands[0].reg == REG_PC, BAD_PC);
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
+ if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/true))
return;
- encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
+ encode_arm_addr_mode_3 (1, /*is_t=*/false);
}
static void
inst.operands[1].writeback = 1;
}
inst.instruction |= inst.operands[0].reg << 12;
- encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
+ encode_arm_addr_mode_3 (1, /*is_t=*/true);
}
/* Co-processor register load/store.
{
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].reg << 12;
- encode_arm_cp_address (2, TRUE, TRUE, 0);
+ encode_arm_cp_address (2, true, true, 0);
}
static void
do_mov16 (void)
{
bfd_vma imm;
- bfd_boolean top;
+ bool top;
top = (inst.instruction & 0x00400000) != 0;
constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
_("writeback used in preload instruction"));
constraint (!inst.operands[0].preind,
_("unindexed addressing used in preload instruction"));
- encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
+ encode_arm_addr_mode_2 (0, /*is_t=*/false);
}
/* ARMv7: PLI <addr_mode> */
_("writeback used in preload instruction"));
constraint (!inst.operands[0].preind,
_("unindexed addressing used in preload instruction"));
- encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
+ encode_arm_addr_mode_2 (0, /*is_t=*/false);
inst.instruction &= ~PRE_INDEX;
}
inst.operands[0].isreg = 1;
inst.operands[0].writeback = 1;
inst.operands[0].reg = REG_SP;
- encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
+ encode_ldmstm (/*from_push_pop_mnem=*/true);
}
/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
do_vfp_sp_ldst (void)
{
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
- encode_arm_cp_address (1, FALSE, TRUE, 0);
+ encode_arm_cp_address (1, false, true, 0);
}
static void
do_vfp_dp_ldst (void)
{
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
- encode_arm_cp_address (1, FALSE, TRUE, 0);
+ encode_arm_cp_address (1, false, true, 0);
}
}
}
- encode_arm_cp_address (2, TRUE, TRUE, 0);
+ encode_arm_cp_address (2, true, true, 0);
}
\f
/* iWMMXt instructions: strictly in alphabetical order. */
reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
else
reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
- encode_arm_cp_address (1, TRUE, FALSE, reloc);
+ encode_arm_cp_address (1, true, false, reloc);
}
static void
}
inst.instruction |= inst.operands[0].reg << 12;
- encode_arm_cp_address (1, TRUE, TRUE, 0);
+ encode_arm_cp_address (1, true, true, 0);
}
static void
inst.instruction |= inst.operands[1].imm;
}
else
- encode_arm_cp_address (1, TRUE, FALSE, 0);
+ encode_arm_cp_address (1, true, false, 0);
}
static void
reject PC in Rn. */
static void
-encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
+encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
{
- const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
+ const bool is_pc = (inst.operands[i].reg == REG_PC);
constraint (!inst.operands[i].isreg,
_("Instruction does not support =N addresses"));
if (unified_syntax)
{
- bfd_boolean flags;
- bfd_boolean narrow;
+ bool flags;
+ bool narrow;
int opcode;
flags = (inst.instruction == T_MNEM_adds
if (!inst.operands[2].shifted && inst.size_req != 4)
{
if (Rd > 7 || Rs > 7 || Rn > 7)
- narrow = FALSE;
+ narrow = false;
if (narrow)
{
}
else
{
- bfd_boolean narrow;
+ bool narrow;
/* See if we can do this with a 16-bit instruction. */
if (THUMB_SETS_FLAGS (inst.instruction))
narrow = in_pred_block ();
if (Rd > 7 || Rn > 7 || Rs > 7)
- narrow = FALSE;
+ narrow = false;
if (inst.operands[2].shifted)
- narrow = FALSE;
+ narrow = false;
if (inst.size_req == 4)
- narrow = FALSE;
+ narrow = false;
if (narrow
&& Rd == Rs)
}
else
{
- bfd_boolean narrow;
+ bool narrow;
/* See if we can do this with a 16-bit instruction. */
if (THUMB_SETS_FLAGS (inst.instruction))
narrow = in_pred_block ();
if (Rd > 7 || Rn > 7 || Rs > 7)
- narrow = FALSE;
+ narrow = false;
if (inst.operands[2].shifted)
- narrow = FALSE;
+ narrow = false;
if (inst.size_req == 4)
- narrow = FALSE;
+ narrow = false;
if (narrow)
{
set_pred_insn_type (IT_INSN);
now_pred.mask = (inst.instruction & 0xf) | 0x10;
now_pred.cc = cond;
- now_pred.warn_deprecated = FALSE;
+ now_pred.warn_deprecated = false;
now_pred.type = SCALAR_PRED;
/* If the condition is a negative condition, invert the mask. */
/* Helper function used for both push/pop and ldm/stm. */
static void
-encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
- bfd_boolean writeback)
+encode_thumb2_multi (bool do_io, int base, unsigned mask,
+ bool writeback)
{
- bfd_boolean load, store;
+ bool load, store;
gas_assert (base != -1 || !do_io);
load = do_io && ((inst.instruction & (1 << 20)) != 0);
if (unified_syntax)
{
- bfd_boolean narrow;
+ bool narrow;
unsigned mask;
- narrow = FALSE;
+ narrow = false;
/* See if we can use a 16-bit instruction. */
if (inst.instruction < 0xffff /* not ldmdb/stmdb */
&& inst.size_req != 4
inst.instruction = THUMB_OP16 (inst.instruction);
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].imm;
- narrow = TRUE;
+ narrow = true;
}
else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
{
inst.instruction = THUMB_OP16 (opcode);
inst.instruction |= inst.operands[0].reg << 3;
inst.instruction |= (ffs (inst.operands[1].imm)-1);
- narrow = TRUE;
+ narrow = true;
}
}
else if (inst.operands[0] .reg == REG_SP)
THUMB_OP16 (inst.instruction == T_MNEM_stmia
? T_MNEM_push : T_MNEM_pop);
inst.instruction |= inst.operands[1].imm;
- narrow = TRUE;
+ narrow = true;
}
else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
{
THUMB_OP16 (inst.instruction == T_MNEM_stmia
? T_MNEM_str_sp : T_MNEM_ldr_sp);
inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
- narrow = TRUE;
+ narrow = true;
}
}
}
if (inst.instruction < 0xffff)
inst.instruction = THUMB_OP32 (inst.instruction);
- encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
+ encode_thumb2_multi (true /* do_io */, inst.operands[0].reg,
inst.operands[1].imm,
inst.operands[0].writeback);
}
{
if (opcode <= 0xffff)
inst.instruction = THUMB_OP32 (opcode);
- if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/false))
return;
}
if (inst.operands[1].isreg
inst.instruction = THUMB_OP32 (opcode);
inst.instruction |= inst.operands[0].reg << 12;
- encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
+ encode_thumb32_addr_mode (1, /*is_t=*/false, /*is_d=*/false);
check_ldr_r15_aligned ();
return;
}
inst.instruction = THUMB_OP16 (inst.instruction);
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/false))
return;
constraint (!inst.operands[1].preind
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 8;
- encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
+ encode_thumb32_addr_mode (2, /*is_t=*/false, /*is_d=*/true);
}
static void
do_t_ldstt (void)
{
inst.instruction |= inst.operands[0].reg << 12;
- encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
+ encode_thumb32_addr_mode (1, /*is_t=*/true, /*is_d=*/false);
}
static void
int r0off = (inst.instruction == T_MNEM_mov
|| inst.instruction == T_MNEM_movs) ? 8 : 16;
unsigned long opcode;
- bfd_boolean narrow;
- bfd_boolean low_regs;
+ bool narrow;
+ bool low_regs;
low_regs = (Rn <= 7 && Rm <= 7);
opcode = inst.instruction;
narrow = opcode != T_MNEM_movs || low_regs;
if (inst.size_req == 4
|| inst.operands[1].shifted)
- narrow = FALSE;
+ narrow = false;
/* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
if (opcode == T_MNEM_movs && inst.operands[1].isreg
|| inst.instruction == T_MNEM_movs))
{
/* Register shifts are encoded as separate shift instructions. */
- bfd_boolean flags = (inst.instruction == T_MNEM_movs);
+ bool flags = (inst.instruction == T_MNEM_movs);
if (in_pred_block ())
narrow = !flags;
narrow = flags;
if (inst.size_req == 4)
- narrow = FALSE;
+ narrow = false;
if (!low_regs || inst.operands[1].imm > 7)
- narrow = FALSE;
+ narrow = false;
if (Rn != Rm)
- narrow = FALSE;
+ narrow = false;
switch (inst.operands[1].shift_kind)
{
case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
- default: narrow = FALSE; break;
+ default: narrow = false; break;
}
}
{
unsigned Rd;
bfd_vma imm;
- bfd_boolean top;
+ bool top;
top = (inst.instruction & 0x00800000) != 0;
if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
{
int r0off = (inst.instruction == T_MNEM_mvn
|| inst.instruction == T_MNEM_mvns) ? 8 : 16;
- bfd_boolean narrow;
+ bool narrow;
if (inst.size_req == 4
|| inst.instruction > 0xffff
|| inst.operands[1].shifted
|| Rn > 7 || Rm > 7)
- narrow = FALSE;
+ narrow = false;
else if (inst.instruction == T_MNEM_cmn
|| inst.instruction == T_MNEM_tst)
- narrow = TRUE;
+ narrow = true;
else if (THUMB_SETS_FLAGS (inst.instruction))
narrow = !in_pred_block ();
else
/* PR gas/12698: The constraint is only applied for m_profile.
If the user has specified -march=all, we want to ignore it as
we are building for any CPU type, including non-m variants. */
- bfd_boolean m_profile =
+ bool m_profile =
!ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
constraint ((flags != 0) && m_profile, _("selected processor does "
"not support requested special purpose register"));
/* PR gas/12698: The constraint is only applied for m_profile.
If the user has specified -march=all, we want to ignore it as
we are building for any CPU type, including non-m variants. */
- bfd_boolean m_profile =
+ bool m_profile =
!ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
&& (bits & ~(PSR_s | PSR_f)) != 0)
static void
do_t_mul (void)
{
- bfd_boolean narrow;
+ bool narrow;
unsigned Rd, Rn, Rm;
if (!inst.operands[2].present)
&& Rd != Rm)
|| Rn > 7
|| Rm > 7)
- narrow = FALSE;
+ narrow = false;
else if (inst.instruction == T_MNEM_muls)
narrow = !in_pred_block ();
else
constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
constraint (Rn > 7 || Rm > 7,
BAD_HIREG);
- narrow = TRUE;
+ narrow = true;
}
if (narrow)
{
if (unified_syntax)
{
- bfd_boolean narrow;
+ bool narrow;
if (THUMB_SETS_FLAGS (inst.instruction))
narrow = !in_pred_block ();
else
narrow = in_pred_block ();
if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
- narrow = FALSE;
+ narrow = false;
if (inst.size_req == 4)
- narrow = FALSE;
+ narrow = false;
if (!narrow)
{
if (inst.operands[0].immisreg)
reject_bad_reg (inst.operands[0].imm);
- encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
+ encode_thumb32_addr_mode (0, /*is_t=*/false, /*is_d=*/false);
}
static void
else if (unified_syntax)
{
inst.instruction = THUMB_OP32 (inst.instruction);
- encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
+ encode_thumb2_multi (true /* do_io */, 13, mask, true);
}
else
{
do_t_clrm (void)
{
if (unified_syntax)
- encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
+ encode_thumb2_multi (false /* do_io */, -1, inst.operands[0].imm, false);
else
{
inst.error = _("invalid register list to push/pop instruction");
inst.instruction |= Rs << 16;
if (!inst.operands[2].isreg)
{
- bfd_boolean narrow;
+ bool narrow;
if ((inst.instruction & 0x00100000) != 0)
narrow = !in_pred_block ();
narrow = in_pred_block ();
if (Rd > 7 || Rs > 7)
- narrow = FALSE;
+ narrow = false;
if (inst.size_req == 4 || !unified_syntax)
- narrow = FALSE;
+ narrow = false;
if (inst.relocs[0].exp.X_op != O_constant
|| inst.relocs[0].exp.X_add_number != 0)
- narrow = FALSE;
+ narrow = false;
/* Turn rsb #0 into 16-bit neg. We should probably do this via
relaxation, but it doesn't seem worth the hassle. */
if (unified_syntax)
{
- bfd_boolean narrow;
+ bool narrow;
int shift_kind;
switch (inst.instruction)
else
narrow = in_pred_block ();
if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
- narrow = FALSE;
+ narrow = false;
if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
- narrow = FALSE;
+ narrow = false;
if (inst.operands[2].isreg
&& (inst.operands[1].reg != inst.operands[0].reg
|| inst.operands[2].reg > 7))
- narrow = FALSE;
+ narrow = false;
if (inst.size_req == 4)
- narrow = FALSE;
+ narrow = false;
reject_bad_reg (inst.operands[0].reg);
reject_bad_reg (inst.operands[1].reg);
inst.instruction = THUMB_OP32 (inst.instruction);
if (inst.operands[0].hasreloc == 0)
{
- if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
+ if (v8_1_branch_value_check (inst.operands[0].imm, 5, false) == FAIL)
as_bad (BAD_BRANCH_OFF);
inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
if (inst.operands[1].hasreloc == 0)
{
int val = inst.operands[1].imm;
- if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
+ if (v8_1_branch_value_check (inst.operands[1].imm, 17, true) == FAIL)
as_bad (BAD_BRANCH_OFF);
int immA = (val & 0x0001f000) >> 12;
if (inst.operands[1].hasreloc == 0)
{
int val = inst.operands[1].imm;
- if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
+ if (v8_1_branch_value_check (inst.operands[1].imm, 19, true) == FAIL)
as_bad (BAD_BRANCH_OFF);
int immA = (val & 0x0007f000) >> 12;
int value = inst.relocs[0].exp.X_add_number;
value = (is_le) ? -value : value;
- if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
+ if (v8_1_branch_value_check (value, 12, false) == FAIL)
as_bad (BAD_BRANCH_OFF);
int imml, immh;
now_pred.cc = 0;
now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
| ((inst.instruction & 0xe000) >> 13);
- now_pred.warn_deprecated = FALSE;
+ now_pred.warn_deprecated = false;
now_pred.type = VECTOR_PRED;
inst.is_neon = 1;
}
if (!inst.operands[0].present)
inst.instruction |= 1 << 21;
- v8_1_loop_reloc (TRUE);
+ v8_1_loop_reloc (true);
break;
case T_MNEM_wls:
case T_MNEM_wlstp:
- v8_1_loop_reloc (FALSE);
+ v8_1_loop_reloc (false);
/* fall through. */
case T_MNEM_dlstp:
case T_MNEM_dls:
instruction. CHECK contains th. CHECK contains the set of bits to pass to
vfp_or_neon_is_neon for the NEON specific checks. */
-static bfd_boolean
+static bool
check_simd_pred_availability (int fp, unsigned check)
{
if (inst.cond > COND_ALWAYS)
if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
{
inst.error = BAD_FPU;
- return FALSE;
+ return false;
}
inst.pred_insn_type = INSIDE_VPT_INSN;
}
if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
else if (vfp_or_neon_is_neon (check) == FAIL)
- return FALSE;
+ return false;
}
else
{
if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
&& vfp_or_neon_is_neon (check) == FAIL)
- return FALSE;
+ return false;
if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
}
-return TRUE;
+return true;
}
/* Neon instruction encoders, in approximate order of appearance. */
static void
do_neon_dyadic_i_su (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
static void
do_neon_dyadic_i64_su (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
+ if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
enum neon_shape rs;
struct neon_type_el et;
static void
do_neon_shl (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
if (!inst.operands[2].isreg)
constraint (imm < 0 || (unsigned)imm >= et.size,
_("immediate out of range for shift"));
NEON_ENCODE (IMMED, inst);
- neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
+ neon_imm_shift (false, 0, neon_quad (rs), et, imm);
}
else
{
static void
do_neon_qshl (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
if (!inst.operands[2].isreg)
constraint (imm < 0 || (unsigned)imm >= et.size,
_("immediate out of range for shift"));
NEON_ENCODE (IMMED, inst);
- neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
+ neon_imm_shift (true, et.type == NT_unsigned, neon_quad (rs), et, imm);
}
else
{
static void
do_neon_rshl (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
{
enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
if (rs == NS_QQQ
- && !check_simd_pred_availability (FALSE,
+ && !check_simd_pred_availability (false,
NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
else if (rs != NS_QQQ
/* Because neon_select_shape makes the second operand a copy of the first
if the second operand is not present. */
if (rs == NS_QQI
- && !check_simd_pred_availability (FALSE,
+ && !check_simd_pred_availability (false,
NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
else if (rs != NS_QQI
static void
do_neon_cmp (void)
{
- neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
+ neon_compare (N_SUF_32, N_S_32 | N_F_16_32, false);
}
static void
do_neon_cmp_inv (void)
{
- neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
+ neon_compare (N_SUF_32, N_S_32 | N_F_16_32, true);
}
static void
do_neon_ceq (void)
{
- neon_compare (N_IF_32, N_IF_32, FALSE);
+ neon_compare (N_IF_32, N_IF_32, false);
}
/* For multiply instructions, we have the possibility of 16-bit or 32-bit
if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
return;
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
+ if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
if (inst.operands[2].isscalar)
&& try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
return;
- if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH))
+ if (!check_simd_pred_availability (true, NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
return;
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
+ if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
if (inst.operands[2].isscalar)
static void
do_neon_qdmulh (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
if (inst.operands[2].isscalar)
static void
do_neon_qrdmlah (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
{
static void
do_neon_sli (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
int imm = inst.operands[2].imm;
constraint (imm < 0 || (unsigned)imm >= et.size,
_("immediate out of range for insert"));
- neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
+ neon_imm_shift (false, 0, neon_quad (rs), et, imm);
}
static void
do_neon_sri (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
int imm = inst.operands[2].imm;
constraint (imm < 1 || (unsigned)imm > et.size,
_("immediate out of range for insert"));
- neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
+ neon_imm_shift (false, 0, neon_quad (rs), et, et.size - imm);
}
static void
do_neon_qshlu_imm (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
Unsigned types have OP set to 1. */
inst.instruction |= (et.type == NT_unsigned) << 8;
/* The rest of the bits are the same as other immediate shifts. */
- neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
+ neon_imm_shift (false, 0, neon_quad (rs), et, imm);
}
static void
constraint (imm < 1 || (unsigned)imm > et.size,
_("immediate out of range"));
- neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
+ neon_imm_shift (true, et.type == NT_unsigned, 0, et, et.size - imm);
}
static void
/* FIXME: The manual is kind of unclear about what value U should have in
VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
must be 1. */
- neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
+ neon_imm_shift (true, 1, 0, et, et.size - imm);
}
static void
constraint (imm < 1 || (unsigned)imm > et.size,
_("immediate out of range for narrowing operation"));
- neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
+ neon_imm_shift (false, 0, 0, et, et.size - imm);
}
static void
et = neon_check_type (2, NS_QDI,
N_EQK | N_DBL, N_SU_32 | N_KEY);
NEON_ENCODE (IMMED, inst);
- neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
+ neon_imm_shift (true, et.type == NT_unsigned, 0, et, imm);
}
}
inst.instruction |= op << 7;
inst.instruction |= rm << 16;
inst.instruction |= 0xf0000000;
- inst.is_neon = TRUE;
+ inst.is_neon = true;
}
static void
|| flavour == neon_cvt_flavour_s32_f32
|| flavour == neon_cvt_flavour_u32_f32))
{
- if (!check_simd_pred_availability (TRUE,
+ if (!check_simd_pred_availability (true,
NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
}
|| flavour == neon_cvt_flavour_s32_f32
|| flavour == neon_cvt_flavour_u32_f32))
{
- if (!check_simd_pred_availability (TRUE,
+ if (!check_simd_pred_availability (true,
NEON_CHECK_CC | NEON_CHECK_ARCH8))
return;
}
|| flavour == neon_cvt_flavour_s32_f32
|| flavour == neon_cvt_flavour_u32_f32))
{
- if (!check_simd_pred_availability (TRUE,
+ if (!check_simd_pred_availability (true,
NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
}
{
NEON_ENCODE (FLOAT, inst);
- if (!check_simd_pred_availability (TRUE,
+ if (!check_simd_pred_availability (true,
NEON_CHECK_CC | NEON_CHECK_ARCH8))
return;
}
static void
-do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
+do_neon_cvttb_2 (bool t, bool to, bool is_double)
{
if (is_double)
mark_feature_used (&fpu_vfp_ext_armv8);
}
static void
-do_neon_cvttb_1 (bfd_boolean t)
+do_neon_cvttb_1 (bool t)
{
enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
else if (rs == NS_QQ || rs == NS_QQI)
{
int single_to_half = 0;
- if (!check_simd_pred_availability (TRUE, NEON_CHECK_ARCH))
+ if (!check_simd_pred_availability (true, NEON_CHECK_ARCH))
return;
enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
{
inst.error = NULL;
- do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
+ do_neon_cvttb_2 (t, /*to=*/true, /*is_double=*/false);
}
else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
{
inst.error = NULL;
- do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
+ do_neon_cvttb_2 (t, /*to=*/false, /*is_double=*/false);
}
else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
{
_(BAD_FPU));
inst.error = NULL;
- do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
+ do_neon_cvttb_2 (t, /*to=*/true, /*is_double=*/true);
}
else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
{
_(BAD_FPU));
inst.error = NULL;
- do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
+ do_neon_cvttb_2 (t, /*to=*/false, /*is_double=*/true);
}
else if (neon_check_type (2, rs, N_BF16 | N_VFP, N_F32).type != NT_invtype)
{
inst.error = NULL;
inst.instruction |= (1 << 8);
inst.instruction &= ~(1 << 9);
- do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
+ do_neon_cvttb_2 (t, /*to=*/true, /*is_double=*/false);
}
else
return;
static void
do_neon_cvtb (void)
{
- do_neon_cvttb_1 (FALSE);
+ do_neon_cvttb_1 (false);
}
static void
do_neon_cvtt (void)
{
- do_neon_cvttb_1 (TRUE);
+ do_neon_cvttb_1 (true);
}
static void
static void
do_neon_mvn (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
+ if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
if (inst.operands[1].isreg)
static void
do_neon_rev (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
N_8 | N_16 | N_32 | N_KEY, N_EQK);
if (rs == NS_QR)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH))
return;
}
else
case NS_QQ: /* case 0/1. */
{
- if (!check_simd_pred_availability (FALSE,
+ if (!check_simd_pred_availability (false,
NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
/* The architecture manual I have doesn't explicitly state which
/* fall through. */
case NS_QI: /* case 2/3. */
- if (!check_simd_pred_availability (FALSE,
+ if (!check_simd_pred_availability (false,
NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
inst.instruction = 0x0800010;
static void
do_neon_rshift_round_imm (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
constraint (imm < 1 || (unsigned)imm > et.size,
_("immediate out of range for shift"));
- neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
+ neon_imm_shift (true, et.type == NT_unsigned, neon_quad (rs), et,
et.size - imm);
}
static void
do_neon_sat_abs_neg (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
+ if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
return;
enum neon_shape rs;
static void
do_neon_cls (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
static void
do_neon_clz (void)
{
- if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
+ if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
enum neon_shape rs;
do_t_vldr_vstr_sysreg (void)
{
int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
- bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
+ bool is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
/* Use of PC is UNPREDICTABLE. */
if (inst.operands[1].reg == REG_PC)
inst.instruction = 0xec000f80;
if (is_vldr)
inst.instruction |= 1 << sysreg_vldr_bitno;
- encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
+ encode_arm_cp_address (1, true, false, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
}
static void
do_vldr_vstr (void)
{
- bfd_boolean sysreg_op = !inst.operands[0].isreg;
+ bool sysreg_op = !inst.operands[0].isreg;
/* VLDR/VSTR (System Register). */
if (sysreg_op)
if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
return;
- if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH8))
+ if (!check_simd_pred_availability (true, NEON_CHECK_CC | NEON_CHECK_ARCH8))
return;
neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
if (et.type == NT_invtype)
return;
- if (!check_simd_pred_availability (TRUE,
+ if (!check_simd_pred_availability (true,
NEON_CHECK_CC | NEON_CHECK_ARCH8))
return;
_("immediate out of range"));
rot /= 90;
- if (!check_simd_pred_availability (TRUE,
+ if (!check_simd_pred_availability (true,
NEON_CHECK_ARCH8 | NEON_CHECK_CC))
return;
check_cde_operand (size_t index, int is_dual)
{
unsigned Rx = inst.operands[index].reg;
- bfd_boolean isvec = inst.operands[index].isvec;
+ bool isvec = inst.operands[index].isvec;
if (is_dual == 0 && thumb_mode)
constraint (
!((Rx <= 14 && Rx != 13) || (Rx == REG_PC && isvec)),
_("Register must be an even register between r0-r10."));
}
-static bfd_boolean
+static bool
cde_coproc_enabled (unsigned coproc)
{
switch (coproc)
case 5: return mark_feature_used (&arm_ext_cde5);
case 6: return mark_feature_used (&arm_ext_cde6);
case 7: return mark_feature_used (&arm_ext_cde7);
- default: return FALSE;
+ default: return false;
}
}
#undef cde_coproc_pos
static void
-cxn_handle_predication (bfd_boolean is_accum)
+cxn_handle_predication (bool is_accum)
{
if (is_accum && conditional_insn ())
set_pred_insn_type (INSIDE_IT_INSN);
}
static void
-do_custom_instruction_1 (int is_dual, bfd_boolean is_accum)
+do_custom_instruction_1 (int is_dual, bool is_accum)
{
constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
}
static void
-do_custom_instruction_2 (int is_dual, bfd_boolean is_accum)
+do_custom_instruction_2 (int is_dual, bool is_accum)
{
constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
}
static void
-do_custom_instruction_3 (int is_dual, bfd_boolean is_accum)
+do_custom_instruction_3 (int is_dual, bool is_accum)
{
constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
now_pred.block_length = 1;
mapping_state (MAP_THUMB);
now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
- now_pred.warn_deprecated = FALSE;
- now_pred.insn_cond = TRUE;
+ now_pred.warn_deprecated = false;
+ now_pred.insn_cond = true;
}
/* Close an automatic IT block.
handle_pred_state (void)
{
now_pred.state_handled = 1;
- now_pred.insn_cond = FALSE;
+ now_pred.insn_cond = false;
switch (now_pred.state)
{
}
else
{
- now_pred.insn_cond = TRUE;
+ now_pred.insn_cond = true;
now_pred_add_mask (inst.cond);
}
/* Fallthrough. */
case NEUTRAL_IT_INSN:
now_pred.block_length++;
- now_pred.insn_cond = TRUE;
+ now_pred.insn_cond = true;
if (now_pred.block_length > 4)
force_automatic_it_block_close ();
now_pred.mask &= 0x1f;
is_last = now_pred.mask == 0x10;
}
- now_pred.insn_cond = TRUE;
+ now_pred.insn_cond = true;
switch (inst.pred_insn_type)
{
{
as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
"performance deprecated in ARMv8-A and ARMv8-R"));
- now_pred.warn_deprecated = TRUE;
+ now_pred.warn_deprecated = true;
}
else
{
"instructions of the following class are "
"performance deprecated in ARMv8-A and "
"ARMv8-R: %s"), p->description);
- now_pred.warn_deprecated = TRUE;
+ now_pred.warn_deprecated = true;
break;
}
as_tsktsk (_("IT blocks containing more than one conditional "
"instruction are performance deprecated in ARMv8-A and "
"ARMv8-R"));
- now_pred.warn_deprecated = TRUE;
+ now_pred.warn_deprecated = true;
}
}
t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
here, hence the "known" in the function name. */
-static bfd_boolean
+static bool
known_t32_only_insn (const struct asm_opcode *opcode)
{
/* Original Thumb-1 wide instruction. */
|| opcode->tencode == do_t_branch23
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
- return TRUE;
+ return true;
/* Wide-only instruction added to ARMv8-M Baseline. */
if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Whether wide instruction variant can be used if available for a valid OPCODE
in ARCH. */
-static bfd_boolean
+static bool
t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
{
if (known_t32_only_insn (opcode))
- return TRUE;
+ return true;
/* Instruction with narrow and wide encoding added to ARMv8-M. Availability
of variant T3 of B.W is checked in do_t_branch. */
if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
&& opcode->tencode == do_t_branch)
- return TRUE;
+ return true;
/* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
&& opcode->tencode == do_t_mov_cmp
/* Make sure CMP instruction is not affected. */
&& opcode->aencode == do_mov)
- return TRUE;
+ return true;
/* Wide instruction variants of all instructions with narrow *and* wide
variants become available with ARMv6t2. Other opcodes are either
narrow-only or wide-only and are thus available if OPCODE is valid. */
if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
- return TRUE;
+ return true;
/* OPCODE with narrow only instruction variant or wide variant not
available. */
- return FALSE;
+ return false;
}
void
inst.instruction = opcode->tvalue;
- if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
+ if (!parse_operands (p, opcode->operands, /*thumb=*/true))
{
/* Prepare the pred_insn_type for those encodings that don't set
it. */
}
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
{
- bfd_boolean is_bx;
+ bool is_bx;
/* bx is allowed on v5 cores, and sometimes on v4 cores. */
is_bx = (opcode->aencode == do_bx);
else
inst.instruction |= inst.cond << 28;
inst.size = INSN_SIZE;
- if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
+ if (!parse_operands (p, opcode->operands, /*thumb=*/false))
{
it_fsm_pre_encode ();
opcode->aencode ();
THUMB_SET_FUNC (sym, 1);
- label_is_thumb_function_name = FALSE;
+ label_is_thumb_function_name = false;
}
dwarf2_emit_label (sym);
}
-bfd_boolean
+bool
arm_data_in_code (void)
{
if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
*input_line_pointer = '/';
input_line_pointer += 5;
*input_line_pointer = 0;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
char *
should appear in both upper and lowercase variants. Some registers
also have mixed-case names. */
-#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
+#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true, 0 }
#define REGNUM(p,n,t) REGDEF(p##n, n, t)
#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
#define REGSET(p,t) \
/* Return TRUE iff the definition of symbol S could be pre-empted
(overridden) at link or load time. */
-static bfd_boolean
+static bool
symbol_preemptible (symbolS *s)
{
/* Weak symbols can always be pre-empted. */
if (S_IS_WEAK (s))
- return TRUE;
+ return true;
/* Non-global symbols cannot be pre-empted. */
if (! S_IS_EXTERNAL (s))
- return FALSE;
+ return false;
#ifdef OBJ_ELF
/* In ELF, a global symbol can be marked protected, or private. In that
case it can't be pre-empted (other definitions in the same link unit
would violate the ODR). */
if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
- return FALSE;
+ return false;
#endif
/* Other global symbols might be pre-empted. */
- return TRUE;
+ return true;
}
/* Return the size of a relaxable branch instruction. BITS is the
void
arm_init_frag (fragS * fragP, int max_chars)
{
- bfd_boolean frag_thumb_mode;
+ bool frag_thumb_mode;
/* If the current ARM vs THUMB mode has not already
been recorded into this frag then do so now. */
case BFD_RELOC_THUMB_PCREL_BRANCH23:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
base = fixP->fx_where + fixP->fx_frag->fr_address;
case BFD_RELOC_THUMB_PCREL_BLX:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& THUMB_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
base = fixP->fx_where + fixP->fx_frag->fr_address;
case BFD_RELOC_ARM_PCREL_BLX:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
base = fixP->fx_where + fixP->fx_frag->fr_address;
case BFD_RELOC_ARM_PCREL_CALL:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& THUMB_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
base = fixP->fx_where + fixP->fx_frag->fr_address;
}
}
-static bfd_boolean flag_warn_syms = TRUE;
+static bool flag_warn_syms = true;
-bfd_boolean
+bool
arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
{
/* PR 18347 - Warn if the user attempts to create a symbol with the same
free (nbuf);
}
- return FALSE;
+ return false;
}
/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
a constant. Prevent this and force a relocation when the first symbols
is a thumb function. */
-bfd_boolean
+bool
arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
{
if (op == O_subtract
l->X_op = O_subtract;
l->X_op_symbol = r->X_add_symbol;
l->X_add_number -= r->X_add_number;
- return TRUE;
+ return true;
}
/* Process as normal. */
- return FALSE;
+ return false;
}
/* Encode Thumb2 unconditional branches and calls. The encoding
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
&& fixP->fx_addsy
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& THUMB_IS_FUNC (fixP->fx_addsy))
/* Flip the bl to blx. This is a simple flip
case BFD_RELOC_ARM_PCREL_JUMP:
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
&& fixP->fx_addsy
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& THUMB_IS_FUNC (fixP->fx_addsy))
{
temp = 1;
if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
&& fixP->fx_addsy
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& ARM_IS_FUNC (fixP->fx_addsy))
{
case BFD_RELOC_THUMB_PCREL_BRANCH20:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
{
about it. */
if (fixP->fx_addsy
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& THUMB_IS_FUNC (fixP->fx_addsy))
{
is converted to a blx. */
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
{
gas_assert (!fixP->fx_done);
{
bfd_vma insn;
- bfd_boolean is_mov;
+ bool is_mov;
bfd_vma encoded_addend = value;
/* Check that addend can be encoded in instruction. */
case BFD_RELOC_THUMB_PCREL_BRANCH5:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
{
/* Force a relocation for a branch 5 bits wide. */
fixP->fx_done = 0;
}
- if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
+ if (v8_1_branch_value_check (value, 5, false) == FAIL)
as_bad_where (fixP->fx_file, fixP->fx_line,
BAD_BRANCH_OFF);
case BFD_RELOC_THUMB_PCREL_BFCSEL:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
{
case BFD_RELOC_ARM_THUMB_BF17:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
{
fixP->fx_done = 0;
}
- if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
+ if (v8_1_branch_value_check (value, 17, true) == FAIL)
as_bad_where (fixP->fx_file, fixP->fx_line,
BAD_BRANCH_OFF);
case BFD_RELOC_ARM_THUMB_BF19:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
{
fixP->fx_done = 0;
}
- if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
+ if (v8_1_branch_value_check (value, 19, true) == FAIL)
as_bad_where (fixP->fx_file, fixP->fx_line,
BAD_BRANCH_OFF);
case BFD_RELOC_ARM_THUMB_BF13:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
{
fixP->fx_done = 0;
}
- if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
+ if (v8_1_branch_value_check (value, 13, true) == FAIL)
as_bad_where (fixP->fx_file, fixP->fx_line,
BAD_BRANCH_OFF);
case BFD_RELOC_ARM_THUMB_LOOP12:
if (fixP->fx_addsy
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& ARM_IS_FUNC (fixP->fx_addsy)
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
{
|| ((insn & 0xffffffff) == 0xf01fc001))
value = -value;
- if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
+ if (v8_1_branch_value_check (value, 12, false) == FAIL)
as_bad_where (fixP->fx_file, fixP->fx_line,
BAD_BRANCH_OFF);
if (fixP->fx_done || !seg->use_rela_p)
addresses also ought to have their bottom bit set (assuming that
they reside in Thumb code), but at the moment they will not. */
-bfd_boolean
+bool
arm_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
/* Preserve relocations against symbols with function type. */
if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
- return FALSE;
+ return false;
if (THUMB_IS_FUNC (fixP->fx_addsy)
&& fixP->fx_subsy == NULL)
- return FALSE;
+ return false;
/* We need the symbol name for the VTABLE entries. */
if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
- return FALSE;
+ return false;
/* Don't allow symbols to be discarded on GOT related relocs. */
if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
|| fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
|| fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
- return FALSE;
+ return false;
/* Similarly for group relocations. */
if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
&& fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
|| fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
- return FALSE;
+ return false;
/* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
|| fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
- return FALSE;
+ return false;
/* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
offsets, so keep these symbols. */
if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
&& fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
" in ARMv8-A and ARMv8-R"), &warn_on_restrict_it, 1, NULL},
{"mno-warn-restrict-it", NULL, &warn_on_restrict_it, 0, NULL},
- {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
- {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
+ {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), true, NULL},
+ {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), false, NULL},
{NULL, NULL, NULL, 0, NULL}
};
struct arm_long_option_table
{
- const char * option; /* Substring to match. */
- const char * help; /* Help information. */
- bfd_boolean (*func) (const char *subopt); /* Function to decode sub-option. */
- const char * deprecated; /* If non-null, print this message. */
+ const char *option; /* Substring to match. */
+ const char *help; /* Help information. */
+ bool (*func) (const char *subopt); /* Function to decode sub-option. */
+ const char *deprecated; /* If non-null, print this message. */
};
-static bfd_boolean
+static bool
arm_parse_extension (const char *str, const arm_feature_set *opt_set,
arm_feature_set *ext_set,
const struct arm_ext_table *ext_table)
if (*str != '+')
{
as_bad (_("invalid architectural extension"));
- return FALSE;
+ return false;
}
str++;
{
as_bad (_("must specify extensions to add before specifying "
"those to remove"));
- return FALSE;
+ return false;
}
}
if (len == 0)
{
as_bad (_("missing architectural extension"));
- return FALSE;
+ return false;
}
gas_assert (adding_value != -1);
if (ext_table != NULL)
{
const struct arm_ext_table * ext_opt = ext_table;
- bfd_boolean found = FALSE;
+ bool found = false;
for (; ext_opt->name != NULL; ext_opt++)
if (ext_opt->name_len == len
&& strncmp (ext_opt->name, str, len) == 0)
continue;
ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
}
- found = TRUE;
+ found = true;
break;
}
if (found)
if (i == nb_allowed_archs)
{
as_bad (_("extension does not apply to the base architecture"));
- return FALSE;
+ return false;
}
/* Add or remove the extension. */
as_bad (_("architectural extensions must be specified in "
"alphabetical order"));
- return FALSE;
+ return false;
}
else
{
str = ext;
};
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
arm_parse_fp16_opt (const char *str)
{
if (strcasecmp (str, "ieee") == 0)
else
{
as_bad (_("unrecognised float16 format \"%s\""), str);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
arm_parse_cpu (const char *str)
{
const struct arm_cpu_option_table *opt;
if (len == 0)
{
as_bad (_("missing cpu name `%s'"), str);
- return FALSE;
+ return false;
}
for (opt = arm_cpus; opt->name != NULL; opt++)
if (ext != NULL)
return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
- return TRUE;
+ return true;
}
as_bad (_("unknown cpu `%s'"), str);
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
arm_parse_arch (const char *str)
{
const struct arm_arch_option_table *opt;
if (len == 0)
{
as_bad (_("missing architecture name `%s'"), str);
- return FALSE;
+ return false;
}
for (opt = arm_archs; opt->name != NULL; opt++)
return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
opt->ext_table);
- return TRUE;
+ return true;
}
as_bad (_("unknown architecture `%s'\n"), str);
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
arm_parse_fpu (const char * str)
{
const struct arm_option_fpu_value_table * opt;
if (streq (opt->name, str))
{
mfpu_opt = &opt->value;
- return TRUE;
+ return true;
}
as_bad (_("unknown floating point format `%s'\n"), str);
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
arm_parse_float_abi (const char * str)
{
const struct arm_option_value_table * opt;
if (streq (opt->name, str))
{
mfloat_abi_opt = opt->value;
- return TRUE;
+ return true;
}
as_bad (_("unknown floating point abi `%s'\n"), str);
- return FALSE;
+ return false;
}
#ifdef OBJ_ELF
-static bfd_boolean
+static bool
arm_parse_eabi (const char * str)
{
const struct arm_option_value_table *opt;
if (streq (opt->name, str))
{
meabi_flags = opt->value;
- return TRUE;
+ return true;
}
as_bad (_("unknown EABI `%s'\n"), str);
- return FALSE;
+ return false;
}
#endif
-static bfd_boolean
+static bool
arm_parse_it_mode (const char * str)
{
- bfd_boolean ret = TRUE;
+ bool ret = true;
if (streq ("arm", str))
implicit_it_mode = IMPLICIT_IT_MODE_ARM;
{
as_bad (_("unknown implicit IT mode `%s', should be "\
"arm, thumb, always, or never."), str);
- ret = FALSE;
+ ret = false;
}
return ret;
}
-static bfd_boolean
+static bool
arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
{
- codecomposer_syntax = TRUE;
+ codecomposer_syntax = true;
arm_comment_chars[0] = ';';
arm_line_separator_chars[0] = 0;
- return TRUE;
+ return true;
}
struct arm_long_option_table arm_long_opts[] =
#endif
case OPTION_FIX_V4BX:
- fix_v4bx = TRUE;
+ fix_v4bx = true;
break;
#ifdef OBJ_ELF
case OPTION_FDPIC:
- arm_fdpic = TRUE;
+ arm_fdpic = true;
break;
#endif /* OBJ_ELF */
/* Return whether features in the *NEEDED feature set are available via
extensions for the architecture whose feature set is *ARCH_FSET. */
-static bfd_boolean
+static bool
have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
const arm_feature_set *needed)
{
will always be generated for it, so applying the symbol value now
will result in a double offset being stored in the relocation. */
&& (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
+ && !S_FORCE_RELOC (fixP->fx_addsy, true))
{
switch (fixP->fx_r_type)
{
/* We conditionally support labels without a colon. */
#define LABELS_WITHOUT_COLONS codecomposer_syntax
-extern bfd_boolean codecomposer_syntax;
+extern bool codecomposer_syntax;
#define tc_symbol_chars arm_symbol_chars
extern const char arm_symbol_chars[];
extern int arm_relax_frag (asection *, struct frag *, long);
#define md_optimize_expr(l,o,r) arm_optimize_expr (l, o, r)
-extern bfd_boolean arm_optimize_expr (expressionS *, operatorT, expressionS *);
+extern bool arm_optimize_expr (expressionS *, operatorT, expressionS *);
#define md_cleanup() arm_cleanup ()
#define TC_START_LABEL_WITHOUT_COLON(NUL_CHAR, NEXT_CHAR) \
tc_start_label_without_colon ()
-extern bfd_boolean tc_start_label_without_colon (void);
+extern bool tc_start_label_without_colon (void);
#define tc_frob_label(S) arm_frob_label (S)
#ifdef OBJ_ELF
#define md_end arm_md_end
extern void arm_md_end (void);
-bfd_boolean arm_is_eabi (void);
+bool arm_is_eabi (void);
#define md_post_relax_hook arm_md_post_relax ()
extern void arm_md_post_relax (void);
extern void arm_cleanup (void);
extern void arm_start_line_hook (void);
extern void arm_frob_label (symbolS *);
-extern bfd_boolean arm_data_in_code (void);
+extern bool arm_data_in_code (void);
extern char * arm_canonicalize_symbol_name (char *);
extern void arm_adjust_symtab (void);
extern void armelf_frob_symbol (symbolS *, int *);
bfd_reloc_code_real_type);
extern void arm_init_frag (struct frag *, int);
extern void arm_handle_align (struct frag *);
-extern bfd_boolean arm_fix_adjustable (struct fix *);
+extern bool arm_fix_adjustable (struct fix *);
extern int arm_elf_section_type (const char *, size_t);
extern int tc_arm_regname_to_dw2regnum (char *regname);
extern void tc_arm_frame_initial_instructions (void);
extern char arm_line_separator_chars[];
#define TC_EQUAL_IN_INSN(c, s) arm_tc_equal_in_insn ((c), (s))
-extern bfd_boolean arm_tc_equal_in_insn (int, char *);
+extern bool arm_tc_equal_in_insn (int, char *);
#define TC_LARGEST_EXPONENT_IS_NORMAL(PRECISION) \
arm_is_largest_exponent_ok ((PRECISION))
struct avr_opcodes_s
{
- const char * name;
- const char * constraints;
- const char * opcode;
- int insn_size; /* In words. */
- int isa;
- unsigned int bin_opcode;
+ const char *name;
+ const char *constraints;
+ const char *opcode;
+ int insn_size; /* In words. */
+ int isa;
+ unsigned int bin_opcode;
};
#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
void
avr_offset_expression (& op_expr);
str = input_line_pointer;
fix_new_exp (frag_now, where, 3,
- &op_expr, FALSE, BFD_RELOC_AVR_6);
+ &op_expr, false, BFD_RELOC_AVR_6);
}
}
break;
case 'h':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
- &op_expr, FALSE, BFD_RELOC_AVR_CALL);
+ &op_expr, false, BFD_RELOC_AVR_CALL);
break;
case 'L':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
- &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
+ &op_expr, true, BFD_RELOC_AVR_13_PCREL);
break;
case 'l':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
- &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
+ &op_expr, true, BFD_RELOC_AVR_7_PCREL);
break;
case 'i':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
- &op_expr, FALSE, BFD_RELOC_16);
+ &op_expr, false, BFD_RELOC_16);
break;
case 'j':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
- &op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16);
+ &op_expr, false, BFD_RELOC_AVR_LDS_STS_16);
break;
case 'M':
r_type = avr_ldi_expression (&op_expr);
str = input_line_pointer;
fix_new_exp (frag_now, where, 3,
- &op_expr, FALSE, r_type);
+ &op_expr, false, r_type);
}
break;
avr_offset_expression (& op_expr);
str = input_line_pointer;
fix_new_exp (frag_now, where, 3,
- & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
+ & op_expr, false, BFD_RELOC_AVR_6_ADIW);
break;
case 'S':
case 'P':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
- &op_expr, FALSE, BFD_RELOC_AVR_PORT6);
+ &op_expr, false, BFD_RELOC_AVR_PORT6);
break;
case 'p':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
- &op_expr, FALSE, BFD_RELOC_AVR_PORT5);
+ &op_expr, false, BFD_RELOC_AVR_PORT5);
break;
case 'E':
return fixp->fx_frag->fr_address + fixp->fx_where;
}
-static bfd_boolean
+static bool
relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
{
default:
if (nbytes == 1)
- fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
+ fix_new_exp (frag, where, nbytes, exp, false, BFD_RELOC_8);
else if (nbytes == 2)
- fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
+ fix_new_exp (frag, where, nbytes, exp, false, BFD_RELOC_16);
else if (nbytes == 4)
- fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
+ fix_new_exp (frag, where, nbytes, exp, false, BFD_RELOC_32);
else
bad = 1;
break;
case BFD_RELOC_AVR_8_HI:
case BFD_RELOC_AVR_8_HLO:
if (nbytes == pexp_mod_data->nbytes)
- fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc);
+ fix_new_exp (frag, where, nbytes, exp, false, pexp_mod_data->reloc);
else
bad = 1;
break;
as_bad (_("illegal %s relocation size: %d"), pexp_mod_data->error, nbytes);
}
-static bfd_boolean
+static bool
mcu_has_3_byte_pc (void)
{
int mach = avr_mcu->mach;
cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
}
-bfd_boolean
+bool
avr_allow_local_subtract (expressionS * left,
expressionS * right,
segT section)
{
/* If we are not in relaxation mode, subtraction is OK. */
if (!linkrelax)
- return TRUE;
+ return true;
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
- return TRUE;
+ return true;
if (left->X_add_symbol == right->X_add_symbol)
- return TRUE;
+ return true;
/* We have to assume that there may be instructions between the
two symbols and that relaxation may increase the distance between
them. */
- return FALSE;
+ return false;
}
void
where = frag_ptr - frag_base;
fix = fix_new (frag_now, where, 4,
section_symbol (record->section),
- record->offset, FALSE, BFD_RELOC_32);
+ record->offset, false, BFD_RELOC_32);
fix->fx_file = "<internal>";
fix->fx_line = 0;
frag_ptr += 4;
{
char *p = fragP->fr_literal + fragP->fr_fix;
- fragP->tc_frag_data.is_align = TRUE;
+ fragP->tc_frag_data.is_align = true;
fragP->tc_frag_data.alignment = fragP->fr_offset;
fragP->tc_frag_data.fill = *p;
fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
{
char *p = fragP->fr_literal + fragP->fr_fix;
- fragP->tc_frag_data.is_org = TRUE;
+ fragP->tc_frag_data.is_org = true;
fragP->tc_frag_data.fill = *p;
fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
}
/* Return TRUE if this section is not one for which we need to record
information in the avr property section. */
-static bfd_boolean
+static bool
exclude_section_from_property_tables (segT sec)
{
/* Only generate property information for sections on which linker
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) avr_allow_local_subtract (l, r, s)
-extern bfd_boolean avr_allow_local_subtract (expressionS *, expressionS *, segT);
+extern bool avr_allow_local_subtract (expressionS *, expressionS *, segT);
#define elf_tc_final_processing avr_elf_final_processing
extern void avr_elf_final_processing (void);
case BFD_RELOC_BFIN_16_LOW:
case BFD_RELOC_BFIN_16_HIGH:
- fixP->fx_done = FALSE;
+ fixP->fx_done = false;
break;
case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
case BFD_RELOC_BFIN_FUNCDESC:
case BFD_RELOC_VTABLE_INHERIT:
case BFD_RELOC_VTABLE_ENTRY:
- fixP->fx_done = FALSE;
+ fixP->fx_done = false;
break;
default:
}
if (!fixP->fx_addsy)
- fixP->fx_done = TRUE;
+ fixP->fx_done = true;
}
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
/* Return true if the fix can be handled by GAS, false if it must
be passed through to the linker. */
-bfd_boolean
+bool
bfin_fix_adjustable (fixS *fixP)
{
switch (fixP->fx_r_type)
*symbol_X_add_number (linelabel) -= last_insn_size;
}
-bfd_boolean
+bool
bfin_eol_in_insn (char *line)
{
/* Allow a new-line to appear in the middle of a multi-issue instruction. */
char *temp = line;
if (*line != '\n')
- return FALSE;
+ return false;
/* A semi-colon followed by a newline is always the end of a line. */
if (line[-1] == ';')
- return FALSE;
+ return false;
if (line[-1] == '|')
- return TRUE;
+ return true;
/* If the || is on the next line, there might be leading whitespace. */
temp++;
while (*temp == ' ' || *temp == '\t') temp++;
if (*temp == '|')
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
bfin_start_label (char *s)
{
while (*s != 0)
{
if (*s == '(' || *s == '[')
- return FALSE;
+ return false;
s++;
}
- return TRUE;
+ return true;
}
int
{
if (fixp->fx_r_type ==BFD_RELOC_BFIN_16_LOW
|| fixp->fx_r_type == BFD_RELOC_BFIN_16_HIGH)
- return TRUE;
+ return true;
return generic_force_reloc (fixp);
}
#define WORKING_DOT_WORD
-extern bfd_boolean bfin_start_label (char *);
+extern bool bfin_start_label (char *);
#define md_number_to_chars number_to_chars_littleendian
#define md_convert_frag(b,s,f) as_fatal ("bfin convert_frag\n");
#define LEX_BR 6
#define TC_EOL_IN_INSN(PTR) (bfin_eol_in_insn(PTR) ? 1 : 0)
-extern bfd_boolean bfin_eol_in_insn (char *);
+extern bool bfin_eol_in_insn (char *);
/* Almost all instructions of Blackfin contain an = character. */
#define TC_EQUAL_IN_INSN(C, NAME) (NAME[0] != '.' || NAME[1] != 0)
#define TC_START_LABEL(STR, NUL_CHAR, NEXT_CHAR) \
(NEXT_CHAR == ':' && bfin_start_label (STR))
#define tc_fix_adjustable(FIX) bfin_fix_adjustable (FIX)
-extern bfd_boolean bfin_fix_adjustable (struct fix *);
+extern bool bfin_fix_adjustable (struct fix *);
#define TC_FORCE_RELOCATION(FIX) bfin_force_relocation (FIX)
extern int bfin_force_relocation (struct fix *);
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
we default to no underscore and required register-prefixes. The
difference is in the default values. */
#ifdef TE_LINUX
-#define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE
+#define DEFAULT_CRIS_AXIS_LINUX_GNU true
#else
-#define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE
+#define DEFAULT_CRIS_AXIS_LINUX_GNU false
#endif
/* Whether we demand that registers have a `$' prefix. Default here. */
-static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU;
+static bool demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU;
/* Whether global user symbols have a leading underscore. Default here. */
-static bfd_boolean symbols_have_leading_underscore
+static bool symbols_have_leading_underscore
= !DEFAULT_CRIS_AXIS_LINUX_GNU;
/* Whether or not we allow PIC, and expand to PIC-friendly constructs. */
-static bfd_boolean pic = FALSE;
+static bool pic = false;
/* Whether or not we allow TLS suffixes. For the moment, we always do. */
-static const bfd_boolean tls = TRUE;
+static const bool tls = true;
/* If we're configured for "cris", default to allow all v0..v10
instructions and register names. */
const char *const suffix;
unsigned int len;
bfd_reloc_code_real_type reloc;
- bfd_boolean pic_p;
- bfd_boolean tls_p;
+ bool pic_p;
+ bool tls_p;
} pic_suffixes[] =
{
#undef PICMAP
-#define PICMAP(s, r) {s, sizeof (s) - 1, r, TRUE, FALSE}
-#define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, TRUE, TRUE}
-#define TLSMAP(s, r) {s, sizeof (s) - 1, r, FALSE, TRUE}
+#define PICMAP(s, r) {s, sizeof (s) - 1, r, true, false}
+#define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, true, true}
+#define TLSMAP(s, r) {s, sizeof (s) - 1, r, false, true}
/* Keep this in order with longest unambiguous prefix first. */
PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT),
PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT),
break;
case OPTION_NO_US:
- demand_register_prefix = TRUE;
+ demand_register_prefix = true;
if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
as_bad (_("--no-underscore is invalid with a.out format"));
else
- symbols_have_leading_underscore = FALSE;
+ symbols_have_leading_underscore = false;
break;
case OPTION_US:
- demand_register_prefix = FALSE;
- symbols_have_leading_underscore = TRUE;
+ demand_register_prefix = false;
+ symbols_have_leading_underscore = true;
break;
case OPTION_PIC:
if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
as_bad (_("--pic is invalid for this object format"));
- pic = TRUE;
+ pic = true;
if (cris_arch != arch_crisv32)
md_long_jump_size = cris_any_v0_v10_long_jump_size_pic;
else
static void
cris_force_reg_prefix (void)
{
- demand_register_prefix = TRUE;
+ demand_register_prefix = true;
}
/* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */
static void
cris_relax_reg_prefix (void)
{
- demand_register_prefix = FALSE;
+ demand_register_prefix = false;
}
/* Adjust for having a leading '_' on all user symbols. */
p = frag_more (bytes);
md_number_to_chars (p, 0, bytes);
- fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
+ fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false,
BFD_RELOC_CRIS_32_DTPREL);
demand_empty_rest_of_line ();
#define LRW_DISP16_LEN 4 /* lrw32. */
/* Declare worker functions. */
-bfd_boolean v1_work_lrw (void);
-bfd_boolean v1_work_jbsr (void);
-bfd_boolean v1_work_fpu_fo (void);
-bfd_boolean v1_work_fpu_fo_fc (void);
-bfd_boolean v1_work_fpu_write (void);
-bfd_boolean v1_work_fpu_read (void);
-bfd_boolean v1_work_fpu_writed (void);
-bfd_boolean v1_work_fpu_readd (void);
-bfd_boolean v2_work_istack (void);
-bfd_boolean v2_work_btsti (void);
-bfd_boolean v2_work_addi (void);
-bfd_boolean v2_work_subi (void);
-bfd_boolean v2_work_add_sub (void);
-bfd_boolean v2_work_rotlc (void);
-bfd_boolean v2_work_bgeni (void);
-bfd_boolean v2_work_not (void);
-bfd_boolean v2_work_jbtf (void);
-bfd_boolean v2_work_jbr (void);
-bfd_boolean v2_work_lrw (void);
-bfd_boolean v2_work_lrsrsw (void);
-bfd_boolean v2_work_jbsr (void);
-bfd_boolean v2_work_jsri (void);
-bfd_boolean v2_work_movih (void);
-bfd_boolean v2_work_ori (void);
-bfd_boolean float_work_fmovi (void);
-bfd_boolean dsp_work_bloop (void);
-bfd_boolean float_work_fpuv3_fmovi (void);
-bfd_boolean float_work_fpuv3_fstore (void);
-bfd_boolean v2_work_addc (void);
+bool v1_work_lrw (void);
+bool v1_work_jbsr (void);
+bool v1_work_fpu_fo (void);
+bool v1_work_fpu_fo_fc (void);
+bool v1_work_fpu_write (void);
+bool v1_work_fpu_read (void);
+bool v1_work_fpu_writed (void);
+bool v1_work_fpu_readd (void);
+bool v2_work_istack (void);
+bool v2_work_btsti (void);
+bool v2_work_addi (void);
+bool v2_work_subi (void);
+bool v2_work_add_sub (void);
+bool v2_work_rotlc (void);
+bool v2_work_bgeni (void);
+bool v2_work_not (void);
+bool v2_work_jbtf (void);
+bool v2_work_jbr (void);
+bool v2_work_lrw (void);
+bool v2_work_lrsrsw (void);
+bool v2_work_jbsr (void);
+bool v2_work_jsri (void);
+bool v2_work_movih (void);
+bool v2_work_ori (void);
+bool float_work_fmovi (void);
+bool dsp_work_bloop (void);
+bool float_work_fpuv3_fmovi (void);
+bool float_work_fpuv3_fstore (void);
+bool v2_work_addc (void);
/* csky-opc.h must be included after workers are declared. */
#include "opcodes/csky-opc.h"
static symbolS * poolsym;
static char poolname[8];
-static bfd_boolean mov_r1_before;
-static bfd_boolean mov_r1_after;
+static bool mov_r1_before;
+static bool mov_r1_after;
const relax_typeS csky_relax_table [] =
{
{NULL, 0}
};
-static bfd_boolean
+static bool
parse_float_abi (const char *str)
{
const struct csky_option_value_table * opt;
if (strcasecmp (opt->name, str) == 0)
{
float_abi = opt->value;
- return TRUE;
+ return true;
}
as_bad (_("unknown floating point abi `%s'\n"), str);
- return FALSE;
+ return false;
}
#ifdef OBJ_ELF
return s;
}
-static bfd_boolean
+static bool
parse_type_ctrlreg (char** oper)
{
int i = -1;
if (*s != '<')
{
SET_ERROR_STRING (ERROR_CREG_ILLEGAL, s);
- return FALSE;
+ return false;
}
s++;
crx = strtol(s, &s, 10);
if (crx < 0 || crx > 31 || *s != ',')
{
SET_ERROR_STRING (ERROR_CREG_ILLEGAL, s);
- return FALSE;
+ return false;
}
s++;
sel = strtol(s, &s, 10);
if (sel < 0 || sel > 31 || *s != '>')
{
SET_ERROR_STRING (ERROR_CREG_ILLEGAL, s);
- return FALSE;
+ return false;
}
s++;
}
if (crx < 0)
{
SET_ERROR_STRING (ERROR_CREG_ILLEGAL, s);
- return FALSE;
+ return false;
}
}
i = (sel << 5) | crx;
if (i < 0)
{
SET_ERROR_STRING (ERROR_CREG_ILLEGAL, s);
- return FALSE;
+ return false;
}
}
*oper = s;
csky_insn.val[csky_insn.idx++] = i;
- return TRUE;
+ return true;
}
static int
return regno;
}
-static bfd_boolean
+static bool
is_reg_sp_with_bracket (char **oper)
{
int reg;
sp_idx = 14;
if (**oper != '(')
- return FALSE;
+ return false;
*oper += 1;
reg = csky_get_reg_val (*oper, &len);
*oper += len;
{
SET_ERROR_STRING (ERROR_UNDEFINE,
"Operand format is error. '(sp)' expected");
- return FALSE;
+ return false;
}
*oper += 1;
csky_insn.val[csky_insn.idx++] = sp_idx;
- return TRUE;
+ return true;
}
SET_ERROR_STRING (ERROR_UNDEFINE,
"Operand format is error. '(sp)' expected");
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
is_reg_sp (char **oper)
{
char sp_name[16];
{
*oper += 2;
csky_insn.val[csky_insn.idx++] = sp_idx;
- return TRUE;
+ return true;
}
len = sprintf (sp_name, "r%d", sp_idx);
{
*oper += len;
csky_insn.val[csky_insn.idx++] = sp_idx;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
static int
return reg;
}
-static bfd_boolean
+static bool
is_reglist_legal (char **oper)
{
int reg1 = -1;
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The first reg must not be r0/r15");
- return FALSE;
+ return false;
}
if (**oper != '-')
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The operand format must be rx-ry");
- return FALSE;
+ return false;
}
*oper += 1;
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The operand format must be r15 in C-SKY V1");
- return FALSE;
+ return false;
}
if (IS_CSKY_V2 (mach_flag))
{
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The operand format must be rx-ry (rx < ry)");
- return FALSE;
+ return false;
}
reg2 = reg2 - reg1;
reg1 <<= 5;
reg1 |= reg2;
}
csky_insn.val[csky_insn.idx++] = reg1;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
is_freglist_legal (char **oper)
{
int reg1 = -1;
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The fpu register format is not recognized.");
- return FALSE;
+ return false;
}
if (**oper != '-')
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The operand format must be vrx-vry/frx-fry.");
- return FALSE;
+ return false;
}
*oper += 1;
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The fpu register format is not recognized.");
- return FALSE;
+ return false;
}
if (reg2 < reg1)
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The operand format must be rx-ry(rx < ry)");
- return FALSE;
+ return false;
}
reg2 = reg2 - reg1;
/* ISA_FLOAT_E1 fstm/fldm fry-frx is within 15.
ISA_FLOAT_7E60 fstm(u)/fldm(u) frx-fry is within 31. */
SET_ERROR_STRING(ERROR_REG_FORMAT, (void *)"frx-fry is over range");
- return FALSE;
+ return false;
}
if ((mach_flag & CSKY_ARCH_MASK) == CSKY_ARCH_860)
{
{
if (reg2 > (int)0x3) {
SET_ERROR_STRING(ERROR_REG_FORMAT, (void *)"vry-vrx is over range");
- return FALSE;
+ return false;
}
}
reg2 <<= shift;
reg1 |= reg2;
csky_insn.val[csky_insn.idx++] = reg1;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
is_reglist_dash_comma_legal (char **oper, struct operand *oprnd)
{
int reg1 = -1;
if (reg1 == -1)
{
SET_ERROR_STRING (ERROR_REG_LIST, NULL);
- return FALSE;
+ return false;
}
flag |= (1 << reg1);
*oper += len;
if (reg2 == -1)
{
SET_ERROR_STRING (ERROR_REG_LIST, NULL);
- return FALSE;
+ return false;
}
*oper += len;
if (reg1 > reg2)
{
SET_ERROR_STRING (ERROR_REG_LIST, NULL);
- return FALSE;
+ return false;
}
while (reg2 >= reg1)
{
if (flag & ~(REGLIST_BITS))
{
SET_ERROR_STRING (ERROR_REG_LIST, NULL);
- return FALSE;
+ return false;
}
/* Check r4-r11. */
int i = 4;
if (oprnd->mask == OPRND_MASK_0_4 && (list & ~OPRND_MASK_0_4))
{
SET_ERROR_STRING (ERROR_REG_LIST, NULL);
- return FALSE;
+ return false;
}
csky_insn.val[csky_insn.idx++] = list;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
is_reg_lshift_illegal (char **oper, int is_float)
{
int value;
if (reg == -1)
{
SET_ERROR_STRING (ERROR_REG_FORMAT, "The register must be r0-r31.");
- return FALSE;
+ return false;
}
*oper += len;
{
SET_ERROR_STRING (ERROR_UNDEFINE,
"Operand format error; should be (rx, ry << n)");
- return FALSE;
+ return false;
}
*oper += 2;
if (e.X_add_number < 0 || e.X_add_number > 3)
{
SET_ERROR_STRING (ERROR_IMM_OVERFLOW, NULL);
- return FALSE;
+ return false;
}
}
else
{
SET_ERROR_STRING (ERROR_EXP_CONSTANT, NULL);
- return FALSE;
+ return false;
}
if (is_float)
value = (reg << 2) | e.X_add_number;
value = (reg << 5) | (1 << e.X_add_number);
csky_insn.val[csky_insn.idx++] = value;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
is_imm_within_range (char **oper, int min, int max)
{
expressionS e;
- bfd_boolean ret = FALSE;
+ bool ret = false;
char *new_oper = parse_exp (*oper, &e);
if (e.X_op == O_constant)
{
- ret = TRUE;
+ ret = true;
*oper = new_oper;
if (e.X_add_number < min || e.X_add_number > max)
{
- ret = FALSE;
+ ret = false;
SET_ERROR_STRING (ERROR_IMM_OVERFLOW, NULL);
}
if (!e.X_unsigned)
return ret;
}
-static bfd_boolean
+static bool
is_imm_within_range_ext (char **oper, int min, int max, int ext)
{
expressionS e;
- bfd_boolean ret = FALSE;
+ bool ret = false;
char *new_oper = parse_exp (*oper, &e);
if (e.X_op == O_constant)
{
- ret = TRUE;
+ ret = true;
*oper = new_oper;
if ((int)e.X_add_number != ext
&& (e.X_add_number < min || e.X_add_number > max))
{
- ret = FALSE;
+ ret = false;
SET_ERROR_STRING (ERROR_IMM_OVERFLOW, NULL);
}
csky_insn.val[csky_insn.idx++] = e.X_add_number;
return ret;
}
-static bfd_boolean
+static bool
is_oimm_within_range (char **oper, int min, int max)
{
expressionS e;
- bfd_boolean ret = FALSE;
+ bool ret = false;
char *new_oper = parse_exp (*oper, &e);
if (e.X_op == O_constant)
{
- ret = TRUE;
+ ret = true;
*oper = new_oper;
if (e.X_add_number < min || e.X_add_number > max)
{
- ret = FALSE;
+ ret = false;
SET_ERROR_STRING (ERROR_IMM_OVERFLOW, NULL);
}
csky_insn.val[csky_insn.idx++] = e.X_add_number - 1;
return ret;
}
-static bfd_boolean
+static bool
is_psr_bit (char **oper)
{
const struct psrbit *bits;
{
*oper += strlen (bits[i].name);
csky_insn.val[csky_insn.idx] |= bits[i].value;
- return TRUE;
+ return true;
}
i++;
}
SET_ERROR_STRING (ERROR_OPCODE_PSRBIT, NULL);
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
parse_type_cpidx (char** oper)
{
char *s = *oper;
*oper += 3;
}
else
- return FALSE;
+ return false;
}
else
{
if (e.X_op != O_constant)
{
/* Can not recognize the operand. */
- return FALSE;
+ return false;
}
idx = e.X_add_number;
}
csky_insn.val[csky_insn.idx++] = idx;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
parse_type_cpreg (char** oper)
{
expressionS e;
if (strncasecmp (*oper, "cpr", 3) != 0)
{
SET_ERROR_STRING(ERROR_CPREG_ILLEGAL, *oper);
- return FALSE;
+ return false;
}
*oper += 3;
if (e.X_op != O_constant)
{
SET_ERROR_STRING(ERROR_CPREG_ILLEGAL, *oper);
- return FALSE;
+ return false;
}
csky_insn.val[csky_insn.idx++] = e.X_add_number;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
parse_type_cpcreg (char** oper)
{
expressionS e;
if (strncasecmp (*oper, "cpcr", 4) != 0)
{
SET_ERROR_STRING(ERROR_CPREG_ILLEGAL, *oper);
- return FALSE;
+ return false;
}
*oper += 4;
if (e.X_op != O_constant)
{
SET_ERROR_STRING(ERROR_CPREG_ILLEGAL, *oper);
- return FALSE;
+ return false;
}
csky_insn.val[csky_insn.idx++] = e.X_add_number;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
parse_type_areg (char** oper)
{
int i = 0;
if (i == -1)
{
SET_ERROR_STRING (ERROR_GREG_ILLEGAL, NULL);
- return FALSE;
+ return false;
}
*oper += len;
csky_insn.val[csky_insn.idx++] = i;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
parse_type_freg (char** oper, int even)
{
int reg;
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
(void *)"The fpu register format is not recognized.");
- return FALSE;
+ return false;
}
*oper += len;
csky_insn.opcode_end = *oper;
if (even && reg & 0x1)
{
SET_ERROR_STRING (ERROR_EXP_EVEN_FREG, NULL);
- return FALSE;
+ return false;
}
if (IS_CSKY_V2 (mach_flag)
{
SET_ERROR_INTEGER (ERROR_FREG_OVER_RANGE, reg);
}
- return FALSE;
+ return false;
}
/* TODO: recognize vreg or freg. */
if (reg > 31)
SET_ERROR_INTEGER (ERROR_VREG_OVER_RANGE, reg);
}
csky_insn.val[csky_insn.idx++] = reg;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
parse_ldst_imm (char **oper, struct csky_opcode_info *op ATTRIBUTE_UNUSED,
struct operand *oprnd)
{
if (**oper == '\0' || **oper == ')')
{
csky_insn.val[csky_insn.idx++] = 0;
- return TRUE;
+ return true;
}
expressionS e;
{
/* Not a constant. */
SET_ERROR_STRING(ERROR_UNDEFINE, (void *)"Operand format is error. eg. \"ld rz, (rx, n)\"");
- return FALSE;
+ return false;
}
else if (e.X_add_number < 0 || e.X_add_number >= max)
{
/* Out of range. */
SET_ERROR_STRING(ERROR_IMM_OVERFLOW, NULL);
- return FALSE;
+ return false;
}
if ((e.X_add_number % (1 << shift)) != 0)
{
/* Not aligned. */
SET_ERROR_INTEGER (ERROR_OFFSET_UNALIGNED, ((unsigned long)1 << shift));
- return FALSE;
+ return false;
}
csky_insn.val[csky_insn.idx++] = e.X_add_number >> shift;
- return TRUE;
+ return true;
}
/* Parse the opcode part of an instruction. Fill in the csky_insn
state and return true on success, false otherwise. */
-static bfd_boolean
+static bool
parse_opcode (char *str)
{
#define IS_OPCODE32F(a) (*(a - 2) == '3' && *(a - 1) == '2')
#define IS_OPCODE16F(a) (*(a - 2) == '1' && *(a - 1) == '6')
/* TRUE if this opcode has a suffix, like 'lrw.h'. */
- unsigned int has_suffix = FALSE;
+ unsigned int has_suffix = false;
unsigned int nlen = 0;
char *opcode_end;
char name[OPCODE_MAX_LEN + 1];
if (IS_CSKY_V2 (mach_flag)
&& *opcode_end == '.' && !has_suffix)
{
- has_suffix = TRUE;
+ has_suffix = true;
if (IS_OPCODE32F (opcode_end))
{
csky_insn.flag_force = INSN_OPCODE32F;
name);
if (csky_insn.macro == NULL && csky_insn.opcode == NULL)
- return FALSE;
- return TRUE;
+ return false;
+ return true;
}
/* Main dispatch routine to parse operand OPRND for opcode OP from string
*OPER. */
-static bfd_boolean
+static bool
get_operand_value (struct csky_opcode_info *op,
char **oper, struct operand *oprnd)
{
SET_ERROR_STRING ((oprnd->type == OPRND_TYPE_BRACKET
? ERROR_MISSING_LBRACKET
: ERROR_MISSING_LANGLE_BRACKETS), NULL);
- return FALSE;
+ return false;
}
/* If the oprnd2 is an immediate, it can not be parsed
SET_ERROR_STRING ((oprnd->type == OPRND_TYPE_BRACKET
? ERROR_MISSING_RBRACKET
: ERROR_MISSING_RANGLE_BRACKETS), NULL);
- return FALSE;
+ return false;
}
if (!get_operand_value (op, oper, &soprnd->subs[0]))
{
*s = rc;
- return FALSE;
+ return false;
}
if (**oper == ',')
*oper += 1;
else if (**oper != '\0')
{
SET_ERROR_STRING (ERROR_MISSING_COMMA, NULL);
- return FALSE;
+ return false;
}
if (!get_operand_value (op, oper, &soprnd->subs[1]))
{
*s = rc;
- return FALSE;
+ return false;
}
*s = rc;
*oper += 1;
- return TRUE;
+ return true;
}
switch (oprnd->type)
if (reg == -1)
{
SET_ERROR_STRING (ERROR_GREG_ILLEGAL, NULL);
- return FALSE;
+ return false;
}
else if ((oprnd->type == OPRND_TYPE_GREG0_7 && reg > 7)
|| (oprnd->type == OPRND_TYPE_GREG0_15 && reg > 15))
{
SET_ERROR_INTEGER (ERROR_REG_OVER_RANGE, reg);
- return FALSE;
+ return false;
}
*oper += len;
csky_insn.val[csky_insn.idx++] = reg;
- return TRUE;
+ return true;
}
case OPRND_TYPE_REGnsplr:
{
&& (reg == V1_REG_SP || reg == V1_REG_LR)))
{
SET_ERROR_STRING (ERROR_REG_OVER_RANGE, reg);
- return FALSE;
+ return false;
}
csky_insn.val[csky_insn.idx++] = reg;
*oper += len;
- return TRUE;;
+ return true;;
}
case OPRND_TYPE_REGnr4_r7:
{
*oper += 1;
reg = csky_get_reg_val (*oper, &len);
if (reg == -1 || (reg <= 7 && reg >= 4))
- return FALSE;
+ return false;
csky_insn.val[csky_insn.idx++] = reg;
*oper += len;
if (**oper == ')')
*oper += 1;
- return TRUE;;
+ return true;;
}
case OPRND_TYPE_REGr4_r7:
if (memcmp (*oper, "r4-r7", sizeof ("r4-r7") - 1) == 0)
{
*oper += sizeof ("r4-r7") - 1;
csky_insn.val[csky_insn.idx++] = 0;
- return TRUE;
+ return true;
}
SET_ERROR_STRING (ERROR_OPCODE_ILLEGAL, NULL);
- return FALSE;
+ return false;
case OPRND_TYPE_IMM_LDST:
return parse_ldst_imm (oper, op, oprnd);
case OPRND_TYPE_IMM_FLDST:
&& (op->opcode & 0xffff0000) != 0)
{
SET_ERROR_STRING (ERROR_OPCODE_ILLEGAL, NULL);
- return FALSE;
+ return false;
}
*oper = parse_exp (*oper, &csky_insn.e1);
if (csky_insn.e1.X_op == O_constant)
if (csky_insn.e1.X_add_number & 0x7)
{
SET_ERROR_STRING (ERROR_JMPIX_OVER_RANGE, NULL);
- return FALSE;
+ return false;
}
csky_insn.val[csky_insn.idx++]
= (csky_insn.e1.X_add_number >> 3) - 2;
}
- return TRUE;
+ return true;
case OPRND_TYPE_IMM4b:
return is_imm_within_range (oper, 0, 15);
case OPRND_TYPE_IMM5b:
str_hash_find (csky_opcodes_hash, name);
csky_insn.val[csky_insn.idx - 1] = 1 << val;
}
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case OPRND_TYPE_IMM5b_1_31:
return is_imm_within_range (oper, 1, 31);
return log != -1;
}
else
- return FALSE;
+ return false;
/* This type for "mgeni" in csky v1 ISA. */
case OPRND_TYPE_IMM5b_7_31_POWER:
return log != -1;
}
else
- return FALSE;
+ return false;
case OPRND_TYPE_IMM5b_LS:
return is_imm_within_range (oper,
{
int i = csky_insn.idx - 1;
csky_insn.val[i] = 32 - csky_insn.val[i];
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
case OPRND_TYPE_IMM5b_BMASKI:
csky_insn.opcode = (struct csky_opcode *)
str_hash_find (csky_opcodes_hash, op_movi);
if (csky_insn.opcode == NULL)
- return FALSE;
+ return false;
csky_insn.val[csky_insn.idx - 1] = (1 << mask_val) - 1;
- return TRUE;
+ return true;
}
}
- return TRUE;
+ return true;
case OPRND_TYPE_IMM5b_VSH:
/* For vshri.T and vshli.T. */
val = (val << 1) | (val >> 4);
val &= 0x1f;
csky_insn.val[csky_insn.idx - 1] = val;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
case OPRND_TYPE_IMM8b_BMASKI:
/* For csky v2 bmask, which will transfer to 16bits movi. */
if (is_imm_within_range (oper, 1, 8))
{
unsigned int mask_val = csky_insn.val[csky_insn.idx - 1];
csky_insn.val[csky_insn.idx - 1] = (1 << mask_val) - 1;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
case OPRND_TYPE_OIMM4b:
return is_oimm_within_range (oper, 1, 16);
case OPRND_TYPE_OIMM5b:
}
else imm--;
csky_insn.val[csky_insn.idx - 1] = imm;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
/* For csky v2 bmask inst. */
case OPRND_TYPE_OIMM5b_BMASKI:
{
int mask_val = csky_insn.val[csky_insn.idx - 1];
if (mask_val + 1 == 0)
- return TRUE;
+ return true;
if (mask_val > 0 && mask_val < 16)
{
const char *op_movi = "movi";
csky_insn.opcode = (struct csky_opcode *)
str_hash_find (csky_opcodes_hash, op_movi);
if (csky_insn.opcode == NULL)
- return FALSE;
+ return false;
csky_insn.val[csky_insn.idx - 1] = (1 << (mask_val + 1)) - 1;
- return TRUE;
+ return true;
}
}
- return TRUE;
+ return true;
case OPRND_TYPE_IMM7b:
return is_imm_within_range (oper, 0, 127);
case OPRND_TYPE_IMM8b:
{
*oper = new_oper;
csky_insn.val[csky_insn.idx++] = e.X_add_number;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case OPRND_TYPE_IMM16b_MOVIH:
case OPRND_TYPE_IMM16b_ORI:
}
input_line_pointer = save;
*oper = parse_exp (curr, &csky_insn.e1);
- return TRUE;
+ return true;
}
case OPRND_TYPE_PSR_BITS_LIST:
{
- int ret = TRUE;
+ int ret = true;
if (csky_insn.number == 0)
- ret = FALSE;
+ ret = false;
else
{
csky_insn.val[csky_insn.idx] = 0;
*oper += 1;
if (!is_psr_bit (oper))
{
- ret = FALSE;
+ ret = false;
break;
}
}
else
- ret = FALSE;
+ ret = false;
if (ret && IS_CSKY_V1 (mach_flag)
&& csky_insn.val[csky_insn.idx] > 8)
- ret = FALSE;
+ ret = false;
}
if (!ret)
SET_ERROR_STRING (ERROR_OPERANDS_ILLEGAL, csky_insn.opcode_end);
{
*oper += strlen (round_mode[i]);
csky_insn.val[csky_insn.idx++] = i;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case OPRND_TYPE_REGLIST_COMMA:
if (**oper != '(')
{
SET_ERROR_STRING (ERROR_MISSING_LBRACKET, NULL);
- return FALSE;
+ return false;
}
*oper += 1;
reg = csky_get_reg_val (*oper, &len);
if (reg == -1)
{
SET_ERROR_STRING (ERROR_EXP_GREG, NULL);
- return FALSE;
+ return false;
}
*oper += len;
if (**oper != ')')
{
SET_ERROR_STRING (ERROR_MISSING_RBRACKET, NULL);
- return FALSE;
+ return false;
}
*oper += 1;
csky_insn.val[csky_insn.idx++] = reg;
- return TRUE;
+ return true;
}
case OPRND_TYPE_REGsp:
return is_reg_sp (oper);
case OPRND_TYPE_OFF16b:
*oper = parse_rt (*oper, 1, &csky_insn.e1, -1);
csky_insn.val[csky_insn.idx++] = 0;
- return TRUE;
+ return true;
case OPRND_TYPE_LABEL_WITH_BRACKET:
case OPRND_TYPE_CONSTANT:
case OPRND_TYPE_ELRW_CONSTANT:
else
csky_insn.val[csky_insn.idx++] = NEED_OUTPUT_LITERAL;
*oper = parse_rt (*oper, 0, &csky_insn.e1, -1);
- return TRUE;
+ return true;
case OPRND_TYPE_FCONSTANT:
*oper = parse_rtf (*oper, 0, &csky_insn.e1);
- return TRUE;
+ return true;
case OPRND_TYPE_SFLOAT:
case OPRND_TYPE_DFLOAT:
*oper = parse_fexp (*oper, &csky_insn.e1, 1, &dbnum);
if (csky_insn.e1.X_op == O_absent)
- return FALSE;
+ return false;
/* Convert the representation from IEEE double to the 13-bit
encoding used internally for fmovis and fmovid. */
if ((dbnum & 0x00000fffffffffffULL) || imm4 < 0 || imm4 > 15)
{
csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL);
- return FALSE;
+ return false;
}
imm8 = (dbnum & 0x000ff00000000000ULL) >> 44;
csky_insn.e1.X_add_number
| ((imm8 & 0xf0) << 17)
| ((imm4 & 0xf) << 16)
| ((dbnum & 0x8000000000000000ULL) >> 43));
- return TRUE;
+ return true;
}
case OPRND_TYPE_HFLOAT_FMOVI:
case OPRND_TYPE_SFLOAT_FMOVI:
*oper = parse_fexp (*oper, &csky_insn.e1, 1, &dbnum);
if (csky_insn.e1.X_op == O_absent)
- return FALSE;
+ return false;
/* Convert the representation from IEEE double to the 13-bit
encoding used internally for fmovis and fmovid. */
if ((dbnum & 0x00000fffffffffffULL) || imm4 < 0 || imm4 > 15)
{
csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL);
- return TRUE;
+ return true;
}
imm8 = (dbnum & 0x000ff00000000000ULL) >> 44;
sign = (dbnum & 0x8000000000000000ULL) >> 58;
| ((imm8 & 0xfc) << 18)
| ((imm4 & 0xf) << 16)
| sign);
- return TRUE;
+ return true;
}
/* For grs v2. */
case OPRND_TYPE_IMM_OFF18b:
*oper = parse_exp (*oper, &csky_insn.e1);
- return TRUE;
+ return true;
case OPRND_TYPE_BLOOP_OFF4b:
*oper = parse_exp (*oper, &csky_insn.e2);
if (csky_insn.e2.X_op == O_symbol)
{
csky_insn.opcode_end = *oper;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
case OPRND_TYPE_BLOOP_OFF12b:
case OPRND_TYPE_OFF10b:
if (csky_insn.e1.X_op == O_symbol)
{
csky_insn.opcode_end = *oper;
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
/* For xtrb0(1)(2)(3) and div in csky v1 ISA. */
case OPRND_TYPE_REG_r1a:
{
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The first operand must be register r1.");
- return FALSE;
+ return false;
}
if (reg != 1)
- mov_r1_after = TRUE;
+ mov_r1_after = true;
*oper += len;
csky_insn.opcode_end = *oper;
csky_insn.val[csky_insn.idx++] = reg;
- return TRUE;
+ return true;
}
case OPRND_TYPE_REG_r1b:
{
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The second operand must be register r1.");
- return FALSE;
+ return false;
}
if (reg != 1)
{
unsigned int mov_insn = CSKYV1_INST_MOV_R1_RX;
mov_insn |= reg << 4;
- mov_r1_before = TRUE;
+ mov_r1_before = true;
csky_insn.output = frag_more (2);
dwarf2_emit_insn (0);
md_number_to_chars (csky_insn.output, mov_insn, 2);
*oper += len;
csky_insn.opcode_end = *oper;
csky_insn.val[csky_insn.idx++] = reg;
- return TRUE;
+ return true;
}
case OPRND_TYPE_DUMMY_REG:
{
if (reg == -1)
{
SET_ERROR_STRING (ERROR_GREG_ILLEGAL, NULL);
- return FALSE;
+ return false;
}
if (reg != csky_insn.val[0])
{
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The second register must be the same as the first.");
- return FALSE;
+ return false;
}
*oper += len;
csky_insn.opcode_end = *oper;
csky_insn.val[csky_insn.idx++] = reg;
- return TRUE;
+ return true;
}
case OPRND_TYPE_2IN1_DUMMY:
{
if (reg == -1)
{
SET_ERROR_STRING (ERROR_GREG_ILLEGAL, NULL);
- return FALSE;
+ return false;
}
/* dummy reg's real type should be same with first operand. */
if (op->oprnd.oprnds[0].type == OPRND_TYPE_GREG0_15)
else if (op->oprnd.oprnds[0].type == OPRND_TYPE_GREG0_7)
max = 7;
else
- return FALSE;
+ return false;
if (reg < min || reg > max)
- return FALSE;
+ return false;
csky_insn.val[csky_insn.idx++] = reg;
/* if it is the last operands. */
if (csky_insn.idx > 2)
else if (csky_insn.val[0] == csky_insn.val[2])
csky_insn.val[2] = 0;
else
- return FALSE;
+ return false;
}
*oper += len;
csky_insn.opcode_end = *oper;
- return TRUE;
+ return true;
}
case OPRND_TYPE_DUP_GREG0_7:
case OPRND_TYPE_DUP_GREG0_15:
else
SET_ERROR_STRING (ERROR_REG_FORMAT,
"The register must be r0-r15");
- return FALSE;
+ return false;
}
if (reg > max_reg)
{
SET_ERROR_STRING (ERROR_REG_OVER_RANGE, reg);
- return FALSE;
+ return false;
}
reg |= reg << shift_num;
*oper += len;
csky_insn.opcode_end = *oper;
csky_insn.val[csky_insn.idx++] = reg;
- return TRUE;
+ return true;
}
case OPRND_TYPE_CONST1:
*oper = parse_exp (*oper, &csky_insn.e1);
{
csky_insn.opcode_end = *oper;
if (csky_insn.e1.X_add_number != 1)
- return FALSE;
+ return false;
csky_insn.val[csky_insn.idx++] = 1;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
case OPRND_TYPE_UNCOND10b:
case OPRND_TYPE_UNCOND16b:
*oper = parse_exp (*oper, &csky_insn.e1);
if (csky_insn.e1.X_op == O_constant)
- return FALSE;
+ return false;
input_line_pointer = *oper;
csky_insn.opcode_end = *oper;
csky_insn.relax.max = UNCD_DISP16_LEN;
csky_insn.relax.var = UNCD_DISP10_LEN;
csky_insn.relax.subtype = UNCD_DISP10;
csky_insn.val[csky_insn.idx++] = 0;
- return TRUE;
+ return true;
case OPRND_TYPE_COND10b:
case OPRND_TYPE_COND16b:
*oper = parse_exp (*oper, &csky_insn.e1);
if (csky_insn.e1.X_op == O_constant)
- return FALSE;
+ return false;
input_line_pointer = *oper;
csky_insn.opcode_end = *oper;
/* CK801 doesn't have 32-bit bt/bf insns; relax to a short
csky_insn.relax.subtype = COND_DISP10;
}
csky_insn.val[csky_insn.idx++] = 0;
- return TRUE;
+ return true;
case OPRND_TYPE_JCOMPZ:
*oper = parse_exp (*oper, &csky_insn.e1);
if (csky_insn.e1.X_op == O_constant)
- return FALSE;
+ return false;
input_line_pointer = *oper;
csky_insn.opcode_end = *oper;
csky_insn.relax.max = JCOMPZ_DISP32_LEN;
csky_insn.relax.subtype = JCOMPZ_DISP16;
csky_insn.max = JCOMPZ_DISP32_LEN;
csky_insn.val[csky_insn.idx++] = 0;
- return TRUE;
+ return true;
case OPRND_TYPE_JBTF:
*oper = parse_exp (*oper, &csky_insn.e1);
input_line_pointer = *oper;
csky_insn.relax.subtype = C (COND_JUMP_S, 0);
csky_insn.val[csky_insn.idx++] = 0;
csky_insn.max = C32_LEN_S + 2;
- return TRUE;
+ return true;
case OPRND_TYPE_JBR:
*oper = parse_exp (*oper, &csky_insn.e1);
input_line_pointer = *oper;
csky_insn.relax.subtype = C (UNCD_JUMP_S, 0);
csky_insn.val[csky_insn.idx++] = 0;
csky_insn.max = U32_LEN_S + 2;
- return TRUE;
+ return true;
case OPRND_TYPE_JBSR:
if (do_force2bsr)
*oper = parse_exp (*oper, &csky_insn.e1);
input_line_pointer = *oper;
csky_insn.opcode_end = *oper;
csky_insn.val[csky_insn.idx++] = 0;
- return TRUE;
+ return true;
case OPRND_TYPE_REGLIST_DASH_COMMA:
return is_reglist_dash_comma_legal (oper, oprnd);
if (e.X_add_number > 31)
{
SET_ERROR_STRING (ERROR_IMM_OVERFLOW, NULL);
- return FALSE;
+ return false;
}
csky_insn.val[csky_insn.idx++] = e.X_add_number;
if (oprnd->type == OPRND_TYPE_LSB2SIZE)
if (csky_insn.val[csky_insn.idx - 1] > csky_insn.val[csky_insn.idx - 2])
{
SET_ERROR_STRING (ERROR_IMM_OVERFLOW, NULL);
- return FALSE;
+ return false;
}
csky_insn.val[csky_insn.idx - 2] -= e.X_add_number;
}
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
case OPRND_TYPE_AREG_WITH_LSHIFT:
return is_reg_lshift_illegal (oper, 0);
unsigned int val = csky_insn.val[idx];
(*oper)++;
csky_insn.val[idx - 1] |= val << 4;
- return TRUE;
+ return true;
}
else
SET_ERROR_STRING (ERROR_MISSING_RSQUARE_BRACKETS, NULL);
else
SET_ERROR_STRING (ERROR_MISSING_LSQUARE_BRACKETS, NULL);
}
- return FALSE;
+ return false;
default:
break;
/* error code. */
}
- return FALSE;
+ return false;
}
/* Subroutine of parse_operands. */
-static bfd_boolean
+static bool
parse_operands_op (char *str, struct csky_opcode_info *op)
{
int i;
for (i = 0; i < OP_TABLE_NUM && op[i].operand_num != -2; i++)
{
- flag_pass = TRUE;
+ flag_pass = true;
csky_insn.idx = 0;
oper = str;
/* if operand_num = -1, it is a insn with a REGLIST type operand.i. */
{
/* The smaller err_num is more serious. */
SET_ERROR_INTEGER (ERROR_OPERANDS_NUMBER, op[i].operand_num);
- flag_pass = FALSE;
+ flag_pass = false;
continue;
}
else
{
SET_ERROR_STRING (ERROR_MISSING_COMMA, NULL);
- flag_pass = FALSE;
+ flag_pass = false;
break;
}
}
else if (!is_end_of_line[(unsigned char) *oper])
{
SET_ERROR_STRING (ERROR_BAD_END, NULL);
- flag_pass = FALSE;
+ flag_pass = false;
break;
}
else
{
/* Parse operands success, set opcode_idx. */
csky_insn.opcode_idx = i;
- return TRUE;
+ return true;
}
else
error_state.opnum = j + 1;
}
/* Parse operands in ALL tables end. */
- return FALSE;
+ return false;
}
/* Parse the operands according to operand type. */
-static bfd_boolean
+static bool
parse_operands (char *str)
{
char *oper = str;
if (parse_operands_op (oper, csky_insn.opcode->op16))
{
csky_insn.isize = 2;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
else if (csky_insn.flag_force == INSN_OPCODE32F
&& (csky_insn.opcode->isa_flag32 & isa_flag) != 0)
if (parse_operands_op (oper, csky_insn.opcode->op32))
{
csky_insn.isize = 4;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
else
{
&& parse_operands_op (oper, csky_insn.opcode->op16))
{
csky_insn.isize = 2;
- return TRUE;
+ return true;
}
if ((csky_insn.opcode->isa_flag32 & isa_flag) != 0
&& parse_operands_op (oper, csky_insn.opcode->op32))
{
csky_insn.isize = 4;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
}
-static bfd_boolean
+static bool
csky_generate_frags (void)
{
/* frag more relax reloc. */
csky_insn.opcode->reloc32);
}
}
- return TRUE;
+ return true;
}
/* Return the bits of VAL shifted according to MASK. The bits of MASK
return 0;
}
-static bfd_boolean
+static bool
csky_generate_insn (void)
{
int i = 0;
void
md_assemble (char *str)
{
- bfd_boolean must_check_literals = TRUE;
+ bool must_check_literals = true;
csky_insn.isize = 0;
csky_insn.idx = 0;
csky_insn.max = 0;
memset (csky_insn.val, 0, sizeof (int) * MAX_OPRND_NUM);
/* Initialize err_num. */
error_state.err_num = ERROR_NONE;
- mov_r1_before = FALSE;
- mov_r1_after = FALSE;
+ mov_r1_before = false;
+ mov_r1_after = false;
mapping_state (MAP_TEXT);
/* Tie dwarf2 debug info to every insn if set option --gdwarf2. */
{
unsigned int mov_insn = CSKYV1_INST_MOV_RX_R1;
mov_insn |= csky_insn.val[0];
- mov_r1_before = TRUE;
+ mov_r1_before = true;
csky_insn.output = frag_more (2);
dwarf2_emit_insn (0);
md_number_to_chars (csky_insn.output, mov_insn, 2);
/* Return true if the fix can be handled by GAS, false if it must
be passed through to the linker. */
-bfd_boolean
+bool
csky_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
return;
}
-static bfd_boolean
+static bool
get_macro_reg_vals (int *reg1, int *reg2, int *reg3)
{
int nlen;
if (*s != ',')
{
csky_show_error (ERROR_MISSING_COMMA, 0, NULL, NULL);
- return FALSE;
+ return false;
}
s++;
*reg2 = csky_get_reg_val (s, &nlen);
if (*s != ',')
{
csky_show_error (ERROR_MISSING_COMMA, 0, NULL, NULL);
- return FALSE;
+ return false;
}
s++;
*reg3 = csky_get_reg_val (s, &nlen);
if (*s != '\0')
{
csky_show_error (ERROR_BAD_END, 0, s, NULL);
- return FALSE;
+ return false;
}
if (*reg1 == -1 || *reg2 == -1 || *reg3 == -1)
{
as_bad (_("register number out of range"));
- return FALSE;
+ return false;
}
if (*reg1 != *reg2)
{
as_bad (_("dest and source1 must be the same register"));
- return FALSE;
+ return false;
}
if (*reg1 >= 15 || *reg3 >= 15)
{
as_bad (_("64-bit operator src/dst register must be less than 15"));
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* addc64 rx, rx, ry -> cmplt rx, rx, addc rx, ry, addc rx+1, ry+1. */
/* The following are worker functions for C-SKY v1. */
-bfd_boolean
+bool
v1_work_lrw (void)
{
int reg;
}
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v1_work_fpu_fo (void)
{
int i = 0;
md_assemble (buff);
sprintf (buff, "cpwir r%d", greg);
md_assemble (buff);
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
v1_work_fpu_fo_fc (void)
{
int i = 0;
sprintf (buff, "cprc");
md_assemble (buff);
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
v1_work_fpu_write (void)
{
int greg;
sprintf (buff, "cpwgr r%d,cpr%d", greg, freg);
md_assemble (buff);
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
v1_work_fpu_read (void)
{
int greg;
sprintf (buff, "cprgr r%d,cpr%d", greg, freg);
md_assemble (buff);
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
v1_work_fpu_writed (void)
{
int greg;
if (greg & 0x1)
{
as_bad (_("even register number required"));
- return FALSE;
+ return false;
}
/* Now get greg and freg, we can write instruction to floating unit. */
if (target_big_endian)
else
sprintf (buff, "cpwgr r%d,cpr%d", greg+1, freg + 1);
md_assemble (buff);
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
v1_work_fpu_readd (void)
{
int greg;
if (greg & 0x1)
{
as_bad (_("even register number required"));
- return FALSE;
+ return false;
}
/* Now get greg and freg, we can write instruction to floating unit. */
if (target_big_endian)
sprintf (buff, "cprgr r%d,cpr%d", greg+1, freg + 1);
md_assemble (buff);
- return FALSE;
+ return false;
}
/* The following are for csky pseudo handling. */
-bfd_boolean
+bool
v1_work_jbsr (void)
{
csky_insn.output = frag_more (2);
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
/* The following are worker functions for csky v2 instruction handling. */
/* For nie/nir/ipush/ipop. */
-bfd_boolean
+bool
v2_work_istack (void)
{
if (!do_intr_stack)
{
csky_show_error (ERROR_OPCODE_ILLEGAL, 0, NULL, NULL);
- return FALSE;
+ return false;
}
csky_insn.output = frag_more (csky_insn.isize);
csky_insn.inst = csky_insn.opcode->op16[0].opcode;
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_btsti (void)
{
if (!do_extend_lrw
|| IS_CSKY_ARCH_801 (mach_flag)))
{
csky_show_error (ERROR_OPCODE_ILLEGAL, 0, NULL, NULL);
- return FALSE;
+ return false;
}
if (!do_extend_lrw && csky_insn.isize == 2)
csky_insn.isize = 4;
csky_generate_insn ();
/* Write inst to frag. */
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_addi (void)
{
csky_insn.isize = 2;
{
csky_show_error (ERROR_OPERANDS_ILLEGAL, 0,
csky_insn.opcode_end, NULL);
- return FALSE;
+ return false;
}
}
else if (csky_insn.number == 3)
{
csky_show_error (ERROR_OPERANDS_ILLEGAL, 0,
(char *)csky_insn.opcode_end, NULL);
- return FALSE;
+ return false;
}
}
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_subi (void)
{
csky_insn.isize = 2;
{
csky_show_error (ERROR_OPERANDS_ILLEGAL, 0,
(char *)csky_insn.opcode_end, NULL);
- return FALSE;
+ return false;
}
}
else if (csky_insn.number == 3)
{
csky_show_error (ERROR_OPERANDS_ILLEGAL, 0,
(char *)csky_insn.opcode_end, NULL);
- return FALSE;
+ return false;
}
}
csky_insn.output = frag_more (csky_insn.isize);
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_add_sub (void)
{
if (csky_insn.number == 3
csky_show_error (ERROR_REG_OVER_RANGE, 2, NULL, NULL);
}
}
- return FALSE;
+ return false;
}
/* sub rz, rx. */
/* Generate relax or reloc if necessary. */
csky_generate_insn ();
/* Write inst to frag. */
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_rotlc (void)
{
const char *name = "addc";
csky_generate_insn ();
/* Write inst to frag. */
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_bgeni (void)
{
const char *name = NULL;
csky_generate_insn ();
/* Write inst to frag. */
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_not (void)
{
const char *name = "nor";
csky_generate_insn ();
/* Write inst to frag. */
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_jbtf (void)
{
if (csky_insn.e1.X_add_symbol == NULL || csky_insn.e1.X_op == O_constant)
{
csky_show_error (ERROR_UNDEFINE, 0, (void *)"operand is invalid", NULL);
- return FALSE;
+ return false;
}
if (IS_CSKY_ARCH_801 (mach_flag))
}
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_jbr (void)
{
if (csky_insn.e1.X_add_symbol == NULL || csky_insn.e1.X_op == O_constant)
{
csky_show_error (ERROR_UNDEFINE, 0, (void *)"operand is invalid", NULL);
- return FALSE;
+ return false;
}
if (do_long_jump
}
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
#define SIZE_V2_MOVI16(x) ((addressT)x <= 0xff)
#define SIZE_V2_MOVI32(x) ((addressT)x <= 0xffff)
#define SIZE_V2_MOVIH(x) ((addressT)x <= 0xffffffff && (((addressT)x & 0xffff) == 0))
-bfd_boolean
+bool
v2_work_lrw (void)
{
int reg = csky_insn.val[0];
if (is_done)
{
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
if (output_literal)
{
csky_show_error (ERROR_UNDEFINE, 0,
(void *)"The register is out of range.", NULL);
- return FALSE;
+ return false;
}
csky_insn.isize = 2;
csky_insn.output = frag_more (2);
}
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_lrsrsw (void)
{
int reg = csky_insn.val[0];
break;
}
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_jbsr (void)
{
if (do_force2bsr
}
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_jsri (void)
{
/* dump literal. */
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
csky_insn.max = 8;
}
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_movih (void)
{
int rz = csky_insn.val[0];
if (csky_insn.e1.X_unsigned == 1 && csky_insn.e1.X_add_number > 0xffff)
{
csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL);
- return FALSE;
+ return false;
}
else if (csky_insn.e1.X_unsigned == 0 && csky_insn.e1.X_add_number < 0)
{
csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL);
- return FALSE;
+ return false;
}
else
csky_insn.inst |= (csky_insn.e1.X_add_number & 0xffff);
{
void *arg = (void *)"the second operand must be \"SYMBOL >> 16\"";
csky_show_error (ERROR_UNDEFINE, 0, arg, NULL);
- return FALSE;
+ return false;
}
}
csky_insn.isize = 4;
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_ori (void)
{
int rz = csky_insn.val[0];
else
{
csky_show_error (ERROR_IMM_OVERFLOW, 3, NULL, NULL);
- return FALSE;
+ return false;
}
}
else if (csky_insn.e1.X_op == O_bit_and)
{
void *arg = (void *)"the third operand must be \"SYMBOL & 0xffff\"";
csky_show_error (ERROR_UNDEFINE, 0, arg, NULL);
- return FALSE;
+ return false;
}
}
csky_insn.isize = 4;
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
/* Helper function to encode a single/double floating point constant
rounding when converting to the smaller format, just an error if there
is excess precision or the number is too small/large to be represented. */
-bfd_boolean
+bool
float_work_fmovi (void)
{
int rx = csky_insn.val[0];
csky_insn.output = frag_more (4);
csky_insn.isize = 4;
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
/* Like float_work_fmovi, but for FPUV3 fmovi.16, fmovi.32 and fmovi.64
instructions. */
-bfd_boolean
+bool
float_work_fpuv3_fmovi (void)
{
int rx = csky_insn.val[0];
if (imm8 > 255)
{
csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL);
- return FALSE;
+ return false;
}
/* imm8 store at bit [25:20] and [9:8]. */
csky_insn.output = frag_more(4);
csky_insn.isize = 4;
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
dsp_work_bloop (void)
{
int reg = csky_insn.val[0];
}
csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
float_work_fpuv3_fstore(void)
{
/* Generate relax or reloc if necessary. */
csky_insn.isize);
- return TRUE;
+ return true;
}
-bfd_boolean
+bool
v2_work_addc (void)
{
int reg1;
csky_insn.inst,
csky_insn.isize);
- return TRUE;
+ return true;
}
/* The following are for assembler directive handling. */
expressionS *,
bfd_reloc_code_real_type);
extern int csky_force_relocation (fixS *);
-extern bfd_boolean csky_fix_adjustable (fixS *);
+extern bool csky_fix_adjustable (fixS *);
extern void csky_cfi_frame_initial_instructions (void);
extern int tc_csky_regname_to_dw2regnum (char *);
extern long csky_relax_frag (segT, fragS *, long);
/* TRUE if instruction swapping warnings should be inhibited.
--nowarnswap. */
-static bfd_boolean flag_warn_suppress_instructionswap;
+static bool flag_warn_suppress_instructionswap;
/* TRUE if instruction packing should be performed when --gstabs is specified.
--gstabs-packing, --no-gstabs-packing. */
-static bfd_boolean flag_allow_gstabs_packing = 1;
+static bool flag_allow_gstabs_packing = 1;
/* Local functions. */
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
void
unsigned long current_position;
unsigned long symbol_position;
unsigned long value;
- bfd_boolean found_symbol;
+ bool found_symbol;
/* Calculate the address of the current instruction
and the address of the symbol. Do this by summing
the offsets of previous frags until we reach the
frag containing the symbol, and the current frag. */
sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
- found_symbol = FALSE;
+ found_symbol = false;
current_position = frag_now_fix_octets ();
symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
current_position += f->fr_fix + f->fr_offset;
if (f == sym_frag)
- found_symbol = TRUE;
+ found_symbol = true;
if (! found_symbol)
symbol_position += f->fr_fix + f->fr_offset;
}
}
-bfd_boolean
+bool
d10v_fix_adjustable (fixS *fixP)
{
/* We need the symbol name for the VTABLE entries. */
#define tc_frob_label(sym) d10v_frob_label (sym)
#define tc_fix_adjustable(FIX) d10v_fix_adjustable(FIX)
-bfd_boolean d10v_fix_adjustable (struct fix *);
+bool d10v_fix_adjustable (struct fix *);
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
void
we are not optimizing, then we have been asked to produce
an error about such constructs. For the purposes of this
test, subroutine calls are considered to be branches. */
- write_1_short (opcode1, insn1, fx->next, FALSE);
+ write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
/* We must treat repeat instructions likewise, since the
following instruction has to be separate from the repeat
in order to be repeated. */
- write_1_short (opcode1, insn1, fx->next, FALSE);
+ write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
else if (prev_left_kills_right_p)
{
/* The left instruction kills the right slot, so we
must leave it empty. */
- write_1_short (opcode1, insn1, fx->next, FALSE);
+ write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
else if (opcode1->op->unit == IU)
/* Case 103810 is a request from Mitsubishi that opcodes
with EITHER_BUT_PREFER_MU should not be executed in
reverse sequential order. */
- write_1_short (opcode1, insn1, fx->next, FALSE);
+ write_1_short (opcode1, insn1, fx->next, false);
return 1;
}
this alignment request. The alignment of the current frag
can be changed under our feet, for example by a .ascii
directive in the source code. cf testsuite/gas/d30v/reloc.s */
- d30v_cleanup (FALSE);
+ d30v_cleanup (false);
if (pfill == NULL)
{
if (label != NULL)
{
symbolS *sym;
- int label_seen = FALSE;
+ int label_seen = false;
struct frag *old_frag;
valueT old_value;
valueT new_value;
if (symbol_get_frag (sym) == old_frag
&& S_GET_VALUE (sym) == old_value)
{
- label_seen = TRUE;
+ label_seen = true;
symbol_set_frag (sym, frag_now);
S_SET_VALUE (sym, new_value);
}
if ((prev_insn != -1) && prev_seg
&& ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
- d30v_cleanup (FALSE);
+ d30v_cleanup (false);
if (d30v_current_align < 3)
d30v_align (3, NULL, d30v_last_label);
/* If two instructions are present and we already have one saved,
then first write it out. */
- d30v_cleanup (FALSE);
+ d30v_cleanup (false);
/* Assemble first instruction and save it. */
prev_insn = do_assemble (str, &prev_opcode, 1, 0);
of NOPs for us. */
if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
- d30v_cleanup (FALSE);
+ d30v_cleanup (false);
else
{
char *f;
if (prev_insn != -1)
- d30v_cleanup (TRUE);
+ d30v_cleanup (true);
else
{
f = frag_more (8);
{
/* Can't parallelize, flush current instruction and add a
sequential NOP. */
- write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
+ write_1_short (&opcode, (long) insn, fixups->next->next, true);
/* Make the previous instruction the current one. */
extype = EXEC_UNKNOWN;
{
if (extype != EXEC_UNKNOWN)
as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
- d30v_cleanup (FALSE);
+ d30v_cleanup (false);
write_long (&opcode, insn, fixups);
prev_insn = -1;
}
subseg_set (seg, subseg);
prev_insn = -1;
if (use_sequential)
- prev_mul32_p = FALSE;
+ prev_mul32_p = false;
}
return 1;
c++;
if (*c == '.')
- d30v_cleanup (FALSE);
+ d30v_cleanup (false);
}
static void
d30v_frob_label (symbolS *lab)
{
/* Emit any pending instructions. */
- d30v_cleanup (FALSE);
+ d30v_cleanup (false);
/* Update the label's address with the current output pointer. */
symbol_set_frag (lab, frag_now);
#define md_number_to_chars number_to_chars_bigendian
int d30v_cleanup (int);
-#define md_cleanup() d30v_cleanup (FALSE)
+#define md_cleanup() d30v_cleanup (false)
#define TC_START_LABEL(STR, NUL_CHAR, NEXT_CHAR) \
- (NEXT_CHAR == ':' && d30v_cleanup (FALSE))
+ (NEXT_CHAR == ':' && d30v_cleanup (false))
void d30v_start_line (void);
#define md_start_line_hook() d30v_start_line ()
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
/* Write out big-endian. */
number_to_chars_bigendian (buf, val, n);
}
-bfd_boolean
+bool
md_dlx_fix_adjustable (fixS *fixP)
{
/* We need the symbol name for the VTABLE entries. */
extern void dlx_pop_insert (void);
extern int dlx_unrecognized_line (int);
-extern bfd_boolean md_dlx_fix_adjustable (struct fix *);
+extern bool md_dlx_fix_adjustable (struct fix *);
#define md_pop_insert() dlx_pop_insert ()
/* Flag to detect when switching to code section where insn alignment is
implied. */
-static bfd_boolean force_code_align = FALSE;
+static bool force_code_align = false;
static void
epiphany_elf_section_rtn (int i)
if (force_code_align)
{
do_align (1, NULL, 0, 0);
- force_code_align = FALSE;
+ force_code_align = false;
}
}
obj_elf_text (i);
do_align (1, NULL, 0, 0);
- force_code_align = FALSE;
+ force_code_align = false;
}
/* The target specific pseudo-ops which we support. */
/* Set the machine type. */
bfd_default_set_arch_mach (stdoutput, bfd_arch_epiphany, bfd_mach_epiphany32);
- literal_prefix_dollar_hex = TRUE;
+ literal_prefix_dollar_hex = true;
}
valueT
executable section specifier we set an internal flag to denote when
word alignment should be forced. */
if (flags & SEC_CODE)
- force_code_align = TRUE;
+ force_code_align = true;
return flags;
}
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
static symbolS * GOT_symbol;
-static inline bfd_boolean
+static inline bool
epiphany_PIC_related_p (symbolS *sym)
{
expressionS *exp;
if (! sym)
- return FALSE;
+ return false;
if (sym == GOT_symbol)
- return TRUE;
+ return true;
exp = symbol_get_value_expression (sym);
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
/* Return true if can adjust the reloc to be relative to its section
(such as .data) instead of relative to some symbol. */
-bfd_boolean
+bool
epiphany_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;
reloc_type = fixP->fx_r_type;
if (fixP->fx_addsy == NULL)
- return TRUE;
+ return true;
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
- return FALSE;
+ return false;
if (S_IS_WEAK (fixP->fx_addsy))
- return FALSE;
+ return false;
if (pic_code
&& (reloc_type == BFD_RELOC_EPIPHANY_SIMM24
|| reloc_type == BFD_RELOC_EPIPHANY_SIMM8
|| reloc_type == BFD_RELOC_EPIPHANY_HIGH
|| reloc_type == BFD_RELOC_EPIPHANY_LOW))
- return FALSE;
+ return false;
/* Since we don't use partial_inplace, we must not reduce symbols in
mergeable sections to their section symbol. */
if ((S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
void
#define MD_APPLY_SYM_VALUE(FIX) 0
#define tc_fix_adjustable(FIX) epiphany_fix_adjustable (FIX)
-extern bfd_boolean epiphany_fix_adjustable (struct fix *);
+extern bool epiphany_fix_adjustable (struct fix *);
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP,SEC)
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
/* Worker function for fr30_is_colon_insn(). */
return 0;
}
-bfd_boolean
+bool
fr30_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries. */
#define tc_fix_adjustable(FIX) fr30_fix_adjustable (FIX)
struct fix;
-extern bfd_boolean fr30_fix_adjustable (struct fix *);
+extern bool fr30_fix_adjustable (struct fix *);
#define tc_gen_reloc gas_cgen_tc_gen_reloc
#define NOP_KEEP 1 /* Keep these NOPS. */
#define NOP_DELETE 2 /* Delete these NOPS. */
-#define DO_COUNT TRUE
-#define DONT_COUNT FALSE
+#define DO_COUNT true
+#define DONT_COUNT false
/* A list of insns within a VLIW insn. */
struct vliw_insn_list
#endif
static unsigned long frv_mach = bfd_mach_frv;
-static bfd_boolean fr400_audio;
+static bool fr400_audio;
/* Flags to set in the elf header */
static flagword frv_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
{
cpu_flags = EF_FRV_CPU_FR405;
frv_mach = bfd_mach_fr400;
- fr400_audio = TRUE;
+ fr400_audio = true;
}
else if (strcmp (p, "fr400") == 0)
{
cpu_flags = EF_FRV_CPU_FR400;
frv_mach = bfd_mach_fr400;
- fr400_audio = FALSE;
+ fr400_audio = false;
}
else if (strcmp (p, "fr300") == 0)
frv_vliw_reset (& vliw, frv_mach, frv_flags);
}
-bfd_boolean
+bool
frv_md_fdpic_enabled (void)
{
return (frv_flags & EF_FRV_FDPIC) != 0;
int chain_num = 0;
static struct vliw_insn_list *
-frv_insert_vliw_insn (bfd_boolean count)
+frv_insert_vliw_insn (bool count)
{
struct vliw_insn_list *vliw_insn_list_entry;
struct vliw_chain *vliw_chain_entry;
struct vliw_insn_list *insert_before_insn)
{
- bfd_boolean pack_prev = FALSE;
+ bool pack_prev = false;
struct vliw_chain *return_me = NULL;
struct vliw_insn_list *prev_insn = NULL;
struct vliw_insn_list *curr_insn = vliw_to_split->insn_list;
Then don't set pack bit later. */
if (curr_insn->type != VLIW_LABEL_TYPE)
- pack_prev = TRUE;
+ pack_prev = true;
prev_insn = curr_insn;
curr_insn = curr_insn->next;
}
/* Return true if the target implements instruction INSN. */
-static bfd_boolean
+static bool
target_implements_insn_p (const CGEN_INSN *insn)
{
switch (frv_mach)
{
default:
/* bfd_mach_frv or generic. */
- return TRUE;
+ return true;
case bfd_mach_fr300:
case bfd_mach_frvsimple:
switch (operand->type)
{
case FRV_OPERAND_LABEL16:
- fixP->fx_pcrel = TRUE;
+ fixP->fx_pcrel = true;
return BFD_RELOC_FRV_LABEL16;
case FRV_OPERAND_LABEL24:
- fixP->fx_pcrel = TRUE;
+ fixP->fx_pcrel = true;
if (fixP->fx_cgen.opinfo != 0)
return fixP->fx_cgen.opinfo;
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
-bfd_boolean
+bool
frv_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;
#define TARGET_FORMAT (frv_md_fdpic_enabled () \
? "elf32-frvfdpic" : "elf32-frv")
-extern bfd_boolean frv_md_fdpic_enabled (void);
+extern bool frv_md_fdpic_enabled (void);
#define TARGET_BYTES_BIG_ENDIAN 1
#define tc_fix_adjustable(FIX) frv_fix_adjustable (FIX)
struct fix;
-extern bfd_boolean frv_fix_adjustable (struct fix *);
+extern bool frv_fix_adjustable (struct fix *);
/* When relaxing, we need to emit various relocs we otherwise wouldn't. */
#define TC_FORCE_RELOCATION(fix) frv_force_relocation (fix)
unsigned int b;
int f;
expressionS arg;
- bfd_boolean fixed = FALSE;
+ bool fixed = false;
unsigned int sc;
- bfd_boolean can_sc;
+ bool can_sc;
/* Drop leading whitespace. */
while (*str == ' ')
{
b |= 0x400 << FT32_FLD_RIMM_BIT;
op_end = parse_exp_save_ilp (op_end, &arg);
- fixed = TRUE;
+ fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
2,
break;
case FT32_FLD_K20:
op_end = parse_exp_save_ilp (op_end, &arg);
- fixed = TRUE;
+ fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
3,
break;
case FT32_FLD_PA:
op_end = parse_exp_save_ilp (op_end, &arg);
- fixed = TRUE;
+ fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
3,
break;
case FT32_FLD_AA:
op_end = parse_exp_save_ilp (op_end, &arg);
- fixed = TRUE;
+ fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
3,
break;
case FT32_FLD_K16:
op_end = parse_exp_save_ilp (op_end, &arg);
- fixed = TRUE;
+ fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
2,
op_end = parse_exp_save_ilp (op_end, &arg);
if (arg.X_add_number & 0x80)
arg.X_add_number ^= 0x7f00;
- fixed = TRUE;
+ fixed = true;
fix_new_exp (frag_now,
(output - frag_now->fr_literal),
2,
/* TC_FORCE_RELOCATION hook */
-static bfd_boolean
+static bool
relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
return generic_force_reloc (fix);
}
-bfd_boolean
+bool
ft32_allow_local_subtract (expressionS * left,
expressionS * right,
segT section)
{
/* If we are not in relaxation mode, subtraction is OK. */
if (!linkrelax)
- return TRUE;
+ return true;
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
- return TRUE;
+ return true;
if (left->X_add_symbol == right->X_add_symbol)
- return TRUE;
+ return true;
/* We have to assume that there may be instructions between the
two symbols and that relaxation may increase the distance between
them. */
- return FALSE;
+ return false;
}
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) ft32_allow_local_subtract (l, r, s)
-extern bfd_boolean ft32_allow_local_subtract (expressionS *,
- expressionS *,
- segT);
+extern bool ft32_allow_local_subtract (expressionS *, expressionS *, segT);
#define md_operand(x)
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
\f
#define OPTION_H_TICK_HEX (OPTION_MD_BASE)
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
/* Write out big-endian. */
symbolS *sym;
int status;
char *p = *s;
- bfd_boolean have_prefix;
+ bool have_prefix;
/* Skip whitespace before the number. */
while (*p == ' ' || *p == '\t')
num = S_GET_VALUE (sym);
/* Well, we don't really have one, but we do have a
register, so... */
- have_prefix = TRUE;
+ have_prefix = true;
}
else if (S_GET_SEGMENT (sym) == bfd_abs_section_ptr)
num = S_GET_VALUE (sym);
if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, pa11))
as_warn (_("could not update architecture and machine"));
}
- return TRUE;
+ return true;
}
else
- return FALSE;
+ return false;
}
/* Parse a condition for a fcmp instruction. Return the numerical
const char *error_message = "";
char *s, c, *argstart, *name, *save_s;
const char *args;
- int match = FALSE;
+ int match = false;
int comma = 0;
int cmpltr, nullif, flag, cond, need_cond, num;
int immediate_check = 0, pos = -1, len = -1;
/* End of arguments. */
case '\0':
if (*s == '\0')
- match = TRUE;
+ match = true;
break;
case '+':
&& !bfd_set_arch_mach (stdoutput, bfd_arch_hppa, insn->arch))
{
as_warn (_("could not update architecture and machine"));
- match = FALSE;
+ match = false;
}
failed:
/* Mark the fact that we found the .CALLINFO for the
current procedure. */
- callinfo_found = TRUE;
+ callinfo_found = true;
/* Iterate over the .CALLINFO arguments. */
while (!is_end_of_statement ())
as_bad (_("Missing .callinfo."));
}
demand_empty_rest_of_line ();
- within_entry_exit = TRUE;
+ within_entry_exit = true;
#ifdef OBJ_SOM
/* SOM defers building of unwind descriptors until the link phase.
as_bad (_("No .ENTRY for this .EXIT"));
else
{
- within_entry_exit = FALSE;
+ within_entry_exit = false;
process_exit ();
}
}
as_fatal (_("Nested procedures"));
/* Reset global variables for new procedure. */
- callinfo_found = FALSE;
- within_procedure = TRUE;
+ callinfo_found = false;
+ within_procedure = true;
/* Create another call_info structure. */
call_info = XNEW (struct call_info);
hppa_elf_mark_end_of_function ();
#endif
- within_procedure = FALSE;
+ within_procedure = false;
demand_empty_rest_of_line ();
pa_undefine_label ();
}
/* Load default values. */
spnum = 0;
sort = 0;
- loadable = TRUE;
- defined = TRUE;
- private = FALSE;
+ loadable = true;
+ defined = true;
+ private = false;
if (strcmp (space_name, "$TEXT$") == 0)
{
seg = pa_def_spaces[0].segment;
if (!is_end_of_statement ())
{
- print_errors = FALSE;
+ print_errors = false;
ptemp = input_line_pointer + 1;
/* First see if the space was specified as a number rather than
as a name. According to the PA assembly manual the rest of
else if ((strncasecmp (name, "unloadable", 10) == 0))
{
(void) restore_line_pointer (c);
- loadable = FALSE;
+ loadable = false;
}
else if ((strncasecmp (name, "notdefined", 10) == 0))
{
(void) restore_line_pointer (c);
- defined = FALSE;
+ defined = false;
}
else if ((strncasecmp (name, "private", 7) == 0))
{
(void) restore_line_pointer (c);
- private = TRUE;
+ private = true;
}
else
{
}
}
}
- print_errors = TRUE;
+ print_errors = true;
}
if (create_flag && seg == NULL)
|| current_templates->start->opcode_modifier.jump == JUMP_DWORD
|| current_templates->start->opcode_modifier.jump == JUMP_INTERSEGMENT)
{
- bfd_boolean jumpabsolute = FALSE;
+ bool jumpabsolute = false;
if (i.op[this_operand].regs
|| intel_state.base
|| intel_state.index
|| intel_state.is_mem > 1)
- jumpabsolute = TRUE;
+ jumpabsolute = true;
else
switch (intel_state.op_modifier)
{
case O_near_ptr:
if (intel_state.seg)
- jumpabsolute = TRUE;
+ jumpabsolute = true;
else
intel_state.is_mem = 1;
break;
if (intel_state.op_modifier == O_absent)
{
if (intel_state.is_indirect == 1)
- jumpabsolute = TRUE;
+ jumpabsolute = true;
break;
}
as_bad (_("cannot infer the segment part of the operand"));
return 0;
}
else if (S_GET_SEGMENT (intel_state.seg) == reg_section)
- jumpabsolute = TRUE;
+ jumpabsolute = true;
else
{
i386_operand_type types;
}
break;
default:
- jumpabsolute = TRUE;
+ jumpabsolute = true;
break;
}
if (jumpabsolute)
{
- i.jumpabsolute = TRUE;
+ i.jumpabsolute = true;
intel_state.is_mem |= 1;
}
}
unsigned char prefix[MAX_PREFIXES];
/* Register is in low 3 bits of opcode. */
- bfd_boolean short_form;
+ bool short_form;
/* The operand to a branch insn indicates an absolute branch. */
- bfd_boolean jumpabsolute;
+ bool jumpabsolute;
/* Extended states. */
enum
} xstate;
/* Has GOTPC or TLS relocation. */
- bfd_boolean has_gotpc_tls_reloc;
+ bool has_gotpc_tls_reloc;
/* RM and SIB are the modrm byte and the sib byte where the
addressing modes of this insn are encoded. */
} disp_encoding;
/* Prefer the REX byte in encoding. */
- bfd_boolean rex_encoding;
+ bool rex_encoding;
/* Disable instruction size optimization. */
- bfd_boolean no_optimize;
+ bool no_optimize;
/* How to encode vector instructions. */
enum
}
}
-static INLINE bfd_boolean
+static INLINE bool
is_evex_encoding (const insn_template *t)
{
return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
|| t->opcode_modifier.sae;
}
-static INLINE bfd_boolean
+static INLINE bool
is_any_vex_encoding (const insn_template *t)
{
return t->opcode_modifier.vex || is_evex_encoding (t);
&& i.op[x].regs->reg_num > 3)
{
gas_assert (!(i.op[x].regs->reg_flags & RegRex));
- i.rex_encoding = FALSE;
+ i.rex_encoding = false;
break;
}
break;
case Prefix_REX:
/* {rex} */
- i.rex_encoding = TRUE;
+ i.rex_encoding = true;
break;
case Prefix_NoOptimize:
/* {nooptimize} */
- i.no_optimize = TRUE;
+ i.no_optimize = true;
break;
default:
abort ();
break;
if (j < MAX_OPERANDS)
{
- bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0);
+ bool override = (i.prefix[ADDR_PREFIX] != 0);
addr_prefix_disp = j;
static int
process_suffix (void)
{
- bfd_boolean is_crc32 = FALSE, is_movx = FALSE;
+ bool is_crc32 = false, is_movx = false;
/* If matched instruction specifies an explicit instruction mnemonic
suffix, use it. */
}
static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit,
- bfd_boolean do_sse2avx)
+ bool do_sse2avx)
{
if (r->reg_flags & RegRex)
{
i.rm.reg = i.op[dest].regs->reg_num;
i.rm.regmem = i.op[source].regs->reg_num;
set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
- set_rex_vrex (i.op[source].regs, REX_B, FALSE);
+ set_rex_vrex (i.op[source].regs, REX_B, false);
}
else
{
i.rm.reg = i.op[source].regs->reg_num;
i.rm.regmem = i.op[dest].regs->reg_num;
set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
- set_rex_vrex (i.op[source].regs, REX_R, FALSE);
+ set_rex_vrex (i.op[source].regs, REX_R, false);
}
if (flag_code != CODE_64BIT && (i.rex & REX_R))
{
i.sib.index = NO_INDEX_REGISTER;
else
i.sib.index = i.index_reg->reg_num;
- set_rex_vrex (i.index_reg, REX_X, FALSE);
+ set_rex_vrex (i.index_reg, REX_X, false);
}
}
/* Return TRUE iff PLT32 relocation should be used for branching to
symbol S. */
-static bfd_boolean
+static bool
need_plt32_p (symbolS *s)
{
/* PLT32 relocation is ELF only. */
if (!IS_ELF)
- return FALSE;
+ return false;
#ifdef TE_SOLARIS
/* Don't emit PLT32 relocation on Solaris: neither native linker nor
krtld support it. */
- return FALSE;
+ return false;
#endif
/* Since there is no need to prepare for PLT branch on x86-64, we
can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
be used as a marker for 32-bit PC-relative branches. */
if (!object_64bit)
- return FALSE;
+ return false;
if (s == NULL)
- return FALSE;
+ return false;
/* Weak or undefined symbol need PLT32 relocation. */
if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
- return TRUE;
+ return true;
/* Non-global symbol doesn't need PLT32 relocation. */
if (! S_IS_EXTERNAL (s))
- return FALSE;
+ return false;
/* Other global symbols need PLT32 relocation. NB: Symbol with
non-default visibilities are treated as normal global symbol
so that PLT32 relocation can be used as a marker for 32-bit
PC-relative branches. It is useful for linker relaxation. */
- return TRUE;
+ return true;
}
#endif
if (!object_64bit)
{
reloc_type = BFD_RELOC_386_GOTPC;
- i.has_gotpc_tls_reloc = TRUE;
+ i.has_gotpc_tls_reloc = true;
i.op[n].imms->X_add_number +=
encoding_length (insn_start_frag, insn_start_off, p);
}
case BFD_RELOC_X86_64_GOTTPOFF:
case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
case BFD_RELOC_X86_64_TLSDESC_CALL:
- i.has_gotpc_tls_reloc = TRUE;
+ i.has_gotpc_tls_reloc = true;
default:
break;
}
reloc_type = BFD_RELOC_X86_64_GOTPC32;
else if (size == 8)
reloc_type = BFD_RELOC_X86_64_GOTPC64;
- i.has_gotpc_tls_reloc = TRUE;
+ i.has_gotpc_tls_reloc = true;
i.op[n].imms->X_add_number +=
encoding_length (insn_start_frag, insn_start_off, p);
}
int len;
const enum bfd_reloc_code_real rel[2];
const i386_operand_type types64;
- bfd_boolean need_GOT_symbol;
+ bool need_GOT_symbol;
} gotrel[] = {
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
{ STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
BFD_RELOC_SIZE32 },
- OPERAND_TYPE_IMM32_64, FALSE },
+ OPERAND_TYPE_IMM32_64, false },
#endif
{ STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
BFD_RELOC_X86_64_PLTOFF64 },
- OPERAND_TYPE_IMM64, TRUE },
+ OPERAND_TYPE_IMM64, true },
{ STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
BFD_RELOC_X86_64_PLT32 },
- OPERAND_TYPE_IMM32_32S_DISP32, FALSE },
+ OPERAND_TYPE_IMM32_32S_DISP32, false },
{ STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
BFD_RELOC_X86_64_GOTPLT64 },
- OPERAND_TYPE_IMM64_DISP64, TRUE },
+ OPERAND_TYPE_IMM64_DISP64, true },
{ STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
BFD_RELOC_X86_64_GOTOFF64 },
- OPERAND_TYPE_IMM64_DISP64, TRUE },
+ OPERAND_TYPE_IMM64_DISP64, true },
{ STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
BFD_RELOC_X86_64_GOTPCREL },
- OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
+ OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
BFD_RELOC_X86_64_TLSGD },
- OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
+ OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
_dummy_first_bfd_reloc_code_real },
- OPERAND_TYPE_NONE, TRUE },
+ OPERAND_TYPE_NONE, true },
{ STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
BFD_RELOC_X86_64_TLSLD },
- OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
+ OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
BFD_RELOC_X86_64_GOTTPOFF },
- OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
+ OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
BFD_RELOC_X86_64_TPOFF32 },
- OPERAND_TYPE_IMM32_32S_64_DISP32_64, TRUE },
+ OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
{ STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
_dummy_first_bfd_reloc_code_real },
- OPERAND_TYPE_NONE, TRUE },
+ OPERAND_TYPE_NONE, true },
{ STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
BFD_RELOC_X86_64_DTPOFF32 },
- OPERAND_TYPE_IMM32_32S_64_DISP32_64, TRUE },
+ OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
{ STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
_dummy_first_bfd_reloc_code_real },
- OPERAND_TYPE_NONE, TRUE },
+ OPERAND_TYPE_NONE, true },
{ STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
_dummy_first_bfd_reloc_code_real },
- OPERAND_TYPE_NONE, TRUE },
+ OPERAND_TYPE_NONE, true },
{ STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
BFD_RELOC_X86_64_GOT32 },
- OPERAND_TYPE_IMM32_32S_64_DISP32, TRUE },
+ OPERAND_TYPE_IMM32_32S_64_DISP32, true },
{ STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
BFD_RELOC_X86_64_GOTPC32_TLSDESC },
- OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
+ OPERAND_TYPE_IMM32_32S_DISP32, true },
{ STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
BFD_RELOC_X86_64_TLSDESC_CALL },
- OPERAND_TYPE_IMM32_32S_DISP32, TRUE },
+ OPERAND_TYPE_IMM32_32S_DISP32, true },
};
char *cp;
unsigned int j;
branch template. */
static templates aux_templates;
const insn_template *t = current_templates->start;
- bfd_boolean has_intel64 = FALSE;
+ bool has_intel64 = false;
aux_templates.start = t;
while (++t < current_templates->end)
!= current_templates->start->opcode_modifier.jump)
break;
if ((t->opcode_modifier.isa64 >= INTEL64))
- has_intel64 = TRUE;
+ has_intel64 = true;
}
if (t < current_templates->end)
{
if (t < current_templates->end)
{
static templates aux_templates;
- bfd_boolean recheck;
+ bool recheck;
aux_templates.start = t;
for (; t < current_templates->end; ++t)
++op_string;
if (is_space_char (*op_string))
++op_string;
- i.jumpabsolute = TRUE;
+ i.jumpabsolute = true;
}
/* Check if operand is a register. */
++op_string;
if (is_space_char (*op_string))
++op_string;
- i.jumpabsolute = TRUE;
+ i.jumpabsolute = true;
}
goto do_memory_reference;
}
{
/* This outputs the LITTLENUMs in REVERSE order;
in accord with the bigendian 386. */
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
\f
static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
/* Verify that @r can be used in the current context. */
-static bfd_boolean check_register (const reg_entry *r)
+static bool check_register (const reg_entry *r)
{
if (allow_pseudo_reg)
- return TRUE;
+ return true;
if (operand_type_all_zero (&r->reg_type))
- return FALSE;
+ return false;
if ((r->reg_type.bitfield.dword
|| (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
|| r->reg_type.bitfield.class == RegCR
|| r->reg_type.bitfield.class == RegDR)
&& !cpu_arch_flags.bitfield.cpui386)
- return FALSE;
+ return false;
if (r->reg_type.bitfield.class == RegTR
&& (flag_code == CODE_64BIT
|| !cpu_arch_flags.bitfield.cpui386
|| cpu_arch_isa_flags.bitfield.cpui586
|| cpu_arch_isa_flags.bitfield.cpui686))
- return FALSE;
+ return false;
if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
- return FALSE;
+ return false;
if (!cpu_arch_flags.bitfield.cpuavx512f)
{
if (r->reg_type.bitfield.zmmword
|| r->reg_type.bitfield.class == RegMask)
- return FALSE;
+ return false;
if (!cpu_arch_flags.bitfield.cpuavx)
{
if (r->reg_type.bitfield.ymmword)
- return FALSE;
+ return false;
if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
- return FALSE;
+ return false;
}
}
if (r->reg_type.bitfield.tmmword
&& (!cpu_arch_flags.bitfield.cpuamx_tile
|| flag_code != CODE_64BIT))
- return FALSE;
+ return false;
if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
- return FALSE;
+ return false;
/* Don't allow fake index register unless allow_index_reg isn't 0. */
if (!allow_index_reg && r->reg_num == RegIZ)
- return FALSE;
+ return false;
/* Upper 16 vector registers are only available with VREX in 64bit
mode, and require EVEX encoding. */
{
if (!cpu_arch_flags.bitfield.cpuavx512f
|| flag_code != CODE_64BIT)
- return FALSE;
+ return false;
if (i.vec_encoding == vex_encoding_default)
i.vec_encoding = vex_encoding_evex;
if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
&& (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR)
&& flag_code != CODE_64BIT)
- return FALSE;
+ return false;
if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
&& !intel_syntax)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* REG_STRING starts *before* REGISTER_PREFIX. */
{
struct label_fix *next;
struct symbol *sym;
- bfd_boolean dw2_mark_labels;
+ bool dw2_mark_labels;
};
#ifdef TE_VMS
segT saved_seg;
subsegT saved_subseg;
unw_rec_list *ptr;
- bfd_boolean mark;
+ bool mark;
if (!md.last_text_seg)
return;
/* In case there are labels following the last instruction, resolve
those now. */
- mark = FALSE;
+ mark = false;
for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
{
symbol_set_value_now (lfix->sym);
int n, i, j, first, curr, last_slot;
bfd_vma t0 = 0, t1 = 0;
struct label_fix *lfix;
- bfd_boolean mark_label;
+ bool mark_label;
struct insn_fix *ifix;
char mnemonic[16];
fixS *fix;
continue; /* Try next slot. */
/* Now is a good time to fix up the labels for this insn. */
- mark_label = FALSE;
+ mark_label = false;
for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
{
S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
fix = XOBNEW (¬es, struct label_fix);
fix->sym = sym;
fix->next = CURR_SLOT.tag_fixups;
- fix->dw2_mark_labels = FALSE;
+ fix->dw2_mark_labels = false;
CURR_SLOT.tag_fixups = fix;
return;
/* Set the machine type. */
bfd_default_set_arch_mach (stdoutput, bfd_arch_ip2k, ip2k_mach);
- literal_prefix_dollar_hex = TRUE;
+ literal_prefix_dollar_hex = true;
}
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
-bfd_boolean
+bool
iq2000_fix_adjustable (fixS * fixP)
{
bfd_reloc_code_real_type reloc_type;
reloc_type = fixP->fx_r_type;
if (fixP->fx_addsy == NULL)
- return TRUE;
+ return true;
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
- return FALSE;
+ return false;
if (S_IS_WEAK (fixP->fx_addsy))
- return FALSE;
+ return false;
/* We need the symbol name for the VTABLE entries. */
if ( reloc_type == BFD_RELOC_VTABLE_INHERIT
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
static void
#define tc_gen_reloc gas_cgen_tc_gen_reloc
-extern void iq2000_frob_file (void);
-extern bfd_boolean iq2000_fix_adjustable (struct fix *);
-extern int iq2000_force_relocation (struct fix *);
+extern void iq2000_frob_file (void);
+extern bool iq2000_fix_adjustable (struct fix *);
+extern int iq2000_force_relocation (struct fix *);
/* Return true if we can partially resolve a relocation now. */
-bfd_boolean
+bool
lm32_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Relaxation isn't required/supported on this target. */
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
-extern bfd_boolean lm32_fix_adjustable (struct fix *);
+extern bool lm32_fix_adjustable (struct fix *);
#define tc_fix_adjustable(FIX) lm32_fix_adjustable (FIX)
#endif /* TC_LM32_H */
/* Process [[indirect-operands]] in instruction str. */
-static bfd_boolean
+static bool
m32c_indirect_operand (char *str)
{
char *new_str;
}
if (indirection[1] == none && indirection[2] == none)
- return FALSE;
+ return false;
operand = 1;
ns_len = strlen (str);
*ns = s[0];
ns += 1;
if (ns >= ns_end)
- return FALSE;
+ return false;
if (s[0] == 0)
break;
}
md_assemble (new_str);
free (new_str);
- return TRUE;
+ return true;
}
void
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
-bfd_boolean
+bool
m32c_fix_adjustable (fixS * fixP)
{
int reloc;
extern void m32c_apply_fix (struct fix *, valueT *, segT);
#define tc_fix_adjustable(fixP) m32c_fix_adjustable (fixP)
-extern bfd_boolean m32c_fix_adjustable (struct fix *);
+extern bool m32c_fix_adjustable (struct fix *);
/* When relaxing, we need to emit various relocs we otherwise wouldn't. */
#define TC_FORCE_RELOCATION(fix) m32c_force_relocation (fix)
|| CGEN_FIELDS_BITSIZE (&b->fields) != 16)
abort ();
- if (first_writes_to_seconds_operands (a, b, TRUE))
+ if (first_writes_to_seconds_operands (a, b, true))
return _("instructions write to the same destination register.");
a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
if (parallel_p && warn_explicit_parallel_conflicts)
{
- if (first_writes_to_seconds_operands (&first, &second, FALSE))
+ if (first_writes_to_seconds_operands (&first, &second, false))
/* xgettext:c-format */
as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
- if (first_writes_to_seconds_operands (&second, &first, FALSE))
+ if (first_writes_to_seconds_operands (&second, &first, false))
/* xgettext:c-format */
as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
}
else
{
int on_32bit_boundary_p;
- int swap = FALSE;
+ int swap = false;
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
abort ();
&& parallel ()
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
&& ! writes_to_pc (&prev_insn)
- && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
+ && ! first_writes_to_seconds_operands (&prev_insn, &insn, false))
{
if (can_make_parallel (&prev_insn, &insn) == NULL)
make_parallel (insn.buffer);
else if (can_make_parallel (&insn, &prev_insn) == NULL)
- swap = TRUE;
+ swap = true;
}
expand_debug_syms (insn.debug_sym_link, 1);
/* Return true if can adjust the reloc to be relative to its section
(such as .data) instead of relative to some symbol. */
-bfd_boolean
+bool
m32r_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;
#define md_apply_fix gas_cgen_md_apply_fix
#define tc_fix_adjustable(FIX) m32r_fix_adjustable (FIX)
-extern bfd_boolean m32r_fix_adjustable (struct fix *);
+extern bool m32r_fix_adjustable (struct fix *);
/* After creating a fixup for an instruction operand, we need to check for
HI16 relocs and queue them up for later sorting. */
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
valueT
if (mode == M6811_OP_JUMP_REL)
{
fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
- oper, TRUE, BFD_RELOC_8_PCREL);
+ oper, true, BFD_RELOC_8_PCREL);
}
else
{
reloc = BFD_RELOC_8;
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
- oper, FALSE, reloc);
+ oper, false, reloc);
if (reloc != BFD_RELOC_8)
fixp->fx_no_overflow = 1;
}
{
/* Now create a 24-bit fixup. */
fix_new_exp (frag_now, f - frag_now->fr_literal, 3,
- oper, FALSE, BFD_RELOC_M68HC11_24);
+ oper, false, BFD_RELOC_M68HC11_24);
number_to_chars_bigendian (f, 0, 3);
}
else
reloc = BFD_RELOC_M68HC11_LO8;
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
- oper, FALSE, reloc);
+ oper, false, reloc);
fixp->fx_no_overflow = 1;
number_to_chars_bigendian (f, 0, 1);
}
/* Future improvement:
This fixup/reloc isn't adding on constants to symbols. */
fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2,
- oper, TRUE, BFD_RELOC_M68HC12_9_PCREL);
+ oper, true, BFD_RELOC_M68HC12_9_PCREL);
}
else if (mode == M68XG_OP_REL10)
{
/* Future improvement:
This fixup/reloc isn't adding on constants to symbols. */
fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2,
- oper, TRUE, BFD_RELOC_M68HC12_10_PCREL);
+ oper, true, BFD_RELOC_M68HC12_10_PCREL);
}
else
{
reloc = BFD_RELOC_8;
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
- oper, FALSE, reloc);
+ oper, false, reloc);
if (reloc != BFD_RELOC_8)
fixp->fx_no_overflow = 1;
}
operands[0].mode = M6811_OP_LOW_ADDR;
f = frag_more (1);
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
- &operands[0].exp, FALSE, BFD_RELOC_M68HC12_LO8XG);
+ &operands[0].exp, false, BFD_RELOC_M68HC12_LO8XG);
fixp->fx_no_overflow = 1;
number_to_chars_bigendian (f, 0, 1);
operands[0].mode = M6811_OP_HIGH_ADDR;
f = frag_more (1);
fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
- &operands[0].exp, FALSE, BFD_RELOC_M68HC12_HI8XG);
+ &operands[0].exp, false, BFD_RELOC_M68HC12_HI8XG);
fixp->fx_no_overflow = 1;
number_to_chars_bigendian (f, 0, 1);
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
void
/* Return true if the fix can be handled by GAS, false if it must
be passed through to the linker. */
-bfd_boolean
+bool
mcore_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries. */
#include "write.h" /* For definition of fixS */
-extern void md_mcore_end (void);
-extern arelent * tc_gen_reloc (asection *, fixS *);
-extern int mcore_force_relocation (fixS *);
-extern bfd_boolean mcore_fix_adjustable (fixS *);
+extern void md_mcore_end (void);
+extern arelent *tc_gen_reloc (asection *, fixS *);
+extern int mcore_force_relocation (fixS *);
+extern bool mcore_fix_adjustable (fixS *);
#endif /* TC_MCORE */
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
-bfd_boolean
+bool
mep_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;
extern void mep_frob_file (void);
#define tc_fix_adjustable(fixP) mep_fix_adjustable (fixP)
-extern bfd_boolean mep_fix_adjustable (struct fix *);
+extern bool mep_fix_adjustable (struct fix *);
/* After creating a fixup for an instruction operand, we need
to check for HI16 relocs and queue them up for later sorting. */
}
/* Return TRUE if REG1 and REG2 are in paired units. */
-static bfd_boolean
+static bool
is_unit_pair (const metag_reg *reg1, const metag_reg *reg2)
{
if ((reg1->unit == UNIT_A0 &&
(reg2->unit == UNIT_D1)) ||
(reg1->unit == UNIT_D1 &&
(reg2->unit == UNIT_D0)))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Return TRUE if REG1 and REG2 form a register pair. */
-static bfd_boolean
+static bool
is_reg_pair (const metag_reg *reg1, const metag_reg *reg2)
{
if (reg1->unit == UNIT_FX &&
reg2->unit == UNIT_FX &&
reg2->no == reg1->no + 1)
- return TRUE;
+ return true;
if (reg1->no != reg2->no)
- return FALSE;
+ return false;
return is_unit_pair (reg1, reg2);
}
const insn_template *template)
{
const char *l = line;
- bfd_boolean is_movl = MINOR_OPCODE (template->meta_opcode) == MOVL_MINOR;
+ bool is_movl = MINOR_OPCODE (template->meta_opcode) == MOVL_MINOR;
const metag_reg *dest_regs[2];
const metag_reg *port_regs[1];
/* Parse a GET or pipeline MOV instruction. */
static const char *
parse_get (const char *line, const metag_reg **regs, metag_addr *addr,
- unsigned int size, bfd_boolean is_mov)
+ unsigned int size, bool is_mov)
{
const char *l = line;
/* Check a signed integer value can be represented in the given number
of bits. */
-static bfd_boolean
+static bool
within_signed_range (int value, unsigned int bits)
{
int min_val = -(1 << (bits - 1));
/* Check an unsigned integer value can be represented in the given number
of bits. */
-static bfd_boolean
+static bool
within_unsigned_range (unsigned int value, unsigned int bits)
{
return value < (unsigned int)(1 << bits);
}
/* Return TRUE if UNIT can be expressed using a short code. */
-static bfd_boolean
+static bool
is_short_unit (enum metag_unit unit)
{
switch (unit)
case UNIT_A1:
case UNIT_D0:
case UNIT_D1:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
const metag_reg *regs[2];
metag_addr addr;
unsigned int size = metag_get_set_size_bytes (template->meta_opcode);
- bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
unsigned int reg_no;
memset(&addr, 0, sizeof(addr));
if (is_get)
{
- bfd_boolean is_mov = strncmp (template->name, "MOV", 3) == 0;
+ bool is_mov = strncmp (template->name, "MOV", 3) == 0;
l = parse_get (l, regs, &addr, size, is_mov);
const metag_reg *regs[2];
metag_addr addr;
unsigned int size = metag_get_set_ext_size_bytes (template->meta_opcode);
- bfd_boolean is_get = MINOR_OPCODE (template->meta_opcode) == GET_EXT_MINOR;
- bfd_boolean is_mov = MINOR_OPCODE (template->meta_opcode) == MOV_EXT_MINOR;
+ bool is_get = MINOR_OPCODE (template->meta_opcode) == GET_EXT_MINOR;
+ bool is_mov = MINOR_OPCODE (template->meta_opcode) == MOV_EXT_MINOR;
unsigned int reg_unit;
memset(&addr, 0, sizeof(addr));
rmask value if possible. Return the rmask value in RMASK and the
lowest numbered register in LOWEST_REG. Return TRUE if the conversion
was successful. */
-static bfd_boolean
-check_rmask (const metag_reg **regs, size_t regs_read, bfd_boolean is_fpu,
- bfd_boolean is_64bit, unsigned int *lowest_reg,
+static bool
+check_rmask (const metag_reg **regs, size_t regs_read, bool is_fpu,
+ bool is_64bit, unsigned int *lowest_reg,
unsigned int *rmask)
{
unsigned int reg_unit = regs[0]->unit;
if (is_64bit && regs[i]->no % 2)
{
as_bad (_("register list must be even numbered"));
- return FALSE;
+ return false;
}
}
else if (regs[i]->unit != reg_unit)
{
as_bad (_("register list must be from the same unit"));
- return FALSE;
+ return false;
}
if (regs[i]->no < *lowest_reg)
if (*rmask & next_bit)
{
as_bad (_("register list must not contain duplicates"));
- return FALSE;
+ return false;
}
*rmask |= next_bit;
}
- return TRUE;
+ return true;
}
/* Parse an MGET or MSET instruction. */
const char *l = line;
const metag_reg *regs[MGET_MSET_MAX_REGS];
metag_addr addr;
- bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
- bfd_boolean is_fpu = (MINOR_OPCODE (template->meta_opcode) & 0x6) == 0x6;
- bfd_boolean is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) == 0x1;
+ bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bool is_fpu = (MINOR_OPCODE (template->meta_opcode) & 0x6) == 0x6;
+ bool is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) == 0x1;
size_t regs_read = 0;
unsigned int rmask = 0, reg_unit = 0, lowest_reg = 0xffffffff;
const insn_template *template)
{
const char *l = line;
- bfd_boolean is_fpu = template->insn_type == INSN_FPU;
- bfd_boolean is_prime = (MINOR_OPCODE (template->meta_opcode) & 0x2) != 0 && !is_fpu;
- bfd_boolean is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) != 0;
+ bool is_fpu = template->insn_type == INSN_FPU;
+ bool is_prime = (MINOR_OPCODE (template->meta_opcode) & 0x2) != 0 && !is_fpu;
+ bool is_64bit = (MINOR_OPCODE (template->meta_opcode) & 0x1) != 0;
unsigned int rmask = 0;
if (is_prime)
const char *l = line;
char *save_input_line_pointer;
expressionS *exp = &insn->reloc_exp;
- bfd_boolean is_hi = FALSE;
- bfd_boolean is_lo = FALSE;
+ bool is_hi = false;
+ bool is_lo = false;
/* Skip #. */
if (*l == '#')
if (strncasecmp (l, "HI", 2) == 0)
{
- is_hi = TRUE;
+ is_hi = true;
l += 2;
}
else if (strncasecmp (l, "LO", 2) == 0)
{
- is_lo = TRUE;
+ is_lo = true;
l += 2;
}
{
const char *l = line;
const metag_reg *regs[1];
- bfd_boolean top = (template->meta_opcode & 0x1) != 0;
- bfd_boolean is_trace = ((template->meta_opcode >> 2) & 0x1) != 0;
- bfd_boolean sign_extend = 0;
+ bool top = (template->meta_opcode & 0x1) != 0;
+ bool is_trace = ((template->meta_opcode >> 2) & 0x1) != 0;
+ bool sign_extend = 0;
int value = 0;
l = parse_gp_regs (l, regs, 1);
if (!is_short_unit (regs[0]->unit))
{
as_bad (_("register unit must be one of %s"), SHORT_UNITS);
- return FALSE;
+ return false;
}
l = skip_comma (l);
const metag_reg *dest_regs[1];
const metag_reg *src_regs[2];
int value = 0;
- bfd_boolean o1z = 0;
- bfd_boolean imm = ((template->meta_opcode >> 25) & 0x1) != 0;
- bfd_boolean cond = ((template->meta_opcode >> 26) & 0x1) != 0;
- bfd_boolean ca = ((template->meta_opcode >> 5) & 0x1) != 0;
- bfd_boolean top = (template->meta_opcode & 0x1) != 0;
- bfd_boolean sign_extend = 0;
- bfd_boolean is_addr_op = MAJOR_OPCODE (template->meta_opcode) == OPC_ADDR;
- bfd_boolean is_mul = MAJOR_OPCODE (template->meta_opcode) == OPC_MUL;
+ bool o1z = 0;
+ bool imm = ((template->meta_opcode >> 25) & 0x1) != 0;
+ bool cond = ((template->meta_opcode >> 26) & 0x1) != 0;
+ bool ca = ((template->meta_opcode >> 5) & 0x1) != 0;
+ bool top = (template->meta_opcode & 0x1) != 0;
+ bool sign_extend = 0;
+ bool is_addr_op = MAJOR_OPCODE (template->meta_opcode) == OPC_ADDR;
+ bool is_mul = MAJOR_OPCODE (template->meta_opcode) == OPC_MUL;
unsigned int unit_bit = 0;
- bfd_boolean is_quickrot = (template->arg_type & GP_ARGS_QR) != 0;
+ bool is_quickrot = (template->arg_type & GP_ARGS_QR) != 0;
l = parse_gp_regs (l, dest_regs, 1);
}
else
{
- bfd_boolean o2r = 0;
+ bool o2r = 0;
int rs2;
if (cond || !o1z)
if (is_quickrot)
{
const metag_reg *qr_regs[1];
- bfd_boolean limit_regs = imm && cond;
+ bool limit_regs = imm && cond;
l = skip_comma (l);
const metag_reg *regs[2];
const metag_reg *src2_regs[1];
int value = 0;
- bfd_boolean cond = ((template->meta_opcode >> 26) & 0x1) != 0;
- bfd_boolean ca = ((template->meta_opcode >> 5) & 0x1) != 0;
+ bool cond = ((template->meta_opcode >> 26) & 0x1) != 0;
+ bool ca = ((template->meta_opcode >> 5) & 0x1) != 0;
unsigned int unit_bit = 0;
l = parse_gp_regs (l, regs, 2);
{
const char *l = line;
const metag_reg *regs[2];
- bfd_boolean swap_inst = MAJOR_OPCODE (template->meta_opcode) == OPC_MISC;
- bfd_boolean is_bexl = 0;
+ bool swap_inst = MAJOR_OPCODE (template->meta_opcode) == OPC_MISC;
+ bool is_bexl = 0;
if (swap_inst && ((template->meta_opcode >> 1) & 0xb) == 0xa)
is_bexl = 1;
const metag_reg *dest_regs[1];
const metag_reg *src_regs[1];
int value = 0;
- bfd_boolean imm = ((template->meta_opcode >> 25) & 0x1) != 0;
- bfd_boolean cond = ((template->meta_opcode >> 26) & 0x1) != 0;
- bfd_boolean top = (template->meta_opcode & 0x1) != 0;
- bfd_boolean sign_extend = 0;
+ bool imm = ((template->meta_opcode >> 25) & 0x1) != 0;
+ bool cond = ((template->meta_opcode >> 26) & 0x1) != 0;
+ bool top = (template->meta_opcode & 0x1) != 0;
+ bool sign_extend = 0;
unsigned int unit_bit = 0;
l = parse_gp_regs (l, dest_regs, 1);
}
else
{
- bfd_boolean o2r = 0;
+ bool o2r = 0;
int rs2;
l = parse_gp_regs (l, src_regs, 1);
const insn_template *template)
{
const char *l = line;
- bfd_boolean to_fpu = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
- bfd_boolean is_mmovl = (MINOR_OPCODE (template->meta_opcode) & 0x1) != 0;
+ bool to_fpu = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bool is_mmovl = (MINOR_OPCODE (template->meta_opcode) & 0x1) != 0;
size_t regs_read = 0;
const metag_reg *regs[16];
unsigned int lowest_data_reg = 0xffffffff;
else
return NULL;
- if (!check_rmask (®s[i], regs_read / 2, TRUE, FALSE, &lowest_data_reg,
+ if (!check_rmask (®s[i], regs_read / 2, true, false, &lowest_data_reg,
&rmask))
return NULL;
}
else
return NULL;
- if (!check_rmask (regs, regs_read / 2, TRUE, FALSE, &lowest_data_reg,
+ if (!check_rmask (regs, regs_read / 2, true, false, &lowest_data_reg,
&rmask))
return NULL;
const insn_template *template)
{
const char *l = line;
- bfd_boolean to_fpu = ((template->meta_opcode >> 7) & 0x1) != 0;
+ bool to_fpu = ((template->meta_opcode >> 7) & 0x1) != 0;
const metag_reg *regs[2];
unsigned int base_unit;
{
const char *l = line;
const metag_reg *regs[3];
- bfd_boolean is_muz = (MINOR_OPCODE (template->meta_opcode) == 0x6
- && ((template->meta_opcode >> 4) & 0x1) != 0);
- bfd_boolean is_o3o = (template->meta_opcode & 0x1) != 0;
- bfd_boolean is_mac = 0;
- bfd_boolean is_maw = 0;
+ bool is_muz = (MINOR_OPCODE (template->meta_opcode) == 0x6
+ && ((template->meta_opcode >> 4) & 0x1) != 0);
+ bool is_o3o = (template->meta_opcode & 0x1) != 0;
+ bool is_mac = 0;
+ bool is_maw = 0;
if (!strncasecmp (template->name, "MAW", 3))
is_maw = 1;
const char *l = line;
int part;
metag_addr addr;
- bfd_boolean is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
+ bool is_get = MAJOR_OPCODE (template->meta_opcode) == OPC_GET;
memset(&addr, 0, sizeof(addr));
addr.reloc_type = BFD_RELOC_UNUSED;
definition. "load" specifies which table to look at. */
static const char *
parse_dsp_template_reg (const char *line, const metag_reg **reg,
- bfd_boolean load)
+ bool load)
{
return __parse_dsp_reg (line, reg, dsp_tmpl_reg_htab[load]);
}
/* Parse a single DSP register from LINE. */
static const char *
parse_dsp_reg (const char *line, const metag_reg **reg,
- bfd_boolean tmpl, bfd_boolean load)
+ bool tmpl, bool load)
{
if (tmpl)
return parse_dsp_template_reg (line, reg, load);
}
/* Return TRUE if UNIT is an address unit. */
-static bfd_boolean
+static bool
is_addr_unit (enum metag_unit unit)
{
switch (unit)
{
case UNIT_A0:
case UNIT_A1:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
/* Return TRUE if UNIT1 and UNIT2 are equivalent units. */
-static bfd_boolean
+static bool
is_same_data_unit (enum metag_unit unit1, enum metag_unit unit2)
{
if (unit1 == unit2)
- return TRUE;
+ return true;
switch (unit1)
{
case UNIT_D0:
if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_RAM_D0)
- return TRUE;
+ return true;
break;
case UNIT_D1:
if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_RAM_D1)
- return TRUE;
+ return true;
break;
case UNIT_ACC_D0:
if (unit2 == UNIT_D0 || unit2 == UNIT_RAM_D0)
- return TRUE;
+ return true;
break;
case UNIT_ACC_D1:
if (unit2 == UNIT_D1 || unit2 == UNIT_RAM_D1)
- return TRUE;
+ return true;
break;
case UNIT_RAM_D0:
if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_D0)
- return TRUE;
+ return true;
break;
case UNIT_RAM_D1:
if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_D1)
- return TRUE;
+ return true;
break;
default:
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
/* Return TRUE if the register NUM is a quickrot control register. */
-static bfd_boolean
+static bool
is_quickrot_reg (unsigned int num)
{
switch (num)
{
case 2:
case 3:
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Return TRUE if REG is an accumulator register. */
-static bfd_boolean
+static bool
is_accumulator_reg (const metag_reg *reg)
{
if (reg->unit == UNIT_ACC_D0 || reg->unit == UNIT_ACC_D1)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Return TRUE if REG is a DSP RAM register. */
-static bfd_boolean
+static bool
is_dspram_reg (const metag_reg *reg)
{
if (reg->unit == UNIT_RAM_D0 || reg->unit == UNIT_RAM_D1)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
static const char *
-__parse_gp_reg (const char *line, const metag_reg **reg, bfd_boolean load)
+__parse_gp_reg (const char *line, const metag_reg **reg, bool load)
{
const char *l = line;
char reg_buf[MAX_REG_LEN];
if (l == NULL)
return NULL;
- l = parse_dsp_reg (l, reg, TRUE, load);
+ l = parse_dsp_reg (l, reg, true, load);
if (l == NULL)
return NULL;
a destination operand. */
static const char *
parse_dsp_regs_list (const char *line, const metag_reg **regs, size_t count,
- size_t *regs_read, bfd_boolean try_gp, bfd_boolean tmpl,
- bfd_boolean load, bfd_boolean first_dst)
+ size_t *regs_read, bool try_gp, bool tmpl,
+ bool load, bool first_dst)
{
const char *l = line;
int seen_regs = 0;
- [DSPRam-DSPRam--] */
static const char *
parse_dsp_addr (const char *line, metag_addr *addr, unsigned int size,
- bfd_boolean load)
+ bool load)
{
const char *l = line, *ll;
const metag_reg *regs[1];
/* Skip opening square bracket. */
l++;
- l = parse_dsp_regs_list (l, regs, 1, ®s_read, TRUE, TRUE, load, FALSE);
+ l = parse_dsp_regs_list (l, regs, 1, ®s_read, true, true, load, false);
if (l == NULL)
return NULL;
if (l == NULL)
return NULL;
- l = parse_dsp_regs_list (l, regs, 1, ®s_read, TRUE, TRUE, load, FALSE);
+ l = parse_dsp_regs_list (l, regs, 1, ®s_read, true, true, load, false);
if (l == NULL)
return NULL;
metag_addr addr;
int unit = 0;
int rd_reg = 0;
- bfd_boolean is_get = (template->meta_opcode & 0x100) != 0;
- bfd_boolean is_dual = (template->meta_opcode & 0x4) != 0;
- bfd_boolean is_template = FALSE;
+ bool is_get = (template->meta_opcode & 0x100) != 0;
+ bool is_dual = (template->meta_opcode & 0x4) != 0;
+ bool is_template = false;
const metag_reg *regs[2];
unsigned int size;
size_t count, regs_read;
if (*l == 'T')
count = 1;
- l = parse_dsp_regs_list (l, regs, count, ®s_read, FALSE,
- FALSE, FALSE, FALSE);
+ l = parse_dsp_regs_list (l, regs, count, ®s_read, false,
+ false, false, false);
l = skip_comma (l);
if (l == NULL)
if (*l == 'T')
count = 1;
- l = parse_dsp_regs_list (l, regs, count, ®s_read, FALSE, FALSE,
- FALSE, FALSE);
+ l = parse_dsp_regs_list (l, regs, count, ®s_read, false, false,
+ false, false);
}
if (l == NULL)
/* The first register dictates the unit. */
if (regs[0]->unit == UNIT_DT)
- is_template = TRUE;
+ is_template = true;
else
{
if (regs[0]->unit == UNIT_D0 || regs[0]->unit == UNIT_RAM_D0 ||
{
const char *l = line;
const metag_reg *regs[TEMPLATE_NUM_REGS];
- bfd_boolean daop_only = FALSE;
+ bool daop_only = false;
int regs_val[4];
int regs_which[4] = { -1, -1, -1, -1}; /* Register or immediate? */
int i;
/* We may only have 3 register operands. */
if (*l == END_OF_INSN && i == 3)
{
- daop_only = TRUE;
+ daop_only = true;
break;
}
this is a load or store. So we have to try looking up the
register name in both the load and store tables. */
const char *l2 = l;
- l = __parse_gp_reg (l, ®s[i], TRUE);
+ l = __parse_gp_reg (l, ®s[i], true);
if (l == NULL)
{
/* Try the store table too. */
- l = __parse_gp_reg (l2, ®s[i], FALSE);
+ l = __parse_gp_reg (l2, ®s[i], false);
if (l == NULL)
{
/* Then try a DSP register. */
template definition is a DSP RAM template definition. */
static const char *
template_mem_ref(const char *line, metag_addr *addr,
- bfd_boolean *dspram, int size, bfd_boolean load)
+ bool *dspram, int size, bool load)
{
const char *l = line;
if (l != NULL)
{
if (is_addr_unit(addr->base_reg->unit))
- *dspram = FALSE;
+ *dspram = false;
else
- *dspram = TRUE;
+ *dspram = true;
}
return l;
/* Sets LOAD to TRUE if this is a Template load definition (otherwise
it's a store). Fills out ADDR, TEMPLATE_REG and ADDR_UNIT. */
static const char *
-parse_template_regs (const char *line, bfd_boolean *load,
+parse_template_regs (const char *line, bool *load,
unsigned int *addr_unit,
const metag_reg **template_reg, metag_addr *addr,
- bfd_boolean *dspram, int size)
+ bool *dspram, int size)
{
const char *l = line;
/* DSP Template load definition (Tx, [Ax]) */
if (*l == 'T')
{
- *load = TRUE;
- l = parse_dsp_reg (l, &template_reg[0], FALSE, FALSE);
+ *load = true;
+ l = parse_dsp_reg (l, &template_reg[0], false, false);
if (l == NULL)
return NULL;
}
else if (*l == ADDR_BEGIN_CHAR) /* DSP Template store ([Ax], Tx) */
{
- *load = FALSE;
+ *load = false;
l = template_mem_ref (l, addr, dspram, size, *load);
l = skip_comma(l);
if (l == NULL)
return NULL;
- l = parse_dsp_reg (l, &template_reg[0], FALSE, FALSE);
+ l = parse_dsp_reg (l, &template_reg[0], false, false);
if (l == NULL)
return NULL;
static const char *
interpret_template_regs(const char *line, metag_insn *insn,
const metag_reg **regs,
- int *regs_shift, bfd_boolean *load, bfd_boolean *dspram,
+ int *regs_shift, bool *load, bool *dspram,
int size, int *ls_shift, int *au_shift,
unsigned int *au, int *imm, int *imm_shift,
unsigned int *imm_mask)
}
/* Does this combination of units need the O2R bit and can it be encoded? */
-static bfd_boolean
+static bool
units_need_o2r (enum metag_unit unit1, enum metag_unit unit2)
{
if (unit1 == unit2)
- return FALSE;
+ return false;
if (unit1 == UNIT_D0 || unit1 == UNIT_ACC_D0 || unit1 == UNIT_RAM_D0)
{
if (unit2 == UNIT_ACC_D0 || unit2 == UNIT_RAM_D0 || unit2 == UNIT_D0)
- return FALSE;
+ return false;
switch (unit2)
{
case UNIT_D1:
case UNIT_RD:
case UNIT_A0:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
if (unit1 == UNIT_D1 || unit1 == UNIT_ACC_D1 || unit1 == UNIT_RAM_D1)
{
if (unit2 == UNIT_ACC_D1 || unit2 == UNIT_RAM_D1 || unit2 == UNIT_D1)
- return FALSE;
+ return false;
switch (unit2)
{
case UNIT_D0:
case UNIT_RD:
case UNIT_A0:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
- return FALSE;
+ return false;
}
/* Return TRUE if this is a DSP data unit. */
-static bfd_boolean
+static bool
is_dsp_data_unit (const metag_reg *reg)
{
switch (reg->unit)
case UNIT_ACC_D1:
case UNIT_RAM_D0:
case UNIT_RAM_D1:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
const metag_reg *regs[4];
metag_addr addr;
size_t regs_read;
- bfd_boolean is_mov = MAJOR_OPCODE (template->meta_opcode) == OPC_ADD;
- bfd_boolean is_cmp = ((MAJOR_OPCODE (template->meta_opcode) == OPC_CMP) &&
- ((template->meta_opcode & 0xee) == 0));
- bfd_boolean is_dual = insn->dsp_width == DSP_WIDTH_DUAL;
- bfd_boolean is_quickrot64 = ((insn->dsp_action_flags & DSP_ACTION_QR64) != 0);
+ bool is_mov = MAJOR_OPCODE (template->meta_opcode) == OPC_ADD;
+ bool is_cmp = (MAJOR_OPCODE (template->meta_opcode) == OPC_CMP
+ && (template->meta_opcode & 0xee) == 0);
+ bool is_dual = insn->dsp_width == DSP_WIDTH_DUAL;
+ bool is_quickrot64 = (insn->dsp_action_flags & DSP_ACTION_QR64) != 0;
int l1_shift = INVALID_SHIFT;
- bfd_boolean load = FALSE;
+ bool load = false;
int ls_shift = INVALID_SHIFT;
- bfd_boolean ar = FALSE;
+ bool ar = false;
int ar_shift = INVALID_SHIFT;
int regs_shift[3] = { INVALID_SHIFT, INVALID_SHIFT, INVALID_SHIFT };
int imm = 0;
(insn->dsp_daoppame_flags & DSP_DAOPPAME_16) != 0);
int mx_shift = INVALID_SHIFT;
int size = is_dual ? 8 : 4;
- bfd_boolean dspram;
- bfd_boolean conditional = (MINOR_OPCODE (template->meta_opcode) & 0x4) != 0;
+ bool dspram;
+ bool conditional = (MINOR_OPCODE (template->meta_opcode) & 0x4) != 0;
/* XFIXME: check the flags are valid with the instruction. */
if (is_quickrot64 && !(template->arg_type & DSP_ARGS_QR))
e.g. ACe.e,ACx.r,ACo.e */
if (template->arg_type & DSP_ARGS_XACC)
{
- ll = parse_dsp_regs_list (l, regs, 3, ®s_read, FALSE, FALSE,
- FALSE, FALSE);
+ ll = parse_dsp_regs_list (l, regs, 3, ®s_read, false, false,
+ false, false);
if (ll != NULL && regs_read == 3
&& is_accumulator_reg (regs[0]))
{
a1_shift = 2;
om_shift = 3;
- ll = parse_dsp_reg (l, ®s[0], FALSE, FALSE);
+ ll = parse_dsp_reg (l, ®s[0], false, false);
if (ll != NULL)
{
/* Using ACe.r as the dst requires one of the P,N or Z
l = ll;
l = skip_comma (l);
l = parse_dsp_regs_list (l, ®s[1], 2, ®s_read,
- TRUE, FALSE, FALSE, FALSE);
+ true, false, false, false);
if (l == NULL || regs_read != 2)
{
as_bad (_("invalid register"));
regs_shift[0] = 19;
- l = parse_dsp_regs_list (l, regs, 2, ®s_read, TRUE, FALSE, FALSE, TRUE);
+ l = parse_dsp_regs_list (l, regs, 2, ®s_read, true, false, false, true);
if (l == NULL || regs_read != 2)
return NULL;
regs_shift[2] = 9;
/* Is Rs2 an accumulator reg, e.g. De.r,Dx.r,De.r|ACe.r */
- ll = parse_dsp_reg (l, ®s[2], FALSE, FALSE);
+ ll = parse_dsp_reg (l, ®s[2], false, false);
if (ll != NULL)
{
l = ll;
om_shift = 3;
ar_shift = 7;
- ar = TRUE;
+ ar = true;
}
else
{
/* De.r,Dx.r,De.r */
- l = __parse_gp_reg (l, ®s[2], TRUE);
+ l = __parse_gp_reg (l, ®s[2], true);
if (l == NULL)
return NULL;
}
return NULL;
}
- l = __parse_gp_reg (l, ®s[3], TRUE);
+ l = __parse_gp_reg (l, ®s[3], true);
if (l == NULL)
{
as_bad (_("invalid fourth register"));
/* Group 2. */
if (template->arg_type & DSP_ARGS_2)
{
- bfd_boolean is_xsd = (MAJOR_OPCODE (template->meta_opcode) == OPC_MISC
- && MINOR_OPCODE (template->meta_opcode) == 0xa);
- bfd_boolean is_fpu_mov = template->insn_type == INSN_DSP_FPU;
- bfd_boolean to_fpu = ((template->meta_opcode >> 7) & 0x1) != 0;
+ bool is_xsd = (MAJOR_OPCODE (template->meta_opcode) == OPC_MISC
+ && MINOR_OPCODE (template->meta_opcode) == 0xa);
+ bool is_fpu_mov = template->insn_type == INSN_DSP_FPU;
+ bool to_fpu = ((template->meta_opcode >> 7) & 0x1) != 0;
if (is_xsd)
du_shift = 0;
/* DSPe.r,Dx.r or DSPx.r,#I16 */
if (template->arg_type & DSP_ARGS_DSP_SRC1)
{
- l = parse_dsp_reg (l, regs, FALSE, FALSE);
+ l = parse_dsp_reg (l, regs, false, false);
if (l == NULL)
{
as_bad (_("invalid register operand #1"));
l1_shift = 4;
}
- ll = __parse_gp_reg (l, ®s[1], TRUE);
+ ll = __parse_gp_reg (l, ®s[1], true);
if (ll == NULL)
{
if (template->arg_type & DSP_ARGS_DSP_SRC2)
{
- l = parse_dsp_reg (l, ®s[1], FALSE, FALSE);
+ l = parse_dsp_reg (l, ®s[1], false, false);
if (l == NULL)
{
as_bad (_("invalid register operand #3"));
du_shift = 24;
l1_shift = 4;
- l = __parse_gp_reg (l, regs, FALSE);
+ l = __parse_gp_reg (l, regs, false);
if (l == NULL)
{
as_bad (_("invalid register operand"));
if (*l == 'A')
{
- l = parse_dsp_reg (l, ®s[1], FALSE, FALSE);
+ l = parse_dsp_reg (l, ®s[1], false, false);
if (l == NULL)
{
as_bad (_("invalid accumulator register"));
}
else
{
- l = __parse_gp_reg (l, ®s[1], TRUE);
+ l = __parse_gp_reg (l, ®s[1], true);
if (l == NULL)
{
as_bad (_("invalid register operand"));
else
{
regs_shift[2] = 9;
- l = __parse_gp_reg (l, ®s[2], TRUE);
+ l = __parse_gp_reg (l, ®s[2], true);
if (l == NULL)
return NULL;
}
};
/* Parse a CPU command line option. */
-static bfd_boolean
+static bool
metag_parse_cpu (const char * str)
{
const struct metag_core_option * opt;
}
/* Parse an FPU command line option. */
-static bfd_boolean
+static bool
metag_parse_fpu (const char * str)
{
const struct metag_core_option * opt;
}
/* Parse a DSP command line option. */
-static bfd_boolean
+static bool
metag_parse_dsp (const char * str)
{
const struct metag_core_option * opt;
{
const char *option; /* Substring to match. */
const char *help; /* Help information. */
- bfd_boolean (*func) (const char *subopt); /* Function to decode sub-option. */
+ bool (*func) (const char *subopt); /* Function to decode sub-option. */
const char *deprecated; /* If non-null, print this message. */
};
}
/* Entry point for instruction parsing. */
-static bfd_boolean
+static bool
parse_insn (const char *line, metag_insn *insn)
{
char mnemonic[MAX_MNEMONIC_LEN];
if (mnemonic_len >= MAX_MNEMONIC_LEN)
{
as_bad (_("instruction mnemonic too long: %s"), line);
- return FALSE;
+ return false;
}
strncpy(mnemonic, line, mnemonic_len);
if (*end != END_OF_INSN)
as_bad (_("junk at end of line: \"%s\""), line);
else
- return TRUE;
+ return true;
}
}
}
else
as_bad (_("unknown mnemonic: \"%s\""), mnemonic);
}
- return FALSE;
+ return false;
}
static void
return generic_force_reloc (fix);
}
-bfd_boolean
+bool
metag_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
case BFD_RELOC_METAG_LOADDR16:
case BFD_RELOC_VTABLE_INHERIT:
case BFD_RELOC_VTABLE_ENTRY:
- fixP->fx_done = FALSE;
+ fixP->fx_done = false;
break;
case BFD_RELOC_METAG_REL8:
}
if (fixP->fx_addsy == NULL)
- fixP->fx_done = TRUE;
+ fixP->fx_done = true;
}
#define MD_APPLY_SYM_VALUE(FIX) 0
#define tc_fix_adjustable(FIX) metag_fix_adjustable (FIX)
-extern bfd_boolean metag_fix_adjustable (struct fix *);
+extern bool metag_fix_adjustable (struct fix *);
#define TC_FORCE_RELOCATION(fix) metag_force_relocation (fix)
extern int metag_force_relocation (struct fix *);
#define OPTION_EL (OPTION_MD_BASE + 1)
void microblaze_generate_symbol (char *sym);
-static bfd_boolean check_spl_reg (unsigned *);
+static bool check_spl_reg (unsigned *);
/* Several places in this file insert raw instructions into the
object. They should generate the instruction
static const char * str_microblaze_ro_anchor = "RO";
static const char * str_microblaze_rw_anchor = "RW";
-static bfd_boolean
+static bool
check_spl_reg (unsigned * reg)
{
if ((*reg == REG_MSR) || (*reg == REG_PC)
|| (*reg == REG_TLBHI) || (*reg == REG_TLBSX)
|| (*reg == REG_SHR) || (*reg == REG_SLR)
|| (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Here we decide which fixups can be adjusted to make them relative to
{
case UNDEFINED_PC_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, TRUE, BFD_RELOC_64_PCREL);
+ fragP->fr_offset, true, BFD_RELOC_64_PCREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case DEFINED_ABS_SEGMENT:
if (fragP->fr_symbol == GOT_symbol)
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC);
+ fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GOTPC);
else
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_64);
+ fragP->fr_offset, false, BFD_RELOC_64);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case DEFINED_RO_SEGMENT:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_32_ROSDA);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_32_ROSDA);
fragP->fr_fix += INST_WORD_SIZE;
fragP->fr_var = 0;
break;
case DEFINED_RW_SEGMENT:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_32_RWSDA);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_32_RWSDA);
fragP->fr_fix += INST_WORD_SIZE;
fragP->fr_var = 0;
break;
case DEFINED_PC_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
- fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_32_LO_PCREL);
+ fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_32_LO_PCREL);
fragP->fr_fix += INST_WORD_SIZE;
fragP->fr_var = 0;
break;
case LARGE_DEFINED_PC_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, TRUE, BFD_RELOC_64_PCREL);
+ fragP->fr_offset, true, BFD_RELOC_64_PCREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case GOT_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GOT);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_GOT);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TEXT_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TEXTREL);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TEXTREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TEXT_PC_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TEXTPCREL);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TEXTPCREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case PLT_OFFSET:
fixP = fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PLT);
+ fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_PLT);
/* fixP->fx_plt = 1; */
(void) fixP;
fragP->fr_fix += INST_WORD_SIZE * 2;
break;
case GOTOFF_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GOTOFF);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_GOTOFF);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TLSGD_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TLSGD);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TLSGD);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TLSLD_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TLSLD);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TLSLD);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
case TLSDTPREL_OFFSET:
fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_TLSDTPREL);
+ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_TLSDTPREL);
fragP->fr_fix += INST_WORD_SIZE * 2;
fragP->fr_var = 0;
break;
linker doesn't know about and discards them, but relocations against them
remain, leading to rld crashes. */
#ifdef TE_IRIX
-int mips_flag_pdr = FALSE;
+int mips_flag_pdr = false;
#else
-int mips_flag_pdr = TRUE;
+int mips_flag_pdr = true;
#endif
#include "ecoff.h"
static enum mips_abi_level mips_abi = NO_ABI;
/* Whether or not we have code that can call pic code. */
-int mips_abicalls = FALSE;
+int mips_abicalls = false;
/* Whether or not we have code which can be put into a shared
library. */
-static bfd_boolean mips_in_shared = TRUE;
+static bool mips_in_shared = true;
/* This is the set of options which may be modified by the .set
pseudo-op. We use a struct so that .set push and .set pop are more
/* True if we should only emit 32-bit microMIPS instructions.
Changed by `.set insn32' and `.set noinsn32', and the -minsn32
and -mno-insn32 command line options. */
- bfd_boolean insn32;
+ bool insn32;
/* Restrict general purpose registers and floating point registers
to 32 bit. This is initially determined when -mgp32 or -mfp32
is passed but can changed if the assembler code uses .set mipsN. */
command line option, and the default CPU. */
int arch;
/* True if ".set sym32" is in effect. */
- bfd_boolean sym32;
+ bool sym32;
/* True if floating-point operations are not allowed. Changed by .set
softfloat or .set hardfloat, by command line options -msoft-float or
-mhard-float. The default is false. */
- bfd_boolean soft_float;
+ bool soft_float;
/* True if only single-precision floating-point operations are allowed.
Changed by .set singlefloat or .set doublefloat, command-line options
-msingle-float or -mdouble-float. The default is false. */
- bfd_boolean single_float;
+ bool single_float;
/* 1 if single-precision operations on odd-numbered registers are
allowed. */
};
/* Specifies whether module level options have been checked yet. */
-static bfd_boolean file_mips_opts_checked = FALSE;
+static bool file_mips_opts_checked = false;
/* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
value has not been initialized. Changed by `.nan legacy' and
{
/* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
/* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
- /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
- /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
- /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1,
+ /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
+ /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ false,
+ /* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
/* init_ase */ 0
};
{
/* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
/* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
- /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
- /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
- /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1,
+ /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
+ /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ false,
+ /* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
/* init_ase */ 0
};
};
/* ...likewise -mfix-loongson2f-jump. */
-static bfd_boolean mips_fix_loongson2f_jump;
+static bool mips_fix_loongson2f_jump;
/* ...likewise -mfix-loongson2f-nop. */
-static bfd_boolean mips_fix_loongson2f_nop;
+static bool mips_fix_loongson2f_nop;
/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
-static bfd_boolean mips_fix_loongson2f;
+static bool mips_fix_loongson2f;
/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
there must be at least one other instruction between an instruction
static int mips_fix_rm7000;
/* ...likewise -mfix-cn63xxp1 */
-static bfd_boolean mips_fix_cn63xxp1;
+static bool mips_fix_cn63xxp1;
/* ...likewise -mfix-r5900 */
-static bfd_boolean mips_fix_r5900;
-static bfd_boolean mips_fix_r5900_explicit;
+static bool mips_fix_r5900;
+static bool mips_fix_r5900_explicit;
/* ...likewise -mfix-loongson3-llsc. */
-static bfd_boolean mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC;
+static bool mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC;
/* We don't relax branches by default, since this causes us to expand
`la .l2 - .l1' if there's a branch between .l1 and .l2, because we
/* TRUE if checks are suppressed for invalid branches between ISA modes.
Needed for broken assembly produced by some GCC versions and some
sloppy code out there, where branches to data labels are present. */
-static bfd_boolean mips_ignore_branch_isa;
+static bool mips_ignore_branch_isa;
\f
/* The expansion of many macros depends on the type of symbol that
they refer to. For example, when generating position-dependent code,
#define MIPS16_EXTEND (0xf000U << 16)
\f
/* Whether or not we are emitting a branch-likely macro. */
-static bfd_boolean emit_branch_likely_macro = FALSE;
+static bool emit_branch_likely_macro = false;
/* Global variables used when generating relaxable macros. See the
comment above RELAX_ENCODE for more details about how relaxation
/* Global variables used to decide whether a macro needs a warning. */
static struct {
/* True if the macro is in a branch delay slot. */
- bfd_boolean delay_slot_p;
+ bool delay_slot_p;
/* Set to the length in bytes required if the macro is in a delay slot
that requires a specific length of instruction, otherwise zero. */
static void append_insn
(struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
- bfd_boolean expansionp);
+ bool expansionp);
static void mips_no_prev_insn (void);
static void macro_build (expressionS *, const char *, const char *, ...);
static void mips16_macro_build
static void s_mips_weakext (int);
static void s_mips_file (int);
static void s_mips_loc (int);
-static bfd_boolean pic_need_relax (symbolS *);
+static bool pic_need_relax (symbolS *);
static int relaxed_branch_length (fragS *, asection *, int);
static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
/* True if we are assembling an instruction. All dot symbols defined during
this time should be treated as code labels. */
-static bfd_boolean mips_assembling_insn;
+static bool mips_assembling_insn;
/* The pdr segment for per procedure frame/regmask info. Not used for
ECOFF debugging. */
static unsigned int
mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
- bfd_boolean enabled_p)
+ bool enabled_p)
{
unsigned int mask;
of MSG. Return true if MSG was used, false if the current message
was kept. */
-static bfd_boolean
+static bool
set_insn_error_format (int argnum, enum mips_insn_error_format format,
const char *msg)
{
/* Give priority to errors against specific arguments, and to
the first whole-instruction message. */
if (insn_error.msg)
- return FALSE;
+ return false;
}
else
{
/* Keep insn_error if it is against a later argument. */
if (argnum < insn_error.min_argnum)
- return FALSE;
+ return false;
/* If both errors are against the same argument but are different,
give up on reporting a specific error for this argument.
{
insn_error.msg = 0;
insn_error.min_argnum += 1;
- return FALSE;
+ return false;
}
}
insn_error.min_argnum = argnum;
insn_error.format = format;
insn_error.msg = msg;
- return TRUE;
+ return true;
}
/* Record an instruction error with no % format fields. ARGNUM and MSG are
/* Return true if string [S, E) is a valid register name, storing its
symbol value in *SYMVAL_PTR if so. */
-static bfd_boolean
+static bool
mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
{
char save_c;
*e = save_c;
if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
- return FALSE;
+ return false;
*symval_ptr = S_GET_VALUE (symbol);
- return TRUE;
+ return true;
}
/* Return true if the string at *SPTR is a valid register name. Allow it
number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
-static bfd_boolean
+static bool
mips_parse_register (char **sptr, unsigned int *symval_ptr,
unsigned int *channels_ptr)
{
if (!mips_parse_register_1 (s, e, &symval))
{
if (!channels_ptr)
- return FALSE;
+ return false;
/* Eat characters from the end of the string that are valid
channel suffixes. The preceding register must be $ACC or
if (channels == 0
|| !mips_parse_register_1 (s, m, &symval)
|| (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
- return FALSE;
+ return false;
}
*sptr = e;
*symval_ptr = symval;
if (channels_ptr)
*channels_ptr = channels;
- return TRUE;
+ return true;
}
/* Check if SPTR points at a valid register specifier according to TYPES.
{
struct mips_operand_token token;
unsigned int regno, channels;
- bfd_boolean decrement_p;
+ bool decrement_p;
if (*s != '(')
return 0;
/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
-static bfd_boolean
+static bool
is_opcode_valid (const struct mips_opcode *mo)
{
int isa = mips_opts.isa;
ase |= mips_ases[i].flags64;
if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
- return FALSE;
+ return false;
/* Check whether the instruction or macro requires single-precision or
double-precision floating-point support. Note that this information is
}
if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
- return FALSE;
+ return false;
if (fp_s && mips_opts.soft_float)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Return TRUE if the MIPS16 opcode MO is valid on the currently
selected ISA and architecture. */
-static bfd_boolean
+static bool
is_opcode_valid_16 (const struct mips_opcode *mo)
{
int isa = mips_opts.isa;
explicitly requested. Always TRUE in the standard MIPS mode.
Use is_size_valid_16 for MIPS16 opcodes. */
-static bfd_boolean
+static bool
is_size_valid (const struct mips_opcode *mo)
{
if (!mips_opts.micromips)
- return TRUE;
+ return true;
if (mips_opts.insn32)
{
if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
- return FALSE;
+ return false;
if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
- return FALSE;
+ return false;
}
if (!forced_insn_length)
- return TRUE;
+ return true;
if (mo->pinfo == INSN_MACRO)
- return FALSE;
+ return false;
return forced_insn_length == micromips_insn_length (mo);
}
/* Return TRUE if the size of the MIPS16 opcode MO matches one
explicitly requested. */
-static bfd_boolean
+static bool
is_size_valid_16 (const struct mips_opcode *mo)
{
if (!forced_insn_length)
- return TRUE;
+ return true;
if (mo->pinfo == INSN_MACRO)
- return FALSE;
+ return false;
if (forced_insn_length == 2 && mips_opcode_32bit_p (mo))
- return FALSE;
+ return false;
if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY))
- return FALSE;
- return TRUE;
+ return false;
+ return true;
}
/* Return TRUE if the microMIPS opcode MO is valid for the delay slot
second pass where the size of the delay slot is ignored and therefore
produce correct code. */
-static bfd_boolean
+static bool
is_delay_slot_valid (const struct mips_opcode *mo)
{
if (!mips_opts.micromips)
- return TRUE;
+ return true;
if (mo->pinfo == INSN_MACRO)
return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
&& micromips_insn_length (mo) != 4)
- return FALSE;
+ return false;
if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
&& micromips_insn_length (mo) != 2)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* For consistency checking, verify that all bits of OPCODE are specified
/* Perform consistency checks on the current options. */
static void
-mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
+mips_check_options (struct mips_set_options *opts, bool abi_checks)
{
/* Check the size of integer registers agrees with the ABI and ISA. */
if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
mips_opts = file_mips_opts;
mips_check_isa_supports_ases ();
- mips_check_options (&file_mips_opts, TRUE);
- file_mips_opts_checked = TRUE;
+ mips_check_options (&file_mips_opts, true);
+ file_mips_opts_checked = true;
if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
as_warn (_("could not set architecture and machine"));
offset_reloc[2] = BFD_RELOC_UNUSED;
mips_mark_labels ();
- mips_assembling_insn = TRUE;
+ mips_assembling_insn = true;
clear_insn_error ();
if (mips_opts.mips16)
else
{
if (offset_expr.X_op != O_absent)
- append_insn (&insn, &offset_expr, offset_reloc, FALSE);
+ append_insn (&insn, &offset_expr, offset_reloc, false);
else
- append_insn (&insn, NULL, unused_reloc, FALSE);
+ append_insn (&insn, NULL, unused_reloc, false);
}
- mips_assembling_insn = FALSE;
+ mips_assembling_insn = false;
}
/* Convenience functions for abstracting away the differences between
MIPS16 and non-MIPS16 relocations. */
-static inline bfd_boolean
+static inline bool
mips16_reloc_p (bfd_reloc_code_real_type reloc)
{
switch (reloc)
case BFD_RELOC_MIPS16_HI16:
case BFD_RELOC_MIPS16_LO16:
case BFD_RELOC_MIPS16_16_PCREL_S1:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
-static inline bfd_boolean
+static inline bool
micromips_reloc_p (bfd_reloc_code_real_type reloc)
{
switch (reloc)
case BFD_RELOC_MICROMIPS_HIGHER:
case BFD_RELOC_MICROMIPS_SCN_DISP:
case BFD_RELOC_MICROMIPS_JALR:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
-static inline bfd_boolean
+static inline bool
jmp_reloc_p (bfd_reloc_code_real_type reloc)
{
return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
}
-static inline bfd_boolean
+static inline bool
b_reloc_p (bfd_reloc_code_real_type reloc)
{
return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
|| reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
}
-static inline bfd_boolean
+static inline bool
got16_reloc_p (bfd_reloc_code_real_type reloc)
{
return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
|| reloc == BFD_RELOC_MICROMIPS_GOT16);
}
-static inline bfd_boolean
+static inline bool
hi16_reloc_p (bfd_reloc_code_real_type reloc)
{
return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
|| reloc == BFD_RELOC_MICROMIPS_HI16_S);
}
-static inline bfd_boolean
+static inline bool
lo16_reloc_p (bfd_reloc_code_real_type reloc)
{
return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
|| reloc == BFD_RELOC_MICROMIPS_LO16);
}
-static inline bfd_boolean
+static inline bool
jalr_reloc_p (bfd_reloc_code_real_type reloc)
{
return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
}
-static inline bfd_boolean
+static inline bool
gprel16_reloc_p (bfd_reloc_code_real_type reloc)
{
return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
/* Return true if RELOC is a PC-relative relocation that does not have
full address range. */
-static inline bfd_boolean
+static inline bool
limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
{
switch (reloc)
case BFD_RELOC_MIPS_26_PCREL_S2:
case BFD_RELOC_MIPS_18_PCREL_S3:
case BFD_RELOC_MIPS_19_PCREL_S2:
- return TRUE;
+ return true;
case BFD_RELOC_32_PCREL:
case BFD_RELOC_HI16_S_PCREL:
return HAVE_64BIT_ADDRESSES;
default:
- return FALSE;
+ return false;
}
}
This is only "might" because SVR4 R_MIPS_GOT16 relocations only
need a matching %lo() when applied to local symbols. */
-static inline bfd_boolean
+static inline bool
reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
{
return (HAVE_IN_PLACE_ADDENDS
/* Return true if the given fixup is followed by a matching R_MIPS_LO16
relocation. */
-static inline bfd_boolean
+static inline bool
fixup_has_matching_lo_p (fixS *fixp)
{
return (fixp->fx_next != NULL
says whether the labels refer to text or data. */
static void
-mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
+mips_move_labels (struct insn_label_list *labels, bool text_p)
{
struct insn_label_list *l;
valueT val;
static void
mips_move_text_labels (void)
{
- mips_move_labels (seg_info (now_seg)->label_list, TRUE);
+ mips_move_labels (seg_info (now_seg)->label_list, true);
}
/* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
-static bfd_boolean
+static bool
s_is_linkonce (symbolS *sym, segT from_seg)
{
- bfd_boolean linkonce = FALSE;
+ bool linkonce = false;
segT symseg = S_GET_SEGMENT (sym);
if (symseg != from_seg && !S_IS_LOCAL (sym))
{
if ((bfd_section_flags (symseg) & SEC_LINK_ONCE))
- linkonce = TRUE;
+ linkonce = true;
/* The GNU toolchain uses an extension for ELF: a section
beginning with the magic string .gnu.linkonce is a
linkonce section. */
if (strncmp (segment_name (symseg), ".gnu.linkonce",
sizeof ".gnu.linkonce" - 1) == 0)
- linkonce = TRUE;
+ linkonce = true;
}
return linkonce;
}
/* Return true if IP is a delayed branch or jump. */
-static inline bfd_boolean
+static inline bool
delayed_branch_p (const struct mips_cl_insn *ip)
{
return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
/* Return true if IP is a compact branch or jump. */
-static inline bfd_boolean
+static inline bool
compact_branch_p (const struct mips_cl_insn *ip)
{
return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
/* Return true if IP is an unconditional branch or jump. */
-static inline bfd_boolean
+static inline bool
uncond_branch_p (const struct mips_cl_insn *ip)
{
return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
/* Return true if IP is a branch-likely instruction. */
-static inline bfd_boolean
+static inline bool
branch_likely_p (const struct mips_cl_insn *ip)
{
return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
/* Operand OPNUM of INSN is an odd-numbered floating-point register.
Check whether that is allowed. */
-static bfd_boolean
+static bool
mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
{
const char *s = insn->name;
- bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
- || FPR_SIZE == 64)
- && mips_opts.oddspreg;
+ bool oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
+ || FPR_SIZE == 64) && mips_opts.oddspreg;
if (insn->pinfo == INSN_MACRO)
/* Let a macro pass, we'll catch it later when it is expanded. */
- return TRUE;
+ return true;
/* Single-precision coprocessor loads and moves are OK for 32-bit registers,
otherwise it depends on oddspreg. */
alternative matches and should therefore be as accommodating as
possible. Match routines should not report errors if something
is only invalid for !LAX_MATCH. */
- bfd_boolean lax_match;
+ bool lax_match;
/* True if a reference to the current AT register was seen. */
- bfd_boolean seen_at;
+ bool seen_at;
};
/* Record that the argument is out of range. */
/* Try to match an OT_CHAR token for character CH. Consume the token
and return true on success, otherwise return false. */
-static bfd_boolean
+static bool
match_char (struct mips_arg_info *arg, char ch)
{
if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
++arg->token;
if (ch == ',')
arg->argnum += 1;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Try to get an expression from the next tokens in ARG. Consume the
tokens and return true on success, storing the expression value in
VALUE and relocation types in R. */
-static bfd_boolean
+static bool
match_expression (struct mips_arg_info *arg, expressionS *value,
bfd_reloc_code_real_type *r)
{
value->X_op = O_constant;
value->X_add_number = 0;
r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
- return TRUE;
+ return true;
}
/* Reject register-based expressions such as "0+$2" and "(($2))".
&& arg->token->u.integer.value.X_op == O_register)
{
set_insn_error (arg->argnum, _("register value used as expression"));
- return FALSE;
+ return false;
}
if (arg->token->type == OT_INTEGER)
*value = arg->token->u.integer.value;
memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
++arg->token;
- return TRUE;
+ return true;
}
set_insn_error_i
(arg->argnum, _("operand %d must be an immediate expression"),
arg->argnum);
- return FALSE;
+ return false;
}
/* Try to get a constant expression from the next tokens in ARG. Consume
the tokens and return true on success, storing the constant value
in *VALUE. */
-static bfd_boolean
+static bool
match_const_int (struct mips_arg_info *arg, offsetT *value)
{
expressionS ex;
bfd_reloc_code_real_type r[3];
if (!match_expression (arg, &ex, r))
- return FALSE;
+ return false;
if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
*value = ex.X_add_number;
match_out_of_range (arg);
else
match_not_constant (arg);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Return the RTYPE_* flags for a register operand of type TYPE that
enum mips_reg_operand_type type, unsigned int regno)
{
if (AT && type == OP_REG_GP && regno == AT)
- arg->seen_at = TRUE;
+ arg->seen_at = true;
if (type == OP_REG_FP
&& (regno & 1) != 0
a register of type TYPE. Return true on success, storing the register
number in *REGNO and warning about any dubious uses. */
-static bfd_boolean
+static bool
match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
unsigned int symval, unsigned int *regno)
{
if (type == OP_REG_VEC)
symval = mips_prefer_vec_regno (symval);
if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
- return FALSE;
+ return false;
*regno = symval & RNUM_MASK;
check_regno (arg, type, *regno);
- return TRUE;
+ return true;
}
/* Try to interpret the next token in ARG as a register of type TYPE.
Consume the token and return true on success, storing the register
number in *REGNO. Return false on failure. */
-static bfd_boolean
+static bool
match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
unsigned int *regno)
{
&& match_regno (arg, type, arg->token->u.regno, regno))
{
++arg->token;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Try to interpret the next token in ARG as a range of registers of type TYPE.
Consume the token and return true on success, storing the register numbers
in *REGNO1 and *REGNO2. Return false on failure. */
-static bfd_boolean
+static bool
match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
unsigned int *regno1, unsigned int *regno2)
{
if (match_reg (arg, type, regno1))
{
*regno2 = *regno1;
- return TRUE;
+ return true;
}
if (arg->token->type == OT_REG_RANGE
&& match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
&& *regno1 <= *regno2)
{
++arg->token;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* OP_INT matcher. */
-static bfd_boolean
+static bool
match_int_operand (struct mips_arg_info *arg,
const struct mips_operand *operand_base)
{
{
/* The operand can be relocated. */
if (!match_expression (arg, &offset_expr, offset_reloc))
- return FALSE;
+ return false;
if (offset_expr.X_op == O_big)
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
if (offset_reloc[0] != BFD_RELOC_UNUSED)
/* Relocation operators were used. Accept the argument and
leave the relocation value in offset_expr and offset_relocs
for the caller to process. */
- return TRUE;
+ return true;
if (offset_expr.X_op != O_constant)
{
if (!arg->lax_match)
{
match_not_constant (arg);
- return FALSE;
+ return false;
}
offset_reloc[0] = BFD_RELOC_LO16;
- return TRUE;
+ return true;
}
/* Clear the global state; we're going to install the operand
if (!arg->lax_match && sval <= max_val)
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
}
}
else
{
if (!match_const_int (arg, &sval))
- return FALSE;
+ return false;
}
arg->last_op_int = sval;
if (sval < min_val || sval > max_val || sval % factor)
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
uval = (unsigned int) sval >> operand->shift;
}
insn_insert_operand (arg->insn, operand_base, uval);
- return TRUE;
+ return true;
}
/* OP_MAPPED_INT matcher. */
-static bfd_boolean
+static bool
match_mapped_int_operand (struct mips_arg_info *arg,
const struct mips_operand *operand_base)
{
operand = (const struct mips_mapped_int_operand *) operand_base;
if (!match_const_int (arg, &sval))
- return FALSE;
+ return false;
num_vals = 1 << operand_base->size;
for (uval = 0; uval < num_vals; uval++)
if (uval == num_vals)
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
insn_insert_operand (arg->insn, operand_base, uval);
- return TRUE;
+ return true;
}
/* OP_MSB matcher. */
-static bfd_boolean
+static bool
match_msb_operand (struct mips_arg_info *arg,
const struct mips_operand *operand_base)
{
max_high = operand->opsize;
if (!match_const_int (arg, &size))
- return FALSE;
+ return false;
high = size + arg->last_op_int;
sval = operand->add_lsb ? high : size;
if (size < 0 || high > max_high || sval < min_val || sval > max_val)
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
insn_insert_operand (arg->insn, operand_base, sval - min_val);
- return TRUE;
+ return true;
}
/* OP_REG matcher. */
-static bfd_boolean
+static bool
match_reg_operand (struct mips_arg_info *arg,
const struct mips_operand *operand_base)
{
operand = (const struct mips_reg_operand *) operand_base;
if (!match_reg (arg, operand->reg_type, ®no))
- return FALSE;
+ return false;
if (operand->reg_map)
{
if (operand->reg_map[uval] == regno)
break;
if (num_vals == uval)
- return FALSE;
+ return false;
}
else
uval = regno;
if (arg->opnum == 1)
arg->dest_regno = regno;
insn_insert_operand (arg->insn, operand_base, uval);
- return TRUE;
+ return true;
}
/* OP_REG_PAIR matcher. */
-static bfd_boolean
+static bool
match_reg_pair_operand (struct mips_arg_info *arg,
const struct mips_operand *operand_base)
{
if (!match_reg (arg, operand->reg_type, ®no1)
|| !match_char (arg, ',')
|| !match_reg (arg, operand->reg_type, ®no2))
- return FALSE;
+ return false;
num_vals = 1 << operand_base->size;
for (uval = 0; uval < num_vals; uval++)
if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
break;
if (uval == num_vals)
- return FALSE;
+ return false;
insn_insert_operand (arg->insn, operand_base, uval);
- return TRUE;
+ return true;
}
/* OP_PCREL matcher. The caller chooses the relocation type. */
-static bfd_boolean
+static bool
match_pcrel_operand (struct mips_arg_info *arg)
{
bfd_reloc_code_real_type r[3];
/* OP_PERF_REG matcher. */
-static bfd_boolean
+static bool
match_perf_reg_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
offsetT sval;
if (!match_const_int (arg, &sval))
- return FALSE;
+ return false;
if (sval != 0
&& (sval != 1
|| strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
{
set_insn_error (arg->argnum, _("invalid performance register"));
- return FALSE;
+ return false;
}
insn_insert_operand (arg->insn, operand, sval);
- return TRUE;
+ return true;
}
/* OP_ADDIUSP matcher. */
-static bfd_boolean
+static bool
match_addiusp_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
unsigned int uval;
if (!match_const_int (arg, &sval))
- return FALSE;
+ return false;
if (sval % 4)
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
sval /= 4;
if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
uval = (unsigned int) sval;
uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
insn_insert_operand (arg->insn, operand, uval);
- return TRUE;
+ return true;
}
/* OP_CLO_CLZ_DEST matcher. */
-static bfd_boolean
+static bool
match_clo_clz_dest_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
unsigned int regno;
if (!match_reg (arg, OP_REG_GP, ®no))
- return FALSE;
+ return false;
insn_insert_operand (arg->insn, operand, regno | (regno << 5));
- return TRUE;
+ return true;
}
/* OP_CHECK_PREV matcher. */
-static bfd_boolean
+static bool
match_check_prev_operand (struct mips_arg_info *arg,
const struct mips_operand *operand_base)
{
operand = (const struct mips_check_prev_operand *) operand_base;
if (!match_reg (arg, OP_REG_GP, ®no))
- return FALSE;
+ return false;
if (!operand->zero_ok && regno == 0)
- return FALSE;
+ return false;
if ((operand->less_than_ok && regno < arg->last_regno)
|| (operand->greater_than_ok && regno > arg->last_regno)
{
arg->last_regno = regno;
insn_insert_operand (arg->insn, operand_base, regno);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* OP_SAME_RS_RT matcher. */
-static bfd_boolean
+static bool
match_same_rs_rt_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
unsigned int regno;
if (!match_reg (arg, OP_REG_GP, ®no))
- return FALSE;
+ return false;
if (regno == 0)
{
set_insn_error (arg->argnum, _("the source register must not be $0"));
- return FALSE;
+ return false;
}
arg->last_regno = regno;
insn_insert_operand (arg->insn, operand, regno | (regno << 5));
- return TRUE;
+ return true;
}
/* OP_LWM_SWM_LIST matcher. */
-static bfd_boolean
+static bool
match_lwm_swm_list_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
reglist = 0;
if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
- return FALSE;
+ return false;
do
{
if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
and any permutations of these. */
if ((reglist & 0xfff1ffff) != 0x80010000)
- return FALSE;
+ return false;
sregs = (reglist >> 17) & 7;
ra = 0;
and any permutations of these. */
if ((reglist & 0x3f00ffff) != 0)
- return FALSE;
+ return false;
ra = (reglist >> 27) & 0x10;
sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
}
sregs += 1;
if ((sregs & -sregs) != sregs)
- return FALSE;
+ return false;
insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
- return TRUE;
+ return true;
}
/* OP_ENTRY_EXIT_LIST matcher. */
const struct mips_operand *operand)
{
unsigned int mask;
- bfd_boolean is_exit;
+ bool is_exit;
/* The format is the same for both ENTRY and EXIT, but the constraints
are different. */
do
{
unsigned int regno1, regno2;
- bfd_boolean is_freg;
+ bool is_freg;
if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
- is_freg = FALSE;
+ is_freg = false;
else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
- is_freg = TRUE;
+ is_freg = true;
else
- return FALSE;
+ return false;
if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
{
else if (regno1 == RA && regno2 == RA)
mask |= 1;
else
- return FALSE;
+ return false;
}
while (match_char (arg, ','));
insn_insert_operand (arg->insn, operand, mask);
- return TRUE;
+ return true;
}
/* Encode regular MIPS SAVE/RESTORE instruction operands according to
/* OP_SAVE_RESTORE_LIST matcher. */
-static bfd_boolean
+static bool
match_save_restore_list_operand (struct mips_arg_info *arg)
{
unsigned int opcode, args, statics, sregs;
{
/* Handle the frame size. */
if (!match_const_int (arg, &frame_size))
- return FALSE;
+ return false;
num_frame_sizes += 1;
}
else
{
if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
- return FALSE;
+ return false;
while (regno1 <= regno2)
{
/* Add $ra to insn. */
ra = 1;
else
- return FALSE;
+ return false;
regno1 += 1;
if (regno1 == 24)
regno1 = 30;
/* Encode args/statics combination. */
if (args & statics)
- return FALSE;
+ return false;
else if (args == 0xf)
/* All $a0-$a3 are args. */
arg_mask = MIPS_SVRS_ALL_ARGS;
num_args += 1;
}
if (args != 0)
- return FALSE;
+ return false;
/* Count static registers. */
num_statics = 0;
num_statics += 1;
}
if (statics != 0)
- return FALSE;
+ return false;
/* Encode args/statics. */
arg_mask = (num_args << 2) | num_statics;
num_sregs += 1;
}
if (sregs != 0)
- return FALSE;
+ return false;
/* Encode frame size. */
if (num_frame_sizes == 0)
{
set_insn_error (arg->argnum, _("missing frame size"));
- return FALSE;
+ return false;
}
if (num_frame_sizes > 1)
{
set_insn_error (arg->argnum, _("frame size specified twice"));
- return FALSE;
+ return false;
}
if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
{
set_insn_error (arg->argnum, _("invalid frame size"));
- return FALSE;
+ return false;
}
frame_size /= 8;
abort ();
arg->insn->insn_opcode = opcode;
- return TRUE;
+ return true;
}
/* OP_MDMX_IMM_REG matcher. */
-static bfd_boolean
+static bool
match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
unsigned int regno, uval;
- bfd_boolean is_qh;
+ bool is_qh;
const struct mips_opcode *opcode;
/* The mips_opcode records whether this is an octobyte or quadhalf
{
set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
arg->argnum);
- return FALSE;
+ return false;
}
if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
- return FALSE;
+ return false;
++arg->token;
/* Check whether this is a vector register or a broadcast of
if (arg->token->u.index > (is_qh ? 3 : 7))
{
set_insn_error (arg->argnum, _("invalid element selector"));
- return FALSE;
+ return false;
}
uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
++arg->token;
{
set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
arg->argnum);
- return FALSE;
+ return false;
}
if (is_qh)
offsetT sval;
if (!match_const_int (arg, &sval))
- return FALSE;
+ return false;
if (sval < 0 || sval > 31)
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
uval |= (sval & 31);
if (is_qh)
uval |= MDMX_FMTSEL_IMM_OB << 5;
}
insn_insert_operand (arg->insn, operand, uval);
- return TRUE;
+ return true;
}
/* OP_IMM_INDEX matcher. */
-static bfd_boolean
+static bool
match_imm_index_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
unsigned int max_val;
if (arg->token->type != OT_INTEGER_INDEX)
- return FALSE;
+ return false;
max_val = (1 << operand->size) - 1;
if (arg->token->u.index > max_val)
{
match_out_of_range (arg);
- return FALSE;
+ return false;
}
insn_insert_operand (arg->insn, operand, arg->token->u.index);
++arg->token;
- return TRUE;
+ return true;
}
/* OP_REG_INDEX matcher. */
-static bfd_boolean
+static bool
match_reg_index_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
unsigned int regno;
if (arg->token->type != OT_REG_INDEX)
- return FALSE;
+ return false;
if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
- return FALSE;
+ return false;
insn_insert_operand (arg->insn, operand, regno);
++arg->token;
- return TRUE;
+ return true;
}
/* OP_PC matcher. */
-static bfd_boolean
+static bool
match_pc_operand (struct mips_arg_info *arg)
{
if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
{
++arg->token;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* OP_REG28 matcher. */
-static bfd_boolean
+static bool
match_reg28_operand (struct mips_arg_info *arg)
{
unsigned int regno;
&& regno == GP)
{
++arg->token;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* OP_NON_ZERO_REG matcher. */
-static bfd_boolean
+static bool
match_non_zero_reg_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
unsigned int regno;
if (!match_reg (arg, OP_REG_GP, ®no))
- return FALSE;
+ return false;
if (regno == 0)
{
set_insn_error (arg->argnum, _("the source register must not be $0"));
- return FALSE;
+ return false;
}
arg->last_regno = regno;
insn_insert_operand (arg->insn, operand, regno);
- return TRUE;
+ return true;
}
/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
register that we need to match. */
-static bfd_boolean
+static bool
match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
{
unsigned int regno;
any changes if the instruction does not match. We just match
unconditionally and report an error if the constant is invalid. */
-static bfd_boolean
+static bool
match_float_constant (struct mips_arg_info *arg, expressionS *imm,
- expressionS *offset, int length, bfd_boolean using_gprs)
+ expressionS *offset, int length, bool using_gprs)
{
char *p;
segT seg, new_seg;
if (arg->token->type != OT_FLOAT)
{
set_insn_error (arg->argnum, _("floating-point expression required"));
- return FALSE;
+ return false;
}
gas_assert (arg->token->u.flt.length == length);
else
imm->X_add_number = bfd_getb32 (data);
offset->X_op = O_absent;
- return TRUE;
+ return true;
}
/* Handle 64-bit constants for which an immediate value is best. */
imm->X_add_number = bfd_getb64 (data);
offset->X_op = O_absent;
}
- return TRUE;
+ return true;
}
/* Switch to the right section. */
/* Switch back to the original section. */
subseg_set (seg, subseg);
- return TRUE;
+ return true;
}
/* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
them. */
-static bfd_boolean
+static bool
match_vu0_suffix_operand (struct mips_arg_info *arg,
const struct mips_operand *operand,
- bfd_boolean match_p)
+ bool match_p)
{
unsigned int uval;
{
/* Check that a single bit is set and convert it into a 2-bit index. */
if ((uval & -uval) != uval)
- return FALSE;
+ return false;
uval = 4 - ffs (uval);
}
if (match_p && insn_extract_operand (arg->insn, operand) != uval)
- return FALSE;
+ return false;
++arg->token;
if (!match_p)
insn_insert_operand (arg->insn, operand, uval);
- return TRUE;
+ return true;
}
/* Try to match a token from ARG against OPERAND. Consume the token
and return true on success, otherwise return false. */
-static bfd_boolean
+static bool
match_operand (struct mips_arg_info *arg,
const struct mips_operand *operand)
{
return match_reg28_operand (arg);
case OP_VU0_SUFFIX:
- return match_vu0_suffix_operand (arg, operand, FALSE);
+ return match_vu0_suffix_operand (arg, operand, false);
case OP_VU0_MATCH_SUFFIX:
- return match_vu0_suffix_operand (arg, operand, TRUE);
+ return match_vu0_suffix_operand (arg, operand, true);
case OP_IMM_INDEX:
return match_imm_index_operand (arg, operand);
/* Return true if modifying general-purpose register REG needs a delay. */
-static bfd_boolean
+static bool
reg_needs_delay (unsigned int reg)
{
unsigned long prev_pinfo;
&& (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
|| ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
&& (gpr_write_mask (&history[0]) & (1 << reg)))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Classify an instruction according to the FIX_VR4120_* enumeration.
/* INSN is a store instruction. Try to record the store information
in STINFO. Return false if the information isn't known. */
-static bfd_boolean
+static bool
fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
const struct mips_cl_insn *insn)
{
/* The instruction must have a known offset. */
if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
- return FALSE;
+ return false;
stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
stinfo->align_to = fix_24k_align_to (insn->insn_mo);
- return TRUE;
+ return true;
}
/* Return the number of nops that would be needed to work around the 24k
fix_loongson2f_jump (ip);
}
-static bfd_boolean
+static bool
has_label_name (const char *arr[], size_t len ,const char *s)
{
unsigned long i;
for (i = 0; i < len; i++)
{
if (!arr[i])
- return FALSE;
+ return false;
if (streq (arr[i], s))
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Fix loongson3 llsc errata: Insert sync before ll/lld. */
ADDRESS_EXPR is an operand of the instruction to be used with
RELOC_TYPE. */
-static bfd_boolean
+static bool
can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
bfd_reloc_code_real_type *reloc_type)
{
/* -O2 and above is required for this optimization. */
if (mips_optimize < 2)
- return FALSE;
+ return false;
/* If we have seen .set volatile or .set nomove, don't optimize. */
if (mips_opts.nomove)
- return FALSE;
+ return false;
/* We can't swap if the previous instruction's position is fixed. */
if (history[0].fixed_p)
- return FALSE;
+ return false;
/* If the previous previous insn was in a .set noreorder, we can't
swap. Actually, the MIPS assembler will swap in this situation.
in which we can not swap the bne and INSN. If gcc is not configured
-with-gnu-as, it does not output the .set pseudo-ops. */
if (history[1].noreorder_p)
- return FALSE;
+ return false;
/* If the previous instruction had a fixup in mips16 mode, we can not swap.
This means that the previous instruction was a 4-byte one anyhow. */
if (mips_opts.mips16 && history[0].fixp[0])
- return FALSE;
+ return false;
/* If the branch is itself the target of a branch, we can not swap.
We cheat on this; all we check for is whether there is a label on
this instruction. If there are any branches to anything other than
a label, users must use .set noreorder. */
if (seg_info (now_seg)->label_list)
- return FALSE;
+ return false;
/* If the previous instruction is in a variant frag other than this
branch's one, we cannot do the swap. This does not apply to
if (!mips_opts.mips16
&& history[0].frag
&& history[0].frag->fr_type == rs_machine_dependent)
- return FALSE;
+ return false;
/* We do not swap with instructions that cannot architecturally
be placed in a branch delay slot, such as SYNC or ERET. We
a delay slot. */
prev_pinfo = history[0].insn_mo->pinfo;
if (prev_pinfo & INSN_NO_DELAY_SLOT)
- return FALSE;
+ return false;
/* Check for conflicts between the branch and the instructions
before the candidate delay slot. */
if (nops_for_insn (0, history + 1, ip) > 0)
- return FALSE;
+ return false;
/* Check for conflicts between the swapped sequence and the
target of the branch. */
if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
- return FALSE;
+ return false;
/* If the branch reads a register that the previous
instruction sets, we can not swap. */
gpr_read = gpr_read_mask (ip);
prev_gpr_write = gpr_write_mask (&history[0]);
if (gpr_read & prev_gpr_write)
- return FALSE;
+ return false;
fpr_read = fpr_read_mask (ip);
prev_fpr_write = fpr_write_mask (&history[0]);
if (fpr_read & prev_fpr_write)
- return FALSE;
+ return false;
/* If the branch writes a register that the previous
instruction sets, we can not swap. */
gpr_write = gpr_write_mask (ip);
if (gpr_write & prev_gpr_write)
- return FALSE;
+ return false;
/* If the branch writes a register that the previous
instruction reads, we can not swap. */
prev_gpr_read = gpr_read_mask (&history[0]);
if (gpr_write & prev_gpr_read)
- return FALSE;
+ return false;
/* If one instruction sets a condition code and the
other one uses a condition code, we can not swap. */
pinfo = ip->insn_mo->pinfo;
if ((pinfo & INSN_READ_COND_CODE)
&& (prev_pinfo & INSN_WRITE_COND_CODE))
- return FALSE;
+ return false;
if ((pinfo & INSN_WRITE_COND_CODE)
&& (prev_pinfo & INSN_READ_COND_CODE))
- return FALSE;
+ return false;
/* If the previous instruction uses the PC, we can not swap. */
prev_pinfo2 = history[0].insn_mo->pinfo2;
if (prev_pinfo2 & INSN2_READ_PC)
- return FALSE;
+ return false;
/* If the previous instruction has an incorrect size for a fixed
branch delay slot in microMIPS mode, we cannot swap. */
if (mips_opts.micromips
&& (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
&& insn_length (history) != 2)
- return FALSE;
+ return false;
if (mips_opts.micromips
&& (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
&& insn_length (history) != 4)
- return FALSE;
+ return false;
/* On the R5900 short loops need to be fixed by inserting a NOP in the
branch delay slot.
int i;
int rv;
- rv = FALSE;
+ rv = false;
/* When the loop includes branches or jumps,
it is not a short loop. */
for (i = 0; i < (distance / 4); i++)
if ((history[i].cleared_p)
|| delayed_branch_p (&history[i]))
{
- rv = TRUE;
+ rv = true;
break;
}
}
if (!rv)
{
/* Insert nop after branch to fix short loop. */
- return FALSE;
+ return false;
}
}
}
- return TRUE;
+ return true;
}
/* Decide how we should add IP to the instruction stream.
/* Try to resolve relocation RELOC against constant OPERAND at assembly time.
Return true on success, storing the resolved value in RESULT. */
-static bfd_boolean
+static bool
calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
offsetT *result)
{
case BFD_RELOC_MIPS_HIGHEST:
case BFD_RELOC_MICROMIPS_HIGHEST:
*result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
- return TRUE;
+ return true;
case BFD_RELOC_MIPS_HIGHER:
case BFD_RELOC_MICROMIPS_HIGHER:
*result = ((operand + 0x80008000ull) >> 32) & 0xffff;
- return TRUE;
+ return true;
case BFD_RELOC_HI16_S:
case BFD_RELOC_HI16_S_PCREL:
case BFD_RELOC_MICROMIPS_HI16_S:
case BFD_RELOC_MIPS16_HI16_S:
*result = ((operand + 0x8000) >> 16) & 0xffff;
- return TRUE;
+ return true;
case BFD_RELOC_HI16:
case BFD_RELOC_MICROMIPS_HI16:
case BFD_RELOC_MIPS16_HI16:
*result = (operand >> 16) & 0xffff;
- return TRUE;
+ return true;
case BFD_RELOC_LO16:
case BFD_RELOC_LO16_PCREL:
case BFD_RELOC_MICROMIPS_LO16:
case BFD_RELOC_MIPS16_LO16:
*result = operand & 0xffff;
- return TRUE;
+ return true;
case BFD_RELOC_UNUSED:
*result = operand;
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
static void
append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
- bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
+ bfd_reloc_code_real_type *reloc_type, bool expansionp)
{
unsigned long prev_pinfo2, pinfo;
- bfd_boolean relaxed_branch = FALSE;
+ bool relaxed_branch = false;
enum append_method method;
- bfd_boolean relax32;
+ bool relax32;
int branch_disp;
if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
&& *reloc_type == BFD_RELOC_16_PCREL_S2
&& delayed_branch_p (ip))
{
- relaxed_branch = TRUE;
+ relaxed_branch = true;
add_relaxed_insn (ip, (relaxed_branch_length
(NULL, NULL,
uncond_branch_p (ip) ? -1
16-bit/32-bit instructions. */
&& !forced_insn_length)
{
- bfd_boolean relax16 = (method != APPEND_ADD_COMPACT
- && *reloc_type > BFD_RELOC_UNUSED);
+ bool relax16 = (method != APPEND_ADD_COMPACT
+ && *reloc_type > BFD_RELOC_UNUSED);
int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
int uncond = uncond_branch_p (ip) ? -1 : 0;
int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
gas_assert (address_expr != NULL);
gas_assert (!mips_relax.sequence);
- relaxed_branch = TRUE;
+ relaxed_branch = true;
if (nods)
method = APPEND_ADD;
if (relax32)
}
else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
{
- bfd_boolean require_unextended;
- bfd_boolean require_extended;
+ bool require_unextended;
+ bool require_extended;
symbolS *symbol;
offsetT offset;
{
ip->fixp[i] = fix_new (ip->frag, ip->where,
ip->fixp[0]->fx_size, NULL, 0,
- FALSE, final_type[i]);
+ false, final_type[i]);
/* Use fx_tcbit to mark compound relocs. */
ip->fixp[0]->fx_tcbit = 1;
/* We need to emit a label at the end of branch-likely macros. */
if (emit_branch_likely_macro)
{
- emit_branch_likely_macro = FALSE;
+ emit_branch_likely_macro = false;
micromips_add_label ();
}
there are more alternatives after OPCODE and SOFT_MATCH is
as for mips_arg_info. */
-static bfd_boolean
+static bool
match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
struct mips_operand_token *tokens, unsigned int opcode_extra,
- bfd_boolean lax_match, bfd_boolean complete_p)
+ bool lax_match, bool complete_p)
{
const char *args;
struct mips_arg_info arg;
/* Fail the match if there were too few operands. */
if (*args)
- return FALSE;
+ return false;
/* Successful match. */
if (!complete_p)
- return TRUE;
+ return true;
clear_insn_error ();
if (arg.dest_regno == arg.last_regno
&& strncmp (insn->insn_mo->name, "jalr", 4) == 0)
|| strncmp (insn->insn_mo->name, "bgezal", 6) == 0))
set_insn_error (0, _("the source register must not be $31"));
check_completed_insn (&arg);
- return TRUE;
+ return true;
}
/* Fail the match if the line has too many operands. */
if (*args == 0)
- return FALSE;
+ return false;
/* Handle characters that need to match exactly. */
if (*args == '(' || *args == ')' || *args == ',')
{
if (match_char (&arg, *args))
continue;
- return FALSE;
+ return false;
}
if (*args == '#')
{
++arg.token;
continue;
}
- return FALSE;
+ return false;
}
/* Handle special macro operands. Work out the properties of
case 'I':
if (!match_const_int (&arg, &imm_expr.X_add_number))
- return FALSE;
+ return false;
imm_expr.X_op = O_constant;
if (GPR_SIZE == 32)
normalize_constant_expr (&imm_expr);
else
{
if (!match_expression (&arg, &offset_expr, offset_reloc))
- return FALSE;
+ return false;
normalize_address_expr (&offset_expr);
}
continue;
case 'F':
if (!match_float_constant (&arg, &imm_expr, &offset_expr,
- 8, TRUE))
- return FALSE;
+ 8, true))
+ return false;
continue;
case 'L':
if (!match_float_constant (&arg, &imm_expr, &offset_expr,
- 8, FALSE))
- return FALSE;
+ 8, false))
+ return false;
continue;
case 'f':
if (!match_float_constant (&arg, &imm_expr, &offset_expr,
- 4, TRUE))
- return FALSE;
+ 4, true))
+ return false;
continue;
case 'l':
if (!match_float_constant (&arg, &imm_expr, &offset_expr,
- 4, FALSE))
- return FALSE;
+ 4, false))
+ return false;
continue;
case 'p':
}
if (!match_operand (&arg, operand))
- return FALSE;
+ return false;
}
}
/* Like match_insn, but for MIPS16. */
-static bfd_boolean
+static bool
match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
struct mips_operand_token *tokens)
{
const char *args;
const struct mips_operand *operand;
const struct mips_operand *ext_operand;
- bfd_boolean pcrel = FALSE;
+ bool pcrel = false;
int required_insn_length;
struct mips_arg_info arg;
int relax_char;
The source is then the same as the destination. */
if (arg.opnum == 1 && *args == ',')
{
- operand = decode_mips16_operand (args[1], FALSE);
+ operand = decode_mips16_operand (args[1], false);
if (operand && mips_optional_operand_p (operand))
{
arg.token = tokens;
/* Fail the match if there were too few operands. */
if (*args)
- return FALSE;
+ return false;
/* Successful match. Stuff the immediate value in now, if
we can. */
*offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
check_completed_insn (&arg);
- return TRUE;
+ return true;
}
/* Fail the match if the line has too many operands. */
if (*args == 0)
- return FALSE;
+ return false;
/* Handle characters that need to match exactly. */
if (*args == '(' || *args == ')' || *args == ',')
{
if (match_char (&arg, *args))
continue;
- return FALSE;
+ return false;
}
arg.opnum += 1;
case 'I':
if (!match_const_int (&arg, &imm_expr.X_add_number))
- return FALSE;
+ return false;
imm_expr.X_op = O_constant;
if (GPR_SIZE == 32)
normalize_constant_expr (&imm_expr);
abort ();
if (operand->type == OP_PCREL)
- pcrel = TRUE;
+ pcrel = true;
else
{
- ext_operand = decode_mips16_operand (c, TRUE);
+ ext_operand = decode_mips16_operand (c, true);
if (operand != ext_operand)
{
if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
}
if (!match_expression (&arg, &offset_expr, offset_reloc))
- return FALSE;
+ return false;
/* '8' is used for SLTI(U) and has traditionally not
been allowed to take relocation operators. */
&& (ext_operand->size != 16 || c == '8'))
{
match_not_constant (&arg);
- return FALSE;
+ return false;
}
if (offset_expr.X_op == O_big)
{
match_out_of_range (&arg);
- return FALSE;
+ return false;
}
relax_char = c;
}
if (!match_operand (&arg, operand))
- return FALSE;
+ return false;
}
}
tried and failed to match under normal conditions and now want to try a
more relaxed match. */
-static bfd_boolean
+static bool
match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
const struct mips_opcode *past, struct mips_operand_token *tokens,
- int opcode_extra, bfd_boolean lax_match)
+ int opcode_extra, bool lax_match)
{
const struct mips_opcode *opcode;
const struct mips_opcode *invalid_delay_slot;
- bfd_boolean seen_valid_for_isa, seen_valid_for_size;
+ bool seen_valid_for_isa, seen_valid_for_size;
/* Search for a match, ignoring alternatives that don't satisfy the
current ISA or forced_length. */
invalid_delay_slot = 0;
- seen_valid_for_isa = FALSE;
- seen_valid_for_size = FALSE;
+ seen_valid_for_isa = false;
+ seen_valid_for_size = false;
opcode = first;
do
{
gas_assert (strcmp (opcode->name, first->name) == 0);
if (is_opcode_valid (opcode))
{
- seen_valid_for_isa = TRUE;
+ seen_valid_for_isa = true;
if (is_size_valid (opcode))
{
- bfd_boolean delay_slot_ok;
+ bool delay_slot_ok;
- seen_valid_for_size = TRUE;
+ seen_valid_for_size = true;
delay_slot_ok = is_delay_slot_valid (opcode);
if (match_insn (insn, opcode, tokens, opcode_extra,
lax_match, delay_slot_ok))
invalid_delay_slot = opcode;
}
else
- return TRUE;
+ return true;
}
}
}
if (invalid_delay_slot)
{
if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
- lax_match, TRUE))
- return TRUE;
+ lax_match, true))
+ return true;
abort ();
}
if (!seen_valid_for_isa)
{
match_invalid_for_isa ();
- return TRUE;
+ return true;
}
/* Handle the case where we didn't try to match an instruction because
set_insn_error_i
(0, _("unrecognized %d-bit version of microMIPS opcode"),
8 * forced_insn_length);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Like match_insns, but for MIPS16. */
-static bfd_boolean
+static bool
match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
struct mips_operand_token *tokens)
{
const struct mips_opcode *opcode;
- bfd_boolean seen_valid_for_isa;
- bfd_boolean seen_valid_for_size;
+ bool seen_valid_for_isa;
+ bool seen_valid_for_size;
/* Search for a match, ignoring alternatives that don't satisfy the
current ISA. There are no separate entries for extended forms so
we deal with forced_length later. */
- seen_valid_for_isa = FALSE;
- seen_valid_for_size = FALSE;
+ seen_valid_for_isa = false;
+ seen_valid_for_size = false;
opcode = first;
do
{
gas_assert (strcmp (opcode->name, first->name) == 0);
if (is_opcode_valid_16 (opcode))
{
- seen_valid_for_isa = TRUE;
+ seen_valid_for_isa = true;
if (is_size_valid_16 (opcode))
{
- seen_valid_for_size = TRUE;
+ seen_valid_for_size = true;
if (match_mips16_insn (insn, opcode, tokens))
- return TRUE;
+ return true;
}
}
++opcode;
if (!seen_valid_for_isa)
{
match_invalid_for_isa ();
- return TRUE;
+ return true;
}
/* Handle the case where we didn't try to match an instruction because
else
set_insn_error
(0, _("unrecognized extended version of MIPS16 opcode"));
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Set up global variables for the start of a new macro. */
va_end (args);
gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
- append_insn (&insn, ep, r, TRUE);
+ append_insn (&insn, ep, r, true);
}
static void
break;
default:
- operand = decode_mips16_operand (c, FALSE);
+ operand = decode_mips16_operand (c, false);
if (!operand)
abort ();
gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
- append_insn (&insn, ep, r, TRUE);
+ append_insn (&insn, ep, r, true);
}
/*
else
macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
if (MIPS_JALR_HINT_P (ep))
- fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
+ fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, false, jalr_reloc);
}
/*
macro_build (ep, call ? "bal" : "b", "p");
/* Set to true so that append_insn adds a label. */
- emit_branch_likely_macro = TRUE;
+ emit_branch_likely_macro = true;
}
else
{
amount that the caller wants to add without inducing overflow
and ALIGN is the known alignment of the value in bytes. */
-static bfd_boolean
+static bool
small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
{
if (offbits == 16)
{
/* Accept any relocation operator if overflow isn't a concern. */
if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
- return TRUE;
+ return true;
/* These relocations are guaranteed not to overflow in correct links. */
if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
|| gprel16_reloc_p (*offset_reloc))
- return TRUE;
+ return true;
}
if (offset_expr.X_op == O_constant
&& offset_high_part (offset_expr.X_add_number, offbits) == 0
&& offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
- return TRUE;
- return FALSE;
+ return true;
+ return false;
}
/*
int ust = 0;
int lp = 0;
int ll_sc_paired = 0;
- bfd_boolean large_offset;
+ bool large_offset;
int off;
int hold_mips_optimize;
unsigned int align;
if (!tokens)
return;
- if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
- && !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
+ if (!match_insns (insn, first, past, tokens, opcode_extra, false)
+ && !match_insns (insn, first, past, tokens, opcode_extra, true))
set_insn_error (0, _("invalid operands"));
obstack_free (&mips_operand_tokens, tokens);
require it to be an integer. */
static const struct mips_int_operand *
-mips16_immed_operand (int type, bfd_boolean extended_p)
+mips16_immed_operand (int type, bool extended_p)
{
const struct mips_operand *operand;
/* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
-static bfd_boolean
+static bool
mips16_immed_in_range_p (const struct mips_int_operand *operand,
bfd_reloc_code_real_type reloc, offsetT sval)
{
const struct mips_int_operand *operand;
unsigned int uval, length;
- operand = mips16_immed_operand (type, FALSE);
+ operand = mips16_immed_operand (type, false);
if (!mips16_immed_in_range_p (operand, reloc, val))
{
/* We need an extended instruction. */
length = mips16_opcode_length (*insn);
if (length == 4)
{
- operand = mips16_immed_operand (type, TRUE);
+ operand = mips16_immed_operand (type, true);
if (!mips16_immed_in_range_p (operand, reloc, val))
as_bad_where (file, line,
_("operand value out of range for instruction"));
move *STR over the operator and store its relocation code in *RELOC.
Leave both *STR and *RELOC alone when returning false. */
-static bfd_boolean
+static bool
parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
{
const struct percent_op_match *percent_op;
percent_op[i].str);
*reloc = BFD_RELOC_UNUSED;
}
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
break;
case OPTION_FIX_LOONGSON3_LLSC:
- mips_fix_loongson3_llsc = TRUE;
+ mips_fix_loongson3_llsc = true;
break;
case OPTION_NO_FIX_LOONGSON3_LLSC:
- mips_fix_loongson3_llsc = FALSE;
+ mips_fix_loongson3_llsc = false;
break;
case OPTION_FIX_LOONGSON2F_JUMP:
- mips_fix_loongson2f_jump = TRUE;
+ mips_fix_loongson2f_jump = true;
break;
case OPTION_NO_FIX_LOONGSON2F_JUMP:
- mips_fix_loongson2f_jump = FALSE;
+ mips_fix_loongson2f_jump = false;
break;
case OPTION_FIX_LOONGSON2F_NOP:
- mips_fix_loongson2f_nop = TRUE;
+ mips_fix_loongson2f_nop = true;
break;
case OPTION_NO_FIX_LOONGSON2F_NOP:
- mips_fix_loongson2f_nop = FALSE;
+ mips_fix_loongson2f_nop = false;
break;
case OPTION_FIX_VR4120:
break;
case OPTION_FIX_CN63XXP1:
- mips_fix_cn63xxp1 = TRUE;
+ mips_fix_cn63xxp1 = true;
break;
case OPTION_NO_FIX_CN63XXP1:
- mips_fix_cn63xxp1 = FALSE;
+ mips_fix_cn63xxp1 = false;
break;
case OPTION_FIX_R5900:
- mips_fix_r5900 = TRUE;
- mips_fix_r5900_explicit = TRUE;
+ mips_fix_r5900 = true;
+ mips_fix_r5900_explicit = true;
break;
case OPTION_NO_FIX_R5900:
- mips_fix_r5900 = FALSE;
- mips_fix_r5900_explicit = TRUE;
+ mips_fix_r5900 = false;
+ mips_fix_r5900_explicit = true;
break;
case OPTION_RELAX_BRANCH:
break;
case OPTION_IGNORE_BRANCH_ISA:
- mips_ignore_branch_isa = TRUE;
+ mips_ignore_branch_isa = true;
break;
case OPTION_NO_IGNORE_BRANCH_ISA:
- mips_ignore_branch_isa = FALSE;
+ mips_ignore_branch_isa = false;
break;
case OPTION_INSN32:
- file_mips_opts.insn32 = TRUE;
+ file_mips_opts.insn32 = true;
break;
case OPTION_NO_INSN32:
- file_mips_opts.insn32 = FALSE;
+ file_mips_opts.insn32 = false;
break;
case OPTION_MSHARED:
- mips_in_shared = TRUE;
+ mips_in_shared = true;
break;
case OPTION_MNO_SHARED:
- mips_in_shared = FALSE;
+ mips_in_shared = false;
break;
case OPTION_MSYM32:
- file_mips_opts.sym32 = TRUE;
+ file_mips_opts.sym32 = true;
break;
case OPTION_MNO_SYM32:
- file_mips_opts.sym32 = FALSE;
+ file_mips_opts.sym32 = false;
break;
/* When generating ELF code, we permit -KPIC and -call_shared to
intended to be compatible with Irix 5. */
case OPTION_CALL_SHARED:
mips_pic = SVR4_PIC;
- mips_abicalls = TRUE;
+ mips_abicalls = true;
break;
case OPTION_CALL_NONPIC:
mips_pic = NO_PIC;
- mips_abicalls = TRUE;
+ mips_abicalls = true;
break;
case OPTION_NON_SHARED:
mips_pic = NO_PIC;
- mips_abicalls = FALSE;
+ mips_abicalls = false;
break;
/* The -xgot option tells the assembler to use 32 bit offsets
break;
case OPTION_M7000_HILO_FIX:
- mips_7000_hilo_fix = TRUE;
+ mips_7000_hilo_fix = true;
break;
case OPTION_MNO_7000_HILO_FIX:
- mips_7000_hilo_fix = FALSE;
+ mips_7000_hilo_fix = false;
break;
case OPTION_MDEBUG:
- mips_flag_mdebug = TRUE;
+ mips_flag_mdebug = true;
break;
case OPTION_NO_MDEBUG:
- mips_flag_mdebug = FALSE;
+ mips_flag_mdebug = false;
break;
case OPTION_PDR:
- mips_flag_pdr = TRUE;
+ mips_flag_pdr = true;
break;
case OPTION_NO_PDR:
- mips_flag_pdr = FALSE;
+ mips_flag_pdr = false;
break;
case OPTION_MVXWORKS_PIC:
for (l = mips_hi_fixup_list; l != NULL; l = l->next)
{
segment_info_type *seginfo;
- bfd_boolean matched_lo_p;
+ bool matched_lo_p;
fixS **hi_pos, **lo_pos, **pos;
gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
relocation. */
hi_pos = NULL;
lo_pos = NULL;
- matched_lo_p = FALSE;
+ matched_lo_p = false;
looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
/* Implement TC_FORCE_RELOCATION_ABS. */
-bfd_boolean
+bool
mips_force_relocation_abs (fixS *fixp)
{
if (generic_force_reloc (fixp))
- return TRUE;
+ return true;
/* These relocations do not have enough bits in the in-place addend
to hold an arbitrary absolute section's offset. */
if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Read the instruction associated with RELOC from BUF. */
/* Return TRUE if the instruction pointed to by FIXP is an invalid jump
to a symbol in another ISA mode, which cannot be converted to JALX. */
-static bfd_boolean
+static bool
fix_bad_cross_mode_jump_p (fixS *fixP)
{
unsigned long opcode;
int other;
char *buf;
- if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
- return FALSE;
+ if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
+ return false;
other = S_GET_OTHER (fixP->fx_addsy);
buf = fixP->fx_frag->fr_literal + fixP->fx_where;
case BFD_RELOC_MICROMIPS_JMP:
return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
default:
- return FALSE;
+ return false;
}
}
/* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
jump to a symbol in the same ISA mode. */
-static bfd_boolean
+static bool
fix_bad_same_mode_jalx_p (fixS *fixP)
{
unsigned long opcode;
int other;
char *buf;
- if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
- return FALSE;
+ if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
+ return false;
other = S_GET_OTHER (fixP->fx_addsy);
buf = fixP->fx_frag->fr_literal + fixP->fx_where;
case BFD_RELOC_MICROMIPS_JMP:
return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
default:
- return FALSE;
+ return false;
}
}
requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
regular MIPS code, to (1 << 2). */
-static bfd_boolean
+static bool
fix_bad_misaligned_jump_p (fixS *fixP, int shift)
{
- bfd_boolean micro_to_mips_p;
+ bool micro_to_mips_p;
valueT val;
int other;
- if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
- return FALSE;
+ if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
+ return false;
other = S_GET_OTHER (fixP->fx_addsy);
val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
MIPS symbols and associated with BAL instructions as these instructions
may be converted to JALX by the linker. */
-static bfd_boolean
+static bool
fix_bad_cross_mode_branch_p (fixS *fixP)
{
- bfd_boolean absolute_p;
+ bool absolute_p;
unsigned long opcode;
asection *symsec;
valueT val;
char *buf;
if (mips_ignore_branch_isa)
- return FALSE;
+ return false;
- if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
- return FALSE;
+ if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
+ return false;
symsec = S_GET_SEGMENT (fixP->fx_addsy);
absolute_p = bfd_is_abs_section (symsec);
must explicitly OR in the ISA bit from symbol annotation as the bit
won't be set in the symbol's value then. */
-static bfd_boolean
+static bool
fix_bad_misaligned_branch_p (fixS *fixP)
{
- bfd_boolean absolute_p;
+ bool absolute_p;
asection *symsec;
valueT isa_bit;
valueT val;
valueT off;
int other;
- if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE))
- return FALSE;
+ if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
+ return false;
symsec = S_GET_SEGMENT (fixP->fx_addsy);
absolute_p = bfd_is_abs_section (symsec);
as_bad_where (fixP->fx_file, fixP->fx_line,
_("branch to a symbol in another ISA mode"));
else if (fixP->fx_addsy
- && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
+ && !S_FORCE_RELOC (fixP->fx_addsy, true)
&& !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
&& (fixP->fx_offset & 0x1) != 0)
as_bad_where (fixP->fx_file, fixP->fx_line,
else if (i == 2)
{
mips_pic = SVR4_PIC;
- mips_abicalls = TRUE;
+ mips_abicalls = true;
}
if (mips_pic == SVR4_PIC)
static enum code_option_type
parse_code_option (char * name)
{
- bfd_boolean isa_set = FALSE;
+ bool isa_set = false;
const struct mips_ase *ase;
if (strncmp (name, "at=", 3) == 0)
else if (name[0] == 'n'
&& name[1] == 'o'
&& (ase = mips_lookup_ase (name + 2)))
- mips_set_ase (ase, &mips_opts, FALSE);
+ mips_set_ase (ase, &mips_opts, false);
else if ((ase = mips_lookup_ase (name)))
- mips_set_ase (ase, &mips_opts, TRUE);
+ mips_set_ase (ase, &mips_opts, true);
else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
{
/* Permit the user to change the ISA and architecture on the fly.
{
mips_opts.arch = p->cpu;
mips_opts.isa = p->isa;
- isa_set = TRUE;
+ isa_set = true;
mips_opts.init_ase = p->ase;
}
}
{
mips_opts.arch = p->cpu;
mips_opts.isa = p->isa;
- isa_set = TRUE;
+ isa_set = true;
mips_opts.init_ase = p->ase;
}
}
else if (strcmp (name, "noautoextend") == 0)
mips_opts.noautoextend = 1;
else if (strcmp (name, "insn32") == 0)
- mips_opts.insn32 = TRUE;
+ mips_opts.insn32 = true;
else if (strcmp (name, "noinsn32") == 0)
- mips_opts.insn32 = FALSE;
+ mips_opts.insn32 = false;
else if (strcmp (name, "sym32") == 0)
- mips_opts.sym32 = TRUE;
+ mips_opts.sym32 = true;
else if (strcmp (name, "nosym32") == 0)
- mips_opts.sym32 = FALSE;
+ mips_opts.sym32 = false;
else
return OPTION_TYPE_BAD;
}
}
- mips_check_options (&mips_opts, FALSE);
+ mips_check_options (&mips_opts, false);
mips_check_isa_supports_ases ();
*input_line_pointer = ch;
s_abicalls (int ignore ATTRIBUTE_UNUSED)
{
mips_pic = SVR4_PIC;
- mips_abicalls = TRUE;
+ mips_abicalls = true;
if (g_switch_seen && g_switch_value != 0)
as_warn (_("-G may not be used with SVR4 PIC code"));
symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
mips_mark_labels ();
- mips_assembling_insn = TRUE;
+ mips_assembling_insn = true;
macro_start ();
macro_build_lui (&ex, mips_gp_register);
mips_gp_register, reg);
macro_end ();
- mips_assembling_insn = FALSE;
+ mips_assembling_insn = false;
demand_empty_rest_of_line ();
}
expression (&ex_sym);
mips_mark_labels ();
- mips_assembling_insn = TRUE;
+ mips_assembling_insn = true;
macro_start ();
if (mips_cpreturn_register == -1)
macro_end ();
- mips_assembling_insn = FALSE;
+ mips_assembling_insn = false;
demand_empty_rest_of_line ();
}
ex.X_add_number = mips_cprestore_offset;
mips_mark_labels ();
- mips_assembling_insn = TRUE;
+ mips_assembling_insn = true;
macro_start ();
macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
SP, HAVE_64BIT_ADDRESSES);
macro_end ();
- mips_assembling_insn = FALSE;
+ mips_assembling_insn = false;
demand_empty_rest_of_line ();
}
}
mips_mark_labels ();
- mips_assembling_insn = TRUE;
+ mips_assembling_insn = true;
macro_start ();
if (mips_cpreturn_register == -1)
macro_end ();
- mips_assembling_insn = FALSE;
+ mips_assembling_insn = false;
demand_empty_rest_of_line ();
}
p = frag_more (bytes);
md_number_to_chars (p, 0, bytes);
- fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
+ fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false, rtype);
demand_empty_rest_of_line ();
mips_clear_insn_labels ();
}
p = frag_more (4);
md_number_to_chars (p, 0, 4);
- fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
+ fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
BFD_RELOC_GPREL32);
demand_empty_rest_of_line ();
p = frag_more (8);
md_number_to_chars (p, 0, 8);
- fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
+ fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
BFD_RELOC_GPREL32)->fx_tcbit = 1;
/* GPREL32 composed with 64 gives a 64-bit GP offset. */
fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
- FALSE, BFD_RELOC_64)->fx_tcbit = 1;
+ false, BFD_RELOC_64)->fx_tcbit = 1;
demand_empty_rest_of_line ();
}
p = frag_more (4);
md_number_to_chars (p, 0, 4);
- fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
+ fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
BFD_RELOC_32_PCREL);
demand_empty_rest_of_line ();
}
mips_mark_labels ();
- mips_assembling_insn = TRUE;
+ mips_assembling_insn = true;
/* Add $gp to the register named as an argument. */
macro_start ();
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
macro_end ();
- mips_assembling_insn = FALSE;
+ mips_assembling_insn = false;
demand_empty_rest_of_line ();
}
/* Return true if the given symbol should be considered local for SVR4 PIC. */
-static bfd_boolean
+static bool
pic_need_relax (symbolS *sym)
{
asection *symsec;
}
if (symbol_section_p (sym))
- return TRUE;
+ return true;
symsec = S_GET_SEGMENT (sym);
symsec = S_GET_SEGMENT (fragp->fr_symbol);
type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
- operand = mips16_immed_operand (type, FALSE);
- if (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
+ operand = mips16_immed_operand (type, false);
+ if (S_FORCE_RELOC (fragp->fr_symbol, true)
|| (operand->root.type == OP_PCREL
? sec != symsec
: !bfd_is_abs_section (symsec)))
return 1;
if (RELAX_MIPS16_PIC (fragp->fr_subtype))
return 0;
- if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec)
+ if (S_FORCE_RELOC (fragp->fr_symbol, true) || sec != symsec)
return 1;
- operand = mips16_immed_operand (type, TRUE);
+ operand = mips16_immed_operand (type, true);
val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
pcrel_op = (const struct mips_pcrel_operand *) operand;
val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
static int
relaxed_branch_length (fragS *fragp, asection *sec, int update)
{
- bfd_boolean toofar;
+ bool toofar;
int length;
if (fragp
else
/* If the symbol is not defined or it's in a different segment,
we emit the long sequence. */
- toofar = TRUE;
+ toofar = true;
if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
fragp->fr_subtype
or SHORT_INSN_SIZE otherwise. */
static int
-frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size)
+frag_branch_delay_slot_size (fragS *fragp, bool al, int short_insn_size)
{
char *buf = fragp->fr_literal + fragp->fr_fix;
static int
relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
{
- bfd_boolean insn32 = TRUE;
- bfd_boolean nods = TRUE;
- bfd_boolean pic = TRUE;
- bfd_boolean al = TRUE;
+ bool insn32 = true;
+ bool nods = true;
+ bool pic = true;
+ bool al = true;
int short_insn_size;
- bfd_boolean toofar;
+ bool toofar;
int length;
if (fragp)
else
/* If the symbol is not defined or it's in a different segment,
we emit the long sequence. */
- toofar = TRUE;
+ toofar = true;
if (fragp && update
&& toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
length = 4;
if (toofar)
{
- bfd_boolean compact_known = fragp != NULL;
- bfd_boolean compact = FALSE;
- bfd_boolean uncond;
+ bool compact_known = fragp != NULL;
+ bool compact = false;
+ bool uncond;
if (fragp)
{
static int
relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
{
- bfd_boolean toofar;
+ bool toofar;
if (fragp
&& S_IS_DEFINED (fragp->fr_symbol)
else
/* If the symbol is not defined or it's in a different segment,
we emit a normal 32-bit branch. */
- toofar = TRUE;
+ toofar = true;
if (fragp && update
&& toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
if (RELAX_BRANCH_P (fragp->fr_subtype))
{
- fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
+ fragp->fr_var = relaxed_branch_length (fragp, segtype, false);
return fragp->fr_var;
}
int length = 4;
if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
- length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
+ length = relaxed_micromips_16bit_branch_length (fragp, segtype, false);
if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
- length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
+ length = relaxed_micromips_32bit_branch_length (fragp, segtype, false);
fragp->fr_var = length;
return length;
{
offsetT old_var = fragp->fr_var;
- fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
+ fragp->fr_var = relaxed_branch_length (fragp, sec, true);
return fragp->fr_var - old_var;
}
offsetT new_var = 4;
if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
- new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
+ new_var = relaxed_micromips_16bit_branch_length (fragp, sec, true);
if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
- new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
+ new_var = relaxed_micromips_32bit_branch_length (fragp, sec, true);
fragp->fr_var = new_var;
return new_var - old_var;
need the relocations. */
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- TRUE, BFD_RELOC_16_PCREL_S2);
+ true, BFD_RELOC_16_PCREL_S2);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- FALSE, BFD_RELOC_MIPS_JMP);
+ false, BFD_RELOC_MIPS_JMP);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- FALSE, BFD_RELOC_MIPS_GOT16);
+ false, BFD_RELOC_MIPS_GOT16);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- FALSE, BFD_RELOC_LO16);
+ false, BFD_RELOC_LO16);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
if (RELAX_MICROMIPS_P (fragp->fr_subtype))
{
char *buf = fragp->fr_literal + fragp->fr_fix;
- bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
- bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
- bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
- bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
- bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
+ bool compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
+ bool insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
+ bool nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
+ bool pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
+ bool al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
- bfd_boolean short_ds;
+ bool short_ds;
unsigned long insn;
fixS *fixp;
case 'D':
fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
fragp->fr_symbol, fragp->fr_offset,
- TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1);
+ true, BFD_RELOC_MICROMIPS_10_PCREL_S1);
break;
case 'E':
fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
fragp->fr_symbol, fragp->fr_offset,
- TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1);
+ true, BFD_RELOC_MICROMIPS_7_PCREL_S1);
break;
default:
abort ();
need the relocations. */
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
+ true, BFD_RELOC_MICROMIPS_16_PCREL_S1);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
/* Refer to it. */
- fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
+ fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, true,
BFD_RELOC_MICROMIPS_16_PCREL_S1);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- FALSE, BFD_RELOC_MICROMIPS_JMP);
+ false, BFD_RELOC_MICROMIPS_JMP);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- FALSE, BFD_RELOC_MICROMIPS_GOT16);
+ false, BFD_RELOC_MICROMIPS_GOT16);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- FALSE, BFD_RELOC_MICROMIPS_LO16);
+ false, BFD_RELOC_MICROMIPS_LO16);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
offsetT val;
char *buf;
unsigned int user_length;
- bfd_boolean need_reloc;
+ bool need_reloc;
unsigned long insn;
- bfd_boolean mac;
- bfd_boolean ext;
+ bool mac;
+ bool ext;
segT symsec;
type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
- operand = mips16_immed_operand (type, FALSE);
+ operand = mips16_immed_operand (type, false);
mac = RELAX_MIPS16_MACRO (fragp->fr_subtype);
ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
symsec = S_GET_SEGMENT (fragp->fr_symbol);
- need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
+ need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, true)
|| (operand->root.type == OP_PCREL && !mac
? asec != symsec
: !bfd_is_abs_section (symsec)));
unsigned long reg;
unsigned long new;
unsigned long op;
- bfd_boolean e2;
+ bool e2;
gas_assert (type == 'A' || type == 'B' || type == 'E');
gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype));
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- FALSE, BFD_RELOC_MIPS16_HI16_S);
+ false, BFD_RELOC_MIPS16_HI16_S);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4,
fragp->fr_symbol, fragp->fr_offset,
- FALSE, BFD_RELOC_MIPS16_LO16);
+ false, BFD_RELOC_MIPS16_LO16);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
{
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- TRUE, reloc);
+ true, reloc);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
}
else
{
relax_substateT subtype = fragp->fr_subtype;
- bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
- bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
+ bool second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
+ bool use_second = (subtype & RELAX_USE_SECOND) != 0;
unsigned int first, second;
fixS *fixp;
Note: this function is shared between GCC and GAS. */
-static bfd_boolean
+static bool
mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
{
while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
Note: this function is shared between GCC and GAS. */
-static bfd_boolean
+static bool
mips_matching_cpu_name_p (const char *canonical, const char *given)
{
/* First see if the name matches exactly, or with a final "000"
turned into "k". */
if (mips_strict_matching_cpu_name_p (canonical, given))
- return TRUE;
+ return true;
/* If not, try comparing based on numerical designation alone.
See if GIVEN is an unadorned number, or 'r' followed by a number. */
if (TOLOWER (*given) == 'r')
given++;
if (!ISDIGIT (*given))
- return FALSE;
+ return false;
/* Skip over some well-known prefixes in the canonical name,
hoping to find a number there too. */
|| mips_force_relocation (FIX))
#define TC_FORCE_RELOCATION_ABS(FIX) mips_force_relocation_abs (FIX)
-extern bfd_boolean mips_force_relocation_abs (struct fix *);
+extern bool mips_force_relocation_abs (struct fix *);
/* Register mask variables. These are set by the MIPS assembly code
and used by ECOFF and possibly other object file formats. */
The testsuite wants it, and it's customary.
We'll deal with the real problems when they come; we share the
problem with most other ports. */
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
/* Convert variable-sized frags into one or more fixups. */
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
-static bfd_boolean
+static bool
data_register_name (expressionS *expressionP)
{
int reg_number;
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
- return FALSE;
+ return false;
}
/* Summary of register_name().
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
-static bfd_boolean
+static bool
address_register_name (expressionS *expressionP)
{
int reg_number;
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
- return FALSE;
+ return false;
}
/* Summary of register_name().
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
-static bfd_boolean
+static bool
other_register_name (expressionS *expressionP)
{
int reg_number;
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
- return FALSE;
+ return false;
}
void
const char *
md_atof (int type, char *litp, int *sizep)
{
- return ieee_md_atof (type, litp, sizep, FALSE);
+ return ieee_md_atof (type, litp, sizep, false);
}
void
the name and the function returns TRUE. Otherwise the input pointer
is left alone and the function returns FALSE. */
-static bfd_boolean
+static bool
get_register_name (expressionS * expressionP,
const struct reg_name * table,
size_t table_length)
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
r_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, r_registers, ARRAY_SIZE (r_registers));
}
-static bfd_boolean
+static bool
xr_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, xr_registers, ARRAY_SIZE (xr_registers));
}
-static bfd_boolean
+static bool
data_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, data_registers, ARRAY_SIZE (data_registers));
}
-static bfd_boolean
+static bool
address_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, address_registers, ARRAY_SIZE (address_registers));
}
-static bfd_boolean
+static bool
float_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, float_registers, ARRAY_SIZE (float_registers));
}
-static bfd_boolean
+static bool
double_register_name (expressionS *expressionP)
{
return get_register_name (expressionP, double_registers, ARRAY_SIZE (double_registers));
}
-static bfd_boolean
+static bool
other_register_name (expressionS *expressionP)
{
int reg_number;
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
- return FALSE;
+ return false;
}
void
const char *
md_atof (int type, char *litp, int *sizep)
{
- return ieee_md_atof (type, litp, sizep, FALSE);
+ return ieee_md_atof (type, litp, sizep, false);
}
void
fix_new_exp (frag, off, size, &fixup.exp, 0, fixup.reloc);
}
-static bfd_boolean
+static bool
check_operand (const struct mn10300_operand *operand,
offsetT val)
{
test = val;
if (test < (offsetT) min || test > (offsetT) max)
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Insert an operand value into an instruction. */
}
/* Label this frag as one that contains instructions. */
- frag_now->tc_frag_data = TRUE;
+ frag_now->tc_frag_data = true;
}
/* If while processing a fixup, a reloc really needs to be created
/* Returns true iff the symbol attached to the frag is at a known location
in the given section, (and hence the relocation to it can be relaxed by
the assembler). */
-static inline bfd_boolean
+static inline bool
has_known_symbol_location (fragS * fragp, asection * sec)
{
symbolS * sym = fragp->fr_symbol;
/* Return zero if the fixup in fixp should be left alone and not
adjusted. */
-bfd_boolean
+bool
mn10300_fix_adjustable (struct fix *fixp)
{
if (fixp->fx_pcrel)
{
if (TC_FORCE_RELOCATION_LOCAL (fixp))
- return FALSE;
+ return false;
}
/* Non-relative relocs can (and must) be adjusted if they do
not meet the criteria below, or the generic criteria. */
else if (TC_FORCE_RELOCATION (fixp))
- return FALSE;
+ return false;
/* Do not adjust relocations involving symbols in code sections,
because it breaks linker relaxations. This could be fixed in the
linker, but this fix is simpler, and it pretty much only affects
object size a little bit. */
if (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE)
- return FALSE;
+ return false;
/* Likewise, do not adjust symbols that won't be merged, or debug
symbols, because they too break relaxation. We do want to adjust
other mergeable symbols, like .rodata, because code relaxations
need section-relative symbols to properly relax them. */
if (! (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE))
- return FALSE;
+ return false;
if (strncmp (S_GET_SEGMENT (fixp->fx_addsy)->name, ".debug", 6) == 0)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
static void
subtraction of two same-section symbols cannot be computed by
the assembler. */
-bfd_boolean
+bool
mn10300_allow_local_subtract (expressionS * left, expressionS * right, segT section)
{
- bfd_boolean result;
+ bool result;
fragS * left_frag;
fragS * right_frag;
fragS * frag;
/* If we are not performing linker relaxation then we have nothing
to worry about. */
if (linkrelax == 0)
- return TRUE;
+ return true;
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
- return TRUE;
+ return true;
/* Otherwise we have to scan the fragments between the two symbols.
If any instructions are found then we have to assume that linker
if (left_frag == right_frag)
return ! left_frag->tc_frag_data;
- result = TRUE;
+ result = true;
for (frag = left_frag; frag != NULL; frag = frag->fr_next)
{
if (frag->tc_frag_data)
- result = FALSE;
+ result = false;
if (frag == right_frag)
break;
}
for (frag = right_frag; frag != NULL; frag = frag->fr_next)
{
if (frag->tc_frag_data)
- result = FALSE;
+ result = false;
if (frag == left_frag)
break;
}
if (frag == NULL)
/* The two symbols are on disjoint fragment chains
- we cannot possibly compute their difference. */
- return FALSE;
+ return false;
return result;
}
The offset from the symbol is used to record the power-of-two alignment
value. The size is set to 0 because the frag may already be aligned,
thus causing cvt_frag_to_fill to reduce the size of the frag to zero. */
- fix_new (frag, frag->fr_fix, 0, & abs_symbol, frag->fr_offset, FALSE,
+ fix_new (frag, frag->fr_fix, 0, & abs_symbol, frag->fr_offset, false,
BFD_RELOC_MN10300_ALIGN);
}
-bfd_boolean
+bool
mn10300_force_relocation (struct fix * fixp)
{
if (linkrelax
&& (fixp->fx_pcrel
|| fixp->fx_r_type == BFD_RELOC_MN10300_ALIGN))
- return TRUE;
+ return true;
return generic_force_reloc (fixp);
}
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#define TC_FORCE_RELOCATION(FIX) mn10300_force_relocation (FIX)
-extern bfd_boolean mn10300_force_relocation (struct fix *);
+extern bool mn10300_force_relocation (struct fix *);
/* tc-mn10300.c uses TC_FORCE_RELOCATION_LOCAL, a macro that should
only appear in write.c. The use is likely incorrect. Duplicating
#define md_number_to_chars number_to_chars_littleendian
#define tc_fix_adjustable(FIX) mn10300_fix_adjustable (FIX)
-extern bfd_boolean mn10300_fix_adjustable (struct fix *);
+extern bool mn10300_fix_adjustable (struct fix *);
/* We do relaxing in the assembler as well as the linker. */
extern const struct relax_type md_relax_table[];
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) mn10300_allow_local_subtract (l, r, s)
-extern bfd_boolean mn10300_allow_local_subtract (expressionS *, expressionS *, segT);
+extern bool mn10300_allow_local_subtract (expressionS *, expressionS *, segT);
#define RELOC_EXPANSION_POSSIBLE
#define MAX_RELOC_EXPANSION 2
-#define TC_FRAG_TYPE bfd_boolean
+#define TC_FRAG_TYPE bool
#define HANDLE_ALIGN(frag) mn10300_handle_align (frag)
extern void mn10300_handle_align (fragS *);
(p - frag_now->fr_literal),
2,
&arg,
- TRUE,
+ true,
BFD_RELOC_MOXIE_10_PCREL);
}
break;
static enum msp_isa selected_isa = MSP_ISA_430Xv2;
-static inline bfd_boolean
+static inline bool
target_is_430x (void)
{
return selected_isa >= MSP_ISA_430X;
}
-static inline bfd_boolean
+static inline bool
target_is_430xv2 (void)
{
return selected_isa == MSP_ISA_430Xv2;
#define OPTION_RELAX 'Q'
#define OPTION_POLYMORPHS 'P'
#define OPTION_LARGE 'l'
-static bfd_boolean large_model = FALSE;
+static bool large_model = false;
#define OPTION_NO_INTR_NOPS 'N'
#define OPTION_INTR_NOPS 'n'
-static bfd_boolean gen_interrupt_nops = FALSE;
+static bool gen_interrupt_nops = false;
#define OPTION_WARN_INTR_NOPS 'y'
#define OPTION_NO_WARN_INTR_NOPS 'Y'
-static bfd_boolean warn_interrupt_nops = TRUE;
+static bool warn_interrupt_nops = true;
#define OPTION_UNKNOWN_INTR_NOPS 'u'
#define OPTION_NO_UNKNOWN_INTR_NOPS 'U'
-static bfd_boolean do_unknown_interrupt_nops = TRUE;
+static bool do_unknown_interrupt_nops = true;
#define OPTION_MCPU 'c'
#define OPTION_DATA_REGION 'r'
-static bfd_boolean upper_data_region_in_use = FALSE;
+static bool upper_data_region_in_use = false;
/* The default is to use the lower region only. */
-static bfd_boolean lower_data_region_only = TRUE;
+static bool lower_data_region_only = true;
/* Deprecated option, silently ignore it for compatibility with GCC <= 10. */
#define OPTION_MOVE_DATA 'd'
return 1;
case OPTION_LARGE:
- large_model = TRUE;
+ large_model = true;
return 1;
case OPTION_NO_INTR_NOPS:
- gen_interrupt_nops = FALSE;
+ gen_interrupt_nops = false;
return 1;
case OPTION_INTR_NOPS:
- gen_interrupt_nops = TRUE;
+ gen_interrupt_nops = true;
return 1;
case OPTION_WARN_INTR_NOPS:
- warn_interrupt_nops = TRUE;
+ warn_interrupt_nops = true;
return 1;
case OPTION_NO_WARN_INTR_NOPS:
- warn_interrupt_nops = FALSE;
+ warn_interrupt_nops = false;
return 1;
case OPTION_UNKNOWN_INTR_NOPS:
- do_unknown_interrupt_nops = TRUE;
+ do_unknown_interrupt_nops = true;
return 1;
case OPTION_NO_UNKNOWN_INTR_NOPS:
- do_unknown_interrupt_nops = FALSE;
+ do_unknown_interrupt_nops = false;
return 1;
case OPTION_MOVE_DATA:
case OPTION_DATA_REGION:
if (strcmp (arg, "upper") == 0
|| strcmp (arg, "either") == 0)
- upper_data_region_in_use = TRUE;
+ upper_data_region_in_use = true;
if (strcmp (arg, "upper") == 0
|| strcmp (arg, "either") == 0
/* With data-region=none, the compiler has generated code assuming
data could be in the upper region, but nothing has been explicitly
placed there. */
|| strcmp (arg, "none") == 0)
- lower_data_region_only = FALSE;
+ lower_data_region_only = false;
return 1;
}
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
void
linkrelax = 1;
}
-static inline bfd_boolean
+static inline bool
is_regname_end (char c)
{
return (c == 0 || ! ISALNUM (c));
msp430_srcoperand (struct msp430_operand_s * op,
char * l,
int bin,
- bfd_boolean * imm_op,
- bfd_boolean allow_20bit_values,
- bfd_boolean constants_allowed)
+ bool * imm_op,
+ bool allow_20bit_values,
+ bool constants_allowed)
{
char * end;
char *__tl = l;
hhi(x) - x = (x >> 48) & 0xffff
The value _MUST_ be an immediate expression: #hlo(1231231231). */
- *imm_op = TRUE;
+ *imm_op = true;
if (strncasecmp (h, "#llo(", 5) == 0)
{
char *m = strrchr (l, ')');
char *t;
- *imm_op = TRUE;
+ *imm_op = true;
if (!h)
break;
msp430_dstoperand (struct msp430_operand_s * op,
char * l,
int bin,
- bfd_boolean allow_20bit_values,
- bfd_boolean constants_allowed)
+ bool allow_20bit_values,
+ bool constants_allowed)
{
- bfd_boolean dummy;
+ bool dummy;
int ret = msp430_srcoperand (op, l, bin, & dummy,
allow_20bit_values,
constants_allowed);
will be returned if a pointer is provided. */
static int
-try_encode_mova (bfd_boolean imm_op,
+try_encode_mova (bool imm_op,
int bin,
struct msp430_operand_s * op1,
struct msp430_operand_s * op2,
else
{
bfd_putl16 ((bfd_vma) bin, frag);
- fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
+ fix_new_exp (frag_now, where, 4, &(op1->exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_SRC);
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
}
else
{
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
- fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE,
+ fix_new_exp (frag_now, where + 2, 2, &(op1->exp), false,
op1->reg == 0 ?
BFD_RELOC_MSP430X_PCR16 :
BFD_RELOC_MSP430X_ABS16);
{
bfd_putl16 ((bfd_vma) bin, frag);
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
- fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE,
+ fix_new_exp (frag_now, where, 4, &(op2->exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_DST);
}
return 4;
else
{
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
- fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE,
+ fix_new_exp (frag_now, where + 2, 2, &(op2->exp), false,
op2->reg == 0 ?
BFD_RELOC_MSP430X_PCR16 :
BFD_RELOC_MSP430X_ABS16);
}
}
- /* imm_op == FALSE. */
+ /* imm_op == false. */
if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP)
{
{
bfd_putl16 ((bfd_vma) bin, frag);
bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
- fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
+ fix_new_exp (frag_now, where, 4, &(op1->exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_SRC);
}
return 4;
/* Insert/inform about adding a NOP if this insn enables interrupts. */
static void
-warn_eint_nop (bfd_boolean prev_insn_is_nop, bfd_boolean prev_insn_is_dint)
+warn_eint_nop (bool prev_insn_is_nop, bool prev_insn_is_dint)
{
if (prev_insn_is_nop
/* If the last insn was a DINT, we will have already warned that a NOP is
to insert/warn about adding a NOP before the current insn. */
static void
-warn_unsure_interrupt (bfd_boolean prev_insn_is_nop,
- bfd_boolean prev_insn_is_dint)
+warn_unsure_interrupt (bool prev_insn_is_nop,
+ bool prev_insn_is_dint)
{
if (prev_insn_is_nop
/* If the last insn was a DINT, we will have already warned that a NOP is
struct msp430_operand_s op1, op2;
int res = 0;
static short ZEROS = 0;
- bfd_boolean byte_op, imm_op;
+ bool byte_op, imm_op;
int op_length = 0;
int fmt;
int extended = 0x1800;
- bfd_boolean extended_op = FALSE;
- bfd_boolean addr_op;
+ bool extended_op = false;
+ bool addr_op;
const char * error_message;
static signed int repeat_count = 0;
- static bfd_boolean prev_insn_is_nop = FALSE;
- static bfd_boolean prev_insn_is_dint = FALSE;
- static bfd_boolean prev_insn_is_eint = FALSE;
+ static bool prev_insn_is_nop = false;
+ static bool prev_insn_is_dint = false;
+ static bool prev_insn_is_eint = false;
/* We might decide before the end of the function that the current insn is
equivalent to DINT/EINT. */
- bfd_boolean this_insn_is_dint = FALSE;
- bfd_boolean this_insn_is_eint = FALSE;
- bfd_boolean fix_emitted;
+ bool this_insn_is_dint = false;
+ bool this_insn_is_eint = false;
+ bool fix_emitted;
/* Opcode is the one from opcodes table
line contains something like
or
.b @r2+, 5(R1). */
- byte_op = FALSE;
- addr_op = FALSE;
+ byte_op = false;
+ addr_op = false;
if (*line == '.')
{
- bfd_boolean check = FALSE;
+ bool check = false;
++ line;
switch (TOLOWER (* line))
case 'b':
/* Byte operation. */
bin |= BYTE_OPERATION;
- byte_op = TRUE;
- check = TRUE;
+ byte_op = true;
+ check = true;
break;
case 'a':
/* "Address" ops work on 20-bit values. */
- addr_op = TRUE;
+ addr_op = true;
bin |= BYTE_OPERATION;
- check = TRUE;
+ check = true;
break;
case 'w':
/* Word operation - this is the default. */
- check = TRUE;
+ check = true;
break;
case 0:
#if 0 /* Enable for debugging. */
as_warn ("treating %s.a as %s", old_name, real_name);
#endif
- addr_op = FALSE;
+ addr_op = false;
bin = opcode->bin_opcode;
}
memset (&op1, 0, sizeof (op1));
memset (&op2, 0, sizeof (op2));
- imm_op = FALSE;
+ imm_op = false;
if ((fmt = opcode->fmt) < 0)
{
}
fmt = (-fmt) - 1;
- extended_op = TRUE;
+ extended_op = true;
}
if (repeat_count)
case 1:
/* Something which works with destination operand. */
line = extract_operand (line, l1, sizeof (l1));
- res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE);
+ res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, true);
if (res)
break;
extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
else if (op1.reg || op1.am == 3) /* Not PC relative. */
- fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_EXT_SRC);
else
- fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_EXT_SRC);
}
{
if (op1.reg)
fix_new_exp (frag_now, where, 2,
- &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
+ &(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
- &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+ &(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
}
line = extract_operand (line, l1, sizeof (l1));
strncpy (l2, l1, sizeof (l2));
l2[sizeof (l2) - 1] = '\0';
- res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
- res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
+ res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, true);
+ res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, true);
if (res)
break; /* An error occurred. All warnings were done before. */
extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
else if (op1.reg || op1.am == 3) /* Not PC relative. */
- fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_EXT_SRC);
else
- fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_EXT_SRC);
}
extended |= (op2.exp.X_add_number >> 16) & 0xf;
else if (op1.mode == OP_EXP)
- fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
+ fix_new_exp (frag_now, where, 8, &(op2.exp), false,
op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
: BFD_RELOC_MSP430X_PCR20_EXT_ODST);
else
- fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op2.exp), false,
op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
: BFD_RELOC_MSP430X_PCR20_EXT_DST);
}
{
if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
- &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
+ &(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
- &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+ &(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
frag += 2;
{
if (op2.reg) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
- &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
+ &(op2.exp), false, CHECK_RELOC_MSP430 (op2));
else
fix_new_exp (frag_now, where, 2,
- &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+ &(op2.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
}
}
line = extract_operand (line, l1, sizeof (l1));
- res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, FALSE);
+ res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, false);
if (res)
break;
- byte_op = FALSE;
- imm_op = FALSE;
+ byte_op = false;
+ imm_op = false;
bin |= ((op1.reg << 8) | (op1.am << 4));
op_length = 2 + 2 * op1.ol;
frag = frag_more (op_length);
if (op1.reg || op1.am == 3)
fix_new_exp (frag_now, where, 2,
- &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
+ &(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
- &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+ &(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
case 4:
/* CALLA instructions. */
- fix_emitted = FALSE;
+ fix_emitted = false;
line = extract_operand (line, l1, sizeof (l1));
- imm_op = FALSE;
+ imm_op = false;
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op,
- extended_op, FALSE);
+ extended_op, false);
if (res)
break;
- byte_op = FALSE;
+ byte_op = false;
op_length = 2 + 2 * op1.ol;
frag = frag_more (op_length);
{
bin |= 0xb0;
- fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 4, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_DST);
- fix_emitted = TRUE;
+ fix_emitted = true;
}
else if (op1.am == 1)
{
{
bin |= 0x90;
- fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 4, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_CALL);
- fix_emitted = TRUE;
+ fix_emitted = true;
}
else
bin |= 0x50 | op1.reg;
{
bin |= 0x80;
- fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 4, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_DST);
- fix_emitted = TRUE;
+ fix_emitted = true;
}
else if (op1.am == 2)
bin |= 0x60 | op1.reg;
if (! fix_emitted)
fix_new_exp (frag_now, where + 2, 2,
- &(op1.exp), FALSE, BFD_RELOC_16);
+ &(op1.exp), false, BFD_RELOC_16);
}
dwarf2_emit_insn (insn_length + op_length);
case 8:
{
- bfd_boolean need_reloc = FALSE;
+ bool need_reloc = false;
int n;
int reg;
else
{
n = 0;
- need_reloc = TRUE;
+ need_reloc = true;
}
op_length = 4;
where = frag - frag_now->fr_literal;
bin |= reg;
if (need_reloc)
- fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 4, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_ADR_SRC);
bfd_putl16 ((bfd_vma) bin, frag);
}
case 9: /* MOVA, BRA, RETA. */
- imm_op = FALSE;
+ imm_op = false;
bin = opcode->bin_opcode;
if (is_opcode ("reta"))
{
line = extract_operand (line, l1, sizeof (l1));
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
- &imm_op, extended_op, FALSE);
+ &imm_op, extended_op, false);
if (is_opcode ("bra"))
{
{
line = extract_operand (line, l2, sizeof (l2));
res += msp430_dstoperand (&op2, l2, opcode->bin_opcode,
- extended_op, TRUE);
+ extended_op, true);
}
if (res)
case 1: /* Format 1, double operand. */
line = extract_operand (line, l1, sizeof (l1));
line = extract_operand (line, l2, sizeof (l2));
- res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
- res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
+ res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, true);
+ res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, true);
if (res)
break; /* Error occurred. All warnings were done before. */
{
/* The GIE bit is being set. */
warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
- this_insn_is_eint = TRUE;
+ this_insn_is_eint = true;
}
else
/* The GIE bit is being cleared. */
- this_insn_is_dint = TRUE;
+ this_insn_is_dint = true;
}
/* If an immediate value which is covered by the constant generator
is the src, then op1 will have been changed to either R2 or R3 by
&& (bin & 0x30) == 0x30)
{
warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
- this_insn_is_eint = TRUE;
+ this_insn_is_eint = true;
}
/* Any other use of the constant generator with destination R2, will
disable interrupts. */
else if (op1.mode == OP_REG
&& (op1.reg == 2 || op1.reg == 3))
- this_insn_is_dint = TRUE;
+ this_insn_is_dint = true;
else if (do_unknown_interrupt_nops)
{
/* FIXME: Couldn't work out whether the insn is enabling or
extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
else if (op1.reg || op1.am == 3) /* Not PC relative. */
- fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_EXT_SRC);
else
- fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_EXT_SRC);
}
extended |= (op2.exp.X_add_number >> 16) & 0xf;
else if (op1.mode == OP_EXP)
- fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
+ fix_new_exp (frag_now, where, 8, &(op2.exp), false,
op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
: BFD_RELOC_MSP430X_PCR20_EXT_ODST);
else
- fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op2.exp), false,
op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
: BFD_RELOC_MSP430X_PCR20_EXT_DST);
}
{
if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
- &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
+ &(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
- &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+ &(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
{
if (op2.reg) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
- &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
+ &(op2.exp), false, CHECK_RELOC_MSP430 (op2));
else
fix_new_exp (frag_now, where, 2,
- &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+ &(op2.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
}
line = extract_operand (line, l1, sizeof (l1));
res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
- &imm_op, extended_op, TRUE);
+ &imm_op, extended_op, true);
if (res)
break; /* Error in operand. */
extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
else if (op1.reg || op1.am == 3) /* Not PC relative. */
- fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_ABS20_EXT_SRC);
else
- fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
+ fix_new_exp (frag_now, where, 6, &(op1.exp), false,
BFD_RELOC_MSP430X_PCR20_EXT_SRC);
}
{
if (op1.reg || op1.am == 3) /* Not PC relative. */
fix_new_exp (frag_now, where, 2,
- &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
+ &(op1.exp), false, CHECK_RELOC_MSP430 (op1));
else
fix_new_exp (frag_now, where, 2,
- &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+ &(op1.exp), true, CHECK_RELOC_MSP430_PCREL);
}
}
}
frag = frag_more (2); /* Instr size is 1 word. */
where = frag - frag_now->fr_literal;
fix_new_exp (frag_now, where, 2,
- &exp, TRUE, BFD_RELOC_MSP430_10_PCREL);
+ &exp, true, BFD_RELOC_MSP430_10_PCREL);
bfd_putl16 ((bfd_vma) bin, frag);
}
if (is_opcode ("nop"))
{
- prev_insn_is_nop = TRUE;
- prev_insn_is_dint = FALSE;
- prev_insn_is_eint = FALSE;
+ prev_insn_is_nop = true;
+ prev_insn_is_dint = false;
+ prev_insn_is_eint = false;
}
else if (this_insn_is_dint || is_dint (opcode->name, bin))
{
- prev_insn_is_dint = TRUE;
- prev_insn_is_eint = FALSE;
- prev_insn_is_nop = FALSE;
+ prev_insn_is_dint = true;
+ prev_insn_is_eint = false;
+ prev_insn_is_nop = false;
check_for_nop |= NOP_CHECK_INTERRUPT;
}
/* NOP is not needed after EINT for 430 ISA. */
else if (target_is_430x () && (this_insn_is_eint || is_eint (opcode->name, bin)))
{
- prev_insn_is_eint = TRUE;
- prev_insn_is_nop = FALSE;
- prev_insn_is_dint = FALSE;
+ prev_insn_is_eint = true;
+ prev_insn_is_nop = false;
+ prev_insn_is_dint = false;
check_for_nop |= NOP_CHECK_INTERRUPT;
}
else
{
- prev_insn_is_nop = FALSE;
- prev_insn_is_dint = FALSE;
- prev_insn_is_eint = FALSE;
+ prev_insn_is_nop = false;
+ prev_insn_is_dint = false;
+ prev_insn_is_eint = false;
}
input_line_pointer = line;
}
}
-static bfd_boolean
+static bool
S_IS_GAS_LOCAL (symbolS * s)
{
const char * name;
unsigned int len;
if (s == NULL)
- return FALSE;
+ return false;
name = S_GET_NAME (s);
len = strlen (name) - 1;
another fix will be applied to the next word of insn anyway. */
if (hc->tlab == 2)
fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
- fragP->fr_offset, TRUE, rela);
+ fragP->fr_offset, true, rela);
fragP->fr_fix += 2;
}
/* Now apply fix. */
fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
- fragP->fr_offset, TRUE, rela);
+ fragP->fr_offset, true, rela);
/* Just fixed 2 bytes. */
fragP->fr_fix += 2;
}
adjusted. We return FALSE here so that linker relaxation will
work. */
-bfd_boolean
+bool
msp430_fix_adjustable (struct fix *fixp ATTRIBUTE_UNUSED)
{
/* If the symbol is in a non-code section then it should be OK. */
if (fixp->fx_addsy
&& ((S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) == 0))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/* Scan uleb128 subtraction expressions and insert fixups for them.
subtraction of two same-section symbols cannot be computed by
the assembler. */
-bfd_boolean
+bool
msp430_allow_local_subtract (expressionS * left,
expressionS * right,
segT section)
{
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
- return TRUE;
+ return true;
if (S_IS_GAS_LOCAL (left->X_add_symbol) || S_IS_GAS_LOCAL (right->X_add_symbol))
- return TRUE;
+ return true;
if (left->X_add_symbol == right->X_add_symbol)
- return TRUE;
+ return true;
/* We have to assume that there may be instructions between the
two symbols and that relaxation may increase the distance between
them. */
- return FALSE;
+ return false;
}
extern int msp430_enable_polys;
#define tc_fix_adjustable(FIX) msp430_fix_adjustable (FIX)
-extern bfd_boolean msp430_fix_adjustable (struct fix *);
+extern bool msp430_fix_adjustable (struct fix *);
/* Allow hexadecimal numbers with 'h' suffix. Note that if the number
starts with a letter it will be interpreted as a symbol name not a
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) msp430_allow_local_subtract (l, r, s)
-extern bfd_boolean msp430_allow_local_subtract (expressionS *, expressionS *, segT);
+extern bool msp430_allow_local_subtract (expressionS *, expressionS *, segT);
#define RELOC_EXPANSION_POSSIBLE
#define MAX_RELOC_EXPANSION 2
/* Set the machine type. */
bfd_default_set_arch_mach (stdoutput, bfd_arch_mt, mt_mach);
- literal_prefix_dollar_hex = TRUE;
+ literal_prefix_dollar_hex = true;
}
void
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
/* See whether we need to force a relocation into the output file. */
gas_cgen_md_apply_fix (fixP, valueP, seg);
}
-bfd_boolean
+bool
mt_fix_adjustable (fixS * fixP)
{
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
}
if (fixP->fx_addsy == NULL)
- return TRUE;
+ return true;
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
- return FALSE;
+ return false;
if (S_IS_WEAK (fixP->fx_addsy))
- return FALSE;
+ return false;
- return 1;
+ return true;
}
extern int mt_force_relocation (struct fix *);
#define tc_fix_adjustable(fixP) mt_fix_adjustable (fixP)
-extern bfd_boolean mt_fix_adjustable (struct fix *);
+extern bool mt_fix_adjustable (struct fix *);
static int enable_16bit = 1;
/* Save for md_assemble to distinguish if this instruction is
expanded from the pseudo instruction. */
-static bfd_boolean pseudo_opcode = FALSE;
+static bool pseudo_opcode = false;
static struct nds32_relocs_pattern *relocs_list = NULL;
/* Save instruction relation to inserting relaxation relocation. */
struct nds32_relocs_pattern
static int in_omit_fp = 0;
extern struct nds32_keyword keyword_gpr[];
/* Tag there is relax relocation having to link. */
-static bfd_boolean relaxing = FALSE;
+static bool relaxing = false;
/* ICT model. */
enum ict_option {
ICT_NONE = 0,
.br_range = BR_RANGE_S16M,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S16M,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
/* We do not use beqz38 and beqzs8 here directly because we
don't want to check register number for specail condition. */
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S64K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false},
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S16K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S16K,
.cond_field =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 15, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 15, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 2,
.relax_branch_isize[BR_RANGE_S256] = 2,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 2,
.relax_branch_isize[BR_RANGE_S256] = 2,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 4,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 0, 0, FALSE}
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 2,
.relax_branch_isize[BR_RANGE_S256] = 2,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 2,
.relax_branch_isize[BR_RANGE_S256] = 2,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 4,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7FF, TRUE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, true},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 0, 0xFFFFF, FALSE},
- {4, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 0, 0xFFFFF, false},
+ {4, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 8,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
.br_range = BR_RANGE_S256,
.cond_field =
{
- {0, 8, 0x7FF, TRUE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, true},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_seq[BR_RANGE_S256] =
{
},
.relax_code_condition[BR_RANGE_S256] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S256] = 4,
.relax_branch_isize[BR_RANGE_S256] = 4,
},
.relax_code_condition[BR_RANGE_S16K] =
{
- {0, 0, 0xFFFFF, FALSE},
- {4, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 0, 0xFFFFF, false},
+ {4, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16K] = 8,
.relax_branch_isize[BR_RANGE_S16K] = 4,
},
.relax_code_condition[BR_RANGE_S64K] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S64K] = 8,
.relax_branch_isize[BR_RANGE_S64K] = 4,
},
.relax_code_condition[BR_RANGE_S16M] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_S16M] = 8,
.relax_branch_isize[BR_RANGE_S16M] = 4,
},
.relax_code_condition[BR_RANGE_U4G] =
{
- {0, 8, 0x7FF, FALSE},
- {0, 20, 0x1F, FALSE},
- {0, 0, 0, FALSE}
+ {0, 8, 0x7FF, false},
+ {0, 20, 0x1F, false},
+ {0, 0, 0, false}
},
.relax_code_size[BR_RANGE_U4G] = 16,
.relax_branch_isize[BR_RANGE_U4G] = 4,
unsigned int pv ATTRIBUTE_UNUSED)
{
char *arg_label = argv[0];
- relaxing = TRUE;
+ relaxing = true;
/* b label */
if (nds32_pic)
{
{
md_assemblef ("j %s", arg_label);
}
- relaxing = FALSE;
+ relaxing = false;
}
static void
unsigned int pv ATTRIBUTE_UNUSED)
{
char *arg_label = argv[0];
- relaxing = TRUE;
+ relaxing = true;
/* bal|call label */
if (nds32_pic)
{
{
md_assemblef ("jal %s", arg_label);
}
- relaxing = FALSE;
+ relaxing = false;
}
static void
return;
}
- relaxing = TRUE;
+ relaxing = true;
/* rt, label */
if (!nds32_pic && !strstr (arg_label, "@"))
{
}
else
as_bad (_("need PIC qualifier with symbol. '%s'"), line);
- relaxing = FALSE;
+ relaxing = false;
}
static void
}
else if (!nds32_pic)
{
- relaxing = TRUE;
+ relaxing = true;
if (strstr (argv[1], "@TPOFF"))
{
/* ls.w $rt, sym@TPOFF */
md_assemblef ("sethi $ta,hi20(%s)", argv[1]);
md_assemblef ("%c%c%si %s,[$ta+lo12(%s)]", ls, size, sign, argv[0], argv[1]);
}
- relaxing = FALSE;
+ relaxing = false;
}
else
{
- relaxing = TRUE;
+ relaxing = true;
/* PIC code. */
if (strstr (argv[1], "@GOTOFF"))
{
{
as_bad (_("needs @GOT or @GOTOFF. %s"), argv[argc]);
}
- relaxing = FALSE;
+ relaxing = false;
}
}
if (label != NULL)
{
symbolS *sym;
- int label_seen = FALSE;
+ int label_seen = false;
struct frag *old_frag;
valueT old_value, new_value;
&& S_GET_VALUE (sym) == old_value)
{
/* Warning HERE! */
- label_seen = TRUE;
+ label_seen = true;
symbol_set_frag (sym, frag_now);
S_SET_VALUE (sym, new_value);
}
group = group->next;
group->next = new;
}
- relaxing = TRUE;
+ relaxing = true;
}
/* Decide the size of vector entries, only accepts 4 or 16 now. */
nds32_elf_build_relax_relation (fixS *fixP, expressionS *pexp, char* out,
struct nds32_asm_insn *insn, fragS *fragP,
const struct nds32_field *fld,
- bfd_boolean pseudo_hint)
+ bool pseudo_hint)
{
struct nds32_relocs_pattern *reloc_ptr;
struct nds32_relocs_group *group;
/* Set relaxing false only for relax_hint trigger it. */
if (!pseudo_opcode)
- relaxing = FALSE;
+ relaxing = false;
}
#define N32_MEM_EXT(insn) ((N32_OP6_MEM << 25) | insn)
/* Find the relaxation pattern according to instructions. */
-static bfd_boolean
+static bool
nds32_find_reloc_table (struct nds32_relocs_pattern *relocs_pattern,
struct nds32_relax_hint_table *hint_info)
{
default:
as_warn (_("relax hint unrecognized instruction: line %d."),
pattern->frag->fr_line);
- return FALSE;
+ return false;
}
}
else
if (!nds32_pic)
as_warn (_("Can not find match relax hint. Line: %d"),
relocs_pattern->frag->fr_line);
- return FALSE;
+ return false;
}
/* Get the match table. */
/* Branch relax pattern. */
relax_info = str_hash_find (nds32_relax_info_hash, opc);
if (!relax_info)
- return FALSE;
+ return false;
fixup_info = relax_info->relax_fixup[range];
code_seq = relax_info->relax_code_seq[range];
seq_size = relax_info->relax_code_size[range];
table_ptr++;
}
if (table_ptr->main_type == 0)
- return FALSE;
+ return false;
}
else
- return FALSE;
+ return false;
hint_fixup = hint_info->relax_fixup;
hint_code = hint_info->relax_code_seq;
memset (hint_fixup, 0, sizeof (nds32_relax_fixup_info_t));
/* Copy code sequence. */
memcpy (hint_code, code_seq, seq_size);
- return TRUE;
+ return true;
}
/* Because there are a lot of variant of load-store, check
#define CLEAN_REG(insn) ((insn) & 0xfe0003ff)
#define GET_OPCODE(insn) ((insn) & 0xfe000000)
-static bfd_boolean
+static bool
nds32_match_hint_insn (struct nds32_opcode *opcode, uint32_t seq)
{
const char *check_insn[] =
insn = CLEAN_REG (opcode->value);
if (insn == seq)
- return TRUE;
+ return true;
switch (seq)
{
|| insn == OP6 (LWI) || insn == OP6 (SWI)
|| insn == OP6 (LWC) || insn == OP6 (SWC)
|| insn == OP6 (LDC) || insn == OP6 (SDC))
- return TRUE;
+ return true;
break;
case OP6 (BR2):
/* This is for LONGCALL5 and LONGCALL6. */
if (insn == OP6 (BR2))
- return TRUE;
+ return true;
break;
case OP6 (BR1):
/* This is for LONGJUMP5 and LONGJUMP6. */
if (opcode->isize == 4
&& (insn == OP6 (BR1) || insn == OP6 (BR2) || insn == OP6 (BR3)))
- return TRUE;
+ return true;
else if (opcode->isize == 2)
{
for (i = 0; i < ARRAY_SIZE (check_insn); i++)
if (strcmp (opcode->opcode, check_insn[i]) == 0)
- return TRUE;
+ return true;
}
break;
case OP6 (MOVI):
/* This is for LONGJUMP7. */
if (opcode->isize == 2 && strcmp (opcode->opcode, "movi55") == 0)
- return TRUE;
+ return true;
break;
case OP6 (MEM):
if (OP6 (MEM) == GET_OPCODE (insn))
- return TRUE;
+ return true;
break;
case OP6 (JREG):
/* bit 24: N32_JI_JAL */ /* feed me! */
if ((insn & ~(N32_BIT (24))) == JREG (JRAL))
- return TRUE;
+ return true;
break;
default:
if (opcode->isize == 2)
{
for (i = 0; i < ARRAY_SIZE (check_insn); i++)
if (strcmp (opcode->opcode, check_insn[i]) == 0)
- return TRUE;
+ return true;
if ((strcmp (opcode->opcode, "add5.pc") == 0) ||
(strcmp (opcode->opcode, "add45") == 0))
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Append relax relocation for link time relaxing. */
/* Check instruction if it can be used for the baseline. */
-static bfd_boolean
+static bool
nds32_check_insn_available (struct nds32_asm_insn insn, const char *str)
{
int attr = insn.attr & ATTR_ALL;
|| (insn.attr & NASM_ATTR_ZOL)))
{
as_bad (_("Not support instruction %s in verbatim."), str);
- return FALSE;
+ return false;
}
free (s);
if (!enable_16bit && insn.opcode->isize == 2)
{
as_bad (_("16-bit instruction is disabled: %s."), str);
- return FALSE;
+ return false;
}
/* No isa setting or all isa can use. */
if (attr == 0 || attr == ATTR_ALL)
- return TRUE;
+ return true;
if (baseline_isa == 0)
{
if ((baseline_isa & attr) == 0)
{
as_bad (_("Instruction %s not supported in the baseline."), str);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Stub of machine dependent. */
struct nds32_relocs_group *group_temp;
fragS *fragP;
int label = label_exist;
- static bfd_boolean pseudo_hint = FALSE;
+ static bool pseudo_hint = false;
popcode = nds32_lookup_pseudo_opcode (str);
/* Note that we need to check 'verbatim' and
{
/* Pseudo instruction is with relax_hint. */
if (relaxing)
- pseudo_hint = TRUE;
- pseudo_opcode = TRUE;
+ pseudo_hint = true;
+ pseudo_opcode = true;
nds32_pseudo_opcode_wrapper (str, popcode);
- pseudo_opcode = FALSE;
- pseudo_hint = FALSE;
+ pseudo_opcode = false;
+ pseudo_hint = false;
nds32_elf_append_relax_relocs (NULL, relocs_list);
/* Free relax_hint group list. */
/* Check the prev_frag is legal. */
static void
-invalid_prev_frag (fragS * fragP, fragS **prev_frag, bfd_boolean relax)
+invalid_prev_frag (fragS * fragP, fragS **prev_frag, bool relax)
{
addressT address;
fragS *frag_start = *prev_frag;
static fragS *prev_frag = NULL;
int adjust = 0;
- invalid_prev_frag (fragP, &prev_frag, TRUE);
+ invalid_prev_frag (fragP, &prev_frag, true);
if (fragP->tc_frag_data.flag & NDS32_FRAG_BRANCH)
adjust = nds32_relax_branch_instructions (segment, fragP, stretch, 0);
static fragS *prev_frag = NULL;
int adjust = 0;
- invalid_prev_frag (fragP, &prev_frag, FALSE);
+ invalid_prev_frag (fragP, &prev_frag, false);
if (fragP->tc_frag_data.flag & NDS32_FRAG_BRANCH)
adjust = nds32_relax_branch_instructions (segment, fragP, 0, 1);
{
}
-static bfd_boolean
+static bool
nds32_relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
/* Implement md_allow_local_subtract. */
-bfd_boolean
+bool
nds32_allow_local_subtract (expressionS *expr_l ATTRIBUTE_UNUSED,
expressionS *expr_r ATTRIBUTE_UNUSED,
segT sec ATTRIBUTE_UNUSED)
{
/* Don't allow any subtraction, because relax may change the code. */
- return FALSE;
+ return false;
}
/* Sort relocation by address.
Return whether this symbol (fixup) can be replaced with
section symbols. */
-bfd_boolean
+bool
nds32_fix_adjustable (fixS *fixP)
{
switch (fixP->fx_r_type)
/* expr.c */
extern int nds32_parse_name (char const *, expressionS *, enum expr_mode, char *);
-extern bfd_boolean nds32_allow_local_subtract (expressionS *, expressionS *, segT);
+extern bool nds32_allow_local_subtract (expressionS *, expressionS *, segT);
#define md_parse_name(name, exprP, mode, nextcharP) \
nds32_parse_name (name, exprP, mode, nextcharP)
#define md_allow_local_subtract(lhs,rhs,sect) nds32_allow_local_subtract (lhs, rhs, sect)
/* write.c. */
extern long nds32_pcrel_from_section (struct fix *, segT);
-extern bfd_boolean nds32_fix_adjustable (struct fix *);
+extern bool nds32_fix_adjustable (struct fix *);
extern void nds32_frob_file (void);
extern void nds32_post_relax_hook (void);
extern void nds32_frob_file_before_fix (void);
int offset;
int bitpos; /* Register position. */
int bitmask; /* Number of register bits. */
- bfd_boolean signed_extend;
+ bool signed_extend;
} nds32_cond_field_t;
/* The max relaxation pattern is 20-bytes including the nop. */
and macro expansions generate a warning.
.set at -> noat = 0, assembly code using at warn but macro expansions
do not generate warnings. */
- bfd_boolean noat;
+ bool noat;
/* .set nobreak -> nobreak = 1 allows assembly code to use ba,bt without
warning.
.set break -> nobreak = 0, assembly code using ba,bt warns. */
- bfd_boolean nobreak;
+ bool nobreak;
/* .cmd line option -relax-all allows all branches and calls to be replaced
with longer versions.
a section. */
relax_optionT relax;
-} nios2_as_options = {FALSE, FALSE, relax_section};
+} nios2_as_options = {false, false, relax_section};
typedef struct nios2_insn_reloc
if (label != NULL && !switched_seg_p)
{
symbolS *sym;
- int label_seen = FALSE;
+ int label_seen = false;
struct frag *old_frag;
valueT old_value;
valueT new_value;
if (symbol_get_frag (sym) == old_frag
&& S_GET_VALUE (sym) == old_value)
{
- label_seen = TRUE;
+ label_seen = true;
symbol_set_frag (sym, frag_now);
S_SET_VALUE (sym, new_value);
}
SKIP_WHITESPACE ();
if (is_end_of_line[(unsigned char) *input_line_pointer])
{
- bfd_boolean done = TRUE;
+ bool done = true;
*endline = 0;
if (!strcmp (directive, "noat"))
- nios2_as_options.noat = TRUE;
+ nios2_as_options.noat = true;
else if (!strcmp (directive, "at"))
- nios2_as_options.noat = FALSE;
+ nios2_as_options.noat = false;
else if (!strcmp (directive, "nobreak"))
- nios2_as_options.nobreak = TRUE;
+ nios2_as_options.nobreak = true;
else if (!strcmp (directive, "break"))
- nios2_as_options.nobreak = FALSE;
+ nios2_as_options.nobreak = false;
else if (!strcmp (directive, "norelax"))
nios2_as_options.relax = relax_none;
else if (!strcmp (directive, "relaxsection"))
else if (!strcmp (directive, "relaxall"))
nios2_as_options.relax = relax_all;
else
- done = FALSE;
+ done = false;
if (done)
{
fragS *sym_frag = symbol_get_frag (symbolp);
offsetT offset;
int n;
- bfd_boolean is_cdx = FALSE;
+ bool is_cdx = false;
target += S_GET_VALUE (symbolp);
if (IS_CDXBRANCH (subtype) && IS_UBRANCH (subtype)
&& offset >= -1024 && offset < 1024)
/* PC-relative CDX branch with 11-bit offset. */
- is_cdx = TRUE;
+ is_cdx = true;
else if (IS_CDXBRANCH (subtype) && IS_CBRANCH (subtype)
&& offset >= -128 && offset < 128)
/* PC-relative CDX branch with 8-bit offset. */
- is_cdx = TRUE;
+ is_cdx = true;
else if (offset >= -32768 && offset < 32768)
/* Fits in PC-relative branch. */
n = 0;
unsigned int addend_mask, addi_mask, op;
offsetT addend, remainder;
int i;
- bfd_boolean is_r2 = (bfd_get_mach (stdoutput) == bfd_mach_nios2r2);
+ bool is_r2 = (bfd_get_mach (stdoutput) == bfd_mach_nios2r2);
/* If this is a CDX branch we're not relaxing, just generate the fixup. */
if (IS_CDXBRANCH (subtype))
/** Fixups and overflow checking. */
/* Check a fixup for overflow. */
-static bfd_boolean
+static bool
nios2_check_overflow (valueT fixup, reloc_howto_type *howto)
{
/* If there is a rightshift, check that the low-order bits are
{
if ((~(~((valueT) 0) << howto->rightshift) & fixup)
&& howto->complain_on_overflow != complain_overflow_dont)
- return TRUE;
+ return true;
fixup = ((signed)fixup) >> howto->rightshift;
}
case complain_overflow_bitfield:
if ((fixup >> howto->bitsize) != 0
&& ((signed) fixup >> howto->bitsize) != -1)
- return TRUE;
+ return true;
break;
case complain_overflow_signed:
if ((fixup & 0x80000000) > 0)
{
/* Check for negative overflow. */
if ((signed) fixup < (signed) (~0U << (howto->bitsize - 1)))
- return TRUE;
+ return true;
}
else
{
/* Check for positive overflow. */
if (fixup >= ((unsigned) 1 << (howto->bitsize - 1)))
- return TRUE;
+ return true;
}
break;
case complain_overflow_unsigned:
if ((fixup >> howto->bitsize) != 0)
- return TRUE;
+ return true;
break;
default:
as_bad (_("error checking for overflow - broken assembler"));
break;
}
- return FALSE;
+ return false;
}
/* Emit diagnostic for fixup overflow. */
int i;
p = argstr;
i = 0;
- bfd_boolean terminate = FALSE;
+ bool terminate = false;
/* This rest of this function is it too fragile and it mostly works,
therefore special case this one. */
}
if (*parsestr == '\0' || (p != NULL && *p == '\0'))
- terminate = TRUE;
+ terminate = true;
++i;
}
symbolS *symp = reloc->reloc_expression.X_add_symbol;
offsetT offset = reloc->reloc_expression.X_add_number;
char *f;
- bfd_boolean is_cdx = (insn->insn_nios2_opcode->size == 2);
+ bool is_cdx = (insn->insn_nios2_opcode->size == 2);
/* Tag dwarf2 debug info to the address at the start of the insn.
We must do it before frag_var() below closes off the frag. */
symbolS *symp = reloc->reloc_expression.X_add_symbol;
offsetT offset = reloc->reloc_expression.X_add_number;
char *f;
- bfd_boolean is_cdx = (insn->insn_nios2_opcode->size == 2);
+ bool is_cdx = (insn->insn_nios2_opcode->size == 2);
/* Tag dwarf2 debug info to the address at the start of the insn.
We must do it before frag_var() below closes off the frag. */
as_fatal (_("duplicate %s"), nios2_ps_insn_info_structs[i].pseudo_insn);
/* Assembler option defaults. */
- nios2_as_options.noat = FALSE;
- nios2_as_options.nobreak = FALSE;
+ nios2_as_options.noat = false;
+ nios2_as_options.nobreak = false;
/* Initialize the alignment data. */
nios2_current_align_seg = now_seg;
unsigned long saved_pinfo = 0;
nios2_insn_infoS thisinsn;
nios2_insn_infoS *insn = &thisinsn;
- bfd_boolean ps_error = FALSE;
+ bool ps_error = false;
/* Make sure we are aligned on an appropriate boundary. */
if (nios2_current_align < nios2_min_align)
{
ps_insn = nios2_translate_pseudo_insn (insn);
if (!ps_insn)
- ps_error = TRUE;
+ ps_error = true;
}
/* If we found invalid pseudo-instruction syntax, the error's already
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
\f
int
discard_rest_of_line ();
}
-static bfd_boolean nodelay = FALSE;
+static bool nodelay = false;
static void
s_nodelay (int val ATTRIBUTE_UNUSED)
{
- nodelay = TRUE;
+ nodelay = true;
}
const char or1k_comment_chars [] = ";#";
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
-bfd_boolean
+bool
or1k_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries. */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
#define md_apply_fix or1k_apply_fix
extern void or1k_apply_fix (struct fix *, valueT *, segT);
-extern bfd_boolean or1k_fix_adjustable (struct fix *);
+extern bool or1k_fix_adjustable (struct fix *);
#define tc_fix_adjustable(FIX) or1k_fix_adjustable (FIX)
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
str = parse_expression (str + 1, operand);
if (operand->error)
return str;
- operand->additional = TRUE;
+ operand->additional = true;
operand->word = operand->reloc.exp.X_add_number;
switch (operand->reloc.exp.X_op)
{
}
str++;
- operand->additional = TRUE;
+ operand->additional = true;
operand->code |= 060;
switch (operand->reloc.exp.X_op)
{
insn.code = op->opcode;
insn.reloc.type = BFD_RELOC_NONE;
op1.error = NULL;
- op1.additional = FALSE;
+ op1.additional = false;
op1.reloc.type = BFD_RELOC_NONE;
op2.error = NULL;
- op2.additional = FALSE;
+ op2.additional = false;
op2.reloc.type = BFD_RELOC_NONE;
str = p;
/* Whether to use user friendly register names. */
#ifndef TARGET_REG_NAMES_P
-#define TARGET_REG_NAMES_P FALSE
+#define TARGET_REG_NAMES_P false
#endif
/* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
applied to constants. */
#define REPORT_OVERFLOW_HI 0
-static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
+static bool reg_names_p = TARGET_REG_NAMES_P;
static void ppc_macro (char *, const struct powerpc_macro *);
static void ppc_byte (int);
* original state.
*/
-static bfd_boolean
+static bool
register_name (expressionS *expressionP)
{
const struct pd_reg *reg;
name = ++input_line_pointer;
else if (!reg_names_p || !ISALPHA (name[0]))
- return FALSE;
+ return false;
c = get_symbol_name (&name);
reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name);
/* Make the rest nice. */
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
- return FALSE;
+ return false;
}
\f
/* This function is called for each symbol seen in an expression. It
to use for condition codes. */
/* Whether to do the special parsing. */
-static bfd_boolean cr_operand;
+static bool cr_operand;
/* Names to recognize in a condition code. This table is sorted. */
static const struct pd_reg cr_names[] =
/* Whether this is Solaris or not. */
#ifdef TARGET_SOLARIS_COMMENT
-#define SOLARIS_P TRUE
+#define SOLARIS_P true
#else
-#define SOLARIS_P FALSE
+#define SOLARIS_P false
#endif
-static bfd_boolean msolaris = SOLARIS_P;
+static bool msolaris = SOLARIS_P;
#endif
#ifdef OBJ_XCOFF
/* Return true if the ppc_xcoff_section structure is already
initialized. */
-static bfd_boolean
+static bool
ppc_xcoff_section_is_initialized (struct ppc_xcoff_section *section)
{
return section->segment != NULL;
and .tdata. These symbols won't be output. */
static void
ppc_init_xcoff_section (struct ppc_xcoff_section *s, segT seg,
- bfd_boolean need_dummy)
+ bool need_dummy)
{
s->segment = seg;
s->next_subsegment = 2;
}
else if (strcmp (arg, "regnames") == 0)
- reg_names_p = TRUE;
+ reg_names_p = true;
else if (strcmp (arg, "no-regnames") == 0)
- reg_names_p = FALSE;
+ reg_names_p = false;
#ifdef OBJ_ELF
/* -mrelocatable/-mrelocatable-lib -- warn about initializations
else if (strcmp (arg, "solaris") == 0)
{
- msolaris = TRUE;
+ msolaris = true;
ppc_comment_chars = ppc_solaris_comment_chars;
}
else if (strcmp (arg, "no-solaris") == 0)
{
- msolaris = FALSE;
+ msolaris = false;
ppc_comment_chars = ppc_eabi_comment_chars;
}
else if (strcmp (arg, "spe2") == 0)
/* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
Return TRUE if there's a problem, otherwise FALSE. */
-static bfd_boolean
+static bool
insn_validate (const struct powerpc_opcode *op)
{
const unsigned char *o;
if ((op->opcode & omask) != op->opcode)
{
as_bad (_("mask trims opcode bits for %s"), op->name);
- return TRUE;
+ return true;
}
/* The operands must not overlap the opcode or each other. */
for (o = op->operands; *o; ++o)
{
- bfd_boolean optional = FALSE;
+ bool optional = false;
if (*o >= num_powerpc_operands)
{
as_bad (_("operand index error for %s"), op->name);
- return TRUE;
+ return true;
}
else
{
{
as_bad (_("operand %d overlap in %s"),
(int) (o - op->operands), op->name);
- return TRUE;
+ return true;
}
omask |= mask;
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
- optional = TRUE;
+ optional = true;
else if (optional)
{
as_bad (_("non-optional operand %d follows optional operand in %s"),
(int) (o - op->operands), op->name);
- return TRUE;
+ return true;
}
}
}
- return FALSE;
+ return false;
}
/* Insert opcodes and macros into hash tables. Called at startup and
const struct powerpc_opcode *op_end;
const struct powerpc_macro *macro;
const struct powerpc_macro *macro_end;
- bfd_boolean bad_insn = FALSE;
+ bool bad_insn = false;
if (ppc_hash != NULL)
htab_delete (ppc_hash);
if (mask != right_bit)
{
as_bad (_("powerpc_operands[%d].bitm invalid"), i);
- bad_insn = TRUE;
+ bad_insn = true;
}
for (j = i + 1; j < num_powerpc_operands; ++j)
if (memcmp (&powerpc_operands[i], &powerpc_operands[j],
{
as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
j, i);
- bad_insn = TRUE;
+ bad_insn = true;
}
}
}
&& new_opcode < PPC_OP (op[-1].opcode))
{
as_bad (_("major opcode is not sorted for %s"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
if ((op->flags & PPC_OPCODE_VLE) != 0)
{
as_bad (_("%s is enabled by vle flag"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
if (PPC_OP (op->opcode) != 4
&& PPC_OP (op->opcode) != 31
&& (op->deprecated & PPC_OPCODE_VLE) == 0)
{
as_bad (_("%s not disabled by vle flag"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
bad_insn |= insn_validate (op);
}
&& str_hash_insert (ppc_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
}
&& new_opcode < PPC_PREFIX_SEG (op[-1].opcode))
{
as_bad (_("major opcode is not sorted for %s"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
bad_insn |= insn_validate (op);
}
&& str_hash_insert (ppc_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
}
&& new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask)))
{
as_bad (_("major opcode is not sorted for %s"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
bad_insn |= insn_validate (op);
&& str_hash_insert (ppc_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
}
if (new_seg < old_seg)
{
as_bad (_("major opcode is not sorted for %s"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
}
&& str_hash_insert (ppc_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
}
&& str_hash_insert (ppc_macro_hash, macro->name, macro, 0) != NULL)
{
as_bad (_("duplicate %s"), macro->name);
- bad_insn = TRUE;
+ bad_insn = true;
}
if (bad_insn)
/* Create XCOFF sections with .text in first, as it's creating dummy symbols
to serve as initial csects. This forces the text csects to precede the
data csects. These symbols will not be output. */
- ppc_init_xcoff_section (&ppc_xcoff_text_section, text_section, TRUE);
- ppc_init_xcoff_section (&ppc_xcoff_data_section, data_section, TRUE);
- ppc_init_xcoff_section (&ppc_xcoff_bss_section, bss_section, FALSE);
+ ppc_init_xcoff_section (&ppc_xcoff_text_section, text_section, true);
+ ppc_init_xcoff_section (&ppc_xcoff_data_section, data_section, true);
+ ppc_init_xcoff_section (&ppc_xcoff_bss_section, bss_section, false);
#endif
}
pc-relative in PC_RELATIVE. */
static unsigned int
-fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative)
+fixup_size (bfd_reloc_code_real_type reloc, bool *pc_relative)
{
unsigned int size = 0;
- bfd_boolean pcrel = FALSE;
+ bool pcrel = false;
switch (reloc)
{
#endif
case BFD_RELOC_PPC_VLE_REL8:
size = 2;
- pcrel = TRUE;
+ pcrel = true;
break;
case BFD_RELOC_32:
case BFD_RELOC_PPC_VLE_REL15:
case BFD_RELOC_PPC_VLE_REL24:
size = 4;
- pcrel = TRUE;
+ pcrel = true;
break;
#ifndef OBJ_XCOFF
case BFD_RELOC_PPC64_PCREL34:
case BFD_RELOC_PPC64_PLT_PCREL34:
size = 8;
- pcrel = TRUE;
+ pcrel = true;
break;
default:
if (((operand->flags & PPC_OPERAND_CR_REG) != 0)
|| (operand->flags & PPC_OPERAND_CR_BIT) != 0)
{
- cr_operand = TRUE;
+ cr_operand = true;
lex_type['%'] |= LEX_BEGIN_NAME;
}
expression (&ex);
- cr_operand = FALSE;
+ cr_operand = false;
lex_type['%'] = save_lex;
}
fixS *fixP;
if (fixups[i].reloc != BFD_RELOC_NONE)
{
- bfd_boolean pcrel;
+ bool pcrel;
unsigned int size = fixup_size (fixups[i].reloc, &pcrel);
int offset = target_big_endian ? (insn_length - size) : 0;
/* This is set if we are creating a .stabx symbol, since we don't want
to handle symbol suffixes for such symbols. */
-static bfd_boolean ppc_stab_symbol;
+static bool ppc_stab_symbol;
/* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common
symbols in the .bss segment as though they were local common
if (!ppc_xcoff_section_is_initialized (section))
{
ppc_init_xcoff_section (section,
- subseg_new (".tbss", 0), FALSE);
+ subseg_new (".tbss", 0), false);
bfd_set_section_flags (section->segment,
SEC_ALLOC | SEC_THREAD_LOCAL);
seg_info (section->segment)->bss = 1;
if (!ppc_xcoff_section_is_initialized (section))
{
ppc_init_xcoff_section (section, subseg_new (".tdata", 0),
- TRUE);
+ true);
bfd_set_section_flags (section->segment, SEC_ALLOC
| SEC_LOAD | SEC_RELOC | SEC_DATA
| SEC_THREAD_LOCAL);
if (!ppc_xcoff_section_is_initialized (section))
{
ppc_init_xcoff_section (section, subseg_new (".tbss", 0),
- FALSE);
+ false);
bfd_set_section_flags (section->segment, SEC_ALLOC |
SEC_THREAD_LOCAL);
seg_info (section->segment)->bss = 1;
c = get_symbol_name (&name);
fix_at_start (symbol_get_frag (ppc_current_csect), 0,
- symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE);
+ symbol_find_or_make (name), 0, false, BFD_RELOC_NONE);
*input_line_pointer = c;
SKIP_WHITESPACE_AFTER_NAME ();
}
++input_line_pointer;
- ppc_stab_symbol = TRUE;
+ ppc_stab_symbol = true;
sym = symbol_make (name);
- ppc_stab_symbol = FALSE;
+ ppc_stab_symbol = false;
symbol_get_tc (sym)->real_name = name;
seen. It tells ppc_adjust_symtab whether it needs to look through
the symbols. */
-static bfd_boolean ppc_saw_abs;
+static bool ppc_saw_abs;
/* Change the name of a symbol just before writing it out. Set the
real name if the .rename pseudo-op was used. Otherwise, remove any
{
/* This is an absolute symbol. The csect will be created by
ppc_adjust_symtab. */
- ppc_saw_abs = TRUE;
+ ppc_saw_abs = true;
a->x_csect.x_smtyp = XTY_LD;
if (symbol_get_tc (sym)->symbol_class == -1)
symbol_get_tc (sym)->symbol_class = XMC_XO;
coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1;
}
- ppc_saw_abs = FALSE;
+ ppc_saw_abs = false;
}
/* Set the VMA for a section. This is called on all the sections in
{
/* -mno-link-relax / -mlink-relax: generate (or not)
relocations for linker relaxation. */
- bfd_boolean link_relax;
+ bool link_relax;
/* -mno-warn-regname-label: do not output a warning that a label name
matches a register name. */
- bfd_boolean warn_regname_label;
+ bool warn_regname_label;
};
-static struct pru_opt_s pru_opt = { TRUE, TRUE };
+static struct pru_opt_s pru_opt = { true, true };
const char *md_shortopts = "r";
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
/* Return true if STR starts with PREFIX, which should be a string literal. */
if (label != NULL && !switched_seg_p)
{
symbolS *sym;
- int label_seen = FALSE;
+ int label_seen = false;
struct frag *old_frag;
valueT old_value;
valueT new_value;
if (symbol_get_frag (sym) == old_frag
&& S_GET_VALUE (sym) == old_value)
{
- label_seen = TRUE;
+ label_seen = true;
symbol_set_frag (sym, frag_now);
S_SET_VALUE (sym, new_value);
}
SKIP_WHITESPACE ();
if (is_end_of_line[(unsigned char) *input_line_pointer])
{
- bfd_boolean done = TRUE;
+ bool done = true;
*endline = 0;
if (!strcmp (directive, "no_warn_regname_label"))
- pru_opt.warn_regname_label = FALSE;
+ pru_opt.warn_regname_label = false;
else
- done = FALSE;
+ done = false;
if (done)
{
}
\f
-static bfd_boolean
+static bool
relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
int i;
p = argstr;
i = 0;
- bfd_boolean terminate = FALSE;
+ bool terminate = false;
/* This rest of this function is it too fragile and it mostly works,
therefore special case this one. */
}
if (*parsestr == '\0' || (p != NULL && *p == '\0'))
- terminate = TRUE;
+ terminate = true;
++i;
}
pru_mode = PRU_MODE_TEST;
break;
case OPTION_LINK_RELAX:
- pru_opt.link_relax = TRUE;
+ pru_opt.link_relax = true;
break;
case OPTION_NO_LINK_RELAX:
- pru_opt.link_relax = FALSE;
+ pru_opt.link_relax = false;
break;
case OPTION_NO_WARN_REGNAME_LABEL:
- pru_opt.warn_regname_label = FALSE;
+ pru_opt.warn_regname_label = false;
break;
default:
return 0;
int
pru_parse_cons_expression (expressionS *exp, int nbytes)
{
- int is_pmem = FALSE;
+ int is_pmem = false;
char *tmp;
tmp = input_line_pointer = skip_space (input_line_pointer);
if (*input_line_pointer == '(')
{
input_line_pointer = skip_space (input_line_pointer + 1);
- is_pmem = TRUE;
+ is_pmem = true;
expression (exp);
if (*input_line_pointer == ')')
else
{
as_bad (_("`)' required"));
- is_pmem = FALSE;
+ is_pmem = false;
}
return is_pmem;
cfi_add_CFA_def_cfa (fp_regno, 0);
}
-bfd_boolean
+bool
pru_allow_local_subtract (expressionS * left,
expressionS * right,
segT section)
{
/* If we are not in relaxation mode, subtraction is OK. */
if (!linkrelax)
- return TRUE;
+ return true;
/* If the symbols are not in a code section then they are OK. */
if ((section->flags & SEC_CODE) == 0)
- return TRUE;
+ return true;
if (left->X_add_symbol == right->X_add_symbol)
- return TRUE;
+ return true;
/* We have to assume that there may be instructions between the
two symbols and that relaxation may increase the distance between
them. */
- return FALSE;
+ return false;
}
/* The difference between same-section symbols may be affected by linker
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) pru_allow_local_subtract (l, r, s)
-extern bfd_boolean pru_allow_local_subtract (expressionS *, expressionS *,
- segT);
+extern bool pru_allow_local_subtract (expressionS *, expressionS *, segT);
#endif /* __TC_PRU__ */
static unsigned xlen = 0; /* The width of an x-register. */
static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
-static bfd_boolean rve_abi = FALSE;
+static bool rve_abi = false;
enum float_abi
{
FLOAT_ABI_DEFAULT = -1,
};
static void
-riscv_set_rvc (bfd_boolean rvc_value)
+riscv_set_rvc (bool rvc_value)
{
if (rvc_value)
elf_flags |= EF_RISCV_RVC;
}
static void
-riscv_set_rve (bfd_boolean rve_value)
+riscv_set_rve (bool rve_value)
{
riscv_opts.rve = rve_value;
}
static riscv_subset_list_t riscv_subsets;
-static bfd_boolean
+static bool
riscv_subset_supports (const char *feature)
{
struct riscv_subset_t *subset;
if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
- return TRUE;
+ return true;
return riscv_lookup_subset (&riscv_subsets, feature, &subset);
}
-static bfd_boolean
+static bool
riscv_multi_subset_supports (enum riscv_insn_class insn_class)
{
switch (insn_class)
default:
as_fatal ("internal: unreachable");
- return FALSE;
+ return false;
}
}
}
/* Indicate -mabi option is explictly set. */
-static bfd_boolean explicit_mabi = FALSE;
+static bool explicit_mabi = false;
static void
-riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
+riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve)
{
abi_xlen = new_xlen;
float_abi = new_float_abi;
if (!explicit_mabi)
{
if (riscv_subset_supports ("q"))
- riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
+ riscv_set_abi (xlen, FLOAT_ABI_QUAD, false);
else if (riscv_subset_supports ("d"))
- riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
+ riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false);
else
- riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
+ riscv_set_abi (xlen, FLOAT_ABI_SOFT, false);
}
else
{
const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* Indicate we are already assemble any instructions or not. */
-static bfd_boolean start_assemble = FALSE;
+static bool start_assemble = false;
/* Indicate ELF attributes are explicitly set. */
-static bfd_boolean explicit_attr = FALSE;
+static bool explicit_attr = false;
/* Indicate CSR or priv instructions are explicitly used. */
-static bfd_boolean explicit_priv_attr = FALSE;
+static bool explicit_priv_attr = false;
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
enum riscv_spec_class abort_version)
{
struct riscv_csr_extra *entry, *pre_entry;
- bfd_boolean need_enrty = TRUE;
+ bool need_enrty = true;
pre_entry = NULL;
entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
&& entry->address == address
&& entry->define_version == define_version
&& entry->abort_version == abort_version)
- need_enrty = FALSE;
+ need_enrty = false;
pre_entry = entry;
entry = entry->next;
}
{
struct riscv_csr_extra *saved_entry = entry;
enum riscv_csr_class csr_class = entry->csr_class;
- bfd_boolean need_check_version = TRUE;
- bfd_boolean result = TRUE;
+ bool need_check_version = true;
+ bool result = true;
switch (csr_class)
{
break;
case CSR_CLASS_F:
result = riscv_subset_supports ("f");
- need_check_version = FALSE;
+ need_check_version = false;
break;
case CSR_CLASS_DEBUG:
- need_check_version = FALSE;
+ need_check_version = false;
break;
default:
as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
return DECODE_REG_NUM (r);
}
-static bfd_boolean
+static bool
reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
{
char *e;
return reg >= 0;
}
-static bfd_boolean
+static bool
arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
{
const char *p = strchr (*s, ',');
size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
if (len == 0)
- return FALSE;
+ return false;
for (i = 0; i < size; i++)
if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
{
*regnop = i;
*s += len;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* For consistency checking, verify that all bits are specified either
by the match/mask part of the instruction definition, or by the
operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
-static bfd_boolean
+static bool
validate_riscv_insn (const struct riscv_opcode *opc, int length)
{
const char *p = opc->args;
{
as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
opc->name, opc->args);
- return FALSE;
+ return false;
}
#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `CF%c'): %s %s"),
c, opc->name, opc->args);
- return FALSE;
+ return false;
}
break;
default:
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `C%c'): %s %s"),
c, opc->name, opc->args);
- return FALSE;
+ return false;
}
break;
case ',': break;
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `F%c'): %s %s"),
c, opc->name, opc->args);
- return FALSE;
+ return false;
}
break;
case 'O': /* Opcode for .insn directive. */
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `F%c'): %s %s"),
c, opc->name, opc->args);
- return FALSE;
+ return false;
}
break;
default:
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `%c'): %s %s"),
c, opc->name, opc->args);
- return FALSE;
+ return false;
}
#undef USE_BITS
if (used_bits != required_bits)
"(bits 0x%lx undefined): %s %s"),
~(unsigned long)(used_bits & required_bits),
opc->name, opc->args);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
struct percent_op_match
static htab_t
init_opcode_hash (const struct riscv_opcode *opcodes,
- bfd_boolean insn_directive_p)
+ bool insn_directive_p)
{
int i = 0;
int length;
if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
as_warn (_("could not set architecture and machine"));
- op_hash = init_opcode_hash (riscv_opcodes, FALSE);
- insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
+ op_hash = init_opcode_hash (riscv_opcodes, false);
+ insn_type_hash = init_opcode_hash (riscv_insn_types, true);
reg_names_hash = str_htab_create ();
hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
ip->fixp = fix_new_exp (ip->frag, ip->where,
bfd_get_reloc_size (howto),
- address_expr, FALSE, reloc_type);
+ address_expr, false, reloc_type);
ip->fixp->fx_tcbit = riscv_opts.relax;
}
static void
check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
- bfd_boolean maybe_csr)
+ bool maybe_csr)
{
if (ex->X_op == O_big)
as_bad (_("unsupported large constant"));
/* Zero extend and sign extend byte/half-word/word. */
static void
-riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
+riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
{
if (sign)
{
break;
case M_ZEXTH:
- riscv_ext (rd, rs1, xlen - 16, FALSE);
+ riscv_ext (rd, rs1, xlen - 16, false);
break;
case M_ZEXTW:
- riscv_ext (rd, rs1, xlen - 32, FALSE);
+ riscv_ext (rd, rs1, xlen - 32, false);
break;
case M_SEXTB:
- riscv_ext (rd, rs1, xlen - 8, TRUE);
+ riscv_ext (rd, rs1, xlen - 8, true);
break;
case M_SEXTH:
- riscv_ext (rd, rs1, xlen - 16, TRUE);
+ riscv_ext (rd, rs1, xlen - 16, true);
break;
default:
move *STR over the operator and store its relocation code in *RELOC.
Leave both *STR and *RELOC alone when returning false. */
-static bfd_boolean
+static bool
parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
const struct percent_op_match *percent_op)
{
"current ABI", percent_op->str);
*reloc = BFD_RELOC_UNUSED;
}
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
static void
"lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
an implicit offset was detected. */
-static bfd_boolean
+static bool
riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
{
/* Check whether there is only a single bracketed expression left.
{
ep->X_op = O_constant;
ep->X_add_number = 0;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* All RISC-V CSR instructions belong to one of these classes. */
CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
CSR address is 0x3. */
-static bfd_boolean
+static bool
riscv_csr_read_only_check (insn_t insn)
{
int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
|| csr_insn == INSN_CSRRC)
&& rs1 != 0)
|| csr_insn == INSN_CSRRW))
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Return True if it is a privileged instruction. Otherwise, return FALSE.
dret is defined in the debug spec, so it should be checked in the future,
too. */
-static bfd_boolean
+static bool
riscv_is_priv_insn (insn_t insn)
{
return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
const struct percent_op_match *p;
const char *error = "unrecognized opcode";
/* Indicate we are assembling instruction with CSR. */
- bfd_boolean insn_with_csr = FALSE;
+ bool insn_with_csr = false;
/* Parse the name of the instruction. Terminate the string if whitespace
is found so that str_hash_find only sees the name part of the string. */
break;
if (riscv_is_priv_insn (ip->insn_opcode))
- explicit_priv_attr = TRUE;
+ explicit_priv_attr = true;
/* Check if we write a read-only CSR by the CSR
instruction. */
if (save_c)
*(argsStart - 1) = save_c;
as_warn (_("read-only CSR is written `%s'"), str);
- insn_with_csr = FALSE;
+ insn_with_csr = false;
}
}
if (*s != '\0')
break;
/* Successful assembly. */
error = NULL;
- insn_with_csr = FALSE;
+ insn_with_csr = false;
goto out;
case 'C': /* RVC */
case '<': /* Shift amount, 0 - 31. */
my_getExpression (imm_expr, s);
- check_absolute_expr (ip, imm_expr, FALSE);
+ check_absolute_expr (ip, imm_expr, false);
if ((unsigned long) imm_expr->X_add_number > 31)
as_bad (_("improper shift amount (%lu)"),
(unsigned long) imm_expr->X_add_number);
case '>': /* Shift amount, 0 - (XLEN-1). */
my_getExpression (imm_expr, s);
- check_absolute_expr (ip, imm_expr, FALSE);
+ check_absolute_expr (ip, imm_expr, false);
if ((unsigned long) imm_expr->X_add_number >= xlen)
as_bad (_("improper shift amount (%lu)"),
(unsigned long) imm_expr->X_add_number);
case 'Z': /* CSRRxI immediate. */
my_getExpression (imm_expr, s);
- check_absolute_expr (ip, imm_expr, FALSE);
+ check_absolute_expr (ip, imm_expr, false);
if ((unsigned long) imm_expr->X_add_number > 31)
as_bad (_("improper CSRxI immediate (%lu)"),
(unsigned long) imm_expr->X_add_number);
continue;
case 'E': /* Control register. */
- insn_with_csr = TRUE;
- explicit_priv_attr = TRUE;
+ insn_with_csr = true;
+ explicit_priv_attr = true;
if (reg_lookup (&s, RCLASS_CSR, ®no))
INSERT_OPERAND (CSR, *ip, regno);
else
{
my_getExpression (imm_expr, s);
- check_absolute_expr (ip, imm_expr, TRUE);
+ check_absolute_expr (ip, imm_expr, true);
if ((unsigned long) imm_expr->X_add_number > 0xfff)
as_bad (_("improper CSR address (%lu)"),
(unsigned long) imm_expr->X_add_number);
}
s = argsStart;
error = _("illegal operands");
- insn_with_csr = FALSE;
+ insn_with_csr = false;
}
out:
before assembling. */
if (!start_assemble)
{
- start_assemble = TRUE;
+ start_assemble = true;
riscv_set_abi_by_arch ();
if (!riscv_set_default_priv_spec (NULL))
break;
case OPTION_NO_PIC:
- riscv_opts.pic = FALSE;
+ riscv_opts.pic = false;
break;
case OPTION_PIC:
- riscv_opts.pic = TRUE;
+ riscv_opts.pic = true;
break;
case OPTION_MABI:
if (strcmp (arg, "ilp32") == 0)
- riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
+ riscv_set_abi (32, FLOAT_ABI_SOFT, false);
else if (strcmp (arg, "ilp32e") == 0)
- riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
+ riscv_set_abi (32, FLOAT_ABI_SOFT, true);
else if (strcmp (arg, "ilp32f") == 0)
- riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
+ riscv_set_abi (32, FLOAT_ABI_SINGLE, false);
else if (strcmp (arg, "ilp32d") == 0)
- riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
+ riscv_set_abi (32, FLOAT_ABI_DOUBLE, false);
else if (strcmp (arg, "ilp32q") == 0)
- riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
+ riscv_set_abi (32, FLOAT_ABI_QUAD, false);
else if (strcmp (arg, "lp64") == 0)
- riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
+ riscv_set_abi (64, FLOAT_ABI_SOFT, false);
else if (strcmp (arg, "lp64f") == 0)
- riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
+ riscv_set_abi (64, FLOAT_ABI_SINGLE, false);
else if (strcmp (arg, "lp64d") == 0)
- riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
+ riscv_set_abi (64, FLOAT_ABI_DOUBLE, false);
else if (strcmp (arg, "lp64q") == 0)
- riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
+ riscv_set_abi (64, FLOAT_ABI_QUAD, false);
else
return 0;
- explicit_mabi = TRUE;
+ explicit_mabi = true;
break;
case OPTION_RELAX:
- riscv_opts.relax = TRUE;
+ riscv_opts.relax = true;
break;
case OPTION_NO_RELAX:
- riscv_opts.relax = FALSE;
+ riscv_opts.relax = false;
break;
case OPTION_ARCH_ATTR:
- riscv_opts.arch_attr = TRUE;
+ riscv_opts.arch_attr = true;
break;
case OPTION_NO_ARCH_ATTR:
- riscv_opts.arch_attr = FALSE;
+ riscv_opts.arch_attr = false;
break;
case OPTION_CSR_CHECK:
- riscv_opts.csr_check = TRUE;
+ riscv_opts.csr_check = true;
break;
case OPTION_NO_CSR_CHECK:
- riscv_opts.csr_check = FALSE;
+ riscv_opts.csr_check = false;
break;
case OPTION_MISA_SPEC:
riscv_set_arch (default_arch_with_ext);
/* Add the RVC extension, regardless of -march, to support .option rvc. */
- riscv_set_rvc (FALSE);
+ riscv_set_rvc (false);
if (riscv_subset_supports ("c"))
- riscv_set_rvc (TRUE);
+ riscv_set_rvc (true);
/* Enable RVE if specified by the -march option. */
- riscv_set_rve (FALSE);
+ riscv_set_rve (false);
if (riscv_subset_supports ("e"))
- riscv_set_rve (TRUE);
+ riscv_set_rve (true);
/* If the CIE to be produced has not been overridden on the command line,
then produce version 3 by default. This allows us to use the full
{
unsigned int subtype;
bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
- bfd_boolean relaxable = FALSE;
+ bool relaxable = false;
offsetT loc;
segT sub_segment;
bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
| bfd_getl32 (buf), buf);
if (fixP->fx_addsy == NULL)
- fixP->fx_done = TRUE;
- relaxable = TRUE;
+ fixP->fx_done = true;
+ relaxable = true;
break;
case BFD_RELOC_RISCV_GOT_HI20:
case BFD_RELOC_RISCV_TPREL_LO12_I:
case BFD_RELOC_RISCV_TPREL_LO12_S:
case BFD_RELOC_RISCV_TPREL_ADD:
- relaxable = TRUE;
+ relaxable = true;
/* Fall through. */
case BFD_RELOC_RISCV_TLS_GOT_HI20:
case BFD_RELOC_RISCV_CALL:
case BFD_RELOC_RISCV_CALL_PLT:
- relaxable = TRUE;
+ relaxable = true;
break;
case BFD_RELOC_RISCV_PCREL_HI20:
*input_line_pointer = '\0';
if (strcmp (name, "rvc") == 0)
- riscv_set_rvc (TRUE);
+ riscv_set_rvc (true);
else if (strcmp (name, "norvc") == 0)
- riscv_set_rvc (FALSE);
+ riscv_set_rvc (false);
else if (strcmp (name, "pic") == 0)
- riscv_opts.pic = TRUE;
+ riscv_opts.pic = true;
else if (strcmp (name, "nopic") == 0)
- riscv_opts.pic = FALSE;
+ riscv_opts.pic = false;
else if (strcmp (name, "relax") == 0)
- riscv_opts.relax = TRUE;
+ riscv_opts.relax = true;
else if (strcmp (name, "norelax") == 0)
- riscv_opts.relax = FALSE;
+ riscv_opts.relax = false;
else if (strcmp (name, "csr-check") == 0)
- riscv_opts.csr_check = TRUE;
+ riscv_opts.csr_check = true;
else if (strcmp (name, "no-csr-check") == 0)
- riscv_opts.csr_check = FALSE;
+ riscv_opts.csr_check = false;
else if (strcmp (name, "push") == 0)
{
struct riscv_option_stack *s;
p = frag_more (bytes);
md_number_to_chars (p, 0, bytes);
- fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
+ fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false,
(bytes == 8
? BFD_RELOC_RISCV_TLS_DTPREL64
: BFD_RELOC_RISCV_TLS_DTPREL32));
will later relax to the correct number of NOPs. We can't compute
the correct alignment now because of other linker relaxations. */
-bfd_boolean
+bool
riscv_frag_align_code (int n)
{
bfd_vma bytes = (bfd_vma) 1 << n;
/* If we are moving to a smaller alignment than the instruction size, then no
alignment is required. */
if (bytes <= insn_alignment)
- return TRUE;
+ return true;
/* When not relaxing, riscv_handle_align handles code alignment. */
if (!riscv_opts.relax)
- return FALSE;
+ return false;
nops = frag_more (worst_case_bytes);
riscv_make_nops (nops, worst_case_bytes);
fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
- &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
+ &ex, false, BFD_RELOC_RISCV_ALIGN);
- return TRUE;
+ return true;
}
/* Implement HANDLE_ALIGN. */
int
md_estimate_size_before_relax (fragS *fragp, asection *segtype)
{
- return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
+ return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false));
}
/* Translate internal representation of relocation info to BFD target
if (RELAX_BRANCH_P (fragp->fr_subtype))
{
offsetT old_var = fragp->fr_var;
- fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
+ fragp->fr_var = relaxed_branch_length (fragp, sec, true);
return fragp->fr_var - old_var;
}
reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
- 2, &exp, FALSE, reloc);
+ 2, &exp, false, reloc);
buf += 2;
goto done;
jump:
/* Jump to the target. */
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
- 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
+ 4, &exp, false, BFD_RELOC_RISCV_JMP);
bfd_putl32 (MATCH_JAL, buf);
buf += 4;
break;
reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
- 4, &exp, FALSE, reloc);
+ 4, &exp, false, reloc);
buf += 4;
break;
unsigned old_xlen;
obj_attribute *attr;
- explicit_attr = TRUE;
+ explicit_attr = true;
switch (tag)
{
case Tag_RISCV_arch:
#define md_undefined_symbol(name) (0)
#define md_operand(x)
-extern bfd_boolean riscv_frag_align_code (int);
+extern bool riscv_frag_align_code (int);
#define md_do_align(N, FILL, LEN, MAX, LABEL) \
if ((N) != 0 && !(FILL) && !need_pass_2 && subseg_text_p (now_seg)) \
{ \
const char FLT_CHARS[] = "dD";
\f
#ifndef TE_LINUX
-bfd_boolean rx_use_conventional_section_names = FALSE;
+bool rx_use_conventional_section_names = false;
static int elf_flags = E_FLAG_RX_ABI;
#else
-bfd_boolean rx_use_conventional_section_names = TRUE;
+bool rx_use_conventional_section_names = true;
static int elf_flags;
#endif
-static bfd_boolean rx_use_small_data_limit = FALSE;
-static bfd_boolean rx_pid_mode = FALSE;
+static bool rx_use_small_data_limit = false;
+static bool rx_pid_mode = false;
static int rx_num_int_regs = 0;
int rx_pid_register;
int rx_gp_register;
return 1;
case OPTION_CONVENTIONAL_SECTION_NAMES:
- rx_use_conventional_section_names = TRUE;
+ rx_use_conventional_section_names = true;
return 1;
case OPTION_RENESAS_SECTION_NAMES:
- rx_use_conventional_section_names = FALSE;
+ rx_use_conventional_section_names = false;
return 1;
case OPTION_SMALL_DATA_LIMIT:
- rx_use_small_data_limit = TRUE;
+ rx_use_small_data_limit = true;
return 1;
case OPTION_RELAX:
return 1;
case OPTION_PID:
- rx_pid_mode = TRUE;
+ rx_pid_mode = true;
elf_flags |= E_FLAG_RX_PID;
return 1;
/* Get the filename. Spaces are allowed, NUL characters are not. */
filename = input_line_pointer;
- last_char = find_end_of_line (filename, FALSE);
+ last_char = find_end_of_line (filename, false);
input_line_pointer = last_char;
while (last_char >= filename && (* last_char == ' ' || * last_char == '\n'))
else
type = SHT_NOBITS;
- obj_elf_change_section (name, type, attr, 0, NULL, FALSE, FALSE);
+ obj_elf_change_section (name, type, attr, 0, NULL, false, false);
}
else /* Try not to redefine a section, especially B_1. */
{
| ((flags & SEC_STRINGS) ? SHF_STRINGS : 0)
| ((flags & SEC_THREAD_LOCAL) ? SHF_TLS : 0);
- obj_elf_change_section (name, type, attr, 0, NULL, FALSE, FALSE);
+ obj_elf_change_section (name, type, attr, 0, NULL, false, false);
}
bfd_set_section_alignment (now_seg, align);
rather than at the start of a line. (eg .EQU or .DEFINE). If one
is found, process it and return TRUE otherwise return FALSE. */
-static bfd_boolean
+static bool
scan_for_infix_rx_pseudo_ops (char * str)
{
char * p;
char * dot = strchr (str, '.');
if (dot == NULL || dot == str)
- return FALSE;
+ return false;
/* A real pseudo-op must be preceded by whitespace. */
if (dot[-1] != ' ' && dot[-1] != '\t')
- return FALSE;
+ return false;
pseudo_op = dot + 1;
if (!ISALNUM (* pseudo_op))
- return FALSE;
+ return false;
for (p = pseudo_op + 1; ISALNUM (* p); p++)
;
else if (strncasecmp ("BTEQU", pseudo_op, p - pseudo_op) == 0)
as_warn (_("The .BTEQU pseudo-op is not implemented."));
else
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
void
tc_gen_reloc (asection * sec ATTRIBUTE_UNUSED, fixS * fixp)
{
static arelent * reloc[5];
- bfd_boolean is_opcode = FALSE;
+ bool is_opcode = false;
if (fixp->fx_r_type == BFD_RELOC_NONE)
{
&& fixp->fx_subsy)
{
fixp->fx_r_type = BFD_RELOC_RX_DIFF;
- is_opcode = TRUE;
+ is_opcode = true;
}
else if (sec)
is_opcode = sec->flags & SEC_CODE;
#define elf_tc_final_processing rx_elf_final_processing
extern void rx_elf_final_processing (void);
-extern bfd_boolean rx_use_conventional_section_names;
+extern bool rx_use_conventional_section_names;
#define TEXT_SECTION_NAME (rx_use_conventional_section_names ? ".text" : "P")
#define DATA_SECTION_NAME (rx_use_conventional_section_names ? ".data" : "D_1")
#define BSS_SECTION_NAME (rx_use_conventional_section_names ? ".bss" : "B_1")
#include "subsegs.h"
#include "dwarf2dbg.h"
#include "opcode/s12z.h"
-#include <stdint.h>
#include <limits.h>
-#include <stdbool.h>
const char comment_chars[] = ";";
register_prefix = xstrdup (arg);
break;
case OPTION_DOLLAR_HEX:
- literal_prefix_dollar_hex = TRUE;
+ literal_prefix_dollar_hex = true;
break;
default:
return 0;
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
valueT
s12z_init_after_args (void)
{
if (flag_traditional_format)
- literal_prefix_dollar_hex = TRUE;
+ literal_prefix_dollar_hex = true;
}
\f
/* Builtin help. */
\f
-static bfd_boolean lex_reg_name (uint16_t which, int *reg);
+static bool lex_reg_name (uint16_t which, int *reg);
-static bfd_boolean
+static bool
lex_constant (long *v)
{
char *end = NULL;
return false;
}
-static bfd_boolean
+static bool
lex_match (char x)
{
char *p = input_line_pointer;
}
-static bfd_boolean
+static bool
lex_expression (expressionS *exp)
{
char *ilp = input_line_pointer;
If EXP_O is non-null, then a symbolic expression is permitted,
in which case, EXP_O will be populated with the parsed expression.
*/
-static bfd_boolean
+static bool
lex_imm (long *v, expressionS *exp_o)
{
char *ilp = input_line_pointer;
}
/* Short mmediate operand */
-static bfd_boolean
+static bool
lex_imm_e4 (long *val)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
lex_match_string (const char *s)
{
char *p = input_line_pointer;
On success, REG will be filled with the index of the register which
was successfully scanned.
*/
-static bfd_boolean
+static bool
lex_reg_name (uint16_t which, int *reg)
{
char *p = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
lex_force_match (char x)
{
char *p = input_line_pointer;
return true;
}
-static bfd_boolean
+static bool
lex_opr (uint8_t *buffer, int *n_bytes, expressionS *exp,
bool immediate_ok)
{
return false;
}
-static bfd_boolean
+static bool
lex_offset (long *val)
{
char *end = NULL;
struct instruction;
-typedef bfd_boolean (*parse_operand_func) (const struct instruction *);
+typedef bool (*parse_operand_func) (const struct instruction *);
struct instruction
{
uint8_t alt_opc;
};
-static bfd_boolean
+static bool
no_operands (const struct instruction *insn)
{
if (*input_line_pointer != '\0')
f - frag_now->fr_literal,
size,
exp,
- FALSE,
+ false,
reloc);
/* Some third party tools seem to use the lower bits
of this addend for flags. They don't get added
return f + 3;
}
-static bfd_boolean
+static bool
opr (const struct instruction *insn)
{
uint8_t buffer[4];
/* Parse a 15 bit offset, as an expression.
LONG_DISPLACEMENT will be set to true if the offset is wider than 7 bits.
*/
-static bfd_boolean
+static bool
lex_15_bit_offset (bool *long_displacement, expressionS *exp)
{
char *ilp = input_line_pointer;
f - frag_now->fr_literal,
2,
exp,
- TRUE,
+ true,
BFD_RELOC_16_PCREL);
fix->fx_addnumber = where - 2;
}
}
}
-static bfd_boolean
+static bool
rel (const struct instruction *insn)
{
bool long_displacement;
return true;
}
-static bfd_boolean
+static bool
reg_inh (const struct instruction *insn)
{
int reg;
/* Special case for CLR X and CLR Y */
-static bfd_boolean
+static bool
clr_xy (const struct instruction *insn ATTRIBUTE_UNUSED)
{
int reg;
return size;
}
-static bfd_boolean
+static bool
mul_reg_reg_reg (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
mul_reg_reg_imm (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
mul_reg_reg_opr (const struct instruction *insn)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
mul_reg_opr_opr (const struct instruction *insn)
{
char *ilp = input_line_pointer;
0x00
};
-static bfd_boolean
+static bool
lex_reg_list (uint16_t grp, uint16_t *reg_bits)
{
if (lex_match (','))
return true;
}
-static bfd_boolean
+static bool
psh_pull (const struct instruction *insn)
{
uint8_t pb =
}
-static bfd_boolean
+static bool
tfr (const struct instruction *insn)
{
int reg1;
return false;
}
-static bfd_boolean
+static bool
imm8 (const struct instruction *insn)
{
long imm;
return true;
}
-static bfd_boolean
+static bool
reg_imm (const struct instruction *insn, int allowed_reg)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
regd_imm (const struct instruction *insn)
{
return reg_imm (insn, REG_BIT_Dn);
}
-static bfd_boolean
+static bool
regdxy_imm (const struct instruction *insn)
{
return reg_imm (insn, REG_BIT_Dn | REG_BIT_XY);
}
-static bfd_boolean
+static bool
regs_imm (const struct instruction *insn)
{
return reg_imm (insn, 0x1U << REG_S);
}
-static bfd_boolean
+static bool
trap_imm (const struct instruction *insn ATTRIBUTE_UNUSED)
{
long imm = -1;
/* Special one byte instruction CMP X, Y */
-static bfd_boolean
+static bool
regx_regy (const struct instruction *insn)
{
int reg;
}
/* Special one byte instruction SUB D6, X, Y */
-static bfd_boolean
+static bool
regd6_regx_regy (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
/* Special one byte instruction SUB D6, Y, X */
-static bfd_boolean
+static bool
regd6_regy_regx (const struct instruction *insn)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
reg_opr (const struct instruction *insn, int allowed_regs,
bool immediate_ok)
{
}
-static bfd_boolean
+static bool
regdxy_opr_dest (const struct instruction *insn)
{
return reg_opr (insn, REG_BIT_Dn | REG_BIT_XY, false);
}
-static bfd_boolean
+static bool
regdxy_opr_src (const struct instruction *insn)
{
return reg_opr (insn, REG_BIT_Dn | REG_BIT_XY, true);
}
-static bfd_boolean
+static bool
regd_opr (const struct instruction *insn)
{
return reg_opr (insn, REG_BIT_Dn, true);
/* OP0: S; OP1: destination OPR */
-static bfd_boolean
+static bool
regs_opr_dest (const struct instruction *insn)
{
return reg_opr (insn, 0x1U << REG_S, false);
}
/* OP0: S; OP1: source OPR */
-static bfd_boolean
+static bool
regs_opr_src (const struct instruction *insn)
{
return reg_opr (insn, 0x1U << REG_S, true);
}
-static bfd_boolean
+static bool
imm_opr (const struct instruction *insn)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
opr_opr (const struct instruction *insn)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
reg67sxy_opr (const struct instruction *insn)
{
int reg;
return true;
}
-static bfd_boolean
+static bool
rotate (const struct instruction *insn, short dir)
{
uint8_t buffer[4];
return false;
}
-static bfd_boolean
+static bool
rol (const struct instruction *insn)
{
return rotate (insn, 1);
}
-static bfd_boolean
+static bool
ror (const struct instruction *insn)
{
return rotate (insn, 0);
left = 1; right = 0;
logical = 0; arithmetic = 1;
*/
-static bfd_boolean
+static bool
lex_shift_reg_imm1 (const struct instruction *insn, short type, short dir)
{
/*
/* Shift instruction with a register operand.
left = 1; right = 0;
logical = 0; arithmetic = 1; */
-static bfd_boolean
+static bool
lex_shift_reg (const struct instruction *insn, short type, short dir)
{
int Dd, Ds, Dn;
}
/* Shift instruction with a OPR operand */
-static bfd_boolean
+static bool
shift_two_operand (const struct instruction *insn)
{
uint8_t sb = 0x34;
}
/* Shift instruction with a OPR operand */
-static bfd_boolean
+static bool
shift_opr_imm (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
/* Shift instruction with a register operand */
-static bfd_boolean
+static bool
shift_reg (const struct instruction *insn)
{
short dir = -1;
return lex_shift_reg (insn, type, dir);
}
-static bfd_boolean
+static bool
bm_regd_imm (const struct instruction *insn)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
bm_opr_reg (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
bm_opr_imm (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
bm_regd_reg (const struct instruction *insn)
{
char *ilp = input_line_pointer;
\f
-static bfd_boolean
+static bool
bf_reg_opr_imm (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
bf_opr_reg_imm (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
-static bfd_boolean
+static bool
bf_reg_reg_imm (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
bf_reg_reg_reg (const struct instruction *insn ATTRIBUTE_UNUSED, short ie)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
bf_opr_reg_reg (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
bf_reg_opr_reg (const struct instruction *insn, short ie)
{
char *ilp = input_line_pointer;
-static bfd_boolean
+static bool
bfe_reg_reg_reg (const struct instruction *insn)
{
return bf_reg_reg_reg (insn, 0);
}
-static bfd_boolean
+static bool
bfi_reg_reg_reg (const struct instruction *insn)
{
return bf_reg_reg_reg (insn, 1);
}
-static bfd_boolean
+static bool
bfe_reg_reg_imm (const struct instruction *insn)
{
return bf_reg_reg_imm (insn, 0);
}
-static bfd_boolean
+static bool
bfi_reg_reg_imm (const struct instruction *insn)
{
return bf_reg_reg_imm (insn, 1);
}
-static bfd_boolean
+static bool
bfe_reg_opr_reg (const struct instruction *insn)
{
return bf_reg_opr_reg (insn, 0);
}
-static bfd_boolean
+static bool
bfi_reg_opr_reg (const struct instruction *insn)
{
return bf_reg_opr_reg (insn, 1);
}
-static bfd_boolean
+static bool
bfe_opr_reg_reg (const struct instruction *insn)
{
return bf_opr_reg_reg (insn, 0);
}
-static bfd_boolean
+static bool
bfi_opr_reg_reg (const struct instruction *insn)
{
return bf_opr_reg_reg (insn, 1);
}
-static bfd_boolean
+static bool
bfe_reg_opr_imm (const struct instruction *insn)
{
return bf_reg_opr_imm (insn, 0);
}
-static bfd_boolean
+static bool
bfi_reg_opr_imm (const struct instruction *insn)
{
return bf_reg_opr_imm (insn, 1);
}
-static bfd_boolean
+static bool
bfe_opr_reg_imm (const struct instruction *insn)
{
return bf_opr_reg_imm (insn, 0);
}
-static bfd_boolean
+static bool
bfi_opr_reg_imm (const struct instruction *insn)
{
return bf_opr_reg_imm (insn, 1);
\f
-static bfd_boolean
+static bool
tb_reg_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
tb_opr_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
\f
-static bfd_boolean
+static bool
test_br_reg_reg_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
return false;
}
-static bfd_boolean
+static bool
test_br_opr_reg_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
test_br_opr_imm_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
}
-static bfd_boolean
+static bool
test_br_reg_imm_rel (const struct instruction *insn)
{
char *ilp = input_line_pointer;
we need to make sure that the linker relaxation is done
correctly, so in some cases we force the original symbol to be
used. */
-bfd_boolean
+bool
tc_s12z_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
{
return true;
extern int tc_s12z_force_relocation (struct fix *);
#define tc_fix_adjustable(X) tc_s12z_fix_adjustable(X)
-extern bfd_boolean tc_s12z_fix_adjustable (struct fix *);
+extern bool tc_s12z_fix_adjustable (struct fix *);
#define md_operand(x)
/* Set to TRUE if the highgprs flag in the ELF header needs to be set
for the output file. */
-static bfd_boolean set_highgprs_p = FALSE;
+static bool set_highgprs_p = false;
/* Whether to use user friendly register names. Default is TRUE. */
#ifndef TARGET_REG_NAMES_P
-#define TARGET_REG_NAMES_P TRUE
+#define TARGET_REG_NAMES_P true
#endif
-static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
+static bool reg_names_p = TARGET_REG_NAMES_P;
/* Set to TRUE if we want to warn about zero base/index registers. */
-static bfd_boolean warn_areg_zero = FALSE;
+static bool warn_areg_zero = false;
/* Generic assembler global variables which must be defined by all
targets. */
* original state.
*/
-static bfd_boolean
+static bool
register_name (expressionS *expressionP)
{
int reg_number;
if (name[0] == '%' && ISALPHA (name[1]))
name = ++input_line_pointer;
else
- return FALSE;
+ return false;
c = get_symbol_name (&name);
reg_number = reg_name_search (name);
/* Make the rest nice. */
expressionP->X_add_symbol = NULL;
expressionP->X_op_symbol = NULL;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
input_line_pointer = start;
- return FALSE;
+ return false;
}
/* Local variables. */
In case of an error, S390_OPCODE_MAXCPU is returned. */
static unsigned int
-s390_parse_cpu (const char * arg,
- unsigned int * ret_flags,
- bfd_boolean allow_extensions)
+s390_parse_cpu (const char *arg,
+ unsigned int *ret_flags,
+ bool allow_extensions)
{
static struct
{
};
static struct
{
- const char * name;
+ const char *name;
unsigned int mask;
- bfd_boolean on;
+ bool on;
} cpu_flags[] =
{
- { "htm", S390_INSTR_FLAG_HTM, TRUE },
- { "nohtm", S390_INSTR_FLAG_HTM, FALSE },
- { "vx", S390_INSTR_FLAG_VX, TRUE },
- { "novx", S390_INSTR_FLAG_VX, FALSE }
+ { "htm", S390_INSTR_FLAG_HTM, true },
+ { "nohtm", S390_INSTR_FLAG_HTM, false },
+ { "vx", S390_INSTR_FLAG_VX, true },
+ { "novx", S390_INSTR_FLAG_VX, false }
};
unsigned int icpu;
char *ilp_bak;
break;
case 'm':
if (arg != NULL && strcmp (arg, "regnames") == 0)
- reg_names_p = TRUE;
+ reg_names_p = true;
else if (arg != NULL && strcmp (arg, "no-regnames") == 0)
- reg_names_p = FALSE;
+ reg_names_p = false;
else if (arg != NULL && strcmp (arg, "warn-areg-zero") == 0)
- warn_areg_zero = TRUE;
+ warn_areg_zero = true;
else if (arg != NULL && strcmp (arg, "31") == 0)
s390_arch_size = 32;
else if (arg != NULL && strcmp (arg, "zarch") == 0)
{
if (s390_arch_size == 32)
- set_highgprs_p = TRUE;
+ set_highgprs_p = true;
current_mode_mask = 1 << S390_OPCODE_ZARCH;
}
else if (arg != NULL && strncmp (arg, "arch=", 5) == 0)
{
- current_cpu = s390_parse_cpu (arg + 5, ¤t_flags, FALSE);
+ current_cpu = s390_parse_cpu (arg + 5, ¤t_flags, false);
if (current_cpu == S390_OPCODE_MAXCPU)
{
as_bad (_("invalid switch -m%s"), arg);
{
const struct s390_opcode *op;
const struct s390_opcode *op_end;
- bfd_boolean dup_insn = FALSE;
+ bool dup_insn = false;
if (s390_opcode_hash != NULL)
htab_delete (s390_opcode_hash);
&& str_hash_insert (s390_opcode_hash, op->name, op, 0) != NULL)
{
as_bad (_("duplicate %s"), op->name);
- dup_insn = TRUE;
+ dup_insn = true;
}
while (op < op_end - 1 && strcmp (op->name, op[1].name) == 0)
/* To make fixup_segment do the pc relative conversion the
pcrel parameter on the fix_new_exp call needs to be FALSE. */
fix_new_exp (frag_now, where - frag_now->fr_literal,
- size, &exp, FALSE, reloc);
+ size, &exp, false, reloc);
}
else
as_bad (_("relocation not applicable"));
/* Return true if all remaining operands in the opcode with
OPCODE_FLAGS can be skipped. */
-static bfd_boolean
+static bool
skip_optargs_p (unsigned int opcode_flags, const unsigned char *opindex_ptr)
{
if ((opcode_flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2))
&& opindex_ptr[0] != '\0'
&& opindex_ptr[1] == '\0')
- return TRUE;
+ return true;
if ((opcode_flags & S390_INSTR_FLAG_OPTPARM2)
&& opindex_ptr[0] != '\0'
&& opindex_ptr[1] != '\0'
&& opindex_ptr[2] == '\0')
- return TRUE;
- return FALSE;
+ return true;
+ return false;
}
/* We need to keep a list of fixups. We can't simply generate them as
}
}
else
- new_cpu = s390_parse_cpu (cpu_string, &new_flags, TRUE);
+ new_cpu = s390_parse_cpu (cpu_string, &new_flags, true);
if (new_cpu == S390_OPCODE_MAXCPU)
as_bad (_("invalid machine `%s'"), cpu_string);
else if (strcmp (mode_string, "zarch") == 0)
{
if (s390_arch_size == 32)
- set_highgprs_p = TRUE;
+ set_highgprs_p = true;
current_mode_mask = 1 << S390_OPCODE_ZARCH;
}
else if (strcmp (mode_string, "zarch_nohighgprs") == 0)
const char *
md_atof (int type, char *litp, int *sizep)
{
- return ieee_md_atof (type, litp, sizep, TRUE);
+ return ieee_md_atof (type, litp, sizep, true);
}
/* Align a section (I don't know why this is machine dependent). */
static void s3_frag_check (fragS * fragp ATTRIBUTE_UNUSED);
static void s3_validate_fix (fixS *fixP);
static int s3_force_relocation (struct fix *fixp);
-static bfd_boolean s3_fix_adjustable (fixS * fixP);
+static bool s3_fix_adjustable (fixS * fixP);
static void s3_elf_final_processing (void);
static int s3_estimate_size_before_relax (fragS * fragp, asection * sec ATTRIBUTE_UNUSED);
static int s3_relax_frag (asection * sec ATTRIBUTE_UNUSED, fragS * fragp, long stretch ATTRIBUTE_UNUSED);
s3_gen_insn_frag (struct s3_score_it *part_1, struct s3_score_it *part_2)
{
char *p;
- bfd_boolean pce_p = FALSE;
+ bool pce_p = false;
int relaxable_p = s3_g_opt;
int relax_size = 0;
struct s3_score_it *inst1 = part_1;
}
static void
-s3_parse_16_32_inst (char *insnstr, bfd_boolean gen_frag_p)
+s3_parse_16_32_inst (char *insnstr, bool gen_frag_p)
{
char c;
char *p;
}
static void
-s3_parse_48_inst (char *insnstr, bfd_boolean gen_frag_p)
+s3_parse_48_inst (char *insnstr, bool gen_frag_p)
{
char c;
char *p;
}
static int
-s3_append_insn (char *str, bfd_boolean gen_frag_p)
+s3_append_insn (char *str, bool gen_frag_p)
{
int retval = s3_SUCCESS;
For an external symbol: lw rD, <sym>($gp)
(BFD_RELOC_SCORE_GOT15 or BFD_RELOC_SCORE_CALL15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
if (reg_rd == s3_PIC_CALL_REG)
s3_inst.reloc.type = BFD_RELOC_SCORE_GOT15;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
sprintf (tmp, "addi_s_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[1], &s3_inst, sizeof (struct s3_score_it));
{
/* Insn 1: lw rD, <sym>($gp) (BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
- if (s3_append_insn (tmp, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, true) == (int) s3_FAIL)
return;
/* Insn 2 */
/* Fix part
For an external symbol: addi rD, <constant> */
sprintf (tmp, "addi r%d, %d", reg_rd, (int)add_number);
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&fix_insts[0], &s3_inst, sizeof (struct s3_score_it));
For a local symbol: addi rD, <sym>+<constant> (BFD_RELOC_GOT_LO16) */
sprintf (tmp, "addi_s_pic r%d, %s + %d", reg_rd,
S_GET_NAME (add_symbol), (int) add_number);
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
/* Insn 1: lw rD, <sym>($gp) (BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
- if (s3_append_insn (tmp, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, true) == (int) s3_FAIL)
return;
/* Insn 2 */
/* Fix part
For an external symbol: ldis r1, HI%<constant> */
sprintf (tmp, "ldis r1, %d", hi);
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&fix_insts[0], &s3_inst, sizeof (struct s3_score_it));
hi += 1;
}
sprintf (tmp, "ldis_pic r1, %d", hi);
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
/* Fix part
For an external symbol: ori r1, LO%<constant> */
sprintf (tmp, "ori r1, %d", lo);
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&fix_insts[0], &s3_inst, sizeof (struct s3_score_it));
/* Var part
For a local symbol: addi r1, <sym>+LO%<constant> (BFD_RELOC_GOT_LO16) */
sprintf (tmp, "addi_u_pic r1, %s + %d", S_GET_NAME (add_symbol), lo);
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
/* Insn 4: add rD, rD, r1 */
sprintf (tmp, "add r%d, r%d, r1", reg_rd, reg_rd);
- if (s3_append_insn (tmp, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, true) == (int) s3_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
if ((s3_score_pic == s3_NO_PIC) || (!s3_inst.reloc.exp.X_add_symbol))
{
sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
}
else
{
sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
else
{
sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
}
/* Output mul/mulu or div/divu or rem/remu. */
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
return;
/* Output mfcel or mfceh. */
- if (s3_append_insn (append_str1, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str1, true) == (int) s3_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
backupstr = tmp;
sprintf (append_str, "li r1 %s", backupstr);
- s3_append_insn (append_str, TRUE);
+ s3_append_insn (append_str, true);
memcpy (&s3_inst, &inst_backup, sizeof (struct s3_score_it));
sprintf (append_str, " r%d, [r1,0]", reg_rd);
if (s3_score_pic == s3_NO_PIC)
{
sprintf (append_str, "cmp! r%d, r%d", reg_a, reg_b);
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
goto out;
if ((inst_main.instruction & 0x3e00007e) == 0x0000004c)
memcpy (append_str, "beq ", 4);
else
memcpy (append_str, "bne ", 4);
memmove (append_str + 4, keep_data, strlen (keep_data) + 1);
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
goto out;
}
else
if (s3_score_pic == s3_NO_PIC)
{
sprintf (append_str, "cmp! r%d, r%d", reg_a, reg_b);
- if (s3_append_insn (append_str, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, false) == (int) s3_FAIL)
goto out;
memcpy (&inst_expand[0], &s3_inst, sizeof (struct s3_score_it));
else
memcpy (append_str, "bne ", 4);
memmove (append_str + 4, keep_data, strlen (keep_data) + 1);
- if (s3_append_insn (append_str, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, false) == (int) s3_FAIL)
goto out;
memcpy (&inst_expand[1], &s3_inst, sizeof (struct s3_score_it));
}
if (s3_score_pic == s3_NO_PIC)
{
sprintf (append_str, "cmpi! r%d, 0", reg_a);
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
goto out;
if ((inst_main.instruction & 0x3e00007e) == 0x0000004c)
memcpy (append_str, "beq ", 4);
else
memcpy (append_str, "bne ", 4);
memmove (append_str + 4, keep_data, strlen (keep_data) + 1);
- if (s3_append_insn (append_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, true) == (int) s3_FAIL)
goto out;
}
else
if (s3_score_pic == s3_NO_PIC)
{
sprintf (append_str, "cmpi! r%d, 0", reg_a);
- if (s3_append_insn (append_str, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, false) == (int) s3_FAIL)
goto out;
memcpy (&inst_expand[0], &s3_inst, sizeof (struct s3_score_it));
if ((inst_main.instruction & 0x3e00007e) == 0x0000004c)
else
memcpy (append_str, "bne ", 4);
memmove (append_str + 4, keep_data, strlen (keep_data) + 1);
- if (s3_append_insn (append_str, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str, false) == (int) s3_FAIL)
goto out;
memcpy (&inst_expand[1], &s3_inst, sizeof (struct s3_score_it));
}
For an external symbol: lw rD, <sym>($gp)
(BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r1, %s", S_GET_NAME (add_symbol));
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&fix_insts[0], &s3_inst, sizeof (struct s3_score_it));
s3_inst.reloc.type = BFD_RELOC_SCORE_GOT15;
memcpy (&var_insts[0], &s3_inst, sizeof (struct s3_score_it));
sprintf (tmp, "addi_s_pic r1, %s", S_GET_NAME (add_symbol));
- if (s3_append_insn (tmp, FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, false) == (int) s3_FAIL)
return;
memcpy (&var_insts[1], &s3_inst, sizeof (struct s3_score_it));
/* Insn 2 or Insn 3: lw/st rD, [r1, constant] */
sprintf (tmp, "%s r%d, [r1, %d]", insn_name, reg_rd, add_number);
- if (s3_append_insn (tmp, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (tmp, true) == (int) s3_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
ld/st rd, [r1, 0] */
for (i = 0; i < 3; i++)
{
- if (s3_append_insn (append_str[i], FALSE) == (int) s3_FAIL)
+ if (s3_append_insn (append_str[i], false) == (int) s3_FAIL)
return;
memcpy (&inst_expand[i], &s3_inst, sizeof (struct s3_score_it));
}
/* Return true if the given symbol should be considered local for s3_PIC. */
-static bfd_boolean
+static bool
s3_pic_need_relax (symbolS *sym, asection *segtype)
{
asection *symsec;
- bfd_boolean linkonce;
+ bool linkonce;
/* Handle the case of a symbol equated to another symbol. */
while (symbol_equated_reloc_p (sym))
symsec = S_GET_SEGMENT (sym);
/* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
- linkonce = FALSE;
+ linkonce = false;
if (symsec != segtype && ! S_IS_LOCAL (sym))
{
if ((bfd_section_flags (symsec) & SEC_LINK_ONCE) != 0)
- linkonce = TRUE;
+ linkonce = true;
/* The GNU toolchain uses an extension for ELF: a section
beginning with the magic string .gnu.linkonce is a linkonce
section. */
if (strncmp (segment_name (symsec), ".gnu.linkonce",
sizeof ".gnu.linkonce" - 1) == 0)
- linkonce = TRUE;
+ linkonce = true;
}
/* This must duplicate the test in adjust_reloc_syms. */
p += 2;
sprintf (second, "%s", p);
- s3_parse_16_32_inst (first, FALSE);
+ s3_parse_16_32_inst (first, false);
if (s3_inst.error)
return;
memcpy (&pec_part_1, &s3_inst, sizeof (s3_inst));
- s3_parse_16_32_inst (second, FALSE);
+ s3_parse_16_32_inst (second, false);
if (s3_inst.error)
return;
demand_empty_rest_of_line ();
sprintf (insn_str, "ld_i32hi r%d, %s", s3_GP, GP_DISP_LABEL);
- if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
sprintf (insn_str, "ld_i32lo r%d, %s", s3_GP, GP_DISP_LABEL);
- if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
sprintf (insn_str, "add r%d, r%d, r%d", s3_GP, s3_GP, reg);
- if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
}
if (cprestore_offset <= 0x3fff)
{
sprintf (insn_str, "sw r%d, [r%d, %d]", s3_GP, reg, cprestore_offset);
- if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
}
else
s3_nor1 = 0;
sprintf (insn_str, "li r1, %d", cprestore_offset);
- if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
sprintf (insn_str, "add r1, r1, r%d", reg);
- if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
sprintf (insn_str, "sw r%d, [r1]", s3_GP);
- if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
s3_nor1 = r1_bak;
}
p = frag_more (4);
s3_md_number_to_chars (p, (valueT) 0, 4);
- fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, BFD_RELOC_GPREL32);
+ fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, BFD_RELOC_GPREL32);
demand_empty_rest_of_line ();
}
/* Add $gp to the register named as an argument. */
sprintf (insn_str, "add r%d, r%d, r%d", reg, reg, s3_GP);
- if (s3_append_insn (insn_str, TRUE) == (int) s3_FAIL)
+ if (s3_append_insn (insn_str, true) == (int) s3_FAIL)
return;
}
if (s3_INSN_IS_PCE_P (str))
s3_parse_pce_inst (str);
else if (s3_INSN_IS_48_P (str))
- s3_parse_48_inst (str, TRUE);
+ s3_parse_48_inst (str, true);
else
- s3_parse_16_32_inst (str, TRUE);
+ s3_parse_16_32_inst (str, true);
if (s3_inst.error)
as_bad (_("%s -- `%s'"), s3_inst.error, s3_inst.str);
return retval;
}
-static bfd_boolean
+static bool
s3_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
/* Implementation of md_frag_check.
Called after md_convert_frag(). */
-bfd_boolean
+bool
score_fix_adjustable (fixS * fixP)
{
if (score3)
extern int score_force_relocation (struct fix *);
#define tc_fix_adjustable(fixp) score_fix_adjustable (fixp)
-extern bfd_boolean score_fix_adjustable (struct fix *);
+extern bool score_fix_adjustable (struct fix *);
#define elf_tc_final_processing score_elf_final_processing
extern void score_elf_final_processing (void);
s7_gen_insn_frag (struct s7_score_it *part_1, struct s7_score_it *part_2)
{
char *p;
- bfd_boolean pce_p = FALSE;
+ bool pce_p = false;
int relaxable_p = s7_g_opt;
int relax_size = 0;
struct s7_score_it *inst1 = part_1;
}
static void
-s7_parse_16_32_inst (char *insnstr, bfd_boolean gen_frag_p)
+s7_parse_16_32_inst (char *insnstr, bool gen_frag_p)
{
char c;
char *p;
}
static int
-s7_append_insn (char *str, bfd_boolean gen_frag_p)
+s7_append_insn (char *str, bool gen_frag_p)
{
int retval = s7_SUCCESS;
char append_str[s7_MAX_LITERAL_POOL_SIZE];
sprintf (append_str, "mlfh! %s", backupstr);
- if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
s7_inst.bwarn = -1;
char append_str[s7_MAX_LITERAL_POOL_SIZE];
sprintf (append_str, "mhfl! %s", backupstr);
- if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
For an external symbol: lw rD, <sym>($gp)
(BFD_RELOC_SCORE_GOT15 or BFD_RELOC_SCORE_CALL15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
if (reg_rd == s7_PIC_CALL_REG)
s7_inst.reloc.type = BFD_RELOC_SCORE_GOT15;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
sprintf (tmp, "addi_s_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[1], &s7_inst, sizeof (struct s7_score_it));
{
/* Insn 1: lw rD, <sym>($gp) (BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
- if (s7_append_insn (tmp, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, true) == (int) s7_FAIL)
return;
/* Insn 2 */
/* Fix part
For an external symbol: addi rD, <constant> */
sprintf (tmp, "addi r%d, %d", reg_rd, (int) add_number);
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&fix_insts[0], &s7_inst, sizeof (struct s7_score_it));
For a local symbol: addi rD, <sym>+<constant> (BFD_RELOC_GOT_LO16) */
sprintf (tmp, "addi_s_pic r%d, %s + %d", reg_rd,
S_GET_NAME (add_symbol), (int) add_number);
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
/* Insn 1: lw rD, <sym>($gp) (BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r%d, %s", reg_rd, S_GET_NAME (add_symbol));
- if (s7_append_insn (tmp, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, true) == (int) s7_FAIL)
return;
/* Insn 2 */
/* Fix part
For an external symbol: ldis r1, HI%<constant> */
sprintf (tmp, "ldis r1, %d", hi);
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&fix_insts[0], &s7_inst, sizeof (struct s7_score_it));
hi += 1;
}
sprintf (tmp, "ldis_pic r1, %d", hi);
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
/* Fix part
For an external symbol: ori r1, LO%<constant> */
sprintf (tmp, "ori r1, %d", lo);
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&fix_insts[0], &s7_inst, sizeof (struct s7_score_it));
/* Var part
For a local symbol: addi r1, <sym>+LO%<constant> (BFD_RELOC_GOT_LO16) */
sprintf (tmp, "addi_u_pic r1, %s + %d", S_GET_NAME (add_symbol), lo);
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
/* Insn 4: add rD, rD, r1 */
sprintf (tmp, "add r%d, r%d, r1", reg_rd, reg_rd);
- if (s7_append_insn (tmp, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
if ((s7_score_pic == s7_NO_PIC) || (!s7_inst.reloc.exp.X_add_symbol))
{
sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
- if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
- if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
}
else
{
sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
- if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
else
{
sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
- if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
}
/* Output mul/mulu or div/divu or rem/remu. */
- if (s7_append_insn (append_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str, true) == (int) s7_FAIL)
return;
/* Output mfcel or mfceh. */
- if (s7_append_insn (append_str1, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str1, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
backupstr = tmp;
sprintf (append_str, "li r1 %s", backupstr);
- s7_append_insn (append_str, TRUE);
+ s7_append_insn (append_str, true);
memcpy (&s7_inst, &inst_backup, sizeof (struct s7_score_it));
sprintf (append_str, " r%d, [r1,0]", reg_rd);
For an external symbol: lw rD, <sym>($gp)
(BFD_RELOC_SCORE_GOT15) */
sprintf (tmp, "lw_pic r1, %s", S_GET_NAME (add_symbol));
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&fix_insts[0], &s7_inst, sizeof (struct s7_score_it));
s7_inst.reloc.type = BFD_RELOC_SCORE_GOT15;
memcpy (&var_insts[0], &s7_inst, sizeof (struct s7_score_it));
sprintf (tmp, "addi_s_pic r1, %s", S_GET_NAME (add_symbol));
- if (s7_append_insn (tmp, FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, false) == (int) s7_FAIL)
return;
memcpy (&var_insts[1], &s7_inst, sizeof (struct s7_score_it));
/* Insn 2 or Insn 3: lw/st rD, [r1, constant] */
sprintf (tmp, "%s r%d, [r1, %d]", insn_name, reg_rd, add_number);
- if (s7_append_insn (tmp, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (tmp, true) == (int) s7_FAIL)
return;
/* Set bwarn as -1, so macro instruction itself will not be generated frag. */
ld/st rd, [r1, 0] */
for (i = 0; i < 3; i++)
{
- if (s7_append_insn (append_str[i], FALSE) == (int) s7_FAIL)
+ if (s7_append_insn (append_str[i], false) == (int) s7_FAIL)
return;
memcpy (&inst_expand[i], &s7_inst, sizeof (struct s7_score_it));
/* Return true if the given symbol should be considered local for s7_PIC. */
-static bfd_boolean
+static bool
s7_pic_need_relax (symbolS *sym, asection *segtype)
{
asection *symsec;
- bfd_boolean linkonce;
+ bool linkonce;
/* Handle the case of a symbol equated to another symbol. */
while (symbol_equated_reloc_p (sym))
symsec = S_GET_SEGMENT (sym);
/* Duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
- linkonce = FALSE;
+ linkonce = false;
if (symsec != segtype && ! S_IS_LOCAL (sym))
{
if ((bfd_section_flags (symsec) & SEC_LINK_ONCE) != 0)
- linkonce = TRUE;
+ linkonce = true;
/* The GNU toolchain uses an extension for ELF: a section
beginning with the magic string .gnu.linkonce is a linkonce
section. */
if (strncmp (segment_name (symsec), ".gnu.linkonce",
sizeof ".gnu.linkonce" - 1) == 0)
- linkonce = TRUE;
+ linkonce = true;
}
/* This must duplicate the test in adjust_reloc_syms. */
p += 2;
strcpy (second, p);
- s7_parse_16_32_inst (first, FALSE);
+ s7_parse_16_32_inst (first, false);
if (s7_inst.error)
return;
q++;
}
- s7_parse_16_32_inst (second, FALSE);
+ s7_parse_16_32_inst (second, false);
if (s7_inst.error)
return;
demand_empty_rest_of_line ();
sprintf (insn_str, "ld_i32hi r%d, %s", s7_GP, GP_DISP_LABEL);
- if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
sprintf (insn_str, "ld_i32lo r%d, %s", s7_GP, GP_DISP_LABEL);
- if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
sprintf (insn_str, "add r%d, r%d, r%d", s7_GP, s7_GP, reg);
- if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
}
if (cprestore_offset <= 0x3fff)
{
sprintf (insn_str, "sw r%d, [r%d, %d]", s7_GP, reg, cprestore_offset);
- if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
}
else
s7_nor1 = 0;
sprintf (insn_str, "li r1, %d", cprestore_offset);
- if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
sprintf (insn_str, "add r1, r1, r%d", reg);
- if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
sprintf (insn_str, "sw r%d, [r1]", s7_GP);
- if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
s7_nor1 = r1_bak;
}
p = frag_more (4);
s7_number_to_chars (p, (valueT) 0, 4);
- fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, BFD_RELOC_GPREL32);
+ fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, BFD_RELOC_GPREL32);
demand_empty_rest_of_line ();
}
/* Add $gp to the register named as an argument. */
sprintf (insn_str, "add r%d, r%d, r%d", reg, reg, s7_GP);
- if (s7_append_insn (insn_str, TRUE) == (int) s7_FAIL)
+ if (s7_append_insn (insn_str, true) == (int) s7_FAIL)
return;
}
if (s7_INSN_IS_PCE_P (str))
s7_parse_pce_inst (str);
else
- s7_parse_16_32_inst (str, TRUE);
+ s7_parse_16_32_inst (str, true);
if (s7_inst.error)
as_bad (_("%s -- `%s'"), s7_inst.error, s7_inst.str);
return retval;
}
-static bfd_boolean
+static bool
s7_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
int insn_size;
int do_relax_p = 0; /* Indicate doing relaxation for this frag. */
int relaxable_p = 0;
- bfd_boolean word_align_p = FALSE;
+ bool word_align_p = false;
fragS *next_fragp;
/* If the instruction address is odd, make it half word align first. */
/* The regular frag_offset_fixed_p doesn't work for rs_align_test
frags. */
-static bfd_boolean
+static bool
align_test_frag_offset_fixed_p (const fragS *frag1, const fragS *frag2,
bfd_vma *offset)
{
if (frag1 == frag2)
{
*offset = off;
- return TRUE;
+ return true;
}
/* Maybe frag2 is after frag1. */
if (frag == frag2)
{
*offset = off;
- return TRUE;
+ return true;
}
}
if (frag == frag1)
{
*offset = off;
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Optimize a difference of symbols which have rs_align_test frag if
char *name = initial_str;
int name_length = 0;
const sh_opcode_info *op;
- bfd_boolean found = FALSE;
+ bool found = false;
/* Identify opcode in string. */
while (ISSPACE (*name))
if (strncasecmp (op->name, name, name_length) == 0
&& op->name[name_length] == '\0')
{
- found = TRUE;
+ found = true;
break;
}
}
#ifdef OBJ_ELF
case OPTION_FDPIC:
- sh_fdpic = TRUE;
+ sh_fdpic = true;
break;
#endif /* OBJ_ELF */
/* See whether the relocation should be resolved locally. */
-static bfd_boolean
+static bool
sh_local_pcrel (fixS *fix)
{
return (! sh_relax
}
#ifdef OBJ_ELF
-bfd_boolean
+bool
sh_fix_adjustable (fixS *fixP)
{
if (fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL
#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_SH_GOTPC
#define tc_fix_adjustable(FIX) sh_fix_adjustable(FIX)
-extern bfd_boolean sh_fix_adjustable (struct fix *);
+extern bool sh_fix_adjustable (struct fix *);
/* Values passed to md_apply_fix don't include symbol values. */
#define MD_APPLY_SYM_VALUE(FIX) 0
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
#ifndef WORKING_DOT_WORD
if (insn->opcode[i].unresolved)
fix_new_exp (frag_now, p - frag_now->fr_literal,
insn->opcode[i].r_nchars, &insn->opcode[i].addr_expr,
- FALSE, insn->opcode[i].r_type);
+ false, insn->opcode[i].r_type);
}
}
{
/* Target data is little-endian, but floats are stored
big-"word"ian. ugh. */
- return ieee_md_atof (type, literalP, sizeP, TRUE);
+ return ieee_md_atof (type, literalP, sizeP, true);
}
arelent *
/* Whether any instructions at all have been seen. Once any
instructions have been seen, architecture attributes merge into the
previous attribute value rather than replacing it. */
-static bfd_boolean tic6x_seen_insns = FALSE;
+static bool tic6x_seen_insns = false;
/* The number of registers in each register file supported by the
current architecture. */
static unsigned int tic6x_num_registers;
/* Whether predication on A0 is possible. */
-static bfd_boolean tic6x_predicate_a0;
+static bool tic6x_predicate_a0;
/* Whether execute packets can cross fetch packet boundaries. */
-static bfd_boolean tic6x_can_cross_fp_boundary;
+static bool tic6x_can_cross_fp_boundary;
/* Whether there are constraints on simultaneous reads and writes of
40-bit data. */
-static bfd_boolean tic6x_long_data_constraints;
+static bool tic6x_long_data_constraints;
/* Whether compact instructions are available. */
-static bfd_boolean tic6x_compact_insns;
+static bool tic6x_compact_insns;
/* Whether to generate RELA relocations. */
-static bfd_boolean tic6x_generate_rela = TRUE;
+static bool tic6x_generate_rela = true;
/* Whether the code uses DSBT addressing. */
-static bfd_boolean tic6x_dsbt;
+static bool tic6x_dsbt;
/* Types of position-independent data (attribute values for
Tag_ABI_PID). */
static tic6x_pid_type tic6x_pid;
/* Whether the code uses position-independent code. */
-static bfd_boolean tic6x_pic;
+static bool tic6x_pic;
/* Table of supported architecture variants. */
typedef struct
UNWIND_A10
};
-static void tic6x_output_unwinding (bfd_boolean need_extab);
+static void tic6x_output_unwinding (bool need_extab);
/* Return the frame unwind state for the current function, allocating
as necessary. */
break;
case OPTION_MGENERATE_REL:
- tic6x_generate_rela = FALSE;
+ tic6x_generate_rela = false;
break;
default:
return;
}
- tic6x_output_unwinding (TRUE);
+ tic6x_output_unwinding (true);
}
/* Parse a .endp directive. */
/* Output a .exidx entry if we have not already done so.
Then switch back to the text section. */
if (!unwind->table_entry)
- tic6x_output_unwinding (FALSE);
+ tic6x_output_unwinding (false);
subseg_set (unwind->saved_seg, unwind->saved_subseg);
}
static void
s_tic6x_nocmp (int ignored ATTRIBUTE_UNUSED)
{
- seg_info (now_seg)->tc_segment_info_data.nocmp = TRUE;
+ seg_info (now_seg)->tc_segment_info_data.nocmp = true;
demand_empty_rest_of_line ();
}
/* Track for each attribute whether it has been set explicitly (and so
should not have a default value set by the assembler). */
-static bfd_boolean tic6x_attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
+static bool tic6x_attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
/* Parse a .c6xabi_attribute directive. */
int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
- tic6x_attributes_set_explicitly[tag] = TRUE;
+ tic6x_attributes_set_explicitly[tag] = true;
}
typedef struct
}
/* Whether the current line being parsed had the "||" parallel bars. */
-static bfd_boolean tic6x_line_parallel;
+static bool tic6x_line_parallel;
/* Whether the current line being parsed started "||^" to indicate an
SPMASKed parallel instruction. */
-static bfd_boolean tic6x_line_spmask;
+static bool tic6x_line_spmask;
/* If the current line being parsed had an instruction predicate, the
creg value for that predicate (which must be nonzero); otherwise
{
char *p, *endp;
unsigned int z;
- bfd_boolean areg;
- bfd_boolean bad_predicate;
+ bool areg;
+ bool bad_predicate;
switch (c)
{
{
if (input_line_pointer[1] == '^')
{
- tic6x_line_spmask = TRUE;
+ tic6x_line_spmask = true;
input_line_pointer += 2;
}
else
input_line_pointer += 1;
if (tic6x_line_parallel)
as_bad (_("multiple '||' on same line"));
- tic6x_line_parallel = TRUE;
+ tic6x_line_parallel = true;
if (tic6x_line_creg)
as_bad (_("'||' after predicate"));
return 1;
endp = p + 1;
p = input_line_pointer;
z = 0;
- bad_predicate = FALSE;
+ bad_predicate = false;
if (*p == '!')
{
z = 1;
p++;
}
if (*p == 'A' || *p == 'a')
- areg = TRUE;
+ areg = true;
else if (*p == 'B' || *p == 'b')
- areg = FALSE;
+ areg = false;
else
{
- areg = TRUE; /* Avoid uninitialized warning. */
- bad_predicate = TRUE;
+ areg = true; /* Avoid uninitialized warning. */
+ bad_predicate = true;
}
if (!bad_predicate)
{
p++;
if (*p != '0' && *p != '1' && *p != '2')
- bad_predicate = TRUE;
+ bad_predicate = true;
else if (p[1] != ']')
- bad_predicate = TRUE;
+ bad_predicate = true;
else
input_line_pointer = p + 2;
}
if (tic6x_line_parallel)
{
as_bad (_("label after '||'"));
- tic6x_line_parallel = FALSE;
- tic6x_line_spmask = FALSE;
+ tic6x_line_parallel = false;
+ tic6x_line_spmask = false;
}
if (tic6x_line_creg)
{
if (tic6x_line_parallel)
{
as_bad (_("'||' not followed by instruction"));
- tic6x_line_parallel = FALSE;
- tic6x_line_spmask = FALSE;
+ tic6x_line_parallel = false;
+ tic6x_line_spmask = false;
}
if (tic6x_line_creg)
{
/* Handle an alignment directive. Return TRUE if the
machine-independent frag generation should be skipped. */
-bfd_boolean
+bool
tic6x_do_align (int n, char *fill, int len ATTRIBUTE_UNUSED, int max)
{
/* Given code alignments of 4, 8, 16 or 32 bytes, we try to handle
char *p;
if (n > 5)
- return FALSE;
+ return false;
/* Machine-independent code would generate a frag here, but we
wish to handle it in a machine-dependent way. */
saved. */
if (p != align_frag->fr_literal)
abort ();
- align_frag->tc_frag_data.is_insns = FALSE;
- return TRUE;
+ align_frag->tc_frag_data.is_insns = false;
+ return true;
}
else
- return FALSE;
+ return false;
}
/* Types of operand for parsing purposes. These are used as bit-masks
tic6x_mem_scaling scaled;
/* Whether the offset is a register (TRUE) or an expression
(FALSE). */
- bfd_boolean offset_is_reg;
+ bool offset_is_reg;
/* The offset. */
union
{
without changing *P (but possibly changing *REG). Do not print any
diagnostics. */
-static bfd_boolean
+static bool
tic6x_parse_register (char **p, tic6x_register *reg)
{
char *r = *p;
break;
default:
- return FALSE;
+ return false;
}
r++;
r++;
}
else
- return FALSE;
+ return false;
if (reg->num > 0 && *r >= '0' && *r <= '9')
{
}
if (*r >= '0' && *r <= '9')
- return FALSE;
+ return false;
if (reg->num >= 32)
- return FALSE;
+ return false;
*p = r;
- return TRUE;
+ return true;
}
/* Parse the initial two characters of a functional unit name starting
- at *P. If OK, set *BASE and *SIDE and return TRUE; otherwise,
+ at *P. If OK, set *BASE and *SIDE and return true; otherwise,
return FALSE. */
-static bfd_boolean
+static bool
tic6x_parse_func_unit_base (char *p, tic6x_func_unit_base *base,
unsigned int *side)
{
- bfd_boolean good_func_unit = TRUE;
+ bool good_func_unit = true;
tic6x_func_unit_base maybe_base = tic6x_func_unit_nfu;
unsigned int maybe_side = 0;
break;
default:
- good_func_unit = FALSE;
+ good_func_unit = false;
break;
}
break;
default:
- good_func_unit = FALSE;
+ good_func_unit = false;
break;
}
OP_FORMS. For diagnostics, this is operand OPNO of an opcode
starting at STR, length OPC_LEN. */
-static bfd_boolean
+static bool
tic6x_parse_operand (char **p, tic6x_operand *op, unsigned int op_forms,
char *str, int opc_len, unsigned int opno)
{
- bfd_boolean operand_parsed = FALSE;
+ bool operand_parsed = false;
char *q = *p;
if ((op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG))
op->form = TIC6X_OP_FUNC_UNIT;
op->value.func_unit.base = base;
op->value.func_unit.side = side;
- operand_parsed = TRUE;
+ operand_parsed = true;
q = rq;
}
}
if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
{
op->form = TIC6X_OP_IRP;
- operand_parsed = TRUE;
+ operand_parsed = true;
q = rq;
}
}
if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
{
op->form = TIC6X_OP_NRP;
- operand_parsed = TRUE;
+ operand_parsed = true;
q = rq;
}
}
{
op->form = TIC6X_OP_CTRL;
op->value.ctrl = crid;
- operand_parsed = TRUE;
+ operand_parsed = true;
q = rq;
if (!(tic6x_ctrl_table[crid].isa_variants & tic6x_features))
as_bad (_("control register '%s' not supported "
if (!operand_parsed
&& (op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG)))
{
- bfd_boolean mem_ok = TRUE;
+ bool mem_ok = true;
char *mq = q;
tic6x_mem_mod mem_mod = tic6x_mem_mod_none;
tic6x_register base_reg;
- bfd_boolean require_offset, permit_offset;
+ bool require_offset, permit_offset;
tic6x_mem_scaling scaled;
- bfd_boolean offset_is_reg;
+ bool offset_is_reg;
expressionS offset_exp;
tic6x_register offset_reg;
if (*mq == '*')
mq++;
else
- mem_ok = FALSE;
+ mem_ok = false;
if (mem_ok)
{
}
if (mem_mod == tic6x_mem_mod_none)
- permit_offset = FALSE;
+ permit_offset = false;
else
- permit_offset = TRUE;
+ permit_offset = true;
if (mem_mod == tic6x_mem_mod_plus || mem_mod == tic6x_mem_mod_minus)
- require_offset = TRUE;
+ require_offset = true;
else
- require_offset = FALSE;
+ require_offset = false;
scaled = tic6x_offset_none;
- offset_is_reg = FALSE;
+ offset_is_reg = false;
if (mem_ok && permit_offset)
{
if (scaled == tic6x_offset_scaled
|| (op_forms & TIC6X_OP_MEM_UNREG))
{
- bfd_boolean reg_ok;
+ bool reg_ok;
char *rq = mq;
reg_ok = tic6x_parse_register (&rq, &offset_reg);
if (*rq == endc)
{
mq = rq;
- offset_is_reg = TRUE;
+ offset_is_reg = true;
}
}
}
if (*mq == endc)
mq++;
else
- mem_ok = FALSE;
+ mem_ok = false;
}
}
if (mem_ok && require_offset && scaled == tic6x_offset_none)
- mem_ok = FALSE;
+ mem_ok = false;
if (mem_ok)
{
skip_whitespace (mq);
if (!is_end_of_line[(unsigned char) *mq] && *mq != ',')
- mem_ok = FALSE;
+ mem_ok = false;
}
if (mem_ok)
op->value.mem.offset.reg = offset_reg;
else
op->value.mem.offset.exp = offset_exp;
- operand_parsed = TRUE;
+ operand_parsed = true;
q = mq;
if (base_reg.num >= tic6x_num_registers)
as_bad (_("register number %u not supported on this architecture"),
if (!operand_parsed && (op_forms & (TIC6X_OP_REG | TIC6X_OP_REGPAIR)))
{
tic6x_register first_reg, second_reg;
- bfd_boolean reg_ok;
+ bool reg_ok;
char *rq = q;
reg_ok = tic6x_parse_register (&rq, &first_reg);
opc_len, str);
op->form = TIC6X_OP_REGPAIR;
op->value.reg = second_reg;
- operand_parsed = TRUE;
+ operand_parsed = true;
q = rq;
}
}
{
op->form = TIC6X_OP_REG;
op->value.reg = first_reg;
- operand_parsed = TRUE;
+ operand_parsed = true;
q = rq;
}
}
expression (&op->value.exp);
q = input_line_pointer;
input_line_pointer = save_input_line_pointer;
- operand_parsed = TRUE;
+ operand_parsed = true;
}
if (operand_parsed)
skip_whitespace (q);
if (!is_end_of_line[(unsigned char) *q] && *q != ',')
{
- operand_parsed = FALSE;
+ operand_parsed = false;
as_bad (_("junk after operand %u of '%.*s'"), opno,
opc_len, str);
while (!is_end_of_line[(unsigned char) *q] && *q != ',')
static void
tic6x_fix_new_exp (fragS *frag, int where, int size, expressionS *exp,
int pcrel, bfd_reloc_code_real_type r_type,
- bfd_boolean fix_adda)
+ bool fix_adda)
{
bfd_reloc_code_real_type new_reloc = BFD_RELOC_UNUSED;
symbolS *subsy = NULL;
return;
}
- tic6x_fix_new_exp (frag, where, size, exp, 0, r_type, FALSE);
+ tic6x_fix_new_exp (frag, where, size, exp, 0, r_type, false);
}
/* Initialize target-specific fix data. */
void
tic6x_init_fix_data (fixS *fixP)
{
- fixP->tc_fix_data.fix_adda = FALSE;
+ fixP->tc_fix_data.fix_adda = false;
fixP->tc_fix_data.fix_subsy = NULL;
}
/* Return true if the fix can be handled by GAS, false if it must
be passed through to the linker. */
-bfd_boolean
+bool
tic6x_fix_adjustable (fixS *fixP)
{
switch (fixP->fx_r_type)
abort ();
mem_ref->mod = tic6x_mem_mod_plus;
mem_ref->scaled = tic6x_offset_unscaled;
- mem_ref->offset_is_reg = FALSE;
+ mem_ref->offset_is_reg = false;
memset (&mem_ref->offset.exp, 0, sizeof mem_ref->offset.exp);
mem_ref->offset.exp.X_op = O_constant;
mem_ref->offset.exp.X_add_number = 0;
if (mem_ref->scaled != tic6x_offset_none)
break;
mem_ref->scaled = tic6x_offset_scaled;
- mem_ref->offset_is_reg = FALSE;
+ mem_ref->offset_is_reg = false;
memset (&mem_ref->offset.exp, 0, sizeof mem_ref->offset.exp);
mem_ref->offset.exp.X_op = O_constant;
mem_ref->offset.exp.X_add_number = 1;
instruction, or 0 if not in such a loop; the only possible problems
are operands being out of range (they already match the
fine-grained form), and inappropriate predication. If this
- succeeds, return the encoding and set *OK to TRUE; otherwise return
+ succeeds, return the encoding and set *OK to true; otherwise return
0 and set *OK to FALSE. If a fix is needed, set *FIX_NEEDED to
true and fill in *FIX_EXP, *FIX_PCREL, *FX_R_TYPE and *FIX_ADDA.
- Print error messages for failure if PRINT_ERRORS is TRUE; the
+ Print error messages for failure if PRINT_ERRORS is true; the
opcode starts at STR and has length OPC_LEN. */
static unsigned int
unsigned int func_unit_cross,
unsigned int func_unit_data_side, int sploop_ii,
expressionS **fix_exp, int *fix_pcrel,
- bfd_reloc_code_real_type *fx_r_type, bfd_boolean *fix_adda,
- bfd_boolean *fix_needed, bfd_boolean *ok,
- bfd_boolean print_errors, char *str, int opc_len)
+ bfd_reloc_code_real_type *fx_r_type, bool *fix_adda,
+ bool *fix_needed, bool *ok,
+ bool print_errors, char *str, int opc_len)
{
const tic6x_opcode *opct;
const tic6x_insn_format *fmt;
if (print_errors)
as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
value = ucexp.X_add_number;
a known relocation for them. */
if (fldd->bitfields[0].low_pos != 7 || fldd->bitfields[0].width != 16)
abort ();
- *fix_needed = TRUE;
+ *fix_needed = true;
*fix_exp = &operands[opno].value.exp;
*fix_pcrel = 0;
*fx_r_type = BFD_RELOC_C6000_ABS_S16;
- *fix_adda = FALSE;
+ *fix_adda = false;
break;
}
sign_value = SEXT (operands[opno].value.exp.X_add_number);
if (print_errors)
as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
value = sign_value + (1 << (fldd->bitfields[0].width - 1));
if (print_errors)
as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
value = operands[opno].value.exp.X_add_number - 1;
as_bad (_("offset in operand %u of '%.*s' not "
"divisible by %u"), opno + 1, opc_len,
str, 1u << bits);
- *ok = FALSE;
+ *ok = false;
return 0;
}
ucexp.X_add_number >>= bits;
check is not needed at this point to encode the value,
and if there is eventually a problem it will be detected
either in md_apply_fix or at link time. */
- *fix_needed = TRUE;
+ *fix_needed = true;
*fix_exp = expp;
*fix_pcrel = 0;
*fx_r_type
= tic6x_dpr_reloc (opct->variable_fields[fld].coding_method);
if (operands[opno].form == TIC6X_OP_EXP)
- *fix_adda = TRUE;
+ *fix_adda = true;
else
- *fix_adda = FALSE;
+ *fix_adda = false;
break;
case tic6x_coding_lcst_low16:
known relocation. */
if (fldd->bitfields[0].low_pos != 7 || fldd->bitfields[0].width != 16)
abort ();
- *fix_needed = TRUE;
+ *fix_needed = true;
*fix_exp = &operands[opno].value.exp;
*fix_pcrel = 0;
*fx_r_type = BFD_RELOC_C6000_ABS_L16;
- *fix_adda = FALSE;
+ *fix_adda = false;
}
break;
known relocation. */
if (fldd->bitfields[0].low_pos != 7 || fldd->bitfields[0].width != 16)
abort ();
- *fix_needed = TRUE;
+ *fix_needed = true;
*fix_exp = &operands[opno].value.exp;
*fix_pcrel = 0;
*fx_r_type = BFD_RELOC_C6000_ABS_H16;
- *fix_adda = FALSE;
+ *fix_adda = false;
}
break;
if (operands[opno].form != TIC6X_OP_EXP)
abort ();
value = 0;
- *fix_needed = TRUE;
+ *fix_needed = true;
*fix_exp = &operands[opno].value.exp;
*fix_pcrel = 1;
if (fldd->bitfields[0].low_pos == 7 && fldd->bitfields[0].width == 21)
/* Opcode table should not use this encoding without a
known relocation. */
abort ();
- *fix_adda = FALSE;
+ *fix_adda = false;
break;
case tic6x_coding_regpair_lsb:
if (print_errors)
as_bad (_("offset in operand %u of '%.*s' out of range"),
opno + 1, opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
if (mem.offset.exp.X_add_number % scale)
as_bad (_("offset in operand %u of '%.*s' not "
"divisible by %u"),
opno + 1, opc_len, str, scale);
- *ok = FALSE;
+ *ok = false;
return 0;
}
value = mem.offset.exp.X_add_number / scale;
if (print_errors)
as_bad (_("offset in operand %u of '%.*s' out of range"),
opno + 1, opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
value = mem.offset.exp.X_add_number;
if (print_errors)
as_bad (_("functional unit already masked for operand "
"%u of '%.*s'"), opno + 1, opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
value |= v;
as_bad (_("'%.*s' instruction not in a software "
"pipelined loop"),
opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
if (print_errors)
as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
value = operands[opno].value.exp.X_add_number;
if (print_errors)
as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
value = operands[opno].value.exp.X_add_number;
if (print_errors)
as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
if (print_errors)
as_bad (_("instruction '%.*s' cannot be predicated"),
opc_len, str);
- *ok = FALSE;
+ *ok = false;
return 0;
}
z = tic6x_field_from_fmt (fmt, tic6x_field_z);
opcode_value |= this_line_z << z->bitfields[0].low_pos;
}
- *ok = TRUE;
+ *ok = true;
return opcode_value;
}
{
char *p;
int opc_len;
- bfd_boolean this_line_parallel;
- bfd_boolean this_line_spmask;
+ bool this_line_parallel;
+ bool this_line_spmask;
unsigned int this_line_creg;
unsigned int this_line_z;
tic6x_label_list *this_insn_label_list;
unsigned int opc_rank[TIC6X_NUM_PREFER];
const tic6x_opcode *opct = NULL;
int min_rank, try_rank, max_rank;
- bfd_boolean num_operands_permitted[TIC6X_MAX_SOURCE_OPERANDS + 1]
- = { FALSE };
+ bool num_operands_permitted[TIC6X_MAX_SOURCE_OPERANDS + 1] = { false };
unsigned int operand_forms[TIC6X_MAX_SOURCE_OPERANDS] = { 0 };
tic6x_operand operands[TIC6X_MAX_SOURCE_OPERANDS];
unsigned int max_num_operands;
unsigned int num_operands_read;
- bfd_boolean ok_this_arch, ok_this_fu, ok_this_arch_fu;
- bfd_boolean bad_operands = FALSE;
+ bool ok_this_arch, ok_this_fu, ok_this_arch_fu;
+ bool bad_operands = false;
unsigned int opcode_value;
- bfd_boolean encoded_ok;
- bfd_boolean fix_needed = FALSE;
+ bool encoded_ok;
+ bool fix_needed = false;
expressionS *fix_exp = NULL;
int fix_pcrel = 0;
bfd_reloc_code_real_type fx_r_type = BFD_RELOC_UNUSED;
- bfd_boolean fix_adda = FALSE;
+ bool fix_adda = false;
fragS *insn_frag;
char *output;
/* Now an instruction has been seen, architecture attributes from
.arch directives merge with rather than overriding the previous
value. */
- tic6x_seen_insns = TRUE;
+ tic6x_seen_insns = true;
/* If no .arch directives or -march options have been seen, we are
assessing instruction validity based on the C674X default, so set
the attribute accordingly. */
this_line_spmask = tic6x_line_spmask;
this_line_creg = tic6x_line_creg;
this_line_z = tic6x_line_z;
- tic6x_line_parallel = FALSE;
- tic6x_line_spmask = FALSE;
+ tic6x_line_parallel = false;
+ tic6x_line_spmask = false;
tic6x_line_creg = 0;
tic6x_line_z = 0;
seginfo = seg_info (now_seg);
specifier. */
if (*p == '.')
{
- bfd_boolean good_func_unit;
+ bool good_func_unit;
tic6x_func_unit_base maybe_base = tic6x_func_unit_nfu;
unsigned int maybe_side = 0;
unsigned int maybe_cross = 0;
p += 5;
}
else
- good_func_unit = FALSE;
+ good_func_unit = false;
}
if (good_func_unit)
num_matching_opcodes = 0;
opcm = XNEWVEC (tic6x_opcode_id, max_matching_opcodes);
max_num_operands = 0;
- ok_this_arch = FALSE;
- ok_this_fu = FALSE;
- ok_this_arch_fu = FALSE;
+ ok_this_arch = false;
+ ok_this_fu = false;
+ ok_this_arch_fu = false;
for (opc = opc_list; opc; opc = opc->next)
{
unsigned int num_operands;
unsigned int i;
- bfd_boolean this_opc_arch_ok = TRUE;
- bfd_boolean this_opc_fu_ok = TRUE;
+ bool this_opc_arch_ok = true;
+ bool this_opc_fu_ok = true;
if (tic6x_insn_format_table[tic6x_opcode_table[opc->id].format].num_bits
!= 32)
continue;
if (!(tic6x_opcode_table[opc->id].isa_variants & tic6x_features))
- this_opc_arch_ok = FALSE;
+ this_opc_arch_ok = false;
if (tic6x_opcode_table[opc->id].func_unit != func_unit_base)
- this_opc_fu_ok = FALSE;
+ this_opc_fu_ok = false;
if (func_unit_side == 1
&& (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SIDE_B_ONLY))
- this_opc_fu_ok = FALSE;
+ this_opc_fu_ok = false;
if (func_unit_cross
&& (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_NO_CROSS))
- this_opc_fu_ok = FALSE;
+ this_opc_fu_ok = false;
if (!func_unit_data_side
&& (tic6x_opcode_table[opc->id].flags
& (TIC6X_FLAG_LOAD | TIC6X_FLAG_STORE)))
- this_opc_fu_ok = FALSE;
+ this_opc_fu_ok = false;
if (func_unit_data_side
&& !(tic6x_opcode_table[opc->id].flags
& (TIC6X_FLAG_LOAD | TIC6X_FLAG_STORE)))
- this_opc_fu_ok = FALSE;
+ this_opc_fu_ok = false;
if (func_unit_data_side == 1
&& (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SIDE_T2_ONLY))
- this_opc_fu_ok = FALSE;
+ this_opc_fu_ok = false;
if (this_opc_arch_ok)
- ok_this_arch = TRUE;
+ ok_this_arch = true;
if (this_opc_fu_ok)
- ok_this_fu = TRUE;
+ ok_this_fu = true;
if (!this_opc_arch_ok || !this_opc_fu_ok)
continue;
- ok_this_arch_fu = TRUE;
+ ok_this_arch_fu = true;
opcm[num_matching_opcodes] = opc->id;
num_matching_opcodes++;
num_operands = tic6x_opcode_table[opc->id].num_operands;
{
operand_forms[i]
|= tic6x_coarse_operand_form (tic6x_operand_func_unit);
- num_operands_permitted[i] = TRUE;
+ num_operands_permitted[i] = true;
}
}
else
operand_forms[i] |= tic6x_coarse_operand_form (f);
}
}
- num_operands_permitted[num_operands] = TRUE;
+ num_operands_permitted[num_operands] = true;
if (num_operands > max_num_operands)
max_num_operands = num_operands;
}
abort ();
num_operands_read = 0;
- while (TRUE)
+ while (true)
{
skip_whitespace (p);
if (is_end_of_line[(unsigned char) *p])
if (num_operands_read > 0)
{
as_bad (_("missing operand after comma"));
- bad_operands = TRUE;
+ bad_operands = true;
}
break;
}
if (max_num_operands == 0)
{
as_bad (_("too many operands to '%.*s'"), opc_len, str);
- bad_operands = TRUE;
+ bad_operands = true;
break;
}
if (!tic6x_parse_operand (&p, &operands[num_operands_read],
operand_forms[num_operands_read], str, opc_len,
num_operands_read + 1))
- bad_operands = TRUE;
+ bad_operands = true;
num_operands_read++;
if (is_end_of_line[(unsigned char) *p])
if (num_operands_read == max_num_operands)
{
as_bad (_("too many operands to '%.*s'"), opc_len, str);
- bad_operands = TRUE;
+ bad_operands = true;
break;
}
continue;
if (!bad_operands && !num_operands_permitted[num_operands_read])
{
as_bad (_("bad number of operands to '%.*s'"), opc_len, str);
- bad_operands = TRUE;
+ bad_operands = true;
}
if (!bad_operands)
for (i = 0; i < num_operands_read; i++)
{
- bfd_boolean coarse_ok = FALSE;
- bfd_boolean fine_ok = FALSE;
+ bool coarse_ok = false;
+ bool fine_ok = false;
tic6x_operand_match fine_failure = tic6x_match_matches;
unsigned int j;
if (operands[i].form != cf)
continue;
- coarse_ok = TRUE;
+ coarse_ok = true;
this_fine_failure
= tic6x_operand_matches_form (&operands[i], f, rw,
func_unit_side,
func_unit_data_side);
if (this_fine_failure == tic6x_match_matches)
{
- fine_ok = TRUE;
+ fine_ok = true;
break;
}
if (fine_failure == tic6x_match_matches
default:
abort ();
}
- bad_operands = TRUE;
+ bad_operands = true;
break;
}
}
operands is valid. Check whether there is an opcode choice
for which all operands are simultaneously valid. */
unsigned int i;
- bfd_boolean found_match = FALSE;
+ bool found_match = false;
for (i = 0; i < TIC6X_NUM_PREFER; i++)
opc_rank[i] = (unsigned int) -1;
for (i = 0; i < num_matching_opcodes; i++)
{
unsigned int j;
- bfd_boolean this_matches = TRUE;
+ bool this_matches = true;
if (!(tic6x_opcode_table[opcm[i]].flags & TIC6X_FLAG_SPMASK)
&& tic6x_opcode_table[opcm[i]].num_operands != num_operands_read)
func_unit_data_side)
!= tic6x_match_matches)
{
- this_matches = FALSE;
+ this_matches = false;
break;
}
}
here. */
abort ();
- found_match = TRUE;
+ found_match = true;
}
}
if (!found_match)
{
as_bad (_("bad operand combination for '%.*s'"), opc_len, str);
- bad_operands = TRUE;
+ bad_operands = true;
}
}
}
opcode_value = 0;
- encoded_ok = FALSE;
+ encoded_ok = false;
for (try_rank = max_rank; try_rank >= min_rank; try_rank--)
{
- fix_needed = FALSE;
+ fix_needed = false;
if (opc_rank[try_rank] == (unsigned int) -1)
continue;
saved. */
if (output != insn_frag->fr_literal)
abort ();
- insn_frag->tc_frag_data.is_insns = TRUE;
+ insn_frag->tc_frag_data.is_insns = true;
insn_frag->tc_frag_data.can_cross_fp_boundary
= tic6x_can_cross_fp_boundary;
}
segment_info_type *info;
frchainS *frchp;
fragS *fragp;
- bfd_boolean have_code = FALSE;
- bfd_boolean have_non_code = FALSE;
+ bool have_code = false;
+ bool have_non_code = false;
info = seg_info (section);
if (info == NULL)
{
case rs_machine_dependent:
if (fragp->tc_frag_data.is_insns)
- have_code = TRUE;
+ have_code = true;
break;
case rs_dummy:
case rs_fill:
if (fragp->fr_fix > 0)
- have_non_code = TRUE;
+ have_non_code = true;
break;
default:
- have_non_code = TRUE;
+ have_non_code = true;
break;
}
for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
look_at_frag:
{
- bfd_boolean go_back = FALSE;
+ bool go_back = false;
frchainS *frchp_next;
fragS *fragp_next;
if (want_insert > 7)
abort ();
want_insert_done_so_far = 0;
- go_back = TRUE;
+ go_back = true;
}
if (!fragp->tc_frag_data.is_insns)
if (want_insert > 7)
abort ();
want_insert_done_so_far = 0;
- go_back = TRUE;
+ go_back = true;
}
else if (want_insert && !go_back)
{
want_insert -= want_insert_done_so_far;
want_insert_done_so_far = 0;
if (want_insert)
- go_back = TRUE;
+ go_back = true;
}
}
}
void
tic6x_frag_init (fragS *fragp)
{
- fragp->tc_frag_data.is_insns = FALSE;
- fragp->tc_frag_data.can_cross_fp_boundary = FALSE;
+ fragp->tc_frag_data.is_insns = false;
+ fragp->tc_frag_data.can_cross_fp_boundary = false;
}
/* Set an attribute if it has not already been set by the user. */
int
tic6x_regname_to_dw2regnum (char *regname)
{
- bfd_boolean reg_ok;
+ bool reg_ok;
tic6x_register reg;
char *rq = regname;
}
static void
-tic6x_output_unwinding (bfd_boolean need_extab)
+tic6x_output_unwinding (bool need_extab)
{
tic6x_unwind_info *unwind = tic6x_get_unwind ();
unsigned safe_mask = unwind->safe_mask;
unwind->cfa_reg = 31;
unwind->return_reg = UNWIND_B3;
unwind->saved_reg_count = 0;
- unwind->pop_rts = FALSE;
+ unwind->pop_rts = false;
unwind->saved_seg = now_seg;
unwind->saved_subseg = now_subseg;
for (reg = 0; reg < TIC6X_NUM_UNWIND_REGS; reg++)
- unwind->reg_saved[reg] = FALSE;
+ unwind->reg_saved[reg] = false;
/* Scan FDE instructions to build up stack frame layout. */
for (insn = fde->data; insn; insn = insn->next)
case DW_CFA_same_value:
reg = tic6x_unwind_reg_from_dwarf (insn->u.r);
if (reg >= 0)
- unwind->reg_saved[reg] = FALSE;
+ unwind->reg_saved[reg] = false;
break;
case DW_CFA_offset:
insn->u.ri.reg);
return;
}
- unwind->reg_saved[reg] = TRUE;
+ unwind->reg_saved[reg] = true;
unwind->reg_offset[reg] = insn->u.ri.offset;
if (insn->u.ri.reg == UNWIND_B3)
unwind->return_reg = UNWIND_B3;
}
unwind->return_reg = reg;
- unwind->reg_saved[UNWIND_B3] = FALSE;
+ unwind->reg_saved[UNWIND_B3] = false;
if (unwind->reg_saved[reg])
{
as_bad (_("unable to restore return address from "
if (reg == TIC6X_NUM_UNWIND_REGS)
{
- unwind->pop_rts = TRUE;
+ unwind->pop_rts = true;
reg_saved_mask = 0;
}
}
int data_bytes;
offsetT reg_offset[TIC6X_NUM_UNWIND_REGS];
- bfd_boolean reg_saved[TIC6X_NUM_UNWIND_REGS];
+ bool reg_saved[TIC6X_NUM_UNWIND_REGS];
int cfa_reg;
int return_reg;
unsigned safe_mask;
unsigned compact_mask;
unsigned reg_saved_mask;
offsetT cfa_offset;
- bfd_boolean pop_rts;
+ bool pop_rts;
/* Only valid for UNWIND_OP_POP_REG */
int saved_reg_count;
} tic6x_unwind_info;
tic6x_label_list *label_list;
/* Whether compact instructions are forbidden here. */
- bfd_boolean nocmp;
+ bool nocmp;
/* If there is a current execute packet, the frag being used for
that execute packet. */
{
/* Whether this machine-dependent frag is used for instructions (as
opposed to code alignment). */
- bfd_boolean is_insns;
+ bool is_insns;
/* For a frag used for instructions, whether it is may cross a fetch
packet boundary (subject to alignment requirements). */
- bfd_boolean can_cross_fp_boundary;
+ bool can_cross_fp_boundary;
} tic6x_frag_info;
#define TC_FRAG_TYPE tic6x_frag_info
#define TC_FRAG_INIT(fragP, max_bytes) tic6x_frag_init (fragP)
left (it represents a value to be encoded literally in the
instruction, whereas a non-constant represents a DP-relative
value counting in the appropriate units). */
- bfd_boolean fix_adda;
+ bool fix_adda;
/* The symbol to be subtracted in case of a PCR_H16 or PCR_L16
reloc. */
symbolS *fix_subsy;
if (tic6x_do_align (n, fill, len, max)) \
goto label; \
} while (0)
-extern bfd_boolean tic6x_do_align (int n, char *fill, int len, int max);
+extern bool tic6x_do_align (int n, char *fill, int len, int max);
#define CONVERT_SYMBOLIC_ATTRIBUTE(name) \
tic6x_convert_symbolic_attribute (name)
bfd_reloc_code_real_type);
#define tc_fix_adjustable(FIX) tic6x_fix_adjustable (FIX)
-extern bfd_boolean tic6x_fix_adjustable (struct fix *);
+extern bool tic6x_fix_adjustable (struct fix *);
#define tc_frob_label(sym) tic6x_frob_label (sym)
extern void tic6x_frob_label (symbolS *sym);
/* Make sure all instructions can be bundled with other
instructions. */
const struct tilegx_opcode *cannot_bundle = NULL;
- bfd_boolean seen_non_nop = FALSE;
+ bool seen_non_nop = false;
for (j = 0; j < current_bundle_index; j++)
{
else if (op->mnemonic != TILEGX_OPC_NOP
&& op->mnemonic != TILEGX_OPC_INFO
&& op->mnemonic != TILEGX_OPC_INFOL)
- seen_non_nop = TRUE;
+ seen_non_nop = true;
}
if (cannot_bundle != NULL && seen_non_nop)
/* Make sure all instructions can be bundled with other
instructions. */
const struct tilepro_opcode *cannot_bundle = NULL;
- bfd_boolean seen_non_nop = FALSE;
+ bool seen_non_nop = false;
for (j = 0; j < current_bundle_index; j++)
{
else if (op->mnemonic != TILEPRO_OPC_NOP
&& op->mnemonic != TILEPRO_OPC_INFO
&& op->mnemonic != TILEPRO_OPC_INFOL)
- seen_non_nop = TRUE;
+ seen_non_nop = true;
}
if (cannot_bundle != NULL && seen_non_nop)
#define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000)
/* Set to TRUE if we want to be pedantic about signed overflows. */
-static bfd_boolean warn_signed_overflows = FALSE;
-static bfd_boolean warn_unsigned_overflows = FALSE;
+static bool warn_signed_overflows = false;
+static bool warn_unsigned_overflows = false;
/* Non-zero if floating point insns are not being used. */
static signed int soft_float = -1;
reg_name_search (const struct reg_name *regs,
int regcount,
const char *name,
- bfd_boolean accept_numbers)
+ bool accept_numbers)
{
int middle, low, high;
int cmp;
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
-static bfd_boolean
+static bool
register_name (expressionS *expressionP)
{
int reg_number;
c = get_symbol_name (&name);
reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT,
- name, FALSE);
+ name, false);
/* Put back the delimiting char. */
(void) restore_line_pointer (c);
expressionP->X_op = O_register;
expressionP->X_add_number = reg_number;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
expressionP->X_op = O_illegal;
- return FALSE;
+ return false;
}
/* Summary of system_register_name().
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
-static bfd_boolean
+static bool
system_register_name (expressionS *expressionP,
- bfd_boolean accept_numbers)
+ bool accept_numbers)
{
int reg_number;
char *name;
expressionP->X_op = O_register;
expressionP->X_add_number = reg_number;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
expressionP->X_op = O_illegal;
- return FALSE;
+ return false;
}
/* Summary of cc_name().
Input_line_pointer->(next non-blank) char after operand, or is in
its original state. */
-static bfd_boolean
+static bool
cc_name (expressionS *expressionP,
- bfd_boolean accept_numbers)
+ bool accept_numbers)
{
int reg_number;
char *name;
expressionP->X_op = O_constant;
expressionP->X_add_number = reg_number;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
expressionP->X_op = O_illegal;
expressionP->X_add_number = 0;
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
float_cc_name (expressionS *expressionP,
- bfd_boolean accept_numbers)
+ bool accept_numbers)
{
int reg_number;
char *name;
expressionP->X_op = O_constant;
expressionP->X_add_number = reg_number;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
expressionP->X_op = O_illegal;
expressionP->X_add_number = 0;
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
cacheop_name (expressionS * expressionP,
- bfd_boolean accept_numbers)
+ bool accept_numbers)
{
int reg_number;
char *name;
expressionP->X_op = O_constant;
expressionP->X_add_number = reg_number;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
expressionP->X_op = O_illegal;
expressionP->X_add_number = 0;
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
prefop_name (expressionS * expressionP,
- bfd_boolean accept_numbers)
+ bool accept_numbers)
{
int reg_number;
char *name;
expressionP->X_op = O_constant;
expressionP->X_add_number = reg_number;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
expressionP->X_op = O_illegal;
expressionP->X_add_number = 0;
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
vector_register_name (expressionS *expressionP)
{
int reg_number;
c = get_symbol_name (&name);
reg_number = reg_name_search (vector_registers, VREG_NAME_CNT,
- name, FALSE);
+ name, false);
/* Put back the delimiting char. */
(void) restore_line_pointer (c);
expressionP->X_op = O_register;
expressionP->X_add_number = reg_number;
- return TRUE;
+ return true;
}
/* Reset the line as if we had not done anything. */
expressionP->X_op = O_illegal;
- return FALSE;
+ return false;
}
static void
if (i == 32)
return _("illegal register included in list");
}
- else if (system_register_name (&exp, TRUE))
+ else if (system_register_name (&exp, true))
{
if (regs == type1_regs)
{
size_t md_longopts_size = sizeof (md_longopts);
-static bfd_boolean v850_data_8 = FALSE;
+static bool v850_data_8 = false;
void
md_show_usage (FILE *stream)
}
if (strcmp (arg, "warn-signed-overflow") == 0)
- warn_signed_overflows = TRUE;
+ warn_signed_overflows = true;
else if (strcmp (arg, "warn-unsigned-overflow") == 0)
- warn_unsigned_overflows = TRUE;
+ warn_unsigned_overflows = true;
else if (strcmp (arg, "v850") == 0)
{
}
else if (strcmp (arg, "8byte-align") == 0)
{
- v850_data_8 = TRUE;
+ v850_data_8 = true;
v850_e_flags |= EF_RH850_DATA_ALIGN8;
}
else if (strcmp (arg, "4byte-align") == 0)
{
- v850_data_8 = FALSE;
+ v850_data_8 = false;
v850_e_flags &= ~ EF_RH850_DATA_ALIGN8;
}
else if (strcmp (arg, "soft-float") == 0)
const char *
md_atof (int type, char *litp, int *sizep)
{
- return ieee_md_atof (type, litp, sizep, FALSE);
+ return ieee_md_atof (type, litp, sizep, false);
}
/* Very gross. */
static bfd_reloc_code_real_type
v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg)
{
- bfd_boolean paren_skipped = FALSE;
+ bool paren_skipped = false;
/* Skip leading opening parenthesis. */
if (*input_line_pointer == '(')
{
++input_line_pointer;
- paren_skipped = TRUE;
+ paren_skipped = true;
}
#define CHECK_(name, reloc) \
char *f = NULL;
int i;
int match;
- bfd_boolean extra_data_after_insn = FALSE;
+ bool extra_data_after_insn = false;
unsigned extra_data_len = 0;
unsigned long extra_data = 0;
char *saved_input_line_pointer;
next_opindex = 0;
insn = opcode->opcode;
extra_data_len = 0;
- extra_data_after_insn = FALSE;
+ extra_data_after_insn = false;
input_line_pointer = str = start_of_operands;
if (operand->flags & V850E_IMMEDIATE32)
{
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 4;
extra_data = 0;
}
errmsg = _("immediate operand is too large");
goto error;
}
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 2;
extra_data = 0;
}
goto error;
}
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 2;
extra_data = 0;
}
if (operand->flags & V850E_IMMEDIATE32)
{
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 4;
extra_data = 0;
}
errmsg = _("immediate operand is too large");
goto error;
}
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 2;
extra_data = 0;
}
goto error;
}
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 2;
extra_data = 0;
}
break;
}
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 2;
extra_data = ex.X_add_number;
}
fixups[fc].reloc = operand->default_reloc;
++fc;
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 2;
extra_data = 0;
}
break;
}
- extra_data_after_insn = TRUE;
+ extra_data_after_insn = true;
extra_data_len = 4;
extra_data = ex.X_add_number;
}
}
else if ((operand->flags & V850_OPERAND_SRG) != 0)
{
- if (!system_register_name (&ex, TRUE))
+ if (!system_register_name (&ex, true))
{
errmsg = _("invalid system register name");
}
}
else if ((operand->flags & V850_OPERAND_CC) != 0)
{
- if (!cc_name (&ex, TRUE))
+ if (!cc_name (&ex, true))
{
errmsg = _("invalid condition code name");
}
}
else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0)
{
- if (!float_cc_name (&ex, TRUE))
+ if (!float_cc_name (&ex, true))
{
errmsg = _("invalid condition code name");
}
}
else if ((operand->flags & V850_OPERAND_CACHEOP) != 0)
{
- if (!cacheop_name (&ex, TRUE))
+ if (!cacheop_name (&ex, true))
errmsg = _("invalid cache operation name");
}
else if ((operand->flags & V850_OPERAND_PREFOP) != 0)
{
- if (!prefop_name (&ex, TRUE))
+ if (!prefop_name (&ex, true))
errmsg = _("invalid pref operation name");
}
else if ((operand->flags & V850_OPERAND_VREG) != 0)
&symbol_rootP, &symbol_lastP);
}
}
- else if (system_register_name (&ex, FALSE)
+ else if (system_register_name (&ex, false)
&& (operand->flags & V850_OPERAND_SRG) == 0)
{
errmsg = _("syntax error: system register not expected");
}
- else if (cc_name (&ex, FALSE)
+ else if (cc_name (&ex, false)
&& (operand->flags & V850_OPERAND_CC) == 0)
{
errmsg = _("syntax error: condition code not expected");
}
- else if (float_cc_name (&ex, FALSE)
+ else if (float_cc_name (&ex, false)
&& (operand->flags & V850_OPERAND_FLOAT_CC) == 0)
{
errmsg = _("syntax error: condition code not expected");
f = frag_more (extra_data_len);
md_number_to_chars (f, extra_data, extra_data_len);
- extra_data_after_insn = FALSE;
+ extra_data_after_insn = false;
}
}
fix_new (frag, where, size, NULL, 0, 0, r);
}
-bfd_boolean
+bool
v850_fix_adjustable (fixS *fixP)
{
if (fixP->fx_addsy == NULL)
#define md_operand(x)
#define tc_fix_adjustable(FIX) v850_fix_adjustable (FIX)
-extern bfd_boolean v850_fix_adjustable (struct fix *);
+extern bool v850_fix_adjustable (struct fix *);
#define TC_FORCE_RELOCATION(FIX) v850_force_relocation(FIX)
extern int v850_force_relocation (struct fix *);
/* Indicate whether a fixup against a locally defined
symbol should be adjusted to be against the section
symbol. */
-bfd_boolean
+bool
visium_fix_adjustable (fixS *fix)
{
/* We need the symbol name for the VTABLE entries. */
#define WORKING_DOT_WORD
#define tc_fix_adjustable(FIXP) visium_fix_adjustable (FIXP)
-extern bfd_boolean visium_fix_adjustable (struct fix *);
+extern bool visium_fix_adjustable (struct fix *);
#define HANDLE_ALIGN(FRAGP) \
if ((FRAGP)->fr_type == rs_align_code) \
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
/* No machine-dependent frags. */
/* Apply a fixup, return TRUE if done (and no relocation is
needed). */
-static bfd_boolean
+static bool
apply_full_field_fix (fixS * fixP, char *buf, bfd_vma val, int size)
{
if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
{
fixP->fx_addnumber = val;
- return FALSE;
+ return false;
}
number_to_chars_littleendian (buf, val, size);
- return TRUE;
+ return true;
}
/* Apply a fixup (potentially PC-relative), set the fx_done flag if
/* Allow '/' in opcodes. */
-static inline bfd_boolean
+static inline bool
is_part_of_opcode (char c)
{
return is_part_of_name (c) || (c == '/');
symbol, or a special relocation for <expr>@got, <expr>@gotcode, and
<expr>@plt{__sigchar_<signature>}. */
-static bfd_boolean
+static bool
wasm32_leb128 (char **line, int bits, int sign)
{
char *t = input_line_pointer;
/* Read an integer expression and produce an unsigned LEB128 integer,
or a relocation for it. */
-static bfd_boolean
+static bool
wasm32_uleb128 (char **line, int bits)
{
return wasm32_leb128 (line, bits, 0);
/* Read an integer expression and produce a signed LEB128 integer, or
a relocation for it. */
-static bfd_boolean
+static bool
wasm32_sleb128 (char **line, int bits)
{
return wasm32_leb128 (line, bits, 1);
/* Don't replace PLT/GOT relocations with section symbols, so they
don't get an addend. */
-bfd_boolean
+bool
wasm32_fix_adjustable (fixS * fixP)
{
if (fixP->fx_addsy == NULL)
- return TRUE;
+ return true;
if (fixP->fx_r_type == BFD_RELOC_WASM32_LEB128_PLT
|| fixP->fx_r_type == BFD_RELOC_WASM32_LEB128_GOT)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* Generate a reloc for FIXP. */
#define HANDLE_ALIGN(fragP)
-extern bfd_boolean wasm32_fix_adjustable (struct fix *);
+extern bool wasm32_fix_adjustable (struct fix *);
#define tc_fix_adjustable(FIX) wasm32_fix_adjustable (FIX)
/* Type names for blocks and signatures. */
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
valueT
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
int
{
if (((opcode->name[strlen (opcode->name) - 1] == 'l')
&& autoHiLo) || operand.mod == MOD_LOAD_LOW)
- fix_new_exp (frag_now, where, 2, &operand.exp, FALSE,
+ fix_new_exp (frag_now, where, 2, &operand.exp, false,
BFD_RELOC_XGATE_24);
else if (((opcode->name[strlen (opcode->name) - 1]) == 'h'
&& autoHiLo) || operand.mod == MOD_LOAD_HIGH )
- fix_new_exp (frag_now, where, 2, &operand.exp, FALSE,
+ fix_new_exp (frag_now, where, 2, &operand.exp, false,
BFD_RELOC_XGATE_IMM8_HI);
else
as_bad (_("you must use a hi/lo directive or 16-bit macro "
"to load a 16-bit value."));
}
else if (*op_constraint == '5')
- fix_new_exp (frag_now, where, 2, &operand.exp, FALSE,
+ fix_new_exp (frag_now, where, 2, &operand.exp, false,
BFD_RELOC_XGATE_IMM5);
else if (*op_constraint == '4')
- fix_new_exp (frag_now, where, 2, &operand.exp, FALSE,
+ fix_new_exp (frag_now, where, 2, &operand.exp, false,
BFD_RELOC_XGATE_IMM4);
else if (*op_constraint == '3')
- fix_new_exp (frag_now, where, 2, &operand.exp, FALSE,
+ fix_new_exp (frag_now, where, 2, &operand.exp, false,
BFD_RELOC_XGATE_IMM3);
else
as_bad (_(":unknown relocation constraint size"));
if (operand.exp.X_op != O_register)
{
if (*op_constraint == '9')
- fix_new_exp (frag_now, where, 2, &operand.exp, TRUE,
+ fix_new_exp (frag_now, where, 2, &operand.exp, true,
BFD_RELOC_XGATE_PCREL_9);
else if (*op_constraint == 'a')
- fix_new_exp (frag_now, where, 2, &operand.exp, TRUE,
+ fix_new_exp (frag_now, where, 2, &operand.exp, true,
BFD_RELOC_XGATE_PCREL_10);
}
else
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
}
-static bfd_boolean skipping_fptr = FALSE;
+static bool skipping_fptr = false;
void
md_assemble (char * str)
/* Make sure that if we had an erroneous input line which triggered
the skipping_fptr boolean that it does not affect following lines. */
- skipping_fptr = FALSE;
+ skipping_fptr = false;
/* Initialize GAS's cgen interface for a new instruction. */
gas_cgen_init_parse ();
example) might be local symbols and we want the expression
to be evaluated now. This kind of thing can happen when
gcc is generating computed gotos. */
- skipping_fptr = TRUE;
+ skipping_fptr = true;
else if (skipping_fptr)
- skipping_fptr = FALSE;
+ skipping_fptr = false;
else
e->X_op = O_fptr_symbol;
}
/* Return true if a relocation against a symbol may be replaced with
a relocation against section+offset. */
-bfd_boolean
+bool
xstormy16_fix_adjustable (fixS * fixP)
{
/* We need the symbol name for the VTABLE entries. */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
- return FALSE;
+ return false;
if (fixP->fx_r_type == BFD_RELOC_XSTORMY16_FPTR16)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
/* This is a copy of gas_cgen_md_apply_fix, with some enhancements to
const char *
md_atof (int type, char * litP, int * sizeP)
{
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
#define md_apply_fix xstormy16_md_apply_fix
#define tc_fix_adjustable(FIX) xstormy16_fix_adjustable (FIX)
-extern bfd_boolean xstormy16_fix_adjustable (struct fix *);
+extern bool xstormy16_fix_adjustable (struct fix *);
#define TC_FORCE_RELOCATION(fix) xstormy16_force_relocation (fix)
extern int xstormy16_force_relocation (struct fix *);
/* Flags to indicate whether the hardware supports the density and
absolute literals options. */
-bfd_boolean density_supported;
-bfd_boolean absolute_literals_supported;
+bool density_supported;
+bool absolute_literals_supported;
static unsigned microarch_earliest;
/* Some functions are only valid in the front end. This variable
allows us to assert that we haven't crossed over into the
back end. */
-static bfd_boolean past_xtensa_end = FALSE;
+static bool past_xtensa_end = false;
/* Flags for properties of the last instruction in a segment. */
#define FLAG_IS_A0_WRITER 0x1
typedef struct
{
const char *name;
- bfd_boolean can_be_negated;
+ bool can_be_negated;
} directive_infoS;
const directive_infoS directive_info[] =
{
- { "none", FALSE },
- { "literal", FALSE },
- { "density", TRUE },
- { "transform", TRUE },
- { "freeregs", FALSE },
- { "longcalls", TRUE },
- { "literal_prefix", FALSE },
- { "schedule", TRUE },
- { "absolute-literals", TRUE }
+ { "none", false },
+ { "literal", false },
+ { "density", true },
+ { "transform", true },
+ { "freeregs", false },
+ { "longcalls", true },
+ { "literal_prefix", false },
+ { "schedule", true },
+ { "absolute-literals", true }
};
-bfd_boolean directive_state[] =
-{
- FALSE, /* none */
- FALSE, /* literal */
- FALSE, /* density */
- TRUE, /* transform */
- FALSE, /* freeregs */
- FALSE, /* longcalls */
- FALSE, /* literal_prefix */
- FALSE, /* schedule */
- FALSE /* absolute_literals */
+bool directive_state[] =
+{
+ false, /* none */
+ false, /* literal */
+ false, /* density */
+ true, /* transform */
+ false, /* freeregs */
+ false, /* longcalls */
+ false, /* literal_prefix */
+ false, /* schedule */
+ false /* absolute_literals */
};
/* A circular list of all potential and actual literal pool locations
/* Various Other Internal Functions. */
-extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
-static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
+extern bool xg_is_single_relaxable_insn (TInsn *, TInsn *, bool);
+static bool xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
static void xtensa_mark_literal_pool_location (void);
static addressT get_expanded_loop_offset (xtensa_opcode);
static fragS *get_literal_pool_location (segT);
static void set_literal_pool_location (segT, fragS *);
static void xtensa_set_frag_assembly_state (fragS *);
static void finish_vinsn (vliw_insn *);
-static bfd_boolean emit_single_op (TInsn *);
+static bool emit_single_op (TInsn *);
static int total_frag_text_expansion (fragS *);
-static bfd_boolean use_trampolines = TRUE;
+static bool use_trampolines = true;
static void xtensa_check_frag_count (void);
-static void xtensa_create_trampoline_frag (bfd_boolean);
+static void xtensa_create_trampoline_frag (bool);
static void xtensa_maybe_create_trampoline_frag (void);
struct trampoline_frag;
static int init_trampoline_frag (fragS *);
static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset);
-static void xtensa_maybe_create_literal_pool_frag (bfd_boolean, bfd_boolean);
-static bfd_boolean auto_litpools = FALSE;
+static void xtensa_maybe_create_literal_pool_frag (bool, bool);
+static bool auto_litpools = false;
static int auto_litpool_limit = 0;
-static bfd_boolean xtensa_is_init_fini (segT seg);
+static bool xtensa_is_init_fini (segT seg);
/* Alignment Functions. */
static int get_text_align_power (unsigned);
-static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
+static int get_text_align_max_fill_size (int, bool, bool);
static int branch_align_power (segT);
/* Helpers for xtensa_relax_frag(). */
/* Accessors for additional per-subsegment information. */
static unsigned get_last_insn_flags (segT, subsegT);
-static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
+static void set_last_insn_flags (segT, subsegT, unsigned, bool);
static float get_subseg_total_freq (segT, subsegT);
static float get_subseg_target_freq (segT, subsegT);
static void set_subseg_freq (segT, subsegT, float, float);
static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
static void xtensa_restore_emit_state (emit_state *);
-static segT cache_literal_section (bfd_boolean);
+static segT cache_literal_section (bool);
/* op_placement_info functions. */
static void init_op_placement_info_table (void);
-extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
+extern bool opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
static int xg_get_single_size (xtensa_opcode);
static xtensa_format xg_get_single_format (xtensa_opcode);
static int xg_get_single_slot (xtensa_opcode);
/* TInsn and IStack functions. */
-static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
-static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
-static bfd_boolean tinsn_has_complex_operands (const TInsn *);
-static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
-static bfd_boolean tinsn_check_arguments (const TInsn *);
+static bool tinsn_has_symbolic_operands (const TInsn *);
+static bool tinsn_has_invalid_symbolic_operands (const TInsn *);
+static bool tinsn_has_complex_operands (const TInsn *);
+static bool tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
+static bool tinsn_check_arguments (const TInsn *);
static void tinsn_from_chars (TInsn *, char *, int);
static void tinsn_immed_from_frag (TInsn *, fragS *, int);
static int get_num_stack_text_bytes (IStack *);
static int get_num_stack_literal_bytes (IStack *);
-static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf);
+static bool tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf);
/* vliw_insn functions. */
static void xg_init_vinsn (vliw_insn *);
static void xg_copy_vinsn (vliw_insn *, vliw_insn *);
static void xg_clear_vinsn (vliw_insn *);
-static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
+static bool vinsn_has_specific_opcodes (vliw_insn *);
static void xg_free_vinsn (vliw_insn *);
-static bfd_boolean vinsn_to_insnbuf
- (vliw_insn *, char *, fragS *, bfd_boolean);
+static bool vinsn_to_insnbuf
+ (vliw_insn *, char *, fragS *, bool);
static void vinsn_from_chars (vliw_insn *, char *);
/* Expression Utilities. */
-bfd_boolean expr_is_const (const expressionS *);
+bool expr_is_const (const expressionS *);
offsetT get_expr_const (const expressionS *);
void set_expr_const (expressionS *, offsetT);
-bfd_boolean expr_is_register (const expressionS *);
+bool expr_is_register (const expressionS *);
offsetT get_expr_register (const expressionS *);
void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
-bfd_boolean expr_is_equal (expressionS *, expressionS *);
+bool expr_is_equal (expressionS *, expressionS *);
static void copy_expr (expressionS *, const expressionS *);
/* Section renaming. */
\f
/* Command-line Options. */
-bfd_boolean use_literal_section = TRUE;
+bool use_literal_section = true;
enum flix_level produce_flix = FLIX_ALL;
-static bfd_boolean align_targets = TRUE;
-static bfd_boolean warn_unaligned_branch_targets = FALSE;
-static bfd_boolean has_a0_b_retw = FALSE;
-static bfd_boolean workaround_a0_b_retw = FALSE;
-static bfd_boolean workaround_b_j_loop_end = FALSE;
-static bfd_boolean workaround_short_loop = FALSE;
-static bfd_boolean maybe_has_short_loop = FALSE;
-static bfd_boolean workaround_close_loop_end = FALSE;
-static bfd_boolean maybe_has_close_loop_end = FALSE;
-static bfd_boolean enforce_three_byte_loop_align = FALSE;
-static bfd_boolean opt_linkrelax = TRUE;
+static bool align_targets = true;
+static bool warn_unaligned_branch_targets = false;
+static bool has_a0_b_retw = false;
+static bool workaround_a0_b_retw = false;
+static bool workaround_b_j_loop_end = false;
+static bool workaround_short_loop = false;
+static bool maybe_has_short_loop = false;
+static bool workaround_close_loop_end = false;
+static bool maybe_has_close_loop_end = false;
+static bool enforce_three_byte_loop_align = false;
+static bool opt_linkrelax = true;
/* When workaround_short_loops is TRUE, all loops with early exits must
have at least 3 instructions. workaround_all_short_loops is a modifier
workaround_short_loop actions, all straightline loopgtz and loopnez
must have at least 3 instructions. */
-static bfd_boolean workaround_all_short_loops = FALSE;
+static bool workaround_all_short_loops = false;
/* Generate individual property section for every section.
This option is defined in BDF library. */
-extern bfd_boolean elf32xtensa_separate_props;
+extern bool elf32xtensa_separate_props;
/* Xtensa ABI.
This option is defined in BDF library. */
/* Enable all workarounds for pre-T1050.0 hardware. */
if (earliest < 105000 || latest < 105000)
{
- workaround_a0_b_retw |= TRUE;
- workaround_b_j_loop_end |= TRUE;
- workaround_short_loop |= TRUE;
- workaround_close_loop_end |= TRUE;
- workaround_all_short_loops |= TRUE;
- enforce_three_byte_loop_align = TRUE;
+ workaround_a0_b_retw |= true;
+ workaround_b_j_loop_end |= true;
+ workaround_short_loop |= true;
+ workaround_close_loop_end |= true;
+ workaround_all_short_loops |= true;
+ enforce_three_byte_loop_align = true;
}
}
as_warn (_("--no-density option is ignored"));
return 1;
case option_link_relax:
- opt_linkrelax = TRUE;
+ opt_linkrelax = true;
return 1;
case option_no_link_relax:
- opt_linkrelax = FALSE;
+ opt_linkrelax = false;
return 1;
case option_flix:
produce_flix = FLIX_ALL;
as_warn (_("--no-relax is deprecated; use --no-transform instead"));
return md_parse_option (option_no_transform, arg);
case option_longcalls:
- directive_state[directive_longcalls] = TRUE;
+ directive_state[directive_longcalls] = true;
return 1;
case option_no_longcalls:
- directive_state[directive_longcalls] = FALSE;
+ directive_state[directive_longcalls] = false;
return 1;
case option_text_section_literals:
- use_literal_section = FALSE;
+ use_literal_section = false;
return 1;
case option_no_text_section_literals:
- use_literal_section = TRUE;
+ use_literal_section = true;
return 1;
case option_absolute_literals:
if (!absolute_literals_supported)
as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
return 0;
}
- directive_state[directive_absolute_literals] = TRUE;
+ directive_state[directive_absolute_literals] = true;
return 1;
case option_no_absolute_literals:
- directive_state[directive_absolute_literals] = FALSE;
+ directive_state[directive_absolute_literals] = false;
return 1;
case option_workaround_a0_b_retw:
- workaround_a0_b_retw = TRUE;
+ workaround_a0_b_retw = true;
return 1;
case option_no_workaround_a0_b_retw:
- workaround_a0_b_retw = FALSE;
+ workaround_a0_b_retw = false;
return 1;
case option_workaround_b_j_loop_end:
- workaround_b_j_loop_end = TRUE;
+ workaround_b_j_loop_end = true;
return 1;
case option_no_workaround_b_j_loop_end:
- workaround_b_j_loop_end = FALSE;
+ workaround_b_j_loop_end = false;
return 1;
case option_workaround_short_loop:
- workaround_short_loop = TRUE;
+ workaround_short_loop = true;
return 1;
case option_no_workaround_short_loop:
- workaround_short_loop = FALSE;
+ workaround_short_loop = false;
return 1;
case option_workaround_all_short_loops:
- workaround_all_short_loops = TRUE;
+ workaround_all_short_loops = true;
return 1;
case option_no_workaround_all_short_loops:
- workaround_all_short_loops = FALSE;
+ workaround_all_short_loops = false;
return 1;
case option_workaround_close_loop_end:
- workaround_close_loop_end = TRUE;
+ workaround_close_loop_end = true;
return 1;
case option_no_workaround_close_loop_end:
- workaround_close_loop_end = FALSE;
+ workaround_close_loop_end = false;
return 1;
case option_no_workarounds:
- workaround_a0_b_retw = FALSE;
- workaround_b_j_loop_end = FALSE;
- workaround_short_loop = FALSE;
- workaround_all_short_loops = FALSE;
- workaround_close_loop_end = FALSE;
+ workaround_a0_b_retw = false;
+ workaround_b_j_loop_end = false;
+ workaround_short_loop = false;
+ workaround_all_short_loops = false;
+ workaround_close_loop_end = false;
return 1;
case option_align_targets:
- align_targets = TRUE;
+ align_targets = true;
return 1;
case option_no_align_targets:
- align_targets = FALSE;
+ align_targets = false;
return 1;
case option_warn_unaligned_targets:
- warn_unaligned_branch_targets = TRUE;
+ warn_unaligned_branch_targets = true;
return 1;
case option_rename_section_name:
you perform any transformation, always check if transform
is available. If you use the functions we provide for this
purpose, you will be ok. */
- directive_state[directive_transform] = FALSE;
+ directive_state[directive_transform] = false;
return 1;
case option_trampolines:
- use_trampolines = TRUE;
+ use_trampolines = true;
return 1;
case option_no_trampolines:
- use_trampolines = FALSE;
+ use_trampolines = false;
return 1;
case option_auto_litpools:
- auto_litpools = TRUE;
- use_literal_section = FALSE;
+ auto_litpools = true;
+ use_literal_section = false;
if (auto_litpool_limit <= 0)
auto_litpool_limit = MAX_AUTO_POOL_LITERALS / 2;
return 1;
case option_no_auto_litpools:
- auto_litpools = FALSE;
+ auto_litpools = false;
auto_litpool_limit = -1;
return 1;
if (value < 100 || value > 10000)
as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
auto_litpool_limit = value;
- auto_litpools = TRUE;
- use_literal_section = FALSE;
+ auto_litpools = true;
+ use_literal_section = false;
return 1;
}
case option_separate_props:
- elf32xtensa_separate_props = TRUE;
+ elf32xtensa_separate_props = true;
return 1;
case option_no_separate_props:
- elf32xtensa_separate_props = FALSE;
+ elf32xtensa_separate_props = false;
return 1;
case option_abi_windowed:
typedef struct state_stackS_struct
{
directiveE directive;
- bfd_boolean negated;
- bfd_boolean old_state;
+ bool negated;
+ bool old_state;
const char *file;
unsigned int line;
const void *datum;
};
-static bfd_boolean
+static bool
use_transform (void)
{
/* After md_end, you should be checking frag by frag, rather
}
-static bfd_boolean
+static bool
do_align_targets (void)
{
/* Do not use this function after md_end; just look at align_targets
static void
-directive_push (directiveE directive, bfd_boolean negated, const void *datum)
+directive_push (directiveE directive, bool negated, const void *datum)
{
const char *file;
unsigned int line;
static void
directive_pop (directiveE *directive,
- bfd_boolean *negated,
+ bool *negated,
const char **file,
unsigned int *line,
const void **datum)
while (directive_state_stack)
{
directiveE directive;
- bfd_boolean negated;
+ bool negated;
const char *file;
unsigned int line;
const void *datum;
}
-static bfd_boolean
+static bool
inside_directive (directiveE dir)
{
state_stackS *top = directive_state_stack;
static void
-get_directive (directiveE *directive, bfd_boolean *negated)
+get_directive (directiveE *directive, bool *negated)
{
int len;
unsigned i;
const char *directive_string;
if (strncmp (input_line_pointer, "no-", 3) != 0)
- *negated = FALSE;
+ *negated = false;
else
{
- *negated = TRUE;
+ *negated = true;
input_line_pointer += 3;
}
xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
{
directiveE directive;
- bfd_boolean negated;
+ bool negated;
emit_state *state;
lit_state *ls;
xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
{
directiveE begin_directive, end_directive;
- bfd_boolean begin_negated, end_negated;
+ bool begin_negated, end_negated;
const char *file;
unsigned int line;
emit_state *state;
demand_empty_rest_of_line ();
}
-static bfd_boolean is_leb128_expr;
+static bool is_leb128_expr;
static void
xtensa_leb128 (int sign)
{
- is_leb128_expr = TRUE;
+ is_leb128_expr = true;
s_leb128 (sign);
- is_leb128_expr = FALSE;
+ is_leb128_expr = false;
}
\f
/* Find the matching reloc type. */
static bfd_reloc_code_real_type
-map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal)
+map_operator_to_reloc (unsigned char operator, bool is_literal)
{
unsigned int i;
bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
tokenize_arguments (char **args, char *str)
{
char *old_input_line_pointer;
- bfd_boolean saw_comma = FALSE;
- bfd_boolean saw_arg = FALSE;
- bfd_boolean saw_colon = FALSE;
+ bool saw_comma = false;
+ bool saw_arg = false;
+ bool saw_colon = false;
int num_args = 0;
char *arg_end, *arg;
int arg_len;
input_line_pointer++;
if (saw_comma || saw_colon || !saw_arg)
goto err;
- saw_colon = TRUE;
+ saw_colon = true;
break;
case ',':
input_line_pointer++;
if (saw_comma || saw_colon || !saw_arg)
goto err;
- saw_comma = TRUE;
+ saw_comma = true;
break;
default:
input_line_pointer = arg_end;
num_args += 1;
- saw_comma = FALSE;
- saw_colon = FALSE;
- saw_arg = TRUE;
+ saw_comma = false;
+ saw_colon = false;
+ saw_arg = true;
break;
}
}
/* Parse the arguments to an opcode. Return TRUE on error. */
-static bfd_boolean
+static bool
parse_arguments (TInsn *insn, int num_args, char **arg_strings)
{
expressionS *tok, *last_tok;
xtensa_opcode opcode = insn->opcode;
- bfd_boolean had_error = TRUE;
+ bool had_error = true;
xtensa_isa isa = xtensa_default_isa;
int n, num_regs = 0;
int opcode_operand_count;
goto err;
insn->ntok = tok - insn->tok;
- had_error = FALSE;
+ had_error = false;
err:
input_line_pointer = old_input_line_pointer;
xtensa_sysreg sr;
char *opname, *new_opname;
const char *sr_name;
- bfd_boolean has_underbar = FALSE;
+ bool has_underbar = false;
opname = *popname;
if (opname[0] == '_')
{
- has_underbar = TRUE;
+ has_underbar = true;
opname += 1;
}
xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
{
char *opname = *popname;
- bfd_boolean has_underbar = FALSE;
+ bool has_underbar = false;
if (*opname == '_')
{
- has_underbar = TRUE;
+ has_underbar = true;
opname += 1;
}
#endif /* TENSILICA_DEBUG */
-static bfd_boolean
+static bool
is_direct_call_opcode (xtensa_opcode opcode)
{
xtensa_isa isa = xtensa_default_isa;
int n, num_operands;
if (xtensa_opcode_is_call (isa, opcode) != 1)
- return FALSE;
+ return false;
num_operands = xtensa_opcode_num_operands (isa, opcode);
for (n = 0; n < num_operands; n++)
{
if (xtensa_operand_is_register (isa, opcode, n) == 0
&& xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
Returns non-zero on failure. */
static int
-decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
+decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bool *is_alt)
{
if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
&& reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
{
*slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
- *is_alt = FALSE;
+ *is_alt = false;
}
else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
&& reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
{
*slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
- *is_alt = TRUE;
+ *is_alt = true;
}
else
return -1;
when a given option term is true. The meaning of all of the option
terms is given interpretation by this function. */
-static bfd_boolean
+static bool
xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option)
{
if (strcmp (option->option_name, "realnop") == 0
{
/* These conditions were evaluated statically when building the
relaxation table. There's no need to reevaluate them now. */
- return TRUE;
+ return true;
}
else if (strcmp (option->option_name, "FREEREG") == 0)
return insn->extra_arg.X_op == O_register;
}
-static bfd_boolean
+static bool
xg_instruction_matches_or_options (TInsn *insn,
const ReqOrOptionList *or_option)
{
for (option = or_option; option != NULL; option = option->next)
{
if (xg_instruction_matches_option_term (insn, option))
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
{
const ReqOption *req_options;
/* Must match one of the OR clauses. */
if (!xg_instruction_matches_or_options (insn,
req_options->or_option_terms))
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Return the transition rule that matches or NULL if none matches. */
-static bfd_boolean
+static bool
xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
{
PreconditionList *condition_l;
if (rule->opcode != insn->opcode)
- return FALSE;
+ return false;
for (condition_l = rule->conditions;
condition_l != NULL;
{
case OP_EQUAL:
if (get_expr_const (exp1) != cond->op_data)
- return FALSE;
+ return false;
break;
case OP_NOTEQUAL:
if (get_expr_const (exp1) == cond->op_data)
- return FALSE;
+ return false;
break;
default:
- return FALSE;
+ return false;
}
}
else if (expr_is_register (exp1))
{
case OP_EQUAL:
if (get_expr_register (exp1) != cond->op_data)
- return FALSE;
+ return false;
break;
case OP_NOTEQUAL:
if (get_expr_register (exp1) == cond->op_data)
- return FALSE;
+ return false;
break;
default:
- return FALSE;
+ return false;
}
}
else
- return FALSE;
+ return false;
break;
case OP_OPERAND:
{
case OP_EQUAL:
if (!expr_is_equal (exp1, exp2))
- return FALSE;
+ return false;
break;
case OP_NOTEQUAL:
if (expr_is_equal (exp1, exp2))
- return FALSE;
+ return false;
break;
}
break;
case OP_LITERAL:
case OP_LABEL:
default:
- return FALSE;
+ return false;
}
}
if (!xg_instruction_matches_options (insn, rule->options))
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
static int
transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
{
- bfd_boolean a_greater = FALSE;
- bfd_boolean b_greater = FALSE;
+ bool a_greater = false;
+ bool b_greater = false;
ReqOptionList *l_a = a->options;
ReqOptionList *l_b = b->options;
&& strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
{
if (prefer_const16)
- a_greater = TRUE;
+ a_greater = true;
else
- b_greater = TRUE;
+ b_greater = true;
}
else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
&& strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
{
if (prefer_const16)
- b_greater = TRUE;
+ b_greater = true;
else
- a_greater = TRUE;
+ a_greater = true;
}
else
return 0;
\f
/* Various Other Internal Functions. */
-static bfd_boolean
+static bool
is_unique_insn_expansion (TransitionRule *r)
{
if (!r->to_instr || r->to_instr->next != NULL)
- return FALSE;
+ return false;
if (r->to_instr->typ != INSTR_INSTR)
- return FALSE;
- return TRUE;
+ return false;
+ return true;
}
exclude cases like ADDI being "widened" to an ADDMI, which may
later be relaxed to an ADDMI/ADDI pair. */
-bfd_boolean
-xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
+bool
+xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bool narrow_only)
{
TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
TransitionList *l;
<= xg_get_single_size (rule->to_instr->opcode)))
{
if (match)
- return FALSE;
+ return false;
match = rule;
}
}
if (!match)
- return FALSE;
+ return false;
if (targ)
xg_build_to_insn (targ, insn, match->to_instr);
- return TRUE;
+ return true;
}
}
-static bfd_boolean
+static bool
xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
{
int steps_taken = 0;
if (xg_instruction_matches_rule (insn, rule))
{
if (steps_taken == lateral_steps)
- return TRUE;
+ return true;
steps_taken++;
}
}
- return FALSE;
+ return false;
}
}
-static bfd_boolean
+static bool
xg_valid_literal_expression (const expressionS *exp)
{
switch (exp->X_op)
case O_tlsarg:
case O_tpoff:
case O_dtpoff:
- return TRUE;
+ return true;
default:
- return FALSE;
+ return false;
}
}
/* This will check to see if the value can be converted into the
operand type. It will return TRUE if it does not fit. */
-static bfd_boolean
+static bool
xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
{
uint32 valbuf = value;
if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
- return TRUE;
- return FALSE;
+ return true;
+ return false;
}
/* Assumes: All immeds are constants. Check that all constants fit
into their immeds; return FALSE if not. */
-static bfd_boolean
+static bool
xg_immeds_fit (const TInsn *insn)
{
xtensa_isa isa = xtensa_default_isa;
case O_register:
case O_constant:
if (xg_check_operand (exp->X_add_number, insn->opcode, i))
- return FALSE;
+ return false;
break;
default:
/* The symbol should have a fixup associated with it. */
- gas_assert (FALSE);
+ gas_assert (false);
break;
}
}
- return TRUE;
+ return true;
}
/* This should only be called after we have an initial
estimate of the addresses. */
-static bfd_boolean
+static bool
xg_symbolic_immeds_fit (const TInsn *insn,
segT pc_seg,
fragS *pc_frag,
case O_register:
case O_constant:
if (xg_check_operand (exp->X_add_number, insn->opcode, i))
- return FALSE;
+ return false;
break;
case O_lo16:
case O_hi16:
/* Check for the worst case. */
if (xg_check_operand (0xffff, insn->opcode, i))
- return FALSE;
+ return false;
break;
case O_symbol:
If pc_frag == 0, then we don't have frag locations yet. */
if (pc_frag == 0
|| xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
- return FALSE;
+ return false;
/* If it is a weak symbol or a symbol in a different section,
it cannot be known to fit at assembly time. */
&& ! pc_frag->tc_frag_data.use_longcalls
&& (! S_IS_WEAK (exp->X_add_symbol)
|| S_IS_DEFINED (exp->X_add_symbol)))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
symbolP = exp->X_add_symbol;
new_offset = target;
xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
if (xg_check_operand (new_offset, insn->opcode, i))
- return FALSE;
+ return false;
break;
default:
/* The symbol should have a fixup associated with it. */
- return FALSE;
+ return false;
}
}
- return TRUE;
+ return true;
}
/* Return TRUE on success. */
-static bfd_boolean
+static bool
xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
{
BuildOp *op;
op = bi->ops;
targ->opcode = bi->opcode;
targ->insn_type = ITYPE_INSN;
- targ->is_specific_opcode = FALSE;
+ targ->is_specific_opcode = false;
for (; op != NULL; op = op->next)
{
break;
case OP_FREEREG:
if (insn->extra_arg.X_op != O_register)
- return FALSE;
+ return false;
copy_expr (&targ->tok[op_num], &insn->extra_arg);
break;
case OP_LITERAL:
/* For const16 we can create relocations for these. */
if (targ->opcode == XTENSA_UNDEFINED
|| (targ->opcode != xtensa_const16_opcode))
- return FALSE;
+ return false;
gas_assert (op_data < insn->ntok);
/* Need to build a O_lo16 or O_hi16. */
copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
else if (op->typ == OP_OPERAND_LOW16U)
targ->tok[op_num].X_op = O_lo16;
else
- return FALSE;
+ return false;
}
}
break;
targ->tok[op_num].X_add_number = val;
}
else
- return FALSE; /* We cannot use a relocation for this. */
+ return false; /* We cannot use a relocation for this. */
break;
}
gas_assert (0);
op = bi->ops;
targ->opcode = XTENSA_UNDEFINED;
targ->insn_type = ITYPE_LITERAL;
- targ->is_specific_opcode = FALSE;
+ targ->is_specific_opcode = false;
for (; op != NULL; op = op->next)
{
int op_num = op->op_num;
gas_assert (op_data < insn->ntok);
/* We can only pass resolvable literals through. */
if (!xg_valid_literal_expression (&insn->tok[op_data]))
- return FALSE;
+ return false;
copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
break;
case OP_LITERAL:
op = bi->ops;
targ->opcode = XTENSA_UNDEFINED;
targ->insn_type = ITYPE_LABEL;
- targ->is_specific_opcode = FALSE;
+ targ->is_specific_opcode = false;
/* Literal with no ops is a label? */
gas_assert (op == NULL);
break;
gas_assert (0);
}
- return TRUE;
+ return true;
}
/* Return TRUE on success. */
-static bfd_boolean
+static bool
xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
{
for (; bi != NULL; bi = bi->next)
TInsn *next_insn = istack_push_space (istack);
if (!xg_build_to_insn (next_insn, insn, bi))
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* Return TRUE on valid expansion. */
-static bfd_boolean
+static bool
xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
{
int stack_size = istack->ninsn;
/* This is it. Expand the rule to the stack. */
if (!xg_build_to_stack (istack, insn, rule->to_instr))
- return FALSE;
+ return false;
/* Check to see if it fits. */
for (i = stack_size; i < istack->ninsn; i++)
&& !xg_immeds_fit (tinsn))
{
istack->ninsn = stack_size;
- return FALSE;
+ return false;
}
}
- return TRUE;
+ return true;
}
steps_taken++;
}
}
- return FALSE;
+ return false;
}
\f
current_insn = *insn;
/* Walk through all of the single instruction expansions. */
- while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE))
+ while (xg_is_single_relaxable_insn (¤t_insn, &single_target, false))
{
steps_taken++;
if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
enum xtensa_relax_statesE frag_state,
enum xtensa_relax_statesE slot0_state,
int max_growth,
- bfd_boolean is_insn)
+ bool is_insn)
{
/* Finish off this fragment so that it has at LEAST the desired
max_growth. If it doesn't fit in this fragment, close this one
frag_now->fr_opcode = last_insn;
if (is_insn)
- frag_now->tc_frag_data.is_insn = TRUE;
+ frag_now->tc_frag_data.is_insn = true;
frag_var (rs_machine_dependent, max_growth, max_growth,
frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
/* Return TRUE if the target frag is one of the next non-empty frags. */
-static bfd_boolean
+static bool
is_next_frag_target (const fragS *fragP, const fragS *target)
{
if (fragP == NULL)
- return FALSE;
+ return false;
for (; fragP; fragP = fragP->fr_next)
{
if (fragP == target)
- return TRUE;
+ return true;
if (fragP->fr_fix != 0)
- return FALSE;
+ return false;
if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
- return FALSE;
+ return false;
if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
&& ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
- return FALSE;
+ return false;
if (fragP->fr_type == rs_space)
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
{
xtensa_isa isa = xtensa_default_isa;
if (xtensa_opcode_is_branch (isa, insn->opcode) != 1
&& xtensa_opcode_is_jump (isa, insn->opcode) != 1)
- return FALSE;
+ return false;
for (i = 0; i < num_ops; i++)
{
}
}
if (target_op == -1)
- return FALSE;
+ return false;
if (insn->ntok <= target_op)
- return FALSE;
+ return false;
if (insn->tok[target_op].X_op != O_symbol)
- return FALSE;
+ return false;
sym = insn->tok[target_op].X_add_symbol;
if (sym == NULL)
- return FALSE;
+ return false;
if (insn->tok[target_op].X_add_number != 0)
- return FALSE;
+ return false;
target_frag = symbol_get_frag (sym);
if (target_frag == NULL)
- return FALSE;
+ return false;
if (is_next_frag_target (fragP->fr_next, target_frag)
&& S_GET_VALUE (sym) == target_frag->fr_address)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
int i = 1;
if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
&& insn->tok[i].X_op == O_symbol)
- symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
+ symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = true;
return;
}
&& insn->tok[i].X_op == O_symbol)
{
symbolS *sym = insn->tok[i].X_add_symbol;
- symbol_get_tc (sym)->is_branch_target = TRUE;
+ symbol_get_tc (sym)->is_branch_target = true;
if (S_IS_DEFINED (sym))
- symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
+ symbol_get_frag (sym)->tc_frag_data.is_branch_target = true;
}
}
}
/* Return FALSE if no error. */
-static bfd_boolean
+static bool
xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
{
int num_ops = 0;
case INSTR_LABEL_DEF:
abort ();
}
- new_insn->is_specific_opcode = FALSE;
+ new_insn->is_specific_opcode = false;
new_insn->debug_line = old_insn->debug_line;
new_insn->loc_directive_seen = old_insn->loc_directive_seen;
}
new_insn->ntok = num_ops;
- return FALSE;
+ return false;
}
/* Return TRUE if it was simplified. */
-static bfd_boolean
+static bool
xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
{
TransitionRule *rule;
BuildInstr *insn_spec;
if (old_insn->is_specific_opcode || !density_supported)
- return FALSE;
+ return false;
rule = xg_instruction_match (old_insn);
if (rule == NULL)
- return FALSE;
+ return false;
insn_spec = rule->to_instr;
/* There should only be one. */
gas_assert (insn_spec != NULL);
gas_assert (insn_spec->next == NULL);
if (insn_spec->next != NULL)
- return FALSE;
+ return false;
xg_build_token_insn (insn_spec, old_insn, new_insn);
- return TRUE;
+ return true;
}
tokens into the stack or relax it and place multiple
instructions/literals onto the stack. Return FALSE if no error. */
-static bfd_boolean
+static bool
xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
{
int noperands;
TInsn new_insn;
- bfd_boolean do_expand;
+ bool do_expand;
tinsn_init (&new_insn);
orig_insn->ntok,
xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
noperands);
- return TRUE;
+ return true;
}
if (orig_insn->ntok > noperands)
as_warn (ngettext ("found %d operand for '%s': Expected %d",
orig_insn->ntok = noperands;
if (tinsn_has_invalid_symbolic_operands (orig_insn))
- return TRUE;
+ return true;
/* Special case for extui opcode which has constraints not handled
by the ordinary operand encoding checks. The number of operands
if (shiftimm + maskimm > 32)
{
as_bad (_("immediate operands sum to greater than 32"));
- return TRUE;
+ return true;
}
}
so that the assembly scheduler will keep the L32R/CALLX instructions
adjacent. */
if (is_direct_call_opcode (orig_insn->opcode))
- do_expand = FALSE;
+ do_expand = false;
if (tinsn_has_symbolic_operands (orig_insn))
{
now if an operand is "complex" (e.g., difference of symbols) and
will have to be stored as a literal regardless of the value. */
if (!tinsn_has_complex_operands (orig_insn))
- do_expand = FALSE;
+ do_expand = false;
}
else if (xg_immeds_fit (orig_insn))
- do_expand = FALSE;
+ do_expand = false;
if (do_expand)
xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
else
istack_push (istack, orig_insn);
- return FALSE;
+ return false;
}
static int linkonce_len = sizeof (".gnu.linkonce.") - 1;
-static bfd_boolean
+static bool
get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
{
flagword flags, link_once_flags;
emit_state state;
symbolS *lit_sym = NULL;
bfd_reloc_code_real_type reloc;
- bfd_boolean pcrel = FALSE;
+ bool pcrel = false;
char *p;
/* size = 4 for L32R. It could easily be larger when we move to
switch (emit_val->X_op)
{
case O_pcrel:
- pcrel = TRUE;
+ pcrel = true;
/* fall through */
case O_pltrel:
case O_tlsfunc:
case O_dtpoff:
p = frag_more (litsize);
xtensa_set_frag_assembly_state (frag_now);
- reloc = map_operator_to_reloc (emit_val->X_op, TRUE);
+ reloc = map_operator_to_reloc (emit_val->X_op, true);
if (emit_val->X_add_symbol)
emit_val->X_op = O_symbol;
else
lit_saved_frag = frag_now;
frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
- xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
+ xg_finish_frag (0, RELAX_LITERAL, 0, size, false);
/* Go back. */
xtensa_restore_emit_state (&state);
/* Put in a fixup record based on the opcode.
Return TRUE on success. */
-static bfd_boolean
+static bool
xg_add_opcode_fix (TInsn *tinsn,
int opnum,
xtensa_format fmt,
{
as_bad (_("invalid relocation for operand %i of '%s'"),
opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
- return FALSE;
+ return false;
}
/* Handle erroneous "@h" and "@l" expressions here before they propagate
{
as_bad (_("invalid expression for operand %i of '%s'"),
opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
- return FALSE;
+ return false;
}
/* Next try the generic relocs. */
if (reloc == BFD_RELOC_NONE)
{
as_bad (_("invalid relocation in instruction slot %i"), slot);
- return FALSE;
+ return false;
}
howto = bfd_reloc_type_lookup (stdoutput, reloc);
{
as_bad (_("undefined symbol for opcode \"%s\""),
xtensa_opcode_name (xtensa_default_isa, opcode));
- return FALSE;
+ return false;
}
fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
the_fix->tc_fix_data.X_add_number = exp->X_add_number;
the_fix->tc_fix_data.slot = slot;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
xg_emit_insn_to_buf (TInsn *tinsn,
char *buf,
fragS *fragP,
offsetT offset,
- bfd_boolean build_fix)
+ bool build_fix)
{
static xtensa_insnbuf insnbuf = NULL;
- bfd_boolean has_symbolic_immed = FALSE;
- bfd_boolean ok = TRUE;
+ bool has_symbolic_immed = false;
+ bool ok = true;
if (!insnbuf)
insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
expressionS *exp = &tinsn->tok[opnum];
if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset))
- ok = FALSE;
+ ok = false;
}
- fragP->tc_frag_data.is_insn = TRUE;
+ fragP->tc_frag_data.is_insn = true;
xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
(unsigned char *) buf, 0);
return ok;
/* Return TRUE if the instruction can write to the specified
integer register. */
-static bfd_boolean
+static bool
is_register_writer (const TInsn *insn, const char *regset, int regnum)
{
int i;
{
if ((insn->tok[i].X_op == O_register)
&& (insn->tok[i].X_add_number == regnum))
- return TRUE;
+ return true;
}
}
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
is_bad_loopend_opcode (const TInsn *tinsn)
{
xtensa_opcode opcode = tinsn->opcode;
if (opcode == XTENSA_UNDEFINED)
- return FALSE;
+ return false;
if (opcode == xtensa_call0_opcode
|| opcode == xtensa_callx0_opcode
|| opcode == xtensa_retw_n_opcode
|| opcode == xtensa_waiti_opcode
|| opcode == xtensa_rsr_lcount_opcode)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
Also, the assembler generates stabs labels that need
not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
-static bfd_boolean
+static bool
is_unaligned_label (symbolS *sym)
{
const char *name = S_GET_NAME (sym);
if (name
&& name[0] == '.'
&& name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
- return TRUE;
+ return true;
/* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
if (fake_size == 0)
|| name[fake_size] == 'L'
|| (name[fake_size] == 'e'
&& strncmp ("endfunc", name+fake_size, 7) == 0)))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
}
-static bfd_boolean
+static bool
next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
{
xtensa_opcode out_opcode;
const fragS *next_fragP = next_non_empty_frag (fragP);
if (next_fragP == NULL)
- return FALSE;
+ return false;
out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
{
*opcode = out_opcode;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
}
-static bfd_boolean
+static bool
next_frag_is_branch_target (const fragS *fragP)
{
/* Sometimes an empty will end up here due to storage allocation issues,
for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
{
if (fragP->tc_frag_data.is_branch_target)
- return TRUE;
+ return true;
if (fragP->fr_fix != 0)
break;
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
next_frag_is_loop_target (const fragS *fragP)
{
/* Sometimes an empty will end up here due storage allocation issues.
for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
{
if (fragP->tc_frag_data.is_loop_target)
- return TRUE;
+ return true;
if (fragP->fr_fix != 0)
break;
}
- return FALSE;
+ return false;
}
frag_now->tc_frag_data.lit_frchain = frchain_now;
frag_now->tc_frag_data.literal_frag = frag_now;
/* Just record this frag. */
- xtensa_maybe_create_literal_pool_frag (FALSE, FALSE);
+ xtensa_maybe_create_literal_pool_frag (false, false);
frag_variant (rs_machine_dependent, 0, 0,
RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
xtensa_set_frag_assembly_state (frag_now);
xtensa_set_frag_assembly_state (fragS *fragP)
{
if (!density_supported)
- fragP->tc_frag_data.is_no_density = TRUE;
+ fragP->tc_frag_data.is_no_density = true;
/* This function is called from subsegs_finish, which is called
after xtensa_end, so we can't use "use_transform" or
"use_schedule" here. */
if (!directive_state[directive_transform])
- fragP->tc_frag_data.is_no_transform = TRUE;
+ fragP->tc_frag_data.is_no_transform = true;
if (directive_state[directive_longcalls])
- fragP->tc_frag_data.use_longcalls = TRUE;
+ fragP->tc_frag_data.use_longcalls = true;
fragP->tc_frag_data.use_absolute_literals =
directive_state[directive_absolute_literals];
- fragP->tc_frag_data.is_assembly_state_set = TRUE;
+ fragP->tc_frag_data.is_assembly_state_set = true;
}
-static bfd_boolean
+static bool
relaxable_section (asection *sec)
{
return ((sec->flags & SEC_DEBUGGING) == 0
{
while (last_fragP != fragP->fr_next)
{
- last_fragP->tc_frag_data.is_no_transform = TRUE;
+ last_fragP->tc_frag_data.is_no_transform = true;
last_fragP = last_fragP->fr_next;
}
}
}
else
{
- fragP->tc_frag_data.is_assembly_state_set = TRUE;
+ fragP->tc_frag_data.is_assembly_state_set = true;
fragP->tc_frag_data.is_no_density =
last_fragP->tc_frag_data.is_no_density;
fragP->tc_frag_data.is_no_transform =
static xtensa_insnbuf slotbuf = NULL;
xtensa_format fmt;
int slot;
- bfd_boolean alt_reloc;
+ bool alt_reloc;
xtensa_opcode opcode;
char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
forward branch, mark the frag accordingly. Backward branches
are handled by xg_add_branch_and_loop_targets. */
if (symbol_get_tc (sym)->is_branch_target)
- symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
+ symbol_get_frag (sym)->tc_frag_data.is_branch_target = true;
/* Loops only go forward, so they can be identified here. */
if (symbol_get_tc (sym)->is_loop_target)
- symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
+ symbol_get_frag (sym)->tc_frag_data.is_loop_target = true;
dwarf2_emit_label (sym);
}
frag_new (0);
xtensa_set_frag_assembly_state (frag_now);
}
- frag_now->tc_frag_data.is_insn = FALSE;
+ frag_now->tc_frag_data.is_insn = false;
xtensa_clear_insn_labels ();
}
xtensa_isa isa = xtensa_default_isa;
char *opname;
unsigned opnamelen;
- bfd_boolean has_underbar = FALSE;
+ bool has_underbar = false;
char *arg_strings[MAX_INSN_ARGS];
int num_args;
TInsn orig_insn; /* Original instruction from the input. */
/* Check for an underbar prefix. */
if (*opname == '_')
{
- has_underbar = TRUE;
+ has_underbar = true;
opname += 1;
}
&& fragP->fr_offset > 0
&& now_seg != bss_section)
{
- fragP->tc_frag_data.is_align = TRUE;
+ fragP->tc_frag_data.is_align = true;
fragP->tc_frag_data.alignment = fragP->fr_offset;
}
int slot;
xtensa_isa isa = xtensa_default_isa;
valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
- bfd_boolean alt_reloc;
+ bool alt_reloc;
if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
return 0;
nearest macro to where the check needs to take place. FIXME: This
seems wrong. */
-bfd_boolean
+bool
xtensa_check_inside_bundle (void)
{
if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
/* This function must always return FALSE because it is called via a
macro that has nothing to do with bundling. */
- return FALSE;
+ return false;
}
/* tc_fix_adjustable hook */
-bfd_boolean
+bool
xtensa_fix_adjustable (fixS *fixP)
{
/* We need the symbol name for the VTABLE entries. */
case BFD_RELOC_8:
if (fixP->fx_subsy)
{
- bfd_boolean neg = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
- < S_GET_VALUE (fixP->fx_subsy);
+ bool neg = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
+ < S_GET_VALUE (fixP->fx_subsy));
switch (fixP->fx_r_type)
{
}
-bfd_boolean
+bool
resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
{
int i;
int copies_in_use = rt->units[stage + cycle][unit];
int copies = (rt->unit_num_copies) (rt->data, unit);
if (copies_in_use >= copies)
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
write the same state, or access the same tieports. That is
checked by check_t1_t2_reads_and_writes. */
-static bfd_boolean
+static bool
resources_conflict (vliw_insn *vinsn)
{
int i;
/* This is the most common case by far. Optimize it. */
if (vinsn->num_slots == 1)
- return FALSE;
+ return false;
if (rt == NULL)
{
for (i = 0; i < vinsn->num_slots; i++)
{
if (!resources_available (rt, vinsn->slots[i].opcode, 0))
- return TRUE;
+ return true;
reserve_resources (rt, vinsn->slots[i].opcode, 0);
}
- return FALSE;
+ return false;
}
\f
/* finish_vinsn, emit_single_op and helper functions. */
-static bfd_boolean find_vinsn_conflicts (vliw_insn *);
+static bool find_vinsn_conflicts (vliw_insn *);
static xtensa_format xg_find_narrowest_format (vliw_insn *);
static void xg_assemble_vliw_tokens (vliw_insn *);
{
symbolS *lit_sym = NULL;
int j;
- bfd_boolean e = FALSE;
- bfd_boolean saved_density = density_supported;
+ bool e = false;
+ bool saved_density = density_supported;
/* We don't want to narrow ops inside multi-slot bundles. */
if (vinsn->num_slots > 1)
- density_supported = FALSE;
+ density_supported = false;
istack_init (&slotstack);
if (vinsn->slots[i].opcode == xtensa_nop_opcode)
if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
{
- e = TRUE;
+ e = true;
continue;
}
static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
-static bfd_boolean
+static bool
find_vinsn_conflicts (vliw_insn *vinsn)
{
int i, j;
{
TInsn *op1 = &vinsn->slots[i];
if (op1->is_specific_opcode)
- op1->keep_wide = TRUE;
+ op1->keep_wide = true;
else
- op1->keep_wide = FALSE;
+ op1->keep_wide = false;
}
for (i = 0 ; i < vinsn->num_slots; i++)
as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
xtensa_opcode_name (isa, op1->opcode), i,
xtensa_opcode_name (isa, op2->opcode), j);
- return TRUE;
+ return true;
case 'd':
as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
xtensa_opcode_name (isa, op1->opcode), i,
xtensa_opcode_name (isa, op2->opcode), j);
- return TRUE;
+ return true;
case 'e':
as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
xtensa_opcode_name (isa, op1->opcode), i,
xtensa_opcode_name (isa, op2->opcode), j);
- return TRUE;
+ return true;
case 'f':
as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
xtensa_opcode_name (isa, op1->opcode), i,
xtensa_opcode_name (isa, op2->opcode), j);
- return TRUE;
+ return true;
default:
/* Everything is OK. */
break;
if (branches > 1)
{
as_bad (_("multiple branches or jumps in the same bundle"));
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
int t2_states;
int t1_interfaces;
int t2_interfaces;
- bfd_boolean t1_volatile = FALSE;
- bfd_boolean t2_volatile = FALSE;
+ bool t1_volatile = false;
+ bool t2_volatile = false;
/* Check registers. */
for (j = 0; j < t2->ntok; j++)
t2_inout = xtensa_interface_inout (isa, t2_int);
if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
- t2_volatile = TRUE;
+ t2_volatile = true;
for (i = 0; i < t1_interfaces; i++)
{
t1_inout = xtensa_interface_inout (isa, t1_int);
if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
- t1_volatile = TRUE;
+ t1_volatile = true;
if (t1_volatile && t2_volatile && (t1_class == t2_class))
return 'f';
if (!v_copy.slots[slot].keep_wide
&& !v_copy.slots[slot].is_specific_opcode
&& xg_is_single_relaxable_insn (&v_copy.slots[slot],
- &widened, TRUE)
+ &widened, true)
&& opcode_fits_format_slot (widened.opcode,
format, slot))
{
each tinsn in the vinsn. */
static int
-relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag)
+relaxation_requirements (vliw_insn *vinsn, bool *pfinish_frag)
{
- bfd_boolean finish_frag = FALSE;
+ bool finish_frag = false;
int extra_space = 0;
int slot;
{
/* A narrow instruction could be widened later to help
alignment issues. */
- if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
+ if (xg_is_single_relaxable_insn (tinsn, 0, true)
&& !tinsn->is_specific_opcode
&& vinsn->num_slots == 1)
{
{
/* A fix record will be added for this instruction prior
to relaxation, so make it end the frag. */
- finish_frag = TRUE;
+ finish_frag = true;
}
}
}
}
-static bfd_boolean
+static bool
emit_single_op (TInsn *orig_insn)
{
int i;
xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
else
if (xg_expand_assembly_insn (&istack, orig_insn))
- return TRUE;
+ return true;
for (i = 0; i < istack.ninsn; i++)
{
break;
}
}
- return FALSE;
+ return false;
}
static void
xg_assemble_vliw_tokens (vliw_insn *vinsn)
{
- bfd_boolean finish_frag;
- bfd_boolean is_jump = FALSE;
- bfd_boolean is_branch = FALSE;
+ bool finish_frag;
+ bool is_jump = false;
+ bool is_branch = false;
xtensa_isa isa = xtensa_default_isa;
int insn_size;
int extra_space;
char *f = NULL;
int slot;
struct dwarf2_line_info debug_line;
- bfd_boolean loc_directive_seen = FALSE;
+ bool loc_directive_seen = false;
TInsn *tinsn;
memset (&debug_line, 0, sizeof (struct dwarf2_line_info));
&& xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
&& use_transform ())
{
- has_a0_b_retw = TRUE;
+ has_a0_b_retw = true;
/* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
After the first assembly pass we will check all of them and
add a nop if needed. */
- frag_now->tc_frag_data.is_insn = TRUE;
+ frag_now->tc_frag_data.is_insn = true;
frag_var (rs_machine_dependent, 4, 4,
RELAX_ADD_NOP_IF_A0_B_RETW,
frag_now->fr_symbol,
frag_now->fr_offset,
NULL);
xtensa_set_frag_assembly_state (frag_now);
- frag_now->tc_frag_data.is_insn = TRUE;
+ frag_now->tc_frag_data.is_insn = true;
frag_var (rs_machine_dependent, 4, 4,
RELAX_ADD_NOP_IF_A0_B_RETW,
frag_now->fr_symbol,
|| tinsn->debug_line.column < debug_line.column))
debug_line = tinsn->debug_line;
if (tinsn->loc_directive_seen)
- loc_directive_seen = TRUE;
+ loc_directive_seen = true;
}
/* Special cases for instructions that force an alignment... */
target_sym = vinsn->slots[0].tok[1].X_add_symbol;
xtensa_set_frag_assembly_state (frag_now);
- frag_now->tc_frag_data.is_insn = TRUE;
+ frag_now->tc_frag_data.is_insn = true;
max_fill = get_text_align_max_fill_size
(get_text_align_power (xtensa_fetch_width),
- TRUE, frag_now->tc_frag_data.is_no_density);
+ true, frag_now->tc_frag_data.is_no_density);
if (use_transform ())
frag_var (rs_machine_dependent, max_fill, max_fill,
is_bad_loopend_opcode (&vinsn->slots[0]));
}
else
- set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
+ set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, false);
insn_size = xtensa_format_length (isa, vinsn->format);
{
f = frag_more (insn_size + extra_space);
xtensa_set_frag_assembly_state (frag_now);
- frag_now->tc_frag_data.is_insn = TRUE;
+ frag_now->tc_frag_data.is_insn = true;
}
- vinsn_to_insnbuf (vinsn, f, frag_now, FALSE);
+ vinsn_to_insnbuf (vinsn, f, frag_now, false);
if (vinsn->format == XTENSA_UNDEFINED)
return;
if (tinsn->subtype == RELAX_NARROW)
gas_assert (vinsn->num_slots == 1);
if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
- is_jump = TRUE;
+ is_jump = true;
if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
- is_branch = TRUE;
+ is_branch = true;
if (tinsn->subtype || tinsn->symbol || tinsn->offset
|| tinsn->literal_frag || is_jump || is_branch)
- finish_frag = TRUE;
+ finish_frag = true;
}
if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
- frag_now->tc_frag_data.is_specific_opcode = TRUE;
+ frag_now->tc_frag_data.is_specific_opcode = true;
if (finish_frag)
{
{
if (workaround_short_loop && use_transform ())
{
- maybe_has_short_loop = TRUE;
- frag_now->tc_frag_data.is_insn = TRUE;
+ maybe_has_short_loop = true;
+ frag_now->tc_frag_data.is_insn = true;
frag_var (rs_machine_dependent, 4, 4,
RELAX_ADD_NOP_IF_SHORT_LOOP,
frag_now->fr_symbol, frag_now->fr_offset, NULL);
- frag_now->tc_frag_data.is_insn = TRUE;
+ frag_now->tc_frag_data.is_insn = true;
frag_var (rs_machine_dependent, 4, 4,
RELAX_ADD_NOP_IF_SHORT_LOOP,
frag_now->fr_symbol, frag_now->fr_offset, NULL);
loop at least 12 bytes away from another loop's end. */
if (workaround_close_loop_end && use_transform ())
{
- maybe_has_close_loop_end = TRUE;
- frag_now->tc_frag_data.is_insn = TRUE;
+ maybe_has_close_loop_end = true;
+ frag_now->tc_frag_data.is_insn = true;
frag_var (rs_machine_dependent, 12, 12,
RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
frag_now->fr_symbol, frag_now->fr_offset, NULL);
xtensa_set_frag_assembly_state (frag_now);
xtensa_maybe_create_trampoline_frag ();
/* Always create one here. */
- xtensa_maybe_create_literal_pool_frag (TRUE, FALSE);
+ xtensa_maybe_create_literal_pool_frag (true, false);
}
else if (is_branch && do_align_targets ())
{
&& xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
{
float freq = get_subseg_total_freq (now_seg, now_subseg);
- frag_now->tc_frag_data.is_insn = TRUE;
+ frag_now->tc_frag_data.is_insn = true;
frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
frag_now->fr_symbol, frag_now->fr_offset, NULL);
xtensa_set_frag_assembly_state (frag_now);
directive_balance ();
xtensa_flush_pending_output ();
- past_xtensa_end = TRUE;
+ past_xtensa_end = true;
xtensa_move_literals ();
struct trampoline_chain_entry *entry;
size_t n_entries;
size_t n_max;
- bfd_boolean needs_sorting;
+ bool needs_sorting;
};
struct trampoline_chain_index
struct trampoline_chain *entry;
size_t n_entries;
size_t n_max;
- bfd_boolean needs_sorting;
+ bool needs_sorting;
};
struct trampoline_index
if (++unreachable_count > 10)
{
- xtensa_create_trampoline_frag (FALSE);
+ xtensa_create_trampoline_frag (false);
clear_frag_count ();
unreachable_count = 0;
}
if (get_frag_count () > 8000)
{
- xtensa_create_trampoline_frag (TRUE);
+ xtensa_create_trampoline_frag (true);
clear_frag_count ();
unreachable_count = 0;
}
/* We create an area for a possible literal pool every N (default 5000)
frags or so. */
- xtensa_maybe_create_literal_pool_frag (TRUE, TRUE);
+ xtensa_maybe_create_literal_pool_frag (true, true);
}
static xtensa_insnbuf trampoline_buf = NULL;
}
static void
-xtensa_create_trampoline_frag (bfd_boolean needs_jump_around)
+xtensa_create_trampoline_frag (bool needs_jump_around)
{
/* Emit a frag where we can place intermediate jump instructions,
in case we need to jump farther than 128K bytes.
xg_add_trampoline_to_seg (ts, fragP);
}
-static bfd_boolean xg_is_trampoline_frag_full (const fragS *fragP)
+static bool xg_is_trampoline_frag_full (const fragS *fragP)
{
return fragP->fr_var < 3;
}
{
qsort (tc->entry, tc->n_entries, sizeof (*tc->entry),
xg_order_trampoline_chain_entry);
- tc->needs_sorting = FALSE;
+ tc->needs_sorting = false;
}
/* Find entry index in the given chain with maximal address <= source. */
{
qsort (idx->entry, idx->n_entries, sizeof (*idx->entry),
xg_order_trampoline_chain);
- idx->needs_sorting = FALSE;
+ idx->needs_sorting = false;
}
c.target.sym = sym;
c.target.offset = offset;
e->sym = sym;
e->offset = offset;
++tc->n_entries;
- tc->needs_sorting = TRUE;
+ tc->needs_sorting = true;
}
static struct trampoline_chain *
xg_add_location_to_chain (tc, sym, offset);
++idx->n_entries;
- idx->needs_sorting = TRUE;
+ idx->needs_sorting = true;
return tc;
}
}
static void
-xtensa_maybe_create_literal_pool_frag (bfd_boolean create,
- bfd_boolean only_if_needed)
+xtensa_maybe_create_literal_pool_frag (bool create, bool only_if_needed)
{
struct litpool_seg *lps = litpool_seg_list.next;
fragS *fragP;
struct litpool_frag *lpf;
- bfd_boolean needed = FALSE;
+ bool needed = false;
if (use_literal_section || !auto_litpools)
return;
}
else if (lps->frag_count > auto_litpool_limit)
{
- needed = TRUE;
+ needed = true;
}
else
{
}
else
{
- needed = TRUE;
+ needed = true;
}
}
frag_wane (fragP);
if (fragP->fr_type == rs_machine_dependent
&& fragP->fr_subtype == RELAX_UNREACHABLE)
- fragP->tc_frag_data.is_unreachable = TRUE;
+ fragP->tc_frag_data.is_unreachable = true;
}
}
}
}
-static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
+static bool is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
static void
xtensa_mark_narrow_branches (void)
static offsetT unrelaxed_frag_max_size (fragS *);
-static bfd_boolean
+static bool
is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
{
const expressionS *exp = &tinsn->tok[1];
fragS *target_frag;
if (exp->X_op != O_symbol)
- return FALSE;
+ return false;
target_frag = symbol_get_frag (symbolP);
max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
if (is_branch_jmp_to_next (tinsn, fragP))
- return FALSE;
+ return false;
/* The branch doesn't branch over it's own frag,
but over the subsequent ones. */
fragP = fragP->fr_next;
}
if (max_distance <= MAX_IMMED6 && fragP == target_frag)
- return TRUE;
- return FALSE;
+ return true;
+ return false;
}
zero-cost loop instruction is the last in a section. */
if (targ_frag)
{
- targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
+ targ_frag->tc_frag_data.is_first_loop_insn = true;
/* Do not widen a frag that is the first instruction of a
zero-cost loop. It makes that loop harder to align. */
if (targ_frag->fr_type == rs_machine_dependent
conditional branch or a retw/retw.n, convert this frag to one that
will generate a NOP. In any case close it off with a .fill 0. */
-static bfd_boolean next_instrs_are_b_retw (fragS *);
+static bool next_instrs_are_b_retw (fragS *);
static void
xtensa_fix_a0_b_retw_frags (void)
}
-static bfd_boolean
+static bool
next_instrs_are_b_retw (fragS *fragP)
{
xtensa_opcode opcode;
xtensa_isa isa = xtensa_default_isa;
unsigned int offset = 0;
int slot;
- bfd_boolean branch_seen = FALSE;
+ bool branch_seen = false;
if (!insnbuf)
{
}
if (next_fragP == NULL)
- return FALSE;
+ return false;
/* Check for the conditional branch. */
xtensa_insnbuf_from_chars
(isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
fmt = xtensa_format_decode (isa, insnbuf);
if (fmt == XTENSA_UNDEFINED)
- return FALSE;
+ return false;
for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
{
}
if (!branch_seen)
- return FALSE;
+ return false;
offset += xtensa_format_length (isa, fmt);
if (offset == next_fragP->fr_fix)
}
if (next_fragP == NULL)
- return FALSE;
+ return false;
/* Check for the retw/retw.n. */
xtensa_insnbuf_from_chars
have no problems. */
if (fmt == XTENSA_UNDEFINED
|| xtensa_format_num_slots (isa, fmt) != 1)
- return FALSE;
+ return false;
xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
loop end label, convert this frag to one that will generate a NOP.
In any case close it off with a .fill 0. */
-static bfd_boolean next_instr_is_loop_end (fragS *);
+static bool next_instr_is_loop_end (fragS *);
static void
xtensa_fix_b_j_loop_end_frags (void)
}
-static bfd_boolean
+static bool
next_instr_is_loop_end (fragS *fragP)
{
const fragS *next_fragP;
if (next_frag_is_loop_target (fragP))
- return FALSE;
+ return false;
next_fragP = next_non_empty_frag (fragP);
if (next_fragP == NULL)
- return FALSE;
+ return false;
if (!next_frag_is_loop_target (next_fragP))
- return FALSE;
+ return false;
/* If the size is >= 3 then there is more than one instruction here.
The hardware bug will not fire. */
if (next_fragP->fr_fix > 3)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
then convert this frag (and maybe the next one) to generate a NOP.
In any case close it off with a .fill 0. */
-static int count_insns_to_loop_end (fragS *, bfd_boolean, int);
-static bfd_boolean branch_before_loop_end (fragS *);
+static int count_insns_to_loop_end (fragS *, bool, int);
+static bool branch_before_loop_end (fragS *);
static void
xtensa_fix_short_loop_frags (void)
if (fragP->fr_type == rs_machine_dependent
&& fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
{
- if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
+ if (count_insns_to_loop_end (fragP->fr_next, true, 3) < 3
&& (branch_before_loop_end (fragP->fr_next)
|| (workaround_all_short_loops
&& current_opcode != XTENSA_UNDEFINED
static int
count_insns_to_loop_end (fragS *base_fragP,
- bfd_boolean count_relax_add,
+ bool count_relax_add,
int max_count)
{
fragS *fragP = NULL;
}
-static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
+static bool unrelaxed_frag_has_b_j (fragS *);
-static bfd_boolean
+static bool
branch_before_loop_end (fragS *base_fragP)
{
fragS *fragP;
fragP = fragP->fr_next)
{
if (unrelaxed_frag_has_b_j (fragP))
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
unrelaxed_frag_has_b_j (fragS *fragP)
{
static xtensa_insnbuf insnbuf = NULL;
unsigned int offset = 0;
if (!fragP->tc_frag_data.is_insn)
- return FALSE;
+ return false;
if (!insnbuf)
insnbuf = xtensa_insnbuf_alloc (isa);
(isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
fmt = xtensa_format_decode (isa, insnbuf);
if (fmt == XTENSA_UNDEFINED)
- return FALSE;
+ return false;
for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
{
get_opcode_from_buf (fragP->fr_literal + offset, slot);
if (xtensa_opcode_is_branch (isa, opcode) == 1
|| xtensa_opcode_is_jump (isa, opcode) == 1)
- return TRUE;
+ return true;
}
offset += xtensa_format_length (isa, fmt);
}
- return FALSE;
+ return false;
}
/* Checks to be made after initial assembly but before relaxation. */
-static bfd_boolean is_empty_loop (const TInsn *, fragS *);
-static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
+static bool is_empty_loop (const TInsn *, fragS *);
+static bool is_local_forward_loop (const TInsn *, fragS *);
static void
xtensa_sanity_check (void)
/* Return TRUE if the loop target is the next non-zero fragment. */
-static bfd_boolean
+static bool
is_empty_loop (const TInsn *insn, fragS *fragP)
{
const expressionS *exp;
fragS *next_fragP;
if (insn->insn_type != ITYPE_INSN)
- return FALSE;
+ return false;
if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
- return FALSE;
+ return false;
if (insn->ntok <= LOOP_IMMED_OPN)
- return FALSE;
+ return false;
exp = &insn->tok[LOOP_IMMED_OPN];
if (exp->X_op != O_symbol)
- return FALSE;
+ return false;
symbolP = exp->X_add_symbol;
if (!symbolP)
- return FALSE;
+ return false;
if (symbol_get_frag (symbolP) == NULL)
- return FALSE;
+ return false;
if (S_GET_VALUE (symbolP) != 0)
- return FALSE;
+ return false;
/* Walk through the zero-size fragments from this one. If we find
the target fragment, then this is a zero-size loop. */
next_fragP = next_fragP->fr_next)
{
if (next_fragP == symbol_get_frag (symbolP))
- return TRUE;
+ return true;
if (next_fragP->fr_fix != 0)
- return FALSE;
+ return false;
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
is_local_forward_loop (const TInsn *insn, fragS *fragP)
{
const expressionS *exp;
fragS *next_fragP;
if (insn->insn_type != ITYPE_INSN)
- return FALSE;
+ return false;
if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
- return FALSE;
+ return false;
if (insn->ntok <= LOOP_IMMED_OPN)
- return FALSE;
+ return false;
exp = &insn->tok[LOOP_IMMED_OPN];
if (exp->X_op != O_symbol)
- return FALSE;
+ return false;
symbolP = exp->X_add_symbol;
if (!symbolP)
- return FALSE;
+ return false;
if (symbol_get_frag (symbolP) == NULL)
- return FALSE;
+ return false;
/* Walk through fragments until we find the target.
If we do not find the target, then this is an invalid loop. */
next_fragP = next_fragP->fr_next)
{
if (next_fragP == symbol_get_frag (symbolP))
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
#define XTINFO_NAME "Xtensa_Info"
static int
get_text_align_max_fill_size (int align_pow,
- bfd_boolean use_nops,
- bfd_boolean use_no_density)
+ bool use_nops,
+ bool use_no_density)
{
if (!use_nops)
return (1 << align_pow);
get_text_align_fill_size (addressT address,
int align_pow,
int target_size,
- bfd_boolean use_nops,
- bfd_boolean use_no_density)
+ bool use_nops,
+ bool use_no_density)
{
addressT alignment, fill, fill_limit, fill_step;
- bfd_boolean skip_one = FALSE;
+ bool skip_one = false;
alignment = (1 << align_pow);
gas_assert (target_size > 0 && alignment >= (addressT) target_size);
/* Combine 2- and 3-byte NOPs to fill anything larger than one. */
fill_limit = alignment * 2;
fill_step = 1;
- skip_one = TRUE;
+ skip_one = true;
}
else
{
/* This will assert if it is not possible. */
static int
-get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density)
+get_text_align_nop_count (offsetT fill_size, bool use_no_density)
{
int count = 0;
static int
get_text_align_nth_nop_size (offsetT fill_size,
int n,
- bfd_boolean use_no_density)
+ bool use_no_density)
{
int count = 0;
int align_power;
fragS *first_insn;
xtensa_opcode opcode;
- bfd_boolean is_loop;
+ bool is_loop;
gas_assert (fragP->fr_type == rs_machine_dependent);
gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
record_alignment (now_seg, align_power);
fill_size = get_text_align_fill_size
- (address + pre_opcode_bytes, align_power, first_insn_size, TRUE,
+ (address + pre_opcode_bytes, align_power, first_insn_size, true,
fragP->tc_frag_data.is_no_density);
return address + fill_size;
addressT target_address, loop_insn_offset;
int target_size;
xtensa_opcode loop_opcode;
- bfd_boolean is_loop;
+ bool is_loop;
int align_power;
offsetT opt_diff;
offsetT branch_align;
if (target_size > branch_align)
target_size = branch_align;
opt_diff = get_text_align_fill_size (address, align_power,
- target_size, FALSE, FALSE);
+ target_size, false, false);
*max_diff = (opt_diff + branch_align
- (target_size + ((address + opt_diff) % branch_align)));
address + loop_insn_offset + xg_get_single_size (loop_opcode);
align_power = get_text_align_power (target_size);
opt_diff = get_text_align_fill_size (target_address, align_power,
- target_size, FALSE, FALSE);
+ target_size, false, false);
*max_diff = xtensa_fetch_width
- ((target_address + opt_diff) % xtensa_fetch_width)
static long relax_frag_loop_align (fragS *, long);
static long relax_frag_for_align (fragS *, long);
static long relax_frag_immed
- (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
+ (segT, fragS *, long, int, xtensa_format, int, int *, bool);
/* Get projected address for the first fulcrum on a path from source to
target. */
fixP->tc_fix_data.X_add_symbol = trampoline_frag->fr_symbol;
fixP->tc_fix_data.X_add_number = trampoline_frag->fr_fix - 3;
- trampoline_frag->tc_frag_data.relax_seen = FALSE;
+ trampoline_frag->tc_frag_data.relax_seen = false;
if (xg_is_trampoline_frag_full (trampoline_frag))
xg_remove_trampoline_from_index (idx, tr);
return newfixP;
}
-static bfd_boolean xg_is_relaxable_fixup (fixS *fixP)
+static bool xg_is_relaxable_fixup (fixS *fixP)
{
xtensa_isa isa = xtensa_default_isa;
addressT addr = fixP->fx_frag->fr_address;
if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP ||
fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP)
- return FALSE;
+ return false;
target = S_GET_VALUE (s) + fixP->fx_offset;
delta = target - addr;
if (labs (delta) < J_RANGE - J_MARGIN)
- return FALSE;
+ return false;
xtensa_insnbuf_from_chars (isa, trampoline_buf,
(unsigned char *) fixP->fx_frag->fr_literal +
new_stretch += relax_frag_immed
(now_seg, fragP, stretch,
fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
- fmt, slot, stretched_p, FALSE);
+ fmt, slot, stretched_p, false);
break;
default:
litpool_slotbuf = xtensa_insnbuf_alloc (isa);
}
new_stretch += 3;
- fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */
- fragP->tc_frag_data.is_insn = TRUE;
+ fragP->tc_frag_data.relax_seen = false; /* Need another pass. */
+ fragP->tc_frag_data.is_insn = true;
tinsn_init (&insn);
insn.insn_type = ITYPE_INSN;
insn.opcode = xtensa_j_opcode;
fragP->fr_fix += 3;
fragP->fr_var -= 3;
/* Add a fix-up. */
- fix_new (fragP, 0, 3, fragP->fr_symbol, 0, TRUE,
+ fix_new (fragP, 0, 3, fragP->fr_symbol, 0, true,
BFD_RELOC_XTENSA_SLOT0_OP);
}
break;
/* Tell gas we need another relaxation pass. */
if (! fragP->tc_frag_data.relax_seen)
{
- fragP->tc_frag_data.relax_seen = TRUE;
+ fragP->tc_frag_data.relax_seen = true;
*stretched_p = 1;
}
char *nop_buf = fragP->fr_literal + fragP->fr_fix;
int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
assemble_nop (length, nop_buf);
- fragP->tc_frag_data.is_insn = TRUE;
+ fragP->tc_frag_data.is_insn = true;
if (fragP->fr_var < length)
{
int *wide_nops,
int *narrow_nops,
int *widens,
- bfd_boolean *paddable)
+ bool *paddable)
{
fragS *fragP = *fragPP;
addressT address = fragP->fr_address;
switch (fragP->fr_subtype)
{
case RELAX_UNREACHABLE:
- *paddable = TRUE;
+ *paddable = true;
break;
case RELAX_FILL_NOP:
int num_widens = 0;
int wide_nops = 0;
int narrow_nops = 0;
- bfd_boolean paddable = FALSE;
+ bool paddable = false;
offsetT local_opt_diff;
offsetT opt_diff;
offsetT max_diff;
int glob_widens = 0;
int dnn = 0;
int dw = 0;
- bfd_boolean glob_pad = 0;
+ bool glob_pad = 0;
address = find_address_of_next_align_frag
(&fragP, &glob_widens, &dnn, &dw, &glob_pad);
/* If there is a padable portion, then skip. */
xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf);
xtensa_insnbuf_to_chars (isa, trampoline_buf,
(unsigned char *)fragP->fr_literal + fragP->fr_fix, 3);
- fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, TRUE,
+ fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, true,
BFD_RELOC_XTENSA_SLOT0_OP);
fixP->tc_fix_data.slot = 0;
xtensa_format fmt,
int slot,
int *stretched_p,
- bfd_boolean estimate_only)
+ bool estimate_only)
{
TInsn tinsn;
int old_size;
- bfd_boolean negatable_branch = FALSE;
- bfd_boolean branch_jmp_to_next = FALSE;
- bfd_boolean from_wide_insn = FALSE;
+ bool negatable_branch = false;
+ bool branch_jmp_to_next = false;
+ bool from_wide_insn = false;
xtensa_isa isa = xtensa_default_isa;
IStack istack;
offsetT frag_offset;
xg_clear_vinsn (&cur_vinsn);
vinsn_from_chars (&cur_vinsn, fragP->fr_opcode);
if (cur_vinsn.num_slots > 1)
- from_wide_insn = TRUE;
+ from_wide_insn = true;
tinsn = cur_vinsn.slots[slot];
tinsn_immed_from_frag (&tinsn, fragP, slot);
fixP = add_jump_to_trampoline (tf, fragP);
xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol,
fixP->fx_where);
- fragP->tc_frag_data.relax_seen = FALSE;
+ fragP->tc_frag_data.relax_seen = false;
}
else
{
convert_frag_align_next_opcode (fragS *fragp)
{
char *nop_buf; /* Location for Writing. */
- bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
+ bool use_no_density = fragp->tc_frag_data.is_no_density;
addressT aligned_address;
offsetT fill_size;
int nop, nop_count;
tinsn_init (&single_target);
frag_offset = fragP->fr_opcode - fragP->fr_literal;
- if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
+ if (! xg_is_single_relaxable_insn (&tinsn, &single_target, false))
{
as_bad (_("unable to widen instruction"));
return;
size = xg_get_single_size (single_target.opcode);
xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP,
- frag_offset, TRUE);
+ frag_offset, true);
diff = size - old_size;
gas_assert (diff >= 0);
return;
}
assemble_nop (size, loc);
- fragP->tc_frag_data.is_insn = TRUE;
+ fragP->tc_frag_data.is_insn = true;
fragP->fr_var -= size;
fragP->fr_fix += size;
frag_wane (fragP);
{
char *immed_instr = fragP->fr_opcode;
TInsn orig_tinsn;
- bfd_boolean expanded = FALSE;
- bfd_boolean branch_jmp_to_next = FALSE;
+ bool expanded = false;
+ bool branch_jmp_to_next = false;
char *fr_opcode = fragP->fr_opcode;
xtensa_isa isa = xtensa_default_isa;
- bfd_boolean from_wide_insn = FALSE;
+ bool from_wide_insn = false;
int bytes;
- bfd_boolean is_loop;
+ bool is_loop;
gas_assert (fr_opcode != NULL);
vinsn_from_chars (&cur_vinsn, fr_opcode);
if (cur_vinsn.num_slots > 1)
- from_wide_insn = TRUE;
+ from_wide_insn = true;
orig_tinsn = cur_vinsn.slots[slot];
tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
build_nop (&cur_vinsn.slots[0], bytes);
fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
}
- vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE);
+ vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, true);
xtensa_insnbuf_to_chars
(isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
fragP->fr_var = 0;
int diff;
symbolS *gen_label = NULL;
offsetT frag_offset;
- bfd_boolean first = TRUE;
+ bool first = true;
/* It does not fit. Find something that does and
convert immediately. */
if (first && from_wide_insn)
{
target_offset += xtensa_format_length (isa, fmt);
- first = FALSE;
+ first = false;
if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
target_offset += xg_get_single_size (tinsn->opcode);
}
}
total_size = 0;
- first = TRUE;
+ first = true;
for (i = 0; i < istack.ninsn; i++)
{
TInsn *tinsn = &istack.insn[i];
/* Add a fixup. */
target_seg = S_GET_SEGMENT (lit_sym);
gas_assert (target_seg);
- reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE);
+ reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, true);
fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
- &tinsn->tok[0], FALSE, reloc_type);
+ &tinsn->tok[0], false, reloc_type);
break;
case ITYPE_LABEL:
xg_resolve_literals (tinsn, lit_sym);
if (from_wide_insn && first)
{
- first = FALSE;
+ first = false;
if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
{
cur_vinsn.slots[slot] = *tinsn;
xtensa_format_slot_nop_opcode (isa, fmt, slot);
cur_vinsn.slots[slot].ntok = 0;
}
- vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE);
+ vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, true);
xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf,
(unsigned char *) immed_instr, 0);
- fragP->tc_frag_data.is_insn = TRUE;
+ fragP->tc_frag_data.is_insn = true;
size = xtensa_format_length (isa, fmt);
if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
{
xg_emit_insn_to_buf
(tinsn, immed_instr + size, fragP,
- immed_instr - fragP->fr_literal + size, TRUE);
+ immed_instr - fragP->fr_literal + size, true);
size += xg_get_single_size (tinsn->opcode);
}
}
{
size = xg_get_single_size (tinsn->opcode);
xg_emit_insn_to_buf (tinsn, immed_instr, fragP,
- immed_instr - fragP->fr_literal, TRUE);
+ immed_instr - fragP->fr_literal, true);
}
immed_instr += size;
total_size += size;
diff = total_size - old_size;
gas_assert (diff >= 0);
if (diff != 0)
- expanded = TRUE;
+ expanded = true;
gas_assert (diff <= fragP->fr_var);
fragP->fr_var -= diff;
fragP->fr_fix += diff;
{
/* Add an expansion note on the expanded instruction. */
fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
- &orig_tinsn.tok[0], TRUE,
+ &orig_tinsn.tok[0], true,
BFD_RELOC_XTENSA_ASM_EXPAND);
}
}
set_last_insn_flags (segT seg,
subsegT subseg,
unsigned fl,
- bfd_boolean val)
+ bool val)
{
subseg_map *subseg_e = get_subseg_info (seg, subseg);
if (! subseg_e)
return lp;
}
-static bfd_boolean xtensa_is_init_fini (segT seg)
+static bool xtensa_is_init_fini (segT seg)
{
if (!seg)
return 0;
search_frag = frchain_from->frch_root;
while (search_frag)
{
- search_frag->tc_frag_data.is_literal = TRUE;
+ search_frag->tc_frag_data.is_literal = true;
search_frag = search_frag->fr_next;
}
segment = segment->next;
{
if (directive_state[directive_absolute_literals])
{
- segT lit4_seg = cache_literal_section (TRUE);
+ segT lit4_seg = cache_literal_section (true);
xtensa_switch_section_emit_state (result, lit4_seg, 0);
}
else
{
fragS *pool_location = get_literal_pool_location (now_seg);
segT lit_seg;
- bfd_boolean is_init_fini = xtensa_is_init_fini (now_seg);
+ bool is_init_fini = xtensa_is_init_fini (now_seg);
if (pool_location == NULL
&& !use_literal_section
{
as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
}
- xtensa_maybe_create_literal_pool_frag (TRUE, TRUE);
+ xtensa_maybe_create_literal_pool_frag (true, true);
pool_location = get_literal_pool_location (now_seg);
}
- lit_seg = cache_literal_section (FALSE);
+ lit_seg = cache_literal_section (false);
xtensa_switch_section_emit_state (result, lit_seg, 0);
if (!use_literal_section
/* Predicate function used to look up a section in a particular group. */
-static bfd_boolean
+static bool
match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
{
const char *gname = inf;
The result may be cached in the default_lit_sections structure. */
static segT
-cache_literal_section (bfd_boolean use_abs_literals)
+cache_literal_section (bool use_abs_literals)
{
const char *text_name, *group_name = 0;
const char *base_name, *suffix;
segT *pcached;
segT seg, current_section;
int current_subsec;
- bfd_boolean linkonce = FALSE;
+ bool linkonce = false;
/* Save the current section/subsection. */
current_section = now_seg;
name = concat (".gnu.linkonce", base_name, suffix ? suffix : "",
(char *) NULL);
- linkonce = TRUE;
+ linkonce = true;
}
else
{
#define XTENSA_LIT_SEC_NAME ".xt.lit"
#define XTENSA_PROP_SEC_NAME ".xt.prop"
-typedef bfd_boolean (*frag_predicate) (const fragS *);
+typedef bool (*frag_predicate) (const fragS *);
typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
-static bfd_boolean get_frag_is_literal (const fragS *);
+static bool get_frag_is_literal (const fragS *);
static void xtensa_create_property_segments
(frag_predicate, frag_predicate, const char *, xt_section_type);
static void xtensa_create_xproperty_segments
(frag_flags_fn, const char *, xt_section_type);
-static bfd_boolean exclude_section_from_property_tables (segT);
-static bfd_boolean section_has_property (segT, frag_predicate);
-static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
+static bool exclude_section_from_property_tables (segT);
+static bool section_has_property (segT, frag_predicate);
+static bool section_has_xproperty (segT, frag_flags_fn);
static void add_xt_block_frags
(segT, xtensa_block_info **, frag_predicate, frag_predicate);
-static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
+static bool xtensa_frag_flags_is_empty (const frag_flags *);
static void xtensa_frag_flags_init (frag_flags *);
static void get_frag_property_flags (const fragS *, frag_flags *);
static flagword frag_flags_to_number (const frag_flags *);
/* This function is only meaningful after xtensa_move_literals. */
-static bfd_boolean
+static bool
get_frag_is_literal (const fragS *fragP)
{
gas_assert (fragP != NULL);
fix = fix_new (frag_now, i * 8, 4,
section_symbol (cur_block->sec),
cur_block->offset,
- FALSE, BFD_RELOC_32);
+ false, BFD_RELOC_32);
fix->fx_file = "<internal>";
fix->fx_line = 0;
fix = fix_new (frag_now, i * 12, 4,
section_symbol (cur_block->sec),
cur_block->offset,
- FALSE, BFD_RELOC_32);
+ false, BFD_RELOC_32);
fix->fx_file = "<internal>";
fix->fx_line = 0;
}
-static bfd_boolean
+static bool
exclude_section_from_property_tables (segT sec)
{
flagword flags = bfd_section_flags (sec);
if ((flags & SEC_DEBUGGING)
|| !(flags & SEC_ALLOC)
|| (flags & SEC_MERGE))
- return TRUE;
+ return true;
/* Linker cie and fde optimizations mess up property entries for
eh_frame sections, but there is nothing inside them relevant to
property tables anyway. */
if (strcmp (sec->name, ".eh_frame") == 0)
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
section_has_property (segT sec, frag_predicate property_function)
{
segment_info_type *seginfo = seg_info (sec);
{
if (property_function (fragP)
&& (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
-static bfd_boolean
+static bool
section_has_xproperty (segT sec, frag_flags_fn property_function)
{
segment_info_type *seginfo = seg_info (sec);
frag_flags prop_flags;
property_function (fragP, &prop_flags);
if (!xtensa_frag_flags_is_empty (&prop_flags))
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Break the encapsulation of add_xt_prop_frags here. */
-static bfd_boolean
+static bool
xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
{
if (prop_flags->is_literal
|| prop_flags->is_insn
|| prop_flags->is_data
|| prop_flags->is_unreachable)
- return FALSE;
- return TRUE;
+ return false;
+ return true;
}
{
xtensa_frag_flags_init (prop_flags);
if (fragP->tc_frag_data.is_literal)
- prop_flags->is_literal = TRUE;
+ prop_flags->is_literal = true;
if (fragP->tc_frag_data.is_specific_opcode
|| fragP->tc_frag_data.is_no_transform)
{
- prop_flags->is_no_transform = TRUE;
+ prop_flags->is_no_transform = true;
if (xtensa_frag_flags_is_empty (prop_flags))
- prop_flags->is_data = TRUE;
+ prop_flags->is_data = true;
}
if (fragP->tc_frag_data.is_unreachable)
- prop_flags->is_unreachable = TRUE;
+ prop_flags->is_unreachable = true;
else if (fragP->tc_frag_data.is_insn)
{
- prop_flags->is_insn = TRUE;
+ prop_flags->is_insn = true;
if (fragP->tc_frag_data.is_loop_target)
- prop_flags->insn.is_loop_target = TRUE;
+ prop_flags->insn.is_loop_target = true;
if (fragP->tc_frag_data.is_branch_target)
- prop_flags->insn.is_branch_target = TRUE;
+ prop_flags->insn.is_branch_target = true;
if (fragP->tc_frag_data.is_no_density)
- prop_flags->insn.is_no_density = TRUE;
+ prop_flags->insn.is_no_density = true;
if (fragP->tc_frag_data.use_absolute_literals)
- prop_flags->insn.is_abslit = TRUE;
+ prop_flags->insn.is_abslit = true;
}
if (fragP->tc_frag_data.is_align)
{
- prop_flags->is_align = TRUE;
+ prop_flags->is_align = true;
prop_flags->alignment = fragP->tc_frag_data.alignment;
if (xtensa_frag_flags_is_empty (prop_flags))
- prop_flags->is_data = TRUE;
+ prop_flags->is_data = true;
}
}
}
-static bfd_boolean
+static bool
xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
const frag_flags *prop_flags_2)
{
/* Cannot combine with an end marker. */
if (prop_flags_1->is_literal != prop_flags_2->is_literal)
- return FALSE;
+ return false;
if (prop_flags_1->is_insn != prop_flags_2->is_insn)
- return FALSE;
+ return false;
if (prop_flags_1->is_data != prop_flags_2->is_data)
- return FALSE;
+ return false;
if (prop_flags_1->is_insn)
{
/* Properties of the beginning of the frag. */
if (prop_flags_2->insn.is_loop_target)
- return FALSE;
+ return false;
if (prop_flags_2->insn.is_branch_target)
- return FALSE;
+ return false;
if (prop_flags_1->insn.is_no_density !=
prop_flags_2->insn.is_no_density)
- return FALSE;
+ return false;
if (prop_flags_1->is_no_transform !=
prop_flags_2->is_no_transform)
- return FALSE;
+ return false;
if (prop_flags_1->insn.is_no_reorder !=
prop_flags_2->insn.is_no_reorder)
- return FALSE;
+ return false;
if (prop_flags_1->insn.is_abslit !=
prop_flags_2->insn.is_abslit)
- return FALSE;
+ return false;
}
if (prop_flags_1->is_align)
- return FALSE;
+ return false;
- return TRUE;
+ return true;
}
}
-static bfd_boolean
+static bool
xtensa_xt_block_combine (xtensa_block_info *xt_block,
const xtensa_block_info *xt_block_2)
{
if (xt_block->sec != xt_block_2->sec)
- return FALSE;
+ return false;
if (xt_block->offset + xt_block_aligned_size (xt_block)
!= xt_block_2->offset)
- return FALSE;
+ return false;
if (xt_block_2->size == 0
&& (!xt_block_2->flags.is_unreachable
{
/* Nothing needed. */
if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
- return TRUE;
+ return true;
}
else
{
xt_block->flags.is_align = xt_block_2->flags.is_align;
xt_block->flags.alignment = xt_block_2->flags.alignment;
}
- return TRUE;
+ return true;
}
}
if (!xtensa_frag_flags_combinable (&xt_block->flags,
&xt_block_2->flags))
- return FALSE;
+ return false;
xt_block->size += xt_block_2->size;
if (xt_block_2->flags.is_align)
{
- xt_block->flags.is_align = TRUE;
+ xt_block->flags.is_align = true;
xt_block->flags.alignment = xt_block_2->flags.alignment;
}
- return TRUE;
+ return true;
}
}
-bfd_boolean
+bool
opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
{
return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
}
-bfd_boolean
+bool
istack_empty (IStack *stack)
{
return (stack->ninsn == 0);
}
-bfd_boolean
+bool
istack_full (IStack *stack)
{
return (stack->ninsn == MAX_ISTACK);
/* Return TRUE if ANY of the operands in the insn are symbolic. */
-static bfd_boolean
+static bool
tinsn_has_symbolic_operands (const TInsn *insn)
{
int i;
case O_constant:
break;
default:
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
-bfd_boolean
+bool
tinsn_has_invalid_symbolic_operands (const TInsn *insn)
{
xtensa_isa isa = xtensa_default_isa;
&& insn->opcode != xtensa_const16_opcode))
{
as_bad (_("invalid symbolic operand"));
- return TRUE;
+ return true;
}
}
}
- return FALSE;
+ return false;
}
The relaxation only handles expressions that
boil down to SYMBOL + OFFSET. */
-static bfd_boolean
+static bool
tinsn_has_complex_operands (const TInsn *insn)
{
int i;
case O_hi16:
break;
default:
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
3) The opcode can be encoded in the specified format and slot.
4) Operands are either O_constant or O_symbol, and all constants fit. */
-static bfd_boolean
+static bool
tinsn_to_slotbuf (xtensa_format fmt,
int slot,
TInsn *tinsn,
{
xtensa_isa isa = xtensa_default_isa;
xtensa_opcode opcode = tinsn->opcode;
- bfd_boolean has_fixup = FALSE;
+ bool has_fixup = false;
int noperands = xtensa_opcode_num_operands (isa, opcode);
int i;
{
as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
- return FALSE;
+ return false;
}
for (i = 0; i < noperands; i++)
break;
default:
- has_fixup = TRUE;
+ has_fixup = true;
break;
}
}
Return TRUE if there is a symbol in the immediate field. See also the
assumptions listed for tinsn_to_slotbuf. */
-static bfd_boolean
+static bool
tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
{
static xtensa_insnbuf slotbuf = 0;
static vliw_insn vinsn;
xtensa_isa isa = xtensa_default_isa;
- bfd_boolean has_fixup = FALSE;
+ bool has_fixup = false;
int i;
if (!slotbuf)
/* Check the instruction arguments. Return TRUE on failure. */
-static bfd_boolean
+static bool
tinsn_check_arguments (const TInsn *insn)
{
xtensa_isa isa = xtensa_default_isa;
if (opcode == XTENSA_UNDEFINED)
{
as_bad (_("invalid opcode"));
- return TRUE;
+ return true;
}
if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
{
as_bad (_("too few operands"));
- return TRUE;
+ return true;
}
if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
{
as_bad (_("too many operands"));
- return TRUE;
+ return true;
}
/* Check registers. */
if (t1_inout != 'i' && t2_inout != 'i')
{
as_bad (_("multiple writes to the same register"));
- return TRUE;
+ return true;
}
}
}
}
}
- return FALSE;
+ return false;
}
/* Find the immed. */
tinsn_init (tinsn);
tinsn->insn_type = ITYPE_INSN;
- tinsn->is_specific_opcode = FALSE; /* must not be specific */
+ tinsn->is_specific_opcode = false; /* must not be specific */
tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
for (i = 0; i < tinsn->ntok; i++)
v->format = XTENSA_UNDEFINED;
v->num_slots = 0;
- v->inside_bundle = FALSE;
+ v->inside_bundle = false;
if (xt_saved_debug_type != DEBUG_NONE)
debug_type = xt_saved_debug_type;
}
-static bfd_boolean
+static bool
vinsn_has_specific_opcodes (vliw_insn *v)
{
int i;
for (i = 0; i < v->num_slots; i++)
{
if (v->slots[i].is_specific_opcode)
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
operands. See also the assumptions listed for tinsn_to_slotbuf. */
-static bfd_boolean
+static bool
vinsn_to_insnbuf (vliw_insn *vinsn,
char *frag_offset,
fragS *fragP,
- bfd_boolean record_fixup)
+ bool record_fixup)
{
xtensa_isa isa = xtensa_default_isa;
xtensa_format fmt = vinsn->format;
xtensa_insnbuf insnbuf = vinsn->insnbuf;
int slot;
- bfd_boolean has_fixup = FALSE;
+ bool has_fixup = false;
xtensa_format_encode (isa, fmt, insnbuf);
{
TInsn *tinsn = &vinsn->slots[slot];
expressionS *extra_arg = &tinsn->extra_arg;
- bfd_boolean tinsn_has_fixup =
+ bool tinsn_has_fixup =
tinsn_to_slotbuf (vinsn->format, slot, tinsn,
vinsn->slotbuf[slot]);
fix_new (fragP, frag_offset - fragP->fr_literal,
xtensa_format_length (isa, fmt),
extra_arg->X_add_symbol, extra_arg->X_add_number,
- FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE));
+ false, map_operator_to_reloc (extra_arg->X_op, false));
}
if (tinsn_has_fixup)
{
int i;
xtensa_opcode opcode = tinsn->opcode;
int noperands = xtensa_opcode_num_operands (isa, opcode);
- has_fixup = TRUE;
+ has_fixup = true;
for (i = 0; i < noperands; i++)
{
/* Return TRUE if the expression is an integer constant. */
-bfd_boolean
+bool
expr_is_const (const expressionS *s)
{
return (s->X_op == O_constant);
}
-bfd_boolean
+bool
expr_is_register (const expressionS *s)
{
return (s->X_op == O_register);
/* Return TRUE if the two expressions are equal. */
-bfd_boolean
+bool
expr_is_equal (expressionS *s1, expressionS *s2)
{
if (s1->X_op != s2->X_op)
- return FALSE;
+ return false;
if (s1->X_add_symbol != s2->X_add_symbol)
- return FALSE;
+ return false;
if (s1->X_op_symbol != s2->X_op_symbol)
- return FALSE;
+ return false;
if (s1->X_add_number != s2->X_add_number)
- return FALSE;
- return TRUE;
+ return false;
+ return true;
}
extern void xtensa_post_relax_hook (void);
extern void xtensa_file_arch_init (bfd *);
extern void xtensa_flush_pending_output (void);
-extern bfd_boolean xtensa_fix_adjustable (struct fix *);
+extern bool xtensa_fix_adjustable (struct fix *);
extern void xtensa_symbol_new_hook (symbolS *);
extern long xtensa_relax_frag (fragS *, long, int *);
extern void xtensa_elf_section_change_hook (void);
extern int xtensa_unrecognized_line (int);
-extern bfd_boolean xtensa_check_inside_bundle (void);
+extern bool xtensa_check_inside_bundle (void);
extern void xtensa_handle_align (fragS *);
extern char *xtensa_section_rename (const char *);
opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func);
void resize_resource_table (resource_table *, int);
void clear_resource_table (resource_table *);
-bfd_boolean resources_available (resource_table *, xtensa_opcode, int);
+bool resources_available (resource_table *, xtensa_opcode, int);
void reserve_resources (resource_table *, xtensa_opcode, int);
void release_resources (resource_table *, xtensa_opcode, int);
return str_to_double (litP, sizeP);
break;
}
- return ieee_md_atof (type, litP, sizeP, FALSE);
+ return ieee_md_atof (type, litP, sizeP, false);
}
valueT
}
/* Check whether a symbol involves a register. */
-static bfd_boolean
+static bool
contains_register (symbolS *sym)
{
if (sym)
switch (ex->X_op)
{
case O_register:
- return TRUE;
+ return true;
case O_add:
case O_subtract:
if (ex->X_op_symbol && contains_register (ex->X_op_symbol))
- return TRUE;
+ return true;
/* Fall through. */
case O_uminus:
case O_symbol:
if (ex->X_add_symbol && contains_register (ex->X_add_symbol))
- return TRUE;
+ return true;
break;
default:
}
}
- return FALSE;
+ return false;
}
/* Parse general expression, not looking for indexed addressing. */
if (size <= 2 && val->X_op_symbol)
{
- bfd_boolean simplify = TRUE;
+ bool simplify = true;
int shift = symbol_get_value_expression (val->X_op_symbol)->X_add_number;
if (val->X_op == O_bit_and && shift == (1 << (size*8))-1)
shift = 0;
case 8: r_type = BFD_RELOC_Z80_BYTE1; break;
case 16: r_type = BFD_RELOC_Z80_BYTE2; break;
case 24: r_type = BFD_RELOC_Z80_BYTE3; break;
- default: simplify = FALSE;
+ default: simplify = false;
}
}
else /* if (size == 2) */
{
case 0: r_type = BFD_RELOC_Z80_WORD0; break;
case 16: r_type = BFD_RELOC_Z80_WORD1; break;
- default: simplify = FALSE;
+ default: simplify = false;
}
}
}
}
- fix_new_exp (frag_now, p - frag_now->fr_literal, size, val, FALSE, r_type);
+ fix_new_exp (frag_now, p - frag_now->fr_literal, size, val, false, r_type);
}
static void
*q = 0x8A;
q = frag_more (2);
- fix_new_exp (frag_now, q - frag_now->fr_literal, 2, &arg, FALSE,
+ fix_new_exp (frag_now, q - frag_now->fr_literal, 2, &arg, false,
BFD_RELOC_Z80_16_BE);
return p;
#define EXP_MIN -0x10000
#define EXP_MAX 0x10000
static int
-str_to_broken_float (bfd_boolean *signP, bfd_uint64_t *mantissaP, int *expP)
+str_to_broken_float (bool *signP, bfd_uint64_t *mantissaP, int *expP)
{
char *p;
- bfd_boolean sign;
+ bool sign;
bfd_uint64_t mantissa = 0;
int exponent = 0;
int i;
str_to_zeda32(char *litP, int *sizeP)
{
bfd_uint64_t mantissa;
- bfd_boolean sign;
+ bool sign;
int exponent;
unsigned i;
str_to_float48(char *litP, int *sizeP)
{
bfd_uint64_t mantissa;
- bfd_boolean sign;
+ bool sign;
int exponent;
unsigned i;
static const char *
str_to_ieee754_h(char *litP, int *sizeP)
{
- return ieee_md_atof ('h', litP, sizeP, FALSE);
+ return ieee_md_atof ('h', litP, sizeP, false);
}
static const char *
str_to_ieee754_s(char *litP, int *sizeP)
{
- return ieee_md_atof ('s', litP, sizeP, FALSE);
+ return ieee_md_atof ('s', litP, sizeP, false);
}
static const char *
str_to_ieee754_d(char *litP, int *sizeP)
{
- return ieee_md_atof ('d', litP, sizeP, FALSE);
+ return ieee_md_atof ('d', litP, sizeP, false);
}
#ifdef TARGET_USE_CFIPOP
const char *
md_atof (int type, char *litP, int *sizeP)
{
- return ieee_md_atof (type, litP, sizeP, TRUE);
+ return ieee_md_atof (type, litP, sizeP, true);
}
\f
const char *md_shortopts = "z:";
enum itype_enum insn_type;
xtensa_opcode opcode; /* Literals have an invalid opcode. */
- bfd_boolean is_specific_opcode;
- bfd_boolean keep_wide;
+ bool is_specific_opcode;
+ bool keep_wide;
int ntok;
expressionS tok[MAX_INSN_ARGS];
- bfd_boolean loc_directive_seen;
+ bool loc_directive_seen;
struct dwarf2_line_info debug_line;
/* This field is used for two types of special pseudo ops:
void istack_init (IStack *);
-bfd_boolean istack_empty (IStack *);
-bfd_boolean istack_full (IStack *);
+bool istack_empty (IStack *);
+bool istack_full (IStack *);
TInsn *istack_top (IStack *);
void istack_push (IStack *, TInsn *);
TInsn *istack_push_space (IStack *);
\f
/* Externally visible functions. */
-extern bfd_boolean xg_has_userdef_op_fn (OpType);
+extern bool xg_has_userdef_op_fn (OpType);
extern long xg_apply_userdef_op_fn (OpType, long);
}
-bfd_boolean
+bool
xg_has_userdef_op_fn (OpType op)
{
switch (op)
case OP_OPERAND_HI24S:
case OP_OPERAND_LOW16U:
case OP_OPERAND_HI16U:
- return TRUE;
+ return true;
default:
break;
}
- return FALSE;
+ return false;
}
default:
break;
}
- return FALSE;
+ return false;
}
}
-static bfd_boolean
+static bool
same_operand_name (const opname_map_e *m1, const opname_map_e *m2)
{
if (m1->operand_name == NULL || m2->operand_name == NULL)
- return FALSE;
+ return false;
return (m1->operand_name == m2->operand_name);
}
}
-static bfd_boolean
+static bool
op_is_constant (const opname_map_e *m1)
{
return (m1->operand_name == NULL);
/* Convert a string to a number. E.G.: parse_constant("10", &num) */
-static bfd_boolean
+static bool
parse_constant (const char *in, unsigned *val_p)
{
unsigned val = 0;
const char *p;
if (in == NULL)
- return FALSE;
+ return false;
p = in;
while (*p != '\0')
if (*p >= '0' && *p <= '9')
val = val * 10 + (*p - '0');
else
- return FALSE;
+ return false;
++p;
}
*val_p = val;
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
parse_special_fn (const char *name,
const char **fn_name_p,
const char **arg_name_p)
p_start = strchr (name, '(');
if (p_start == NULL)
- return FALSE;
+ return false;
p_end = strchr (p_start, ')');
if (p_end == NULL)
- return FALSE;
+ return false;
if (p_end[1] != '\0')
- return FALSE;
+ return false;
*fn_name_p = enter_opname_n (name, p_start - name);
*arg_name_p = enter_opname_n (p_start + 1, p_end - p_start - 1);
- return TRUE;
+ return true;
}
split_string (split_rec *rec,
const char *in,
char c,
- bfd_boolean elide_whitespace)
+ bool elide_whitespace)
{
int cnt = 0;
int i;
/* Parse an instruction template like "insn op1, op2, op3". */
-static bfd_boolean
+static bool
parse_insn_templ (const char *s, insn_templ *t)
{
const char *p = s;
p = skip_white (p);
insn_name_len = strcspn (s, " ");
if (insn_name_len == 0)
- return FALSE;
+ return false;
init_insn_templ (t);
t->opcode_name = enter_opname_n (p, insn_name_len);
p = p + insn_name_len;
/* Split by ',' and skip beginning and trailing whitespace. */
- split_string (&oprec, p, ',', TRUE);
+ split_string (&oprec, p, ',', true);
for (i = 0; i < oprec.count; i++)
{
free (e);
clear_split_rec (&oprec);
clear_insn_templ (t);
- return FALSE;
+ return false;
}
}
else
t->operand_map.tail = &e->next;
}
clear_split_rec (&oprec);
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
parse_precond (const char *s, precond_e *precond)
{
/* All preconditions are currently of the form:
len = strcspn (p, " !=");
if (len == 0)
- return FALSE;
+ return false;
precond->opname1 = enter_opname_n (p, len);
p = p + len;
else if (strncmp (p, "!=", 2) == 0)
precond->cmpop = OP_NOTEQUAL;
else
- return FALSE;
+ return false;
p = p + 2;
p = skip_white (p);
if (parse_constant (p, &val))
precond->opval2 = val;
else
- return FALSE;
+ return false;
}
else
precond->opname2 = enter_opname (p);
- return TRUE;
+ return true;
}
}
-static bfd_boolean
+static bool
parse_option_cond (const char *s, ReqOption *option)
{
int i;
"Ands" are divided by "?". */
init_split_rec (&option_term_rec);
- split_string (&option_term_rec, s, '+', TRUE);
+ split_string (&option_term_rec, s, '+', true);
if (option_term_rec.count == 0)
{
clear_split_rec (&option_term_rec);
- return FALSE;
+ return false;
}
for (i = 0; i < option_term_rec.count; i++)
{
char *option_name = option_term_rec.vec[i];
- bfd_boolean is_true = TRUE;
+ bool is_true = true;
ReqOrOption *req;
ReqOrOption **r_p;
if (strncmp (option_name, "no-", 3) == 0)
{
option_name = xstrdup (&option_name[3]);
- is_true = FALSE;
+ is_true = false;
}
else
option_name = xstrdup (option_name);
;
(*r_p) = req;
}
- return TRUE;
+ return true;
}
split_string, it requires that '|' and '?' are only used as
delimiters for predicates and required options. */
-static bfd_boolean
+static bool
parse_insn_pattern (const char *in, insn_pattern *insn)
{
split_rec rec;
init_insn_pattern (insn);
init_split_rec (&optionrec);
- split_string (&optionrec, in, '?', TRUE);
+ split_string (&optionrec, in, '?', true);
if (optionrec.count == 0)
{
clear_split_rec (&optionrec);
- return FALSE;
+ return false;
}
init_split_rec (&rec);
- split_string (&rec, optionrec.vec[0], '|', TRUE);
+ split_string (&rec, optionrec.vec[0], '|', true);
if (rec.count == 0)
{
clear_split_rec (&rec);
clear_split_rec (&optionrec);
- return FALSE;
+ return false;
}
if (!parse_insn_templ (rec.vec[0], &insn->t))
{
clear_split_rec (&rec);
clear_split_rec (&optionrec);
- return FALSE;
+ return false;
}
for (i = 1; i < rec.count; i++)
clear_split_rec (&rec);
clear_split_rec (&optionrec);
clear_insn_pattern (insn);
- return FALSE;
+ return false;
}
/* Append the condition. */
clear_split_rec (&optionrec);
clear_insn_pattern (insn);
clear_req_option_list (&req_option);
- return FALSE;
+ return false;
}
/* Append the condition. */
clear_split_rec (&rec);
clear_split_rec (&optionrec);
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
parse_insn_repl (const char *in, insn_repl *r_p)
{
/* This is a list of instruction templates separated by ';'. */
split_rec rec;
int i;
- split_string (&rec, in, ';', TRUE);
+ split_string (&rec, in, ';', true);
for (i = 0; i < rec.count; i++)
{
{
free (e);
clear_insn_repl (r_p);
- return FALSE;
+ return false;
}
*r_p->tail = e;
r_p->tail = &e->next;
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
transition_applies (insn_pattern *initial_insn,
const char *from_string ATTRIBUTE_UNUSED,
const char *to_string ATTRIBUTE_UNUSED)
if (strncmp (req_or_option->option_name, "IsaUse", 6) == 0)
{
- bfd_boolean option_available = FALSE;
+ bool option_available = false;
char *option_name = req_or_option->option_name + 6;
if (!strcmp (option_name, "DensityInstruction"))
option_available = (XCHAL_HAVE_DENSITY == 1);
as_warn (_("invalid configuration option '%s' in transition rule '%s'"),
req_or_option->option_name, from_string);
if ((option_available ^ req_or_option->is_true) != 0)
- return FALSE;
+ return false;
}
else if (strcmp (req_or_option->option_name, "realnop") == 0)
{
- bfd_boolean nop_available =
+ bool nop_available =
(xtensa_opcode_lookup (xtensa_default_isa, "nop")
!= XTENSA_UNDEFINED);
if ((nop_available ^ req_or_option->is_true) != 0)
- return FALSE;
+ return false;
}
}
- return TRUE;
+ return true;
}
-static bfd_boolean
+static bool
wide_branch_opcode (const char *opcode_name,
const char *suffix,
xtensa_opcode *popcode)
static char wbr_name_buf[20];
if (strncmp (opcode_name, "WIDE.", 5) != 0)
- return FALSE;
+ return false;
strcpy (wbr_name_buf, opcode_name + 5);
strcat (wbr_name_buf, suffix);
if (opcode != XTENSA_UNDEFINED)
{
*popcode = opcode;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
struct req_or_option_list
{
char *option_name;
- bfd_boolean is_true;
+ bool is_true;
ReqOrOptionList *next;
};
extern TransitionTable *xg_build_simplify_table (transition_cmp_fn);
extern TransitionTable *xg_build_widen_table (transition_cmp_fn);
-extern bfd_boolean xg_has_userdef_op_fn (OpType);
+extern bool xg_has_userdef_op_fn (OpType);
extern long xg_apply_userdef_op_fn (OpType, long);
enum flix_level
};
#ifdef SUPPORT_COMPACT_EH
-static bfd_boolean compact_eh;
+static bool compact_eh;
#else
#define compact_eh 0
#endif
emit a byte containing ENCODING. */
static void
-emit_expr_encoded (expressionS *exp, int encoding, bfd_boolean emit_encoding)
+emit_expr_encoded (expressionS *exp, int encoding, bool emit_encoding)
{
unsigned int size = encoding_size (encoding);
bfd_reloc_code_real_type code;
/* Construct a new INSN structure and add it to the end of the insn list
for the currently active FDE. */
-static bfd_boolean cfi_sections_set = FALSE;
+static bool cfi_sections_set = false;
static int cfi_sections = CFI_EMIT_eh_frame;
int all_cfi_sections = 0;
static struct fde_entry *last_fde;
cfi_set_sections (void)
{
frchain_now->frch_cfi_data->cur_fde_data->sections = all_cfi_sections;
- cfi_sections_set = TRUE;
+ cfi_sections_set = true;
}
/* Universal functions to store new instructions. */
else if (strncmp (name, ".eh_frame_entry",
sizeof ".eh_frame_entry") == 0)
{
- compact_eh = TRUE;
+ compact_eh = true;
sections |= CFI_EMIT_eh_frame_compact;
}
#endif
}
demand_empty_rest_of_line ();
- cfi_sections_set = TRUE;
+ cfi_sections_set = true;
all_cfi_sections |= cfi_sections;
cfi_set_sections ();
frchain_now->frch_cfi_data->cur_cfa_offset = 0;
demand_empty_rest_of_line ();
- cfi_sections_set = TRUE;
+ cfi_sections_set = true;
if ((cfi_sections & CFI_EMIT_target) != 0)
tc_cfi_endproc (last_fde);
}
last_fde = frchain_now->frch_cfi_data->cur_fde_data;
- cfi_sections_set = TRUE;
+ cfi_sections_set = true;
if ((cfi_sections & CFI_EMIT_target) != 0
|| (cfi_sections & CFI_EMIT_eh_frame_compact) != 0)
{
else if (fde->per_encoding != DW_EH_PE_omit)
{
*p = 0;
- emit_expr_encoded (&fde->personality, fde->per_encoding, FALSE);
+ emit_expr_encoded (&fde->personality, fde->per_encoding, false);
data_size += encoding_size (fde->per_encoding);
}
else
}
static void
-output_cie (struct cie_entry *cie, bfd_boolean eh_frame, int align)
+output_cie (struct cie_entry *cie, bool eh_frame, int align)
{
symbolS *after_size_address, *end_address;
expressionS exp;
augmentation_size += 1 + encoding_size (cie->per_encoding);
out_uleb128 (augmentation_size); /* Augmentation size. */
- emit_expr_encoded (&cie->personality, cie->per_encoding, TRUE);
+ emit_expr_encoded (&cie->personality, cie->per_encoding, true);
if (cie->lsda_encoding != DW_EH_PE_omit)
out_one (cie->lsda_encoding);
static void
output_fde (struct fde_entry *fde, struct cie_entry *cie,
- bfd_boolean eh_frame, struct cfi_insn_data *first,
+ bool eh_frame, struct cfi_insn_data *first,
int align)
{
symbolS *after_size_address, *end_address;
if (eh_frame)
out_uleb128 (augmentation_size); /* Augmentation size. */
- emit_expr_encoded (&fde->lsda, cie->lsda_encoding, FALSE);
+ emit_expr_encoded (&fde->lsda, cie->lsda_encoding, false);
for (; first; first = first->next)
if (CUR_SEG (first) == CUR_SEG (fde))
}
static struct cie_entry *
-select_cie_for_fde (struct fde_entry *fde, bfd_boolean eh_frame,
+select_cie_for_fde (struct fde_entry *fde, bool eh_frame,
struct cfi_insn_data **pfirst, int align)
{
struct cfi_insn_data *i, *j;
exp.X_add_number = addend;
exp.X_add_symbol = sym;
- emit_expr_encoded (&exp, DW_EH_PE_sdata4 | DW_EH_PE_pcrel, FALSE);
+ emit_expr_encoded (&exp, DW_EH_PE_sdata4 | DW_EH_PE_pcrel, false);
}
static void
if (all_fde_data == 0)
return;
- cfi_sections_set = TRUE;
+ cfi_sections_set = true;
if ((all_cfi_sections & CFI_EMIT_eh_frame) != 0
|| (all_cfi_sections & CFI_EMIT_eh_frame_compact) != 0)
{
fde->end_address = fde->start_address;
}
- cie = select_cie_for_fde (fde, TRUE, &first, 2);
+ cie = select_cie_for_fde (fde, true, &first, 2);
fde->eh_loc = symbol_temp_new_now ();
- output_fde (fde, cie, TRUE, first,
+ output_fde (fde, cie, true, first,
fde->next == NULL ? EH_FRAME_ALIGNMENT : 2);
}
}
flag_traditional_format = save_flag_traditional_format;
}
- cfi_sections_set = TRUE;
+ cfi_sections_set = true;
if ((all_cfi_sections & CFI_EMIT_debug_frame) != 0)
{
int alignment = ffs (DWARF2_ADDR_SIZE (stdoutput)) - 1;
fde->per_encoding = DW_EH_PE_omit;
fde->lsda_encoding = DW_EH_PE_omit;
cfi_change_reg_numbers (fde->data, ccseg);
- cie = select_cie_for_fde (fde, FALSE, &first, alignment);
- output_fde (fde, cie, FALSE, first, alignment);
+ cie = select_cie_for_fde (fde, false, &first, alignment);
+ output_fde (fde, cie, false, first, alignment);
}
}
while (SUPPORT_FRAME_LINKONCE && seek_next_seg == 2);
/* TRUE when we've seen a .loc directive recently. Used to avoid
doing work when there's nothing to do. Will be reset by
dwarf2_consume_line_info. */
-bfd_boolean dwarf2_loc_directive_seen;
+bool dwarf2_loc_directive_seen;
/* TRUE when we've seen any .loc directive at any time during parsing.
Indicates the user wants us to generate a .debug_line section.
Used in dwarf2_finish as sanity check. */
-static bfd_boolean dwarf2_any_loc_directive_seen;
+static bool dwarf2_any_loc_directive_seen;
/* TRUE when we're supposed to set the basic block mark whenever a
label is seen. */
-bfd_boolean dwarf2_loc_mark_labels;
+bool dwarf2_loc_mark_labels;
/* Current location as indicated by the most recent .loc directive. */
static struct dwarf2_line_info current =
/* Find or create (if CREATE_P) an entry for SEG+SUBSEG in ALL_SEGS. */
static struct line_subseg *
-get_line_subseg (segT seg, subsegT subseg, bfd_boolean create_p)
+get_line_subseg (segT seg, subsegT subseg, bool create_p)
{
struct line_seg *s = seg_info (seg)->dwarf2_line_seg;
struct line_subseg **pss, *lss;
e->label = label;
e->loc = *loc;
- lss = get_line_subseg (now_seg, now_subseg, TRUE);
+ lss = get_line_subseg (now_seg, now_subseg, true);
/* Subseg heads are chained to previous subsegs in
dwarf2_finish. */
}
static unsigned int
-get_directory_table_entry (const char * dirname,
- size_t dirlen,
- bfd_boolean can_use_zero)
+get_directory_table_entry (const char *dirname,
+ size_t dirlen,
+ bool can_use_zero)
{
unsigned int d;
return d;
}
-static bfd_boolean
+static bool
assign_file_to_slot (unsigned long i, const char *file, unsigned int dir)
{
if (i >= files_allocated)
if (files_allocated <= old)
{
as_bad (_("file number %lu is too big"), (unsigned long) i);
- return FALSE;
+ return false;
}
files = XRESIZEVEC (struct file_entry, files, files_allocated);
if (files_in_use < i + 1)
files_in_use = i + 1;
- return TRUE;
+ return true;
}
/* Get a .debug_line file number for PATHNAME. If there is a
file = get_basename (pathname);
dir_len = file - pathname;
- dir = get_directory_table_entry (pathname, dir_len, FALSE);
+ dir = get_directory_table_entry (pathname, dir_len, false);
/* Do not use slot-0. That is specifically reserved for use by
the '.file 0 "name"' directive. */
if WITH_MD5 is TRUE then there is a md5 value in generic_bignum.
Returns TRUE if allocation succeeded, FALSE otherwise. */
-static bfd_boolean
-allocate_filename_to_slot (const char * dirname,
- const char * filename,
- unsigned int num,
- bfd_boolean with_md5)
+static bool
+allocate_filename_to_slot (const char *dirname,
+ const char *filename,
+ unsigned int num,
+ bool with_md5)
{
const char *file;
size_t dirlen;
dirs[files[num].dir] = xmemdup0 (dirname, strlen (dirname));
}
- return TRUE;
+ return true;
}
else if (dir != NULL)
{
if (filename_ncmp (filename, dir, dirlen) == 0
&& IS_DIR_SEPARATOR (filename [dirlen])
&& filename_cmp (filename + dirlen + 1, files[num].filename) == 0)
- return TRUE;
+ return true;
}
else /* dir == NULL */
{
dirs[files[num].dir] = xmemdup0 (filename, file - filename);
}
- return TRUE;
+ return true;
}
}
dirname == NULL ? "" : dirname,
dirname == NULL ? "" : "/",
filename);
- return FALSE;
+ return false;
}
if (dirname == NULL)
i = num;
if (! assign_file_to_slot (i, file, d))
- return FALSE;
+ return false;
if (with_md5)
{
else
memset (files[i].md5, 0, NUM_MD5_BYTES);
- return TRUE;
+ return true;
}
/* Returns the current source information. If .file directives have
if (delta == 0)
return;
- lss = get_line_subseg (now_seg, now_subseg, FALSE);
+ lss = get_line_subseg (now_seg, now_subseg, false);
if (!lss)
return;
{
/* Unless we generate DWARF2 debugging information for each
assembler line, we only emit one line symbol for one LOC. */
- dwarf2_loc_directive_seen = FALSE;
+ dwarf2_loc_directive_seen = false;
current.flags &= ~(DWARF2_FLAG_BASIC_BLOCK
| DWARF2_FLAG_PROLOGUE_END
char *
dwarf2_directive_filename (void)
{
- bfd_boolean with_md5 = FALSE;
+ bool with_md5 = false;
valueT num;
char *filename;
const char * dirname = NULL;
if (exp.X_op != O_big)
as_bad (_("md5 value too small or not a constant"));
else
- with_md5 = TRUE;
+ with_md5 = true;
}
}
if (ISDIGIT (*input_line_pointer)
|| *input_line_pointer == '-')
{
- bfd_boolean force_reset = *input_line_pointer == '-';
+ bool force_reset = *input_line_pointer == '-';
value = get_absolute_expression ();
if (value != 0)
}
demand_empty_rest_of_line ();
- dwarf2_any_loc_directive_seen = dwarf2_loc_directive_seen = TRUE;
+ dwarf2_any_loc_directive_seen = dwarf2_loc_directive_seen = true;
debug_type = DEBUG_NONE;
/* If we were given a view id, emit the row right away. */
if (strcmp (sec_name, ".text") != 0)
{
name = concat (".debug_line", sec_name, (char *) NULL);
- subseg_set (subseg_get (name, FALSE), 0);
+ subseg_set (subseg_get (name, false), 0);
}
else
/* Don't create a .debug_line.text section -
that is redundant. Instead just switch back to the
normal .debug_line section. */
- subseg_set (subseg_get (".debug_line", FALSE), 0);
+ subseg_set (subseg_get (".debug_line", false), 0);
}
do
const char *dir;
char *cp;
unsigned int i;
- bfd_boolean emit_md5 = FALSE;
- bfd_boolean emit_timestamps = TRUE;
- bfd_boolean emit_filesize = TRUE;
+ bool emit_md5 = false;
+ bool emit_timestamps = true;
+ bool emit_filesize = true;
segT line_str_seg = NULL;
symbolS *line_strp;
if (((unsigned long) DWARF2_FILE_TIME_NAME ("", "")) == -1UL)
{
- emit_timestamps = FALSE;
+ emit_timestamps = false;
-- columns;
}
if (DWARF2_FILE_SIZE_NAME ("", "") == -1)
{
- emit_filesize = FALSE;
+ emit_filesize = false;
-- columns;
}
break;
if (i < files_in_use)
{
- emit_md5 = TRUE;
+ emit_md5 = true;
++ columns;
}
This section contains the line_end symbol which is used to
compute the size of the linked .debug_line section, as seen
in the DWARF Line Number header. */
- subseg_set (subseg_get (".debug_line_end", FALSE), 0);
+ subseg_set (subseg_get (".debug_line_end", false), 0);
symbol_set_value_now (line_end);
}
/* True when we've seen a .loc directive recently. Used to avoid
doing work when there's nothing to do. */
-extern bfd_boolean dwarf2_loc_directive_seen;
+extern bool dwarf2_loc_directive_seen;
/* True when we're supposed to set the basic block mark whenever a label
is seen. Unless the target is doing Something Weird, just call
dwarf2_emit_label. */
-extern bfd_boolean dwarf2_loc_mark_labels;
+extern bool dwarf2_loc_mark_labels;
extern void dwarf2_init (void);
#define CHAR_BIT 8
#endif
-bfd_boolean literal_prefix_dollar_hex = FALSE;
+bool literal_prefix_dollar_hex = false;
static void floating_constant (expressionS * expressionP);
static valueT generic_bignum_to_int32 (void);
}
else if (c == '"')
{
- bfd_boolean backslash_seen;
+ bool backslash_seen;
* ilp_return = input_line_pointer;
do
int resolve_expression (expressionS *);
-extern bfd_boolean literal_prefix_dollar_hex;
+extern bool literal_prefix_dollar_hex;
their start addresses. Set OFFSET to the difference in address
not already accounted for in the frag FR_ADDRESS. */
-bfd_boolean
+bool
frag_offset_fixed_p (const fragS *frag1, const fragS *frag2, offsetT *offset)
{
const fragS *frag;
if (frag1 == frag2)
{
*offset = off;
- return TRUE;
+ return true;
}
/* Maybe frag2 is after frag1. */
if (frag == frag2)
{
*offset = off;
- return TRUE;
+ return true;
}
}
if (frag == frag1)
{
*offset = off;
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Return TRUE if FRAG2 follows FRAG1 with a fixed relationship
the difference in address not already accounted for in the frag
FR_ADDRESS. */
-bfd_boolean
+bool
frag_offset_ignore_align_p (const fragS *frag1, const fragS *frag2,
offsetT *offset)
{
if (frag1 == frag2)
{
*offset = off;
- return TRUE;
+ return true;
}
frag = frag1;
if (frag == frag2)
{
*offset = off;
- return TRUE;
+ return true;
}
}
- return FALSE;
+ return false;
}
/* Return TRUE if we can determine whether FRAG2 OFF2 appears after
reachable from frag1 following the fr_next links, rather than the
other way round. */
-bfd_boolean
+bool
frag_gtoffset_p (valueT off2, const fragS *frag2,
valueT off1, const fragS *frag1, offsetT *offset)
{
/* Insanity check. */
if (frag2 == frag1 || off1 > frag1->fr_fix)
- return FALSE;
+ return false;
/* If the first symbol offset is at the end of the first frag and
the second symbol offset at the beginning of the second frag then
if (frag == frag2)
{
if (delta == 0)
- return FALSE;
+ return false;
break;
}
/* If we run off the end of the frag chain then we have a case
where frag2 is not after frag1, ie. an O_gt expression not
created for .loc view. */
if (frag == NULL)
- return FALSE;
+ return false;
}
*offset = (off2 - off1 - delta) * OCTETS_PER_BYTE;
- return TRUE;
+ return true;
}
offsetT offset,
char *opcode);
-bfd_boolean frag_offset_fixed_p (const fragS *, const fragS *, offsetT *);
-bfd_boolean frag_offset_ignore_align_p (const fragS *, const fragS *,
- offsetT *);
-bfd_boolean frag_gtoffset_p (valueT, const fragS *, valueT, const fragS *,
- offsetT *);
+bool frag_offset_fixed_p (const fragS *, const fragS *, offsetT *);
+bool frag_offset_ignore_align_p (const fragS *, const fragS *, offsetT *);
+bool frag_gtoffset_p (valueT, const fragS *, valueT, const fragS *, offsetT *);
int get_frag_count (void);
void clear_frag_count (void);
long pos;
long pos2;
int c;
- bfd_boolean found = FALSE;
+ bool found = false;
/* Sanity checks. */
if (file == NULL || buffer == NULL || size <= 1 || file->linenum <= linenum)
if (current_line == linenum)
{
/* We have found the start of the line we seek. */
- found = TRUE;
+ found = true;
/* FIXME: We could skip the read-in-the-line code
below if we know that we already have the whole
{
/* Try to find the first pseudo op on the line. */
size_t i = line_start;
- bfd_boolean had_colon = FALSE;
+ bool had_colon = false;
/* With normal syntax we can suck what we want till we get
to the dot. With the alternate, labels have to start in
}
i++;
line_start = i;
- had_colon = TRUE;
+ had_colon = true;
}
/* Skip trailing whitespace. */
}
else
{
- bfd_boolean in_quotes = FALSE;
+ bool in_quotes = false;
if (irpc && in->ptr[idx] == '"')
{
- in_quotes = TRUE;
+ in_quotes = true;
++idx;
}
void
output_file_close (const char *filename)
{
- bfd_boolean res;
+ bool res;
if (stdoutput == NULL)
return;
#endif
char *input_line_pointer; /*->next char of source file to parse. */
-bfd_boolean input_from_string = FALSE;
+bool input_from_string = false;
#if BITS_PER_CHAR != 8
/* The following table is indexed by[(char)] and will break if
#endif /* HANDLE_BUNDLE */
-static bfd_boolean
+static bool
in_bss (void)
{
flagword flags = bfd_section_flags (now_seg);
#endif
while (input_line_pointer < buffer_limit)
{
- bfd_boolean was_new_line;
+ bool was_new_line;
/* We have more of this buffer to parse. */
/* We now have input_line_pointer->1st char of next line.
input_line_pointer = buf;
buffer_limit = buf + strlen (buf);
- input_from_string = TRUE;
+ input_from_string = true;
}
/* Restore a saved input line pointer. */
input_line_pointer = saved_ilp;
buffer_limit = saved_limit;
- input_from_string = FALSE;
+ input_from_string = false;
saved_ilp = NULL;
}
02110-1301, USA. */
extern char *input_line_pointer; /* -> char we are parsing now. */
-extern bfd_boolean input_from_string;
+extern bool input_from_string;
/* Define to make whitespace be allowed in many syntactically
unnecessary places. Normally undefined. For compatibility with
extern void pop_insert (const pseudo_typeS *);
extern unsigned int get_stab_string_offset
- (const char *, const char *, bfd_boolean);
+ (const char *, const char *, bool);
extern void aout_process_stab (int, const char *, int, int, int);
extern char *demand_copy_string (int *lenP);
extern char *demand_copy_C_string (int *len_pointer);
stabs_generate_asm_lineno emits function relative line number stabs.
Otherwise it emits line number stabs with absolute addresses. Note that
both cases only apply to assembler code assembled with -gstabs. */
-static bfd_boolean in_dot_func_p = FALSE;
+static bool in_dot_func_p = false;
/* Label at start of current function if in_dot_func_p != FALSE. */
static const char *current_function_label;
unsigned int
get_stab_string_offset (const char *string, const char *stabstr_secname,
- bfd_boolean free_stabstr_secname)
+ bool free_stabstr_secname)
{
unsigned int length;
unsigned int retval;
void
stabs_generate_asm_func (const char *funcname, const char *startlabname)
{
- static bfd_boolean void_emitted_p = FALSE;
+ static bool void_emitted_p = false;
char *buf;
unsigned int lineno;
temp_ilp ((char *) "\"void:t1=1\",128,0,0,0");
s_stab ('s');
restore_ilp ();
- void_emitted_p = TRUE;
+ void_emitted_p = true;
}
as_where (&lineno);
free (buf);
current_function_label = xstrdup (startlabname);
- in_dot_func_p = TRUE;
+ in_dot_func_p = true;
}
/* Emit a stab to record the end of a function. */
restore_ilp ();
free (buf);
- in_dot_func_p = FALSE;
+ in_dot_func_p = false;
current_function_label = NULL;
}
|| (EXTERN_FORCE_RELOC
&& (s->bsym->flags & BSF_GLOBAL) != 0)))
|| (s->bsym->flags & BSF_GNU_INDIRECT_FUNCTION) != 0)
- return TRUE;
+ return true;
sec = s->bsym->section;
}
return bfd_is_und_section (sec) || bfd_is_com_section (sec);
RELOC_ENUM r_type /* Relocation type. */)
{
return fix_new_internal (frag, where, size, add_symbol,
- (symbolS *) NULL, offset, pcrel, r_type, FALSE);
+ (symbolS *) NULL, offset, pcrel, r_type, false);
}
/* Create a fixup for an expression. Currently we only support fixups
}
return fix_new_internal (frag, where, size, add, sub, off, pcrel,
- r_type, FALSE);
+ r_type, false);
}
/* Create a fixup at the beginning of FRAG. The arguments are the same
offsetT offset, int pcrel, RELOC_ENUM r_type)
{
return fix_new_internal (frag, 0, size, add_symbol,
- (symbolS *) NULL, offset, pcrel, r_type, TRUE);
+ (symbolS *) NULL, offset, pcrel, r_type, true);
}
/* Generic function to determine whether a fixup requires a relocation. */
int nsyms;
asymbol **asympp;
symbolS *symp;
- bfd_boolean result;
+ bool result;
/* Count symbols. We can't rely on a count made by the loop in
write_object_file, because *_frob_file may add a new symbol or
return;
/* Create a GNU Build Attribute section. */
- sec = subseg_new (GNU_BUILD_ATTRS_SECTION_NAME, FALSE);
+ sec = subseg_new (GNU_BUILD_ATTRS_SECTION_NAME, false);
elf_section_type (sec) = SHT_NOTE;
bfd_set_section_flags (sec, (SEC_READONLY | SEC_HAS_CONTENTS | SEC_DATA
| SEC_OCTETS));
if (symbol_rootP)
{
symbolS *symp;
- bfd_boolean skip_next_symbol = FALSE;
+ bool skip_next_symbol = false;
for (symp = symbol_rootP; symp; symp = symbol_next (symp))
{
/* Don't do anything besides moving the value of the
symbol from the GAS value-field to the BFD value-field. */
symbol_get_bfdsym (symp)->value = S_GET_VALUE (symp);
- skip_next_symbol = FALSE;
+ skip_next_symbol = false;
continue;
}
symbol warned about. Don't let anything object-format or
target-specific muck with it; it's ready for output. */
if (symbol_get_bfdsym (symp)->flags & BSF_WARNING)
- skip_next_symbol = TRUE;
+ skip_next_symbol = true;
}
}
projects / binutils-gdb.git / commitdiff