Added $bu0 cell to simlib.v

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 034244ca62e9fcc76b6df8dcd52ddc89d6b58134..f3d652f0e06d7fbc54134e8109dff70916380802 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -53,6 +53,28 @@ assign Y = ~A_BUF.val;
 endmodule
 
 
+// --------------------------------------------------------
+
+module \$bu0 (A, Y);
+
+parameter A_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+`INPUT_A
+output [Y_WIDTH-1:0] Y;
+
+generate
+       if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A
+               assign Y[A_WIDTH-1:0] = A_BUF.val;
+               assign Y[Y_WIDTH-1:A_WIDTH] = 0;
+       end else begin:B
+               assign Y = +A_BUF.val;
+       end
+endgenerate
+
+endmodule
+
 // --------------------------------------------------------
 
 module \$pos (A, Y);