+2017-03-21 Ivo Raisr <ivo.raisr@oracle.com>
+
+ PR tdep/20928
+ * gdb/sparc-tdep.h (gdbarch_tdep) <sparc64_ccr_type>: New field.
+ * gdb/sparc64-tdep.c (sparc64_ccr_type): New function.
+ (sparc64_fsr_type): Fix %fsr decoding.
+
2017-03-21 Tim Wiederhake <tim.wiederhake@intel.com>
* python/py-record-btrace.c (btpy_insn_data): Change return type
/* ISA-specific data types. */
struct type *sparc_psr_type;
struct type *sparc_fsr_type;
+ struct type *sparc64_ccr_type;
struct type *sparc64_pstate_type;
struct type *sparc64_fsr_type;
struct type *sparc64_fprs_type;
return tdep->sparc64_pstate_type;
}
+static struct type *
+sparc64_ccr_type (struct gdbarch *gdbarch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (tdep->sparc64_ccr_type == NULL)
+ {
+ struct type *type;
+
+ type = arch_flags_type (gdbarch, "builtin_type_sparc64_ccr", 8);
+ append_flags_type_flag (type, 0, "icc.c");
+ append_flags_type_flag (type, 1, "icc.v");
+ append_flags_type_flag (type, 2, "icc.z");
+ append_flags_type_flag (type, 3, "icc.n");
+ append_flags_type_flag (type, 4, "xcc.c");
+ append_flags_type_flag (type, 5, "xcc.v");
+ append_flags_type_flag (type, 6, "xcc.z");
+ append_flags_type_flag (type, 7, "xcc.n");
+
+ tdep->sparc64_ccr_type = type;
+ }
+
+ return tdep->sparc64_ccr_type;
+}
+
static struct type *
sparc64_fsr_type (struct gdbarch *gdbarch)
{
struct type *type;
type = arch_flags_type (gdbarch, "builtin_type_sparc64_fsr", 8);
- append_flags_type_flag (type, 0, "NXA");
- append_flags_type_flag (type, 1, "DZA");
- append_flags_type_flag (type, 2, "UFA");
- append_flags_type_flag (type, 3, "OFA");
- append_flags_type_flag (type, 4, "NVA");
- append_flags_type_flag (type, 5, "NXC");
- append_flags_type_flag (type, 6, "DZC");
- append_flags_type_flag (type, 7, "UFC");
- append_flags_type_flag (type, 8, "OFC");
- append_flags_type_flag (type, 9, "NVC");
+ append_flags_type_flag (type, 0, "NXC");
+ append_flags_type_flag (type, 1, "DZC");
+ append_flags_type_flag (type, 2, "UFC");
+ append_flags_type_flag (type, 3, "OFC");
+ append_flags_type_flag (type, 4, "NVC");
+ append_flags_type_flag (type, 5, "NXA");
+ append_flags_type_flag (type, 6, "DZA");
+ append_flags_type_flag (type, 7, "UFA");
+ append_flags_type_flag (type, 8, "OFA");
+ append_flags_type_flag (type, 9, "NVA");
append_flags_type_flag (type, 22, "NS");
append_flags_type_flag (type, 23, "NXM");
append_flags_type_flag (type, 24, "DZM");
if (regnum == SPARC64_ASI_REGNUM)
return builtin_type (gdbarch)->builtin_int64;
if (regnum == SPARC64_CCR_REGNUM)
- return builtin_type (gdbarch)->builtin_int64;
+ return sparc64_ccr_type (gdbarch);
if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D62_REGNUM)
return builtin_type (gdbarch)->builtin_double;
if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q60_REGNUM)
+2017-03-21 Ivo Raisr <ivo.raisr@oracle.com>
+
+ PR tdep/20928
+ * gdb.arch/sparc64-regs.exp: New file.
+ * gdb.arch/sparc64-regs.S: Likewise.
+
2017-03-21 Tim Wiederhake <tim.wiederhake@intel.com>
* gdb.python/py-record-btrace.exp: Check for buffer on Python 2
--- /dev/null
+/* Copyright 2017 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+ This file is part of the gdb testsuite.
+ KAT for decoding various sparc64 registers. */
+
+.section ".text"
+.align 4
+
+.global main
+.type main, #function
+main:
+ call test_ccr
+ nop
+ call test_fsr
+ nop
+ retl
+ nop
+.size main, .-main
+
+.type test_ccr, #function
+test_ccr:
+ .cfi_startproc
+ wr %g0, 0x01, %ccr
+ wr %g0, 0x02, %ccr
+ wr %g0, 0x03, %ccr
+ wr %g0, 0x04, %ccr
+ wr %g0, 0x05, %ccr
+ wr %g0, 0x06, %ccr
+ wr %g0, 0x07, %ccr
+ wr %g0, 0x08, %ccr
+ wr %g0, 0x09, %ccr
+ wr %g0, 0x0a, %ccr
+ wr %g0, 0x0b, %ccr
+ wr %g0, 0x0c, %ccr
+ wr %g0, 0x0d, %ccr
+ wr %g0, 0x0e, %ccr
+ wr %g0, 0x0f, %ccr
+
+ wr %g0, 0x10, %ccr
+ wr %g0, 0x20, %ccr
+ wr %g0, 0x30, %ccr
+ wr %g0, 0x40, %ccr
+ wr %g0, 0x50, %ccr
+ wr %g0, 0x60, %ccr
+ wr %g0, 0x70, %ccr
+ wr %g0, 0x80, %ccr
+ wr %g0, 0x90, %ccr
+ wr %g0, 0xa0, %ccr
+ wr %g0, 0xb0, %ccr
+ wr %g0, 0xc0, %ccr
+ wr %g0, 0xd0, %ccr
+ wr %g0, 0xe0, %ccr
+ wr %g0, 0xf0, %ccr
+
+ retl
+ nop
+ .cfi_endproc
+.size test_ccr, .-test_ccr
+
+.type test_fsr, #function
+test_fsr:
+ .cfi_startproc
+ wr %g0, 4, %fprs
+ setx flags, %l1, %l0
+ mov 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1 ! sparc64-regs.exp: after first %fsr
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 14, %l1 ! move to fsr.tem fields
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+ stx %l1, [%l0]
+ ldx [%l0], %fsr
+ sllx %l1, 1, %l1
+
+ retl
+ nop
+ .cfi_endproc
+.size test_fsr, .-test_fsr
+
+.section ".data"
+.align 8
+flags: .xword 0x0000000000000000
+.size flags, .-flags
--- /dev/null
+# Copyright 2017 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This file is part of the gdb testsuite.
+
+# Tests decoding of various sparc64 registers.
+# At the moment, only few registers are tested, but more can be added in future.
+
+if ![istarget "sparc64*-*-linux*"] then {
+ verbose "Skipping sparc64 register tests."
+ return 0
+}
+
+standard_testfile .S
+
+set additional_flags "-Wa,-g"
+
+if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile} \
+ [list debug $additional_flags]] } {
+ return -1
+}
+
+if ![runto_main] then {
+ untested "could not run to main"
+ return 0
+}
+
+##########################################
+gdb_test "break $srcfile:test_ccr" "Breakpoint \[0-9\] at .*"
+gdb_test "continue" "Continuing.*"
+gdb_test "si" "wr .*" "single step to the first %ccr test"
+
+proc test_ccr {exp_value exp_text {exp_insn "wr .*"}} {
+ gdb_test "info register ccr" \
+ "ccr $exp_value .*$exp_text.*" \
+ "check %ccr register value equal to $exp_text"
+
+ gdb_test "si" "$exp_insn" "single step to a next %ccr test after $exp_text"
+}
+
+test_ccr "0x1" "icc.c"
+test_ccr "0x2" "icc.v"
+test_ccr "0x3" "icc.c icc.v"
+test_ccr "0x4" "icc.z"
+test_ccr "0x5" "icc.c icc.z"
+test_ccr "0x6" "icc.v icc.z"
+test_ccr "0x7" "icc.c icc.v icc.z"
+test_ccr "0x8" "icc.n"
+test_ccr "0x9" "icc.c icc.n"
+test_ccr "0xa" "icc.v icc.n"
+test_ccr "0xb" "icc.c icc.v icc.n"
+test_ccr "0xc" "icc.z icc.n"
+test_ccr "0xd" "icc.c icc.z icc.n"
+test_ccr "0xe" "icc.v icc.z icc.n"
+test_ccr "0xf" "icc.c icc.v icc.z icc.n"
+
+test_ccr "0x10" "xcc.c"
+test_ccr "0x20" "xcc.v"
+test_ccr "0x30" "xcc.c xcc.v"
+test_ccr "0x40" "xcc.z"
+test_ccr "0x50" "xcc.c xcc.z"
+test_ccr "0x60" "xcc.v xcc.z"
+test_ccr "0x70" "xcc.c xcc.v xcc.z"
+test_ccr "0x80" "xcc.n"
+test_ccr "0x90" "xcc.c xcc.n"
+test_ccr "0xa0" "xcc.v xcc.n"
+test_ccr "0xb0" "xcc.c xcc.v xcc.n"
+test_ccr "0xc0" "xcc.z xcc.n"
+test_ccr "0xd0" "xcc.c xcc.z xcc.n"
+test_ccr "0xe0" "xcc.v xcc.z xcc.n" "retl"
+test_ccr "0xf0" "xcc.c xcc.v xcc.z xcc.n" "nop"
+##########################################
+
+
+##########################################
+set lno [gdb_get_line_number "sparc64-regs.exp: after first %fsr" $srcfile]
+gdb_test "break $srcfile:$lno" "Breakpoint \[0-9\] at .*" \
+ "forward breakpoint to first %fsr test"
+gdb_test "continue" "Continuing.*"
+
+proc test_fsr {exp_value exp_text} {
+ gdb_test "info register fsr" \
+ "fsr $exp_value .*$exp_text.*" \
+ "check %fsr register value equal to $exp_text"
+
+ gdb_test "si" "stx .*" "single step to a next %fsr test (I.) after $exp_text"
+ gdb_test "si" "ldx .*" "single step to a next %fsr test (II.) after $exp_text"
+ gdb_test "si" "sllx .*" "single step to a next %fsr test (III.) after $exp_text"
+}
+
+test_fsr "0x1" "NXC"
+test_fsr "0x2" "DZC"
+test_fsr "0x4" "UFC"
+test_fsr "0x8" "OFC"
+test_fsr "0x10" "NVC"
+test_fsr "0x20" "NXA"
+test_fsr "0x40" "DZA"
+test_fsr "0x80" "UFA"
+test_fsr "0x100" "OFA"
+test_fsr "0x200" "NVA"
+test_fsr "0x800000" "NXM"
+test_fsr "0x1000000" "DZM"
+test_fsr "0x2000000" "UFM"
+test_fsr "0x4000000" "OFM"
+test_fsr "0x8000000" "NVM"
+##########################################
projects / binutils-gdb.git / commitdiff