+++ /dev/null
-<hr size="1"><address style="align: right;"><small>
-Generated on $datetime for $projectname by <a href="http://www.doxygen.org/index.html"> doxygen</a> $doxygenversion</small></address>
-
-</body>
-</html>
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
- * Nathan Binkert
- */
-
-/**
- * @file
- * Dummy definitions of STL classes to pick up relationships in doxygen.
- */
-
-namespace std {
-
-/** STL vector class*/
-template <class T> class vector {
- public:
- /** Dummy Item */
- T item;
-};
-
-/** STL deque class */
-template <class T> class deque {
- public:
- /** Dummy Item */
- T item;
-};
-
-/** STL list class */
-template <class T> class list {
- public:
- /** Dummy Item */
- T item;
-};
-
-/** STL pair class */
-template <class X, class Y> class pair {
- public:
- /** Dummy Item */
- X item1;
- /** Dummy Item */
- Y item2;
-};
-
-}
# If a relative path is entered, it will be relative to the location
# where doxygen was started. If left blank the current directory will be used.
-OUTPUT_DIRECTORY = docs/doxygen
+OUTPUT_DIRECTORY = doxygen
# The OUTPUT_LANGUAGE tag is used to specify the language in which all
# documentation generated by doxygen is written. Doxygen will use this
# each generated HTML page. If it is left blank doxygen will generate a
# standard footer.
-HTML_FOOTER = docs/footer.html
+HTML_FOOTER = doxygen/footer.html
# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
# style sheet that is used by each HTML page. It can be used to
int64_t time;
SparcSystem *sys;
switch (miscReg) {
- /** Full system only ASRs */
+ /* Full system only ASRs */
case MISCREG_SOFTINT:
if (isNonPriv())
return new PrivilegedOpcode;
sTickCompare.schedule(time * Clock::Int::ns);
return NoFault;
- /** Fullsystem only Priv registers. */
+ /* Fullsystem only Priv registers. */
case MISCREG_PIL:
if (FULL_SYSTEM) {
setReg(miscReg, val);
} else
panic("PIL not implemented for syscall emulation\n");
- /** Hyper privileged registers */
+ /* Hyper privileged registers */
case MISCREG_HPSTATE:
case MISCREG_HINTP:
setReg(miscReg, val);
{
switch (miscReg) {
- /** Privileged registers. */
+ /* Privileged registers. */
case MISCREG_SOFTINT:
if (isNonPriv()) {
fault = new PrivilegedOpcode;
return readReg(miscReg);
- /** Hyper privileged registers */
+ /* Hyper privileged registers */
case MISCREG_HPSTATE:
case MISCREG_HINTP:
return readReg(miscReg);
public:
/**
* Constructor.
- * @param startAddr The starting address of the region.
+ * @param _startAddr The starting address of the region.
* @param totalSize The total size of the region.
* @param _chunkSize The size/alignment of chunks into which
* the region should be decomposed.
/// Find the nearest symbol equal to or less than the supplied
/// address (e.g., the label for the enclosing function).
- /// @param address The address to look up.
- /// @param symbol Return reference for symbol string.
- /// @param sym_address Return reference for symbol address.
- /// @param next_sym_address Address of following symbol (for
- /// determining valid range of symbol).
+ /// @param addr The address to look up.
+ /// @param symbol Return reference for symbol string.
+ /// @param symaddr Return reference for symbol address.
+ /// @param nextaddr Address of following symbol (for
+ /// determining valid range of symbol).
/// @retval True if a symbol was found.
bool
findNearestSymbol(Addr addr, std::string &symbol, Addr &symaddr,
}
/// Overload for findNearestSymbol() for callers who don't care
- /// about next_sym_address.
+ /// about nextaddr.
bool
findNearestSymbol(Addr addr, std::string &symbol, Addr &symaddr) const
{
{}
/** return the address ranges that this device responds to.
- * @params range_list range list to populate with ranges
+ * @param range_list range list to populate with ranges
*/
void addressRanges(AddrRangeList &range_list);
/**
* This read always returns -1.
- * @param req The memory request.
+ * @param pkt The memory request.
* @param data Where to put the data.
*/
virtual Tick read(Packet *pkt);
/**
* All writes are simply ignored.
- * @param req The memory request.
+ * @param pkt The memory request.
* @param data the data to not write.
*/
virtual Tick write(Packet *pkt);
/**
* Constructor for the Tsunami Class.
* @param name name of the object
- * @param intrctrl pointer to the interrupt controller
+ * @param s system the object belongs to
+ * @param intctrl pointer to the interrupt controller
*/
Tsunami(const std::string &name, System *s, IntrControl *intctrl);
/**
* Serialize this object to the given output stream.
+ * @param base The base name of the counter object.
* @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
/**
* Serialize this object to the given output stream.
- * @param os The stream to serialize to.
+ * @param base The base name of the counter object.
+ * @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
/**
* Serialize this object to the given output stream.
+ * @param base The base name of the counter object.
* @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
--- /dev/null
+<hr size="1"><address style="align: right;"><small>
+Generated on $datetime for $projectname by <a href="http://www.doxygen.org/index.html"> doxygen</a> $doxygenversion</small></address>
+
+</body>
+</html>
--- /dev/null
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Erik Hallnor
+ * Nathan Binkert
+ */
+
+/**
+ * @file
+ * Dummy definitions of STL classes to pick up relationships in doxygen.
+ */
+
+namespace std {
+
+/** STL vector class*/
+template <class T> class vector {
+ public:
+ /** Dummy Item */
+ T item;
+};
+
+/** STL deque class */
+template <class T> class deque {
+ public:
+ /** Dummy Item */
+ T item;
+};
+
+/** STL list class */
+template <class T> class list {
+ public:
+ /** Dummy Item */
+ T item;
+};
+
+/** STL pair class */
+template <class X, class Y> class pair {
+ public:
+ /** Dummy Item */
+ X item1;
+ /** Dummy Item */
+ Y item2;
+};
+
+}
*/
/**
- * @file Definition of a simple bus bridge without buffering.
+ * @file
+ * Definition of a simple bus bridge without buffering.
*/
#include <algorithm>
*/
/**
- * @file Decleration of a simple bus bridge object with no buffering
+ * @file
+ * Declaration of a simple bus bridge object with no buffering
*/
#ifndef __MEM_BRIDGE_HH__
class Bridge : public MemObject
{
protected:
- /** Decleration of the buses port type, one will be instantiated for each
+ /** Declaration of the buses port type, one will be instantiated for each
of the interfaces connecting to the bus. */
class BridgePort : public Port
{
*/
/**
- * @file Definition of a bus object.
+ * @file
+ * Definition of a bus object.
*/
*/
/**
- * @file Decleration of a bus object.
+ * @file
+ * Declaration of a bus object.
*/
#ifndef __MEM_BUS_HH__
void addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id);
- /** Decleration of the buses port type, one will be instantiated for each
+ /** Declaration of the buses port type, one will be instantiated for each
of the interfaces connecting to the bus. */
class BusPort : public Port
{
/**
* Send a response to the slave interface.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
* @param time The time the response is ready.
*/
void respond(Packet *pkt, Tick time)
/**
* Send a reponse to the slave interface and calculate miss latency.
- * @param req The request to respond to.
+ * @param pkt The request to respond to.
* @param time The time the response is ready.
*/
void respondToMiss(Packet *pkt, Tick time)
/**
* Suppliess the data if cache to cache transfers are enabled.
- * @param req The bus transaction to fulfill.
+ * @param pkt The bus transaction to fulfill.
*/
void respondToSnoop(Packet *pkt)
{
/**
* Performs the access specified by the request.
- * @param req The request to perform.
+ * @param pkt The request to perform.
* @return The result of the access.
*/
bool access(Packet * &pkt);
/**
* Was the request was sent successfully?
- * @param req The request.
+ * @param pkt The request.
* @param success True if the request was sent successfully.
*/
virtual void sendResult(Packet * &pkt, bool success);
/**
* Handles a response (cache line fill/write ack) from the bus.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
*/
void handleResponse(Packet * &pkt);
/**
* Start handling a copy transaction.
- * @param req The copy request to perform.
+ * @param pkt The copy request to perform.
*/
void startCopy(Packet * &pkt);
/**
* Handle a delayed copy transaction.
- * @param req The delayed copy request to continue.
+ * @param pkt The delayed copy request to continue.
* @param addr The address being responded to.
* @param blk The block of the current response.
* @param mshr The mshr being handled.
/**
* Snoops bus transactions to maintain coherence.
- * @param req The current bus transaction.
+ * @param pkt The current bus transaction.
*/
void snoop(Packet * &pkt);
void invalidateBlk(Addr addr, int asid);
/**
- * Aquash all requests associated with specified thread.
+ * Squash all requests associated with specified thread.
* intended for use by I-cache.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum)
{
* time of completion. This function can either update the hierarchy state
* or just perform the access wherever the data is found depending on the
* state of the update flag.
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
* Snoop for the provided request in the cache and return the estimated
* time of completion.
* @todo Can a snoop probe not change state?
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
/**
* Return the proper state given the current state and the bus response.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param oldState The current block state.
* @return The new state.
*/
/**
* Handle snooped bus requests.
* @param cache The cache that snooped the request.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state The new coherence state of the block.
/**
* Return the proper state given the current state and the bus response.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param current The current block state.
* @return The new state.
*/
/**
* Handle snooped bus requests.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state Return the new state for the block.
/**
* Just return readable and writeable.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param current The current block state.
* @return The new state.
*/
/**
* Handle snooped bus requests.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state The new coherence state of the block.
/**
* Handle a cache miss properly. Requests the bus and marks the cache as
* blocked.
- * @param req The request that missed in the cache.
+ * @param pkt The request that missed in the cache.
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
}
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Selects a outstanding pktuest to service.
+ * @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
/**
* Set the command to the given bus command.
- * @param req The request to update.
+ * @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
- * @param req The request to reset.
+ * @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
/**
- * Marks a request as in service (sent on the bus). This can have side
+ * Marks a pktuest as in service (sent on the bus). This can have side
* effect since storage for no response commands is deallocated once they
* are successfully sent.
- * @param req The request that was sent on the bus.
+ * @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt);
/**
- * Frees the resources of the request and unblock the cache.
- * @param req The request that has been satisfied.
- * @param time The time when the request is satisfied.
+ * Frees the resources of the pktuest and unblock the cache.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
/**
- * Removes all outstanding requests for a given thread number. If a request
+ * Removes all outstanding pktuests for a given thread number. If a request
* has been sent to the bus, this function removes all of its targets.
- * @param req->getThreadNum()ber The thread number of the requests to squash.
+ * @param threadNum The thread number of the requests to squash.
*/
void squash(int threadNum);
int size, uint8_t *data, bool compressed);
/**
- * Perform a writeback request.
- * @param req The writeback request.
+ * Perform a writeback pktuest.
+ * @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
/**
- * Returns true if there are outstanding requests.
- * @return True if there are outstanding requests.
+ * Returns true if there are outstanding pktuests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending()
{
/**
* Add a target to the given MSHR. This assumes it is in the miss queue.
* @param mshr The mshr to add a target to.
- * @param req The target to add.
+ * @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
{
/** The block size of the parent cache. */
int blkSize;
- /** Increasing order number assigned to each incoming request. */
+ /** Increasing order number assigned to each incoming pktuest. */
uint64_t order;
bool prefetchMiss;
/**
* Allocate a new MSHR to handle the provided miss.
- * @param req The miss to buffer.
+ * @param pkt The miss to buffer.
* @param size The number of bytes to fetch.
* @param time The time the miss occurs.
* @return A pointer to the new MSHR.
/**
* Allocate a new WriteBuffer to handle the provided write.
- * @param req The write to handle.
+ * @param pkt The write to handle.
* @param size The number of bytes to write.
* @param time The time the write occurs.
* @return A pointer to the new write buffer.
void setPrefetcher(BasePrefetcher *_prefetcher);
/**
- * Handle a cache miss properly. Either allocate an MSHR for the request,
+ * Handle a cache miss properly. Either allocate an MSHR for the pktuest,
* or forward it through the write buffer.
- * @param req The request that missed in the cache.
+ * @param pkt The request that missed in the cache.
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
Packet * &target);
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Selects a outstanding pktuest to service.
+ * @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
/**
* Set the command to the given bus command.
- * @param req The request to update.
+ * @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
- * @param req The request to reset.
+ * @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
/**
- * Marks a request as in service (sent on the bus). This can have side
+ * Marks a pktuest as in service (sent on the bus). This can have side
* effect since storage for no response commands is deallocated once they
* are successfully sent.
- * @param req The request that was sent on the bus.
+ * @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt);
/**
- * Collect statistics and free resources of a satisfied request.
- * @param req The request that has been satisfied.
- * @param time The time when the request is satisfied.
+ * Collect statistics and free resources of a satisfied pktuest.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
/**
- * Removes all outstanding requests for a given thread number. If a request
+ * Removes all outstanding pktuests for a given thread number. If a request
* has been sent to the bus, this function removes all of its targets.
- * @param req->getThreadNum()ber The thread number of the requests to squash.
+ * @param threadNum The thread number of the requests to squash.
*/
void squash(int threadNum);
int size, uint8_t *data, bool compressed);
/**
- * Perform the given writeback request.
- * @param req The writeback request.
+ * Perform the given writeback pktuest.
+ * @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
/**
- * Returns true if there are outstanding requests.
- * @return True if there are outstanding requests.
+ * Returns true if there are outstanding pktuests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending();
/**
* Add a target to the given MSHR. This assumes it is in the miss queue.
* @param mshr The mshr to add a target to.
- * @param req The target to add.
+ * @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
{
/**
* Miss Status and handling Register. This class keeps all the information
- * needed to handle a cache miss including a list of target requests.
+ * needed to handle a cache miss including a list of target pktuests.
*/
class MSHR {
public:
Addr addr;
/** Adress space id of the miss. */
short asid;
- /** True if the request has been sent to the bus. */
+ /** True if the pktuest has been sent to the bus. */
bool inService;
/** Thread number of the miss. */
int threadNum;
- /** The request that is forwarded to the next level of the hierarchy. */
+ /** The pktuest that is forwarded to the next level of the hierarchy. */
Packet * pkt;
/** The number of currently allocated targets. */
short ntargets;
- /** The original requesting command. */
+ /** The original pktuesting command. */
Packet::Command originalCmd;
/** Order number of assigned by the miss queue. */
uint64_t order;
Iterator allocIter;
private:
- /** List of all requests that match the address */
+ /** List of all pktuests that match the address */
TargetList targets;
public:
/**
* Allocate a miss to this MSHR.
- * @param cmd The requesting command.
+ * @param cmd The pktuesting command.
* @param addr The address of the miss.
* @param asid The address space id of the miss.
- * @param size The number of bytes to request.
- * @param req The original miss.
+ * @param size The number of bytes to pktuest.
+ * @param pkt The original miss.
*/
void allocate(Packet::Command cmd, Addr addr, int asid, int size,
Packet * &pkt);
/**
- * Allocate this MSHR as a buffer for the given request.
- * @param target The memory request to buffer.
+ * Allocate this MSHR as a buffer for the given pktuest.
+ * @param target The memory pktuest to buffer.
*/
void allocateAsBuffer(Packet * &target);
void deallocate();
/**
- * Add a request to the list of targets.
+ * Add a pktuest to the list of targets.
* @param target The target.
*/
void allocateTarget(Packet * &target);
#include "mem/cache/miss/mshr.hh"
/**
- * A Class for maintaining a list of pending and allocated memory requests.
+ * A Class for maintaining a list of pending and allocated memory pktuests.
*/
class MSHRQueue {
private:
// Parameters
/**
* The total number of MSHRs in this queue. This number is set as the
- * number of MSHRs requested plus (numReserve - 1). This allows for
+ * number of MSHRs pktuested plus (numReserve - 1). This allows for
* the same number of effective MSHRs while still maintaining the reserve.
*/
const int numMSHRs;
bool findMatches(Addr addr, int asid, std::vector<MSHR*>& matches) const;
/**
- * Find any pending requests that overlap the given request.
- * @param req The request to find.
+ * Find any pending pktuests that overlap the given request.
+ * @param pkt The request to find.
* @return A pointer to the earliest matching MSHR.
*/
MSHR* findPending(Packet * &pkt) const;
/**
- * Allocates a new MSHR for the request and size. This places the request
+ * Allocates a new MSHR for the pktuest and size. This places the request
* as the first target in the MSHR.
- * @param req The request to handle.
+ * @param pkt The request to handle.
* @param size The number in bytes to fetch from memory.
* @return The a pointer to the MSHR allocated.
*
MSHR* allocate(Packet * &pkt, int size = 0);
/**
- * Allocate a read request for the given address, and places the given
+ * Allocate a read pktuest for the given address, and places the given
* target on the target list.
* @param addr The address to fetch.
* @param asid The address space for the fetch.
- * @param size The number of bytes to request.
- * @param target The first target for the request.
+ * @param size The number of bytes to pktuest.
+ * @param target The first target for the pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateFetch(Addr addr, int asid, int size, Packet * &target);
* Allocate a target list for the given address.
* @param addr The address to fetch.
* @param asid The address space for the fetch.
- * @param size The number of bytes to request.
+ * @param size The number of bytes to pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateTargetList(Addr addr, int asid, int size);
* Allocates a target to the given MSHR. Used to keep track of the number
* of outstanding targets.
* @param mshr The MSHR to allocate the target to.
- * @param req The target request.
+ * @param pkt The target request.
*/
void allocateTarget(MSHR* mshr, Packet * &pkt)
{
void markInService(MSHR* mshr);
/**
- * Mark an in service mshr as pending, used to resend a request.
+ * Mark an in service mshr as pending, used to resend a pktuest.
* @param mshr The MSHR to resend.
* @param cmd The command to resend.
*/
void markPending(MSHR* mshr, Packet::Command cmd);
/**
- * Squash outstanding requests with the given thread number. If a request
+ * Squash outstanding pktuests with the given thread number. If a request
* is in service, just squashes the targets.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum);
/**
* Returns true if the pending list is not empty.
- * @return True if there are outstanding requests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending() const
{
}
/**
- * Returns the request at the head of the pendingList.
- * @return The next request to service.
+ * Returns the pktuest at the head of the pendingList.
+ * @return The next pktuest to service.
*/
Packet * getReq() const
{
/**
* Find the block in the cache and update the replacement data. Returns
* the access latency and the in cache flags as a side effect
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The latency of the access.
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block aligned source address.
* @param dest The block aligned destination adddress.
* @param asid The address space ID.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks)
{
/**
* Find the block and update the replacement data. This call also returns
* the access latency as a side effect.
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
/**
* If a block is currently marked copy on write, copy it before writing.
- * @param req The write request.
- * @param writebacks List for any generated writeback requests.
+ * @param pkt The write request.
+ * @param writebacks List for any generated writeback pktuests.
*/
void fixCopy(Packet * &pkt, PacketList &writebacks);
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The request whose block to find.
+ * @param pkt The request whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
Addr blkMask;
- /** Number of NIC requests that hit in the NIC partition */
+ /** Number of NIC pktuests that hit in the NIC partition */
Stats::Scalar<> NR_NP_hits;
- /** Number of NIC requests that hit in the CPU partition */
+ /** Number of NIC pktuests that hit in the CPU partition */
Stats::Scalar<> NR_CP_hits;
- /** Number of CPU requests that hit in the NIC partition */
+ /** Number of CPU pktuests that hit in the NIC partition */
Stats::Scalar<> CR_NP_hits;
- /** Number of CPU requests that hit in the CPU partition */
+ /** Number of CPU pktuests that hit in the CPU partition */
Stats::Scalar<> CR_CP_hits;
/** The number of nic replacements (i.e. misses) */
Stats::Scalar<> nic_repl;
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The memory request whose block to find
+ * @param pkt The memory request whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
bool isTouched;
/** Has this block been used after being brought in? (for LIFO partition) */
bool isUsed;
- /** is this blk a NIC block? (i.e. requested by the NIC) */
+ /** is this blk a NIC block? (i.e. pktuested by the NIC) */
bool isNIC;
/** timestamp of the arrival of this block into the cache */
Tick ts;
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The req whose block to find.
+ * @param pkt The req whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
/**
* @file
- * Base Memory Object decleration.
+ * Base Memory Object declaration.
*/
#ifndef __MEM_MEM_OBJECT_HH__
class System;
/**
- * Page Table Decleration.
+ * Page Table Declaration.
*/
class PageTable
{
*/
/**
- * @file Port object definitions.
+ * @file
+ * Port object definitions.
*/
#include "base/chunk_generator.hh"
/**
* @file
- * Port Object Decleration. Ports are used to interface memory objects to
+ * Port Object Declaration. Ports are used to interface memory objects to
* each other. They will always come in pairs, and we refer to the other
* port object as the peer. These are used to make the design more
* modular so that a specific interface between every type of objcet doesn't
*/
/**
- * @file Decleration of a request, the overall memory request consisting of
+ * @file
+ * Declaration of a request, the overall memory request consisting of
the parts of the request that are persistent throughout the transaction.
*/
*/
/**
- * @file Port object definitions.
+ * @file
+ * Port object definitions.
*/
#include "base/chunk_generator.hh"
/**
* @file
- * Virtual Port Object Decleration. These ports incorporate some translation
+ * Virtual Port Object Declaration. These ports incorporate some translation
* into their access methods. Thus you can use one to read and write data
* to/from virtual addresses.
*/
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