Merge zizzer:/bk/sparcfs

into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
    hand merge

--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e

diff --cc src/arch/sparc/isa_traits.hh
index 287f9065885e09a4e7b7e51f9f327c25eaf3726d,109fdfae7d0fa067223d4e299014df53c95a9780..2bd7ccf3baf6d7c93e5e84631c7723e4a5cf35f9
--- 1/src/arch/sparc/isa_traits.hh
--- 2/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@@ -93,7 -117,43 +90,31 @@@ namespace SparcIS
  
      const int BranchPredAddrShiftAmt = 2;
  
 -    const int MachineBytes = 8;
 -    const int WordBytes = 4;
 -    const int HalfwordBytes = 2;
 -    const int ByteBytes = 1;
 -
 -    void serialize(std::ostream & os);
 -
 -    void unserialize(Checkpoint *cp, const std::string &section);
 -
      StaticInstPtr decodeInst(ExtMachInst);
 -    // return a no-op instruction... used for instruction fetch faults
 -    extern const MachInst NoopMachInst;
 -
+ 
+ #if FULL_SYSTEM
+     ////////// Interrupt Stuff ///////////
+     enum InterruptLevels
+     {
+        INTLEVEL_MIN = 1,
+        INTLEVEL_MAX = 15,
+ 
+        NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN
+     };
+ 
+     // I don't know what it's for, so I don't
+     // know what SPARC's value should be
+     // For loading... XXX This maybe could be USegEnd?? --ali
+     const Addr LoadAddrMask = ULL(0xffffffffff);
+ 
+     /////////// TLB Stuff ////////////
+     const Addr StartVAddrHole = ULL(0x0000800000000000);
+     const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
+     const Addr VAddrAMask = ULL(0xFFFFFFFF);
+     const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
+     const Addr BytesInPageMask = ULL(0x1FFF);
+ 
+ #endif
  }
  
  #endif // __ARCH_SPARC_ISA_TRAITS_HH__

diff --cc src/arch/sparc/miscregfile.cc
index 7b0939c290d71397d84d1a8f4d5dd4654385d647,93737ad013b066308868903470039c53640b7d08..d2164155f2a257b552b3b88d47f01c14050b9763
--- 1/src/arch/sparc/miscregfile.cc
--- 2/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@@ -99,11 -93,34 +99,35 @@@ void MiscRegFile::clear(
      hintp = 0;
      htba = 0;
      hstick_cmpr = 0;
 -    strandStatusReg = 0;
 +    //This is set this way in Legion for some reason
 +    strandStatusReg = 0x50000;
      fsr = 0;
-     implicitInstAsi = ASI_PRIMARY;
-     implicitDataAsi = ASI_PRIMARY;
+ 
+     priContext = 0;
+     secContext = 0;
+     partId = 0;
+     lsuCtrlReg = 0;
+ 
+     iTlbC0TsbPs0 = 0;
+     iTlbC0TsbPs1 = 0;
+     iTlbC0Config = 0;
+     iTlbCXTsbPs0 = 0;
+     iTlbCXTsbPs1 = 0;
+     iTlbCXConfig = 0;
+     iTlbSfsr = 0;
+     iTlbTagAccess = 0;
+ 
+     dTlbC0TsbPs0 = 0;
+     dTlbC0TsbPs1 = 0;
+     dTlbC0Config = 0;
+     dTlbCXTsbPs0 = 0;
+     dTlbCXTsbPs1 = 0;
+     dTlbCXConfig = 0;
+     dTlbSfsr = 0;
+     dTlbSfar = 0;
+     dTlbTagAccess = 0;
+ 
+     memset(scratchPad, 0, sizeof(scratchPad));
  }
  
  MiscReg MiscRegFile::readReg(int miscReg)
@@@ -382,8 -522,7 +529,7 @@@ void MiscRegFile::setRegWithEffect(int 
            //Set up performance counting based on pcr value
            break;
          case MISCREG_PSTATE:
 -          pstate = val;
 +          pstate = val & PSTATE_MASK;
-           setImplicitAsis();
            return;
          case MISCREG_TL:
            tl = val;

diff --cc src/arch/sparc/miscregfile.hh
index 6bc04b5839384311734e94db21ef3c7d645675c7,9cfe3a8cfecab93d92f36660819cf096ad2a9134..90d7229e008e3d6970276a4fb5163309cc0b7d7b
--- 1/src/arch/sparc/miscregfile.hh
--- 2/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@@ -93,12 -93,42 +92,46 @@@ namespace SparcIS
          /** Floating Point Status Register */
          MISCREG_FSR,
  
+         /** MMU Internal Registers */
+         MISCREG_MMU_P_CONTEXT,
+         MISCREG_MMU_S_CONTEXT,
+         MISCREG_MMU_PART_ID,
+         MISCREG_MMU_LSU_CTRL,
+ 
+         MISCREG_MMU_ITLB_C0_TSB_PS0,
+         MISCREG_MMU_ITLB_C0_TSB_PS1,
+         MISCREG_MMU_ITLB_C0_CONFIG,
+         MISCREG_MMU_ITLB_CX_TSB_PS0,
+         MISCREG_MMU_ITLB_CX_TSB_PS1,
+         MISCREG_MMU_ITLB_CX_CONFIG,
+         MISCREG_MMU_ITLB_SFSR,
+         MISCREG_MMU_ITLB_TAG_ACCESS,
+ 
+         MISCREG_MMU_DTLB_C0_TSB_PS0,
+         MISCREG_MMU_DTLB_C0_TSB_PS1,
+         MISCREG_MMU_DTLB_C0_CONFIG,
+         MISCREG_MMU_DTLB_CX_TSB_PS0,
+         MISCREG_MMU_DTLB_CX_TSB_PS1,
+         MISCREG_MMU_DTLB_CX_CONFIG,
+         MISCREG_MMU_DTLB_SFSR,
+         MISCREG_MMU_DTLB_SFAR,
+         MISCREG_MMU_DTLB_TAG_ACCESS,
+ 
+         /** Scratchpad regiscers **/
+         MISCREG_SCRATCHPAD_R0,
+         MISCREG_SCRATCHPAD_R1,
+         MISCREG_SCRATCHPAD_R2,
+         MISCREG_SCRATCHPAD_R3,
+         MISCREG_SCRATCHPAD_R4,
+         MISCREG_SCRATCHPAD_R5,
+         MISCREG_SCRATCHPAD_R6,
+         MISCREG_SCRATCHPAD_R7
 +        MISCREG_NUMMISCREGS
      };
  
 +    const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
 +    const int NumMiscRegs = MISCREG_NUMMISCREGS;
 +
      // The control registers, broken out into fields
      class MiscRegFile
      {