opt_clean: improve warning message

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 72ecc30e7cd3aa7803f5a9c2f4c92ed81d670477..f7de02164e60ca278370c5c4b705dcc550d66d30 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -473,7 +473,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
                                        goto next_wire;
 
                                if (mapped_wire_bit != init[i]) {
-                                       log_warning("Initial value conflict for wire '%s' and value '%s'.\n", log_signal(wire_bit), log_signal(mapped_wire_bit));
+                                       log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i]));
                                        goto next_wire;
                                }
                        }

diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys
index bfc3839557b181824c279cff3846ffd7cb6e562d..0d567608d44664565f71fbeb3e722df7efd594c3 100644 (file)
--- a/tests/opt/opt_clean_init.ys
+++ b/tests/opt/opt_clean_init.ys
@@ -1,4 +1,4 @@
-logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1
+logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1
 logger -expect-no-warnings
 read_verilog <<EOT
 module top;