(no commit message)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 86f219a102138ddac2d3f60c6620a02063b73f31..bdb4b0fcafb1ac13edfd9c20b436cb6873301958 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -61,7 +61,7 @@ result.
         setvl target
         sv.addi/sm=1<<r3 t0, src1.v, 0 # copy src1[i]
         sv.cmpi src2.v, t0 # compare src2 vector to scalar
-        mfcrweird t1, cr0.v, eq # copy CR eq result bits to t1
+        sv.mfcrweird t1, cr0.v, eq # copy CR eq result bits to t1
         srr t1, t1, i # shift up by i before ORing
         or result, result, t1
         srr r3, r3, 1 # shift r3 predicate up by one