fhdl: export log2_int

diff --git a/migen/bus/wishbone2asmi.py b/migen/bus/wishbone2asmi.py
index 23544d0d0857755b5c4d9f59393ebde76d96b268..178925a27307db8f4584a03fbd840b822ed2e9af 100644 (file)
--- a/migen/bus/wishbone2asmi.py
+++ b/migen/bus/wishbone2asmi.py
@@ -4,17 +4,6 @@ from migen.corelogic.fsm import FSM
 from migen.corelogic.misc import split, displacer, chooser
 from migen.corelogic.record import Record
 
-def _log2_int(n):
-       l = 1
-       r = 0
-       while l < n:
-               l *= 2
-               r += 1
-       if l == n:
-               return r
-       else:
-               raise ValueError("Not a power of 2")
-
 # cachesize (in 32-bit words) is the size of the data store, must be a power of 2
 class WB2ASMI:
        def __init__(self, cachesize, asmiport):
@@ -37,9 +26,9 @@ class WB2ASMI:
                
                # Split address:
                # TAG | LINE NUMBER | LINE OFFSET
-               offsetbits = _log2_int(adw//32)
+               offsetbits = log2_int(adw//32)
                addressbits = aaw + offsetbits
-               linebits = _log2_int(self.cachesize) - offsetbits
+               linebits = log2_int(self.cachesize) - offsetbits
                tagbits = aaw - linebits
                adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
                

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 748ea059de70f9745453d7158581df8cbdc6d824..89545c7931341e68d8f3a7e7e48f6483dac8572b 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -4,6 +4,17 @@ import re
 
 from migen.fhdl import tracer
 
+def log2_int(n):
+       l = 1
+       r = 0
+       while l < n:
+               l *= 2
+               r += 1
+       if l == n:
+               return r
+       else:
+               raise ValueError("Not a power of 2")
+
 def bits_for(n):
        if isinstance(n, Constant):
                return n.bv.width