Optimise

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ce93ffb2820b22e4ceff122d3f7164916863b9c9..06496dbc3449c8e62d569cfd5a508d2a94922cf3 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -585,18 +585,17 @@ struct XAigerWriter
                                if (holes_module && !holes_module->cell(stringf("\\u%d", box_id)))
                                        holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
                                RTLIL::Wire *holes_wire;
-                               int num_inputs = 0;
                                // NB: cell->connections_ already sorted from before
                                for (const auto &c : cell->connections()) {
+                                       log_assert(c.second.size() == 1);
                                        if (cell->input(c.first)) {
                                                box_inputs += c.second.size();
                                                if (holes_cell) {
-                                                       holes_wire = holes_module->wire(stringf("\\i%d", num_inputs));
+                                                       holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
                                                        if (!holes_wire) {
-                                                               holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
+                                                               holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
                                                                holes_wire->port_input = true;
                                                        }
-                                                       ++num_inputs;
                                                        holes_cell->setPort(c.first, holes_wire);
                                                }
                                        }