nv10: fixes.

diff --git a/src/gallium/drivers/nv10/nv10_context.h b/src/gallium/drivers/nv10/nv10_context.h
index 8269d6121f0f130cb1061f2ac2e8ece5fce29803..386138556e5daf34eba1ed49137d81f1f62a8b75 100644 (file)
--- a/src/gallium/drivers/nv10/nv10_context.h
+++ b/src/gallium/drivers/nv10/nv10_context.h
@@ -47,11 +47,12 @@ struct nv10_context {
        uint32_t rt_enable;
        struct pipe_buffer *rt[4];
        struct pipe_buffer *zeta;
+       uint32_t lma_offset;
 
        struct {
                struct pipe_buffer *buffer;
                uint32_t format;
-       } tex[16];
+       } tex[2];
 
        unsigned vb_enable;
        struct {

diff --git a/src/gallium/drivers/nv10/nv10_state_emit.c b/src/gallium/drivers/nv10/nv10_state_emit.c
index 1d104e2f913f0ca35f23c7ad127a69e98bef68de..8bf0bd2d6834940124672ebb4b40350e5dde0268 100644 (file)
--- a/src/gallium/drivers/nv10/nv10_state_emit.c
+++ b/src/gallium/drivers/nv10/nv10_state_emit.c
@@ -49,21 +49,21 @@ nv10_emit_hw_state(struct nv10_context *nv10)
                OUT_RELOCl(nv10->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
                /* XXX for when we allocate LMA on nv17 */
 /*             BEGIN_RING(celsius, NV10TCL_LMA_DEPTH_OFFSET, 1);
-               OUT_RELOCl(nv10->zeta+...);*/
+               OUT_RELOCl(nv10->zeta+lma_offset);*/
        }
 
        /* Texture images */
        for (i = 0; i < 2; i++) {
                if (!(nv10->fp_samplers & (1 << i)))
                        continue;
-               BEGIN_RING(celsius, NV10TCL_TX_OFFSET(i), 2);
+               BEGIN_RING(celsius, NV10TCL_TX_OFFSET(i), 1);
                OUT_RELOCl(nv10->tex[i].buffer, 0, NOUVEAU_BO_VRAM |
                           NOUVEAU_BO_GART | NOUVEAU_BO_RD);
-               // XXX
-/*             OUT_RELOCd(nv10->tex[i].buffer, nv10->tex[i].format,
+               BEGIN_RING(celsius, NV10TCL_TX_FORMAT(i), 1);
+               OUT_RELOCd(nv10->tex[i].buffer, nv10->tex[i].format,
                           NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
                           NOUVEAU_BO_OR, NV10TCL_TX_FORMAT_DMA0,
-                          NV10TCL_TX_FORMAT_DMA1);*/
+                          NV10TCL_TX_FORMAT_DMA1);
        }
 }