invoke.texi (SPARC Options): Document -mfix-ut699.

	* doc/invoke.texi (SPARC Options): Document -mfix-ut699.
	* builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the
	mode if the instruction isn't available in the original mode.
	* config/sparc/sparc.opt (mfix-ut699): New option.
	* config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699.
	(divdf3): Turn into expander.
	(divdf3_nofix): New insn.
	(divdf3_fix): Likewise.
	(divsf3): Disable if -mfix-ut699.
	(sqrtdf2): Turn into expander.
	(sqrtdf2_nofix): New insn.
	(sqrtdf2_fix): Likewise.
	(sqrtsf2): Disable if -mfix-ut699.

From-SVN: r199366

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b94d492f6590d9907f3bfde337af897a06ea36f4..40ebbf3f83c5e6c4408b78f23b7ac3c23477e90d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2013-05-28  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * doc/invoke.texi (SPARC Options): Document -mfix-ut699.
+       * builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the
+       mode if the instruction isn't available in the original mode.
+       * config/sparc/sparc.opt (mfix-ut699): New option.
+       * config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699.
+       (divdf3): Turn into expander.
+       (divdf3_nofix): New insn.
+       (divdf3_fix): Likewise.
+       (divsf3): Disable if -mfix-ut699.
+       (sqrtdf2): Turn into expander.
+       (sqrtdf2_nofix): New insn.
+       (sqrtdf2_fix): Likewise.
+       (sqrtsf2): Disable if -mfix-ut699.
+
 2013-05-27  Richard Biener  <rguenther@suse.de>
 
        PR middle-end/57412

diff --git a/gcc/builtins.c b/gcc/builtins.c
index 1fbd2f32eddf80ccf4fe8cefa1dcbbac88aa235a..402bb1fb14762e1b50d6fa84abff8673845f0d74 100644 (file)
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -1961,6 +1961,7 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
   tree fndecl = get_callee_fndecl (exp);
   enum machine_mode mode;
   bool errno_set = false;
+  bool try_widening = false;
   tree arg;
 
   if (!validate_arglist (exp, REAL_TYPE, VOID_TYPE))
@@ -1972,6 +1973,7 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
     {
     CASE_FLT_FN (BUILT_IN_SQRT):
       errno_set = ! tree_expr_nonnegative_p (arg);
+      try_widening = true;
       builtin_optab = sqrt_optab;
       break;
     CASE_FLT_FN (BUILT_IN_EXP):
@@ -2028,8 +2030,10 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
   if (! flag_errno_math || ! HONOR_NANS (mode))
     errno_set = false;
 
-  /* Before working hard, check whether the instruction is available.  */
-  if (optab_handler (builtin_optab, mode) != CODE_FOR_nothing
+  /* Before working hard, check whether the instruction is available, but try
+     to widen the mode for specific operations.  */
+  if ((optab_handler (builtin_optab, mode) != CODE_FOR_nothing
+       || (try_widening && !excess_precision_type (TREE_TYPE (exp))))
       && (!errno_set || !optimize_insn_for_size_p ()))
     {
       rtx result = gen_reg_rtx (mode);

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 292cb2052717e6642e2d6136062e860d086108f8..f710cc7b6b2edb33bd31f5dc5ad4357aee6ba4fe 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -5499,7 +5499,7 @@
   [(set (match_operand:DF 0 "register_operand" "=e")
        (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
                 (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
-  "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
+  "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699"
   "fsmuld\t%1, %2, %0"
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
@@ -5528,20 +5528,37 @@
   "fdivq\t%1, %2, %0"
   [(set_attr "type" "fpdivd")])
 
-(define_insn "divdf3"
+(define_expand "divdf3"
   [(set (match_operand:DF 0 "register_operand" "=e")
        (div:DF (match_operand:DF 1 "register_operand" "e")
                (match_operand:DF 2 "register_operand" "e")))]
   "TARGET_FPU"
+  "")
+
+(define_insn "*divdf3_nofix"
+  [(set (match_operand:DF 0 "register_operand" "=e")
+       (div:DF (match_operand:DF 1 "register_operand" "e")
+               (match_operand:DF 2 "register_operand" "e")))]
+  "TARGET_FPU && !sparc_fix_ut699"
   "fdivd\t%1, %2, %0"
   [(set_attr "type" "fpdivd")
    (set_attr "fptype" "double")])
 
+(define_insn "*divdf3_fix"
+  [(set (match_operand:DF 0 "register_operand" "=e")
+       (div:DF (match_operand:DF 1 "register_operand" "e")
+               (match_operand:DF 2 "register_operand" "e")))]
+  "TARGET_FPU && sparc_fix_ut699"
+  "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]"
+  [(set_attr "type" "fpdivd")
+   (set_attr "fptype" "double")
+   (set_attr "length" "2")])
+
 (define_insn "divsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (div:SF (match_operand:SF 1 "register_operand" "f")
                (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
+  "TARGET_FPU && !sparc_fix_ut699"
   "fdivs\t%1, %2, %0"
   [(set_attr "type" "fpdivs")])
 
@@ -5742,18 +5759,33 @@
   "fsqrtq\t%1, %0"
   [(set_attr "type" "fpsqrtd")])
 
-(define_insn "sqrtdf2"
+(define_expand "sqrtdf2"
   [(set (match_operand:DF 0 "register_operand" "=e")
        (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
   "TARGET_FPU"
+  "")
+
+(define_insn "*sqrtdf2_nofix"
+  [(set (match_operand:DF 0 "register_operand" "=e")
+       (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
+  "TARGET_FPU && !sparc_fix_ut699"
   "fsqrtd\t%1, %0"
   [(set_attr "type" "fpsqrtd")
    (set_attr "fptype" "double")])
 
+(define_insn "*sqrtdf2_fix"
+  [(set (match_operand:DF 0 "register_operand" "=e")
+       (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
+  "TARGET_FPU && sparc_fix_ut699"
+  "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]"
+  [(set_attr "type" "fpsqrtd")
+   (set_attr "fptype" "double")
+   (set_attr "length" "2")])
+
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_FPU"
+  "TARGET_FPU && !sparc_fix_ut699"
   "fsqrts\t%1, %0"
   [(set_attr "type" "fpsqrts")])
 

diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 764c652e83773b220a64c008dcb202026684f2b5..3b50c6c21f9d1e111194649a3fb6415a84f228a1 100644 (file)
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -201,6 +201,10 @@ Target Report RejectNegative Var(sparc_fix_at697f)
 Enable workaround for single erratum of AT697F processor
 (corresponding to erratum #13 of AT697E processor)
 
+mfix-ut699
+Target Report RejectNegative Var(sparc_fix_ut699)
+Enable workarounds for the FP errata of the UT699 processor
+
 Mask(LONG_DOUBLE_128)
 ;; Use 128-bit long double
 

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 5ca55d9e58b6c9f8daafda2387b1ddb2d3fd0868..b0fff0db4def02ada9f2a98b9dd1d16c5843e8c6 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -936,7 +936,7 @@ See RS/6000 and PowerPC Options.
 -mvis2  -mno-vis2  -mvis3  -mno-vis3 @gol
 -mcbcond -mno-cbcond @gol
 -mfmaf  -mno-fmaf  -mpopc  -mno-popc @gol
--mfix-at697f}
+-mfix-at697f -mfix-ut699}
 
 @emph{SPU Options}
 @gccoptlist{-mwarn-reloc -merror-reloc @gol
@@ -19449,6 +19449,11 @@ later.
 @opindex mfix-at697f
 Enable the documented workaround for the single erratum of the Atmel AT697F
 processor (which corresponds to erratum #13 of the AT697E processor).
+
+@item -mfix-ut699
+@opindex mfix-ut699
+Enable the documented workarounds for the floating-point errata of the UT699
+processor.
 @end table
 
 These @samp{-m} options are supported in addition to the above