ip_cksum_add(const void *buf, size_t len, int cksum)
{
uint16_t *sp = (uint16_t *)buf;
- int n, sn;
+ int sn;
sn = len / 2;
- n = (sn + 15) / 16;
-
- /* XXX - unroll loop using Duff's device. */
- switch (sn % 16) {
- case 0: do {
- cksum += *sp++;
- case 15:
- cksum += *sp++;
- case 14:
- cksum += *sp++;
- case 13:
- cksum += *sp++;
- case 12:
- cksum += *sp++;
- case 11:
- cksum += *sp++;
- case 10:
- cksum += *sp++;
- case 9:
- cksum += *sp++;
- case 8:
- cksum += *sp++;
- case 7:
- cksum += *sp++;
- case 6:
- cksum += *sp++;
- case 5:
- cksum += *sp++;
- case 4:
- cksum += *sp++;
- case 3:
- cksum += *sp++;
- case 2:
- cksum += *sp++;
- case 1:
- cksum += *sp++;
- } while (--n > 0);
- }
+
+ do {
+ cksum += *sp++;
+ } while (--sn > 0);
if (len & 1)
cksum += htons(*(u_char *)sp << 8);
template<typename T>
T fromString(const std::string& s,
std::ios_base& (*f)(std::ios_base &) = std::dec)
-throw(std::runtime_error)
{
std::istringstream is(s);
T t;
newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
}
}
+ M5_FALLTHROUGH;
case MISCREG_TTBR0:
case MISCREG_TTBR1:
{
}
}
}
+ M5_FALLTHROUGH;
case MISCREG_SCTLR_EL1:
{
tc->getITBPtr()->invalidateMiscReg();
tc->getDTBPtr()->invalidateMiscReg();
setMiscRegNoEffect(misc_reg, newVal);
}
+ M5_FALLTHROUGH;
case MISCREG_CONTEXTIDR:
case MISCREG_PRRR:
case MISCREG_NMRR:
case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient
warn_if(!attr_hi, "Unpredictable behavior");
+ M5_FALLTHROUGH;
case 0x4: // Device-nGnRE memory or
// Normal memory, Inner Non-cacheable
case 0x8: // Device-nGRE memory or
break;
case MISCREG_DR4:
miscReg = MISCREG_DR6;
- /* Fall through to have the same effects as DR6. */
+ M5_FALLTHROUGH;
case MISCREG_DR6:
{
DR6 dr6 = regVal[MISCREG_DR6];
break;
case MISCREG_DR5:
miscReg = MISCREG_DR7;
- /* Fall through to have the same effects as DR7. */
+ M5_FALLTHROUGH;
case MISCREG_DR7:
{
DR7 dr7 = regVal[MISCREG_DR7];
if (bits(newVal, 63, 4))
fault = std::make_shared<GeneralProtection>(0);
}
+ break;
default:
fault = std::make_shared<GenericISA::M5PanicFault>(
"Unrecognized control register %d.\\n", dest);
fault = std::make_shared<GeneralProtection>(selector);
break;
}
- // Fall through on purpose
+ M5_FALLTHROUGH;
case SegIntGateCheck:
// Make sure the gate's the right type.
if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
# define M5_CLASS_VAR_USED
#endif
+// This can be removed once all compilers support C++17
+#if defined __has_cpp_attribute
+ // Note: We must separate this if statement because GCC < 5.0 doesn't
+ // support the function-like syntax in #if statements.
+ #if __has_cpp_attribute(fallthrough)
+ #define M5_FALLTHROUGH [[fallthrough]]
+ #else
+ #define M5_FALLTHROUGH
+ #endif
+#else
+ // Unsupported (and no warning) on GCC < 7.
+ #define M5_FALLTHROUGH
+#endif
+
// std::make_unique redefined for C++11 compilers
namespace m5
{
#include <iostream>
#include <sstream>
+#include "base/compiler.hh"
+
using namespace std;
namespace cp {
case 'X':
fmt.uppercase = true;
+ M5_FALLTHROUGH;
case 'x':
fmt.base = Format::hex;
fmt.format = Format::integer;
case 'G':
fmt.uppercase = true;
+ M5_FALLTHROUGH;
case 'g':
fmt.format = Format::floating;
fmt.float_format = Format::best;
case 'E':
fmt.uppercase = true;
+ M5_FALLTHROUGH;
case 'e':
fmt.format = Format::floating;
fmt.float_format = Format::scientific;
fmt.fill_zero = true;
break;
}
+ M5_FALLTHROUGH;
case '1':
case '2':
case '3':
// gem5 will try PNG first, and it will fallback to BMP if not
// available.
- /* FALLTHROUGH */
+ M5_FALLTHROUGH;
#if USE_PNG
case Enums::Png:
return std::unique_ptr<PngWriter>(new PngWriter(fb));
deschedule(tickEvent);
_status = Idle;
- /** FALLTHROUGH */
+ M5_FALLTHROUGH;
case Idle:
// Idle, no need to drain
assert(!tickEvent.scheduled());
case MISCREG_ES:
if (seg.unusable)
break;
+ M5_FALLTHROUGH;
case MISCREG_CS:
if (seg.base & 0xffffffff00000000ULL)
warn("Illegal %s base: 0x%x\n", name, seg.base);
case 3:
if (sregs.cs.type == 3 && seg.dpl != 0)
warn("CS type is 3, but SS DPL is != 0.\n");
- /* FALLTHROUGH */
+ M5_FALLTHROUGH;
case 7:
if (!(sregs.cr0 & 1) && seg.dpl != 0)
warn("SS DPL is %i, but CR0 PE is 0\n", seg.dpl);
case MISCREG_GS:
if (seg.unusable)
break;
+ M5_FALLTHROUGH;
case MISCREG_CS:
if (!seg.s)
warn("%s: S flag not set\n", name);
case MISCREG_TSL:
if (seg.unusable)
break;
+ M5_FALLTHROUGH;
case MISCREG_TR:
if (seg.s)
warn("%s: S flag is set\n", name);
case MISCREG_TSL:
if (seg.unusable)
break;
+ M5_FALLTHROUGH;
case MISCREG_TR:
case MISCREG_CS:
if (!seg.present)
break;
case CCRegClass:
os << 'c' << static_cast<unsigned int>(reg.index());
+ break;
default:
panic("Unknown register class: %d", (int)reg.classValue());
}
case MISCREG_CNTPS_CVAL_EL1:
case MISCREG_CNTPS_TVAL_EL1:
case MISCREG_CNTPS_CTL_EL1:
- /* FALLTHROUGH */
+ M5_FALLTHROUGH;
// PL2 phys. timer, non-secure
case MISCREG_CNTHCTL:
case MISCREG_CNTPS_CVAL_EL1:
case MISCREG_CNTPS_TVAL_EL1:
case MISCREG_CNTPS_CTL_EL1:
- /* FALLTHROUGH */
+ M5_FALLTHROUGH;
// PL2 phys. timer, non-secure
case MISCREG_CNTHCTL:
int descLeft = rxDescCache.descLeft();
DPRINTF(EthernetSM, "RXS: descLeft: %d rdmts: %d rdlen: %d\n",
descLeft, regs.rctl.rdmts(), regs.rdlen());
- switch (regs.rctl.rdmts()) {
- case 2: if (descLeft > .125 * regs.rdlen()) break;
- case 1: if (descLeft > .250 * regs.rdlen()) break;
- case 0: if (descLeft > .500 * regs.rdlen()) break;
+
+ // rdmts 2->1/8, 1->1/4, 0->1/2
+ int ratio = (1ULL << (regs.rctl.rdmts() + 1));
+ if (descLeft * ratio <= regs.rdlen()) {
DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) "
"because of descriptors left\n");
postInterrupt(IT_RXDMT);
- break;
}
if (rxFifo.empty())
break;
case CHAN_STATUS:
assert(size == sizeof(uint64_t));
- pkt->set<uint64_t>(cr.status() | ~busy);
+ pkt->set<uint64_t>(cr.status() | (busy ? 0 : 1));
break;
case CHAN_CHAINADDR:
assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
// Supported DMA commands
case WDCC_WRITEDMA:
dmaRead = true; // a write to the disk is a DMA read from memory
+ M5_FALLTHROUGH;
case WDCC_READDMA:
if (!(cmdReg.drive & DRIVE_LBA_BIT))
panic("Attempt to perform CHS access, only supports LBA\n");
case WriteOutputPort:
warn("i8042 \"Write output port\" command not implemented.\n");
lastCommand = WriteOutputPort;
+ break;
case WriteKeyboardOutputBuff:
warn("i8042 \"Write keyboard output buffer\" "
"command not implemented.\n");
lastCommand = WriteKeyboardOutputBuff;
+ break;
case WriteMouseOutputBuff:
DPRINTF(I8042, "Got command to write to mouse output buffer.\n");
lastCommand = WriteMouseOutputBuff;
break;
case 'P':
format = true;
+ M5_FALLTHROUGH;
case 'p':
hexnum = true;
break;
}
}
-
code(' base += ${{enum.ident}}_Controller::getNumControllers();')
else:
code(' base += 0;')
+ code(' M5_FALLTHROUGH;')
code(' case ${{self.c_ident}}_${{enum.ident}}:')
code(' break;')
code.dedent()
#include <algorithm>
#include <cassert>
#include <climits>
+#include <functional>
#include <iosfwd>
#include <memory>
#include <mutex>
* possible to guarantee that the simulation will proceed as it should
* have in the same way that it would have proceeded sans checkpoints.
*/
- void (*seek)(std::shared_ptr<FileFDEntry>)
- = [] (std::shared_ptr<FileFDEntry> ffd)
+ auto seek = [] (std::shared_ptr<FileFDEntry> ffd)
{
if (lseek(ffd->getSimFD(), ffd->getFileOffset(), SEEK_SET) < 0)
fatal("Unable to seek to location in %s", ffd->getFileName());