litescope: create example design derived from SoC that can be used on all targets

diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py
index 44e2328476bee737cb8aea4bc225c15456e15021..cf6af2323484a662d59532d8371d2a44390db7fa 100644 (file)
--- a/misoclib/com/liteeth/example_designs/make.py
+++ b/misoclib/com/liteeth/example_designs/make.py
@@ -119,7 +119,7 @@ System Clk: {} MHz
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
+               csr_csv = cpuif.get_csr_csv(soc.csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-bitstream"]:

diff --git a/misoclib/cpu/peripherals/__init__.py b/misoclib/cpu/peripherals/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index d35ce8c77ba142b8a8d85a52822d045f3518a714..3d90fd63cf15a94304083c4cec1dc66750593200 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -96,6 +96,9 @@ class SoC(Module):
                                self.submodules.sdram = wishbone.SRAM(sdram_size)
                                self.register_mem("sdram", self.mem_map["sdram"], self.sdram.bus, sdram_size)
 
+               elif cpu_or_bridge is not None and not isinstance(cpu_or_bridge, CPU):
+                       self._wb_masters += [cpu_or_bridge.wishbone]
+
                if with_csr:
                        self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width))
                        self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)

diff --git a/misoclib/tools/litescope/example_designs/make.py b/misoclib/tools/litescope/example_designs/make.py
index 64e2c499a28cc262d94ac15232959201443a3a98..27f4e406e6b550edb04f45c21ea5cf630e598cda 100644 (file)
--- a/misoclib/tools/litescope/example_designs/make.py
+++ b/misoclib/tools/litescope/example_designs/make.py
@@ -59,7 +59,10 @@ if __name__ == "__main__":
                top_class = target_module.default_subtarget
 
        if args.platform is None:
-               platform_name = top_class.default_platform
+               if hasattr(top_class, "default_platform"):
+                       platform_name = top_class.default_platform
+               else:
+                       raise ValueError("Target has no default platform, specify a platform with -p your_platform")
        else:
                platform_name = args.platform
        platform_module = _import("mibuild.platforms", platform_name)
@@ -128,7 +131,7 @@ RLE: {}
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
+               csr_csv = cpuif.get_csr_csv(soc.csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-bitstream"]:

diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index a282ffe889940520e561df79bffea68530a8f42e..572a1d0e0906fb2c64c38939b06291d4a72a9010 100644 (file)
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -1,12 +1,6 @@
-import os
-
-from migen.bank import csrgen
-from migen.bus import wishbone, csr
-from migen.bus import wishbone2csr
 from migen.bank.description import *
 
-from targets import *
-
+from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
 from misoclib.tools.litescope.frontend.io import LiteScopeIO
@@ -27,65 +21,30 @@ class _CRG(Module):
                        self.cd_sys.rst.eq(~rst_n)
                ]
 
-class SoC(Module):
-       csr_base = 0x00000000
-       csr_data_width = 32
-       csr_map = {
-               "bridge":                       0,
-               "identifier":           1,
-       }
-       interrupt_map = {}
-       cpu_type = None
-       def __init__(self, platform, clk_freq):
-               self.clk_freq = clk_freq
-               # UART <--> Wishbone bridge
-               self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
-
-               # CSR bridge   0x00000000 (shadow @0x00000000)
-               self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
-               self._wb_masters = [self.uart2wb.wishbone]
-               self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
-               self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
-
-               # CSR
-               self.submodules.identifier = Identifier(0, int(clk_freq))
-
-       def add_cpu_memory_region(self, name, origin, length):
-               self.cpu_memory_regions.append((name, origin, length))
-
-       def add_cpu_csr_region(self, name, origin, busword, obj):
-               self.cpu_csr_regions.append((name, origin, busword, obj))
-
-       def do_finalize(self):
-               # Wishbone
-               self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
-                       self._wb_slaves, register=True)
-
-               # CSR
-               self.submodules.csrbankarray = csrgen.BankArray(self,
-                       lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
-                       data_width=self.csr_data_width)
-               self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
-               for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
-                       self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
-               for name, memory, mapaddr, mmap in self.csrbankarray.srams:
-                       self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
-
 class LiteScopeSoC(SoC, AutoCSR):
-       default_platform = "de0nano"
        csr_map = {
-               "io":   10,
-               "la":   11
+               "io":   16,
+               "la":   17
        }
        csr_map.update(SoC.csr_map)
        def __init__(self, platform):
-               clk_freq = 50*1000000
-               SoC.__init__(self, platform, clk_freq)
-               self.submodules.crg = _CRG(platform.request("clk50"))
+               clk_freq = int((1/(platform.default_clk_period))*1000000000)
+               self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=115200)
+               SoC.__init__(self, platform, clk_freq, self.uart2wb,
+                       with_cpu=False,
+                       with_csr=True, csr_data_width=32,
+                       with_uart=False,
+                       with_identifier=True,
+                       with_timer=False
+               )
+               self.submodules.crg = _CRG(platform.request(platform.default_clk_name))
 
                self.submodules.io = LiteScopeIO(8)
-               self.leds = Cat(*[platform.request("user_led", i) for i in range(8)])
-               self.comb += self.leds.eq(self.io.o)
+               for i in range(8):
+                       try:
+                               self.comb += platform.request("user_led", i).eq(self.io.o[i])
+                       except:
+                               pass
 
                self.submodules.counter0 = counter0 = Counter(bits_sign=8)
                self.submodules.counter1 = counter1 = Counter(bits_sign=8)