Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623

diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v
index c345a3da38338a120825f50564934afe1ce1e6c2..40c378d166f0367f7ce9f8d7b117b5854189bcd7 100644 (file)
--- a/techlibs/xilinx/arith_map.v
+++ b/techlibs/xilinx/arith_map.v
@@ -33,7 +33,21 @@ module _80_xilinx_lcu (P, G, CI, CO);
 
        genvar i;
 
-`ifdef _CLB_CARRY
+`ifdef _EXPLICIT_CARRY
+
+       wire [WIDTH-1:0] C = {CO, CI};
+       wire [WIDTH-1:0] S = P & ~G;
+
+       generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
+               MUXCY muxcy (
+                       .CI(C[i]),
+                       .DI(G[i]),
+                       .S(S[i]),
+                       .O(CO[i])
+               );
+       end endgenerate
+
+`else
 
        localparam CARRY4_COUNT = (WIDTH + 3) / 4;
        localparam MAX_WIDTH    = CARRY4_COUNT * 4;
@@ -97,34 +111,6 @@ module _80_xilinx_lcu (P, G, CI, CO);
                end
 
        end endgenerate
-
-`elsif _EXPLICIT_CARRY
-
-       wire [WIDTH-1:0] C = {CO, CI};
-       wire [WIDTH-1:0] S = P & ~G;
-
-       generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
-               MUXCY muxcy (
-                       .CI(C[i]),
-                       .DI(G[i]),
-                       .S(S[i]),
-                       .O(CO[i])
-               );
-       end endgenerate
-
-`else
-
-       wire [WIDTH-1:0] C = {CO, CI};
-       wire [WIDTH-1:0] S = P & ~G;
-
-       generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
-               MUXCY muxcy (
-                       .CI(C[i]),
-                       .DI(G[i]),
-                       .S(S[i]),
-                       .O(CO[i])
-               );
-       end endgenerate
 `endif
 
 endmodule
@@ -161,79 +147,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 
        genvar i;
 
-`ifdef _CLB_CARRY
-
-       localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
-       localparam MAX_WIDTH    = CARRY4_COUNT * 4;
-       localparam PAD_WIDTH    = MAX_WIDTH - Y_WIDTH;
-
-       wire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, AA ^ BB};
-       wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
-
-       wire [MAX_WIDTH-1:0] C  = CO;
-
-       genvar i;
-       generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
-
-               // Partially occupied CARRY4
-               if ((i+1)*4 > Y_WIDTH) begin
-
-                       // First one
-                       if (i == 0) begin
-                               CARRY4 carry4_1st_part
-                               (
-                               .CYINIT(CI),
-                               .CI    (1'd0),
-                               .DI    (DI[(Y_WIDTH - 1):i*4]),
-                               .S     (S [(Y_WIDTH - 1):i*4]),
-                               .O     (Y [(Y_WIDTH - 1):i*4]),
-                               .CO    (CO[(Y_WIDTH - 1):i*4])
-                               );
-                       // Another one
-                       end else begin
-                               CARRY4 carry4_part
-                               (
-                               .CYINIT(1'd0),
-                               .CI    (C [i*4 - 1]),
-                               .DI    (DI[(Y_WIDTH - 1):i*4]),
-                               .S     (S [(Y_WIDTH - 1):i*4]),
-                               .O     (Y [(Y_WIDTH - 1):i*4]),
-                               .CO    (CO[(Y_WIDTH - 1):i*4])
-                               );
-                       end
-
-               // Fully occupied CARRY4
-               end else begin
-
-                       // First one
-                       if (i == 0) begin
-                               CARRY4 carry4_1st_full
-                               (
-                               .CYINIT(CI),
-                               .CI    (1'd0),
-                               .DI    (DI[((i+1)*4 - 1):i*4]),
-                               .S     (S [((i+1)*4 - 1):i*4]),
-                               .O     (Y [((i+1)*4 - 1):i*4]),
-                               .CO    (CO[((i+1)*4 - 1):i*4])
-                               );
-                       // Another one
-                       end else begin
-                               CARRY4 carry4_full
-                               (
-                               .CYINIT(1'd0),
-                               .CI    (C [i*4 - 1]),
-                               .DI    (DI[((i+1)*4 - 1):i*4]),
-                               .S     (S [((i+1)*4 - 1):i*4]),
-                               .O     (Y [((i+1)*4 - 1):i*4]),
-                               .CO    (CO[((i+1)*4 - 1):i*4])
-                               );
-                       end
-
-               end
-
-       end endgenerate
-
-`elsif _EXPLICIT_CARRY
+`ifdef _EXPLICIT_CARRY
 
        wire [Y_WIDTH-1:0] S = AA ^ BB;
        wire [Y_WIDTH-1:0] DI = AA & BB;
@@ -333,23 +247,74 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 
 `else
 
-       wire [Y_WIDTH-1:0] S = AA ^ BB;
-       wire [Y_WIDTH-1:0] DI = AA & BB;
+       localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
+       localparam MAX_WIDTH    = CARRY4_COUNT * 4;
+       localparam PAD_WIDTH    = MAX_WIDTH - Y_WIDTH;
 
-       wire [Y_WIDTH-1:0] C = {CO, CI};
+       wire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, AA ^ BB};
+       wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
+
+       wire [MAX_WIDTH-1:0] C  = CO;
+
+       genvar i;
+       generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
+
+               // Partially occupied CARRY4
+               if ((i+1)*4 > Y_WIDTH) begin
+
+                       // First one
+                       if (i == 0) begin
+                               CARRY4 carry4_1st_part
+                               (
+                               .CYINIT(CI),
+                               .CI    (1'd0),
+                               .DI    (DI[(Y_WIDTH - 1):i*4]),
+                               .S     (S [(Y_WIDTH - 1):i*4]),
+                               .O     (Y [(Y_WIDTH - 1):i*4]),
+                               .CO    (CO[(Y_WIDTH - 1):i*4])
+                               );
+                       // Another one
+                       end else begin
+                               CARRY4 carry4_part
+                               (
+                               .CYINIT(1'd0),
+                               .CI    (C [i*4 - 1]),
+                               .DI    (DI[(Y_WIDTH - 1):i*4]),
+                               .S     (S [(Y_WIDTH - 1):i*4]),
+                               .O     (Y [(Y_WIDTH - 1):i*4]),
+                               .CO    (CO[(Y_WIDTH - 1):i*4])
+                               );
+                       end
+
+               // Fully occupied CARRY4
+               end else begin
+
+                       // First one
+                       if (i == 0) begin
+                               CARRY4 carry4_1st_full
+                               (
+                               .CYINIT(CI),
+                               .CI    (1'd0),
+                               .DI    (DI[((i+1)*4 - 1):i*4]),
+                               .S     (S [((i+1)*4 - 1):i*4]),
+                               .O     (Y [((i+1)*4 - 1):i*4]),
+                               .CO    (CO[((i+1)*4 - 1):i*4])
+                               );
+                       // Another one
+                       end else begin
+                               CARRY4 carry4_full
+                               (
+                               .CYINIT(1'd0),
+                               .CI    (C [i*4 - 1]),
+                               .DI    (DI[((i+1)*4 - 1):i*4]),
+                               .S     (S [((i+1)*4 - 1):i*4]),
+                               .O     (Y [((i+1)*4 - 1):i*4]),
+                               .CO    (CO[((i+1)*4 - 1):i*4])
+                               );
+                       end
+
+               end
 
-       generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-               MUXCY muxcy (
-                       .CI(C[i]),
-                       .DI(DI[i]),
-                       .S(S[i]),
-                       .O(CO[i])
-               );
-               XORCY xorcy (
-                       .CI(C[i]),
-                       .LI(S[i]),
-                       .O(Y[i])
-               );
        end endgenerate
 
 `endif

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3dc05cd109c775f0ac4dbcdc39f54769ccd90f06..5c3b5179dc1321cae7a5d895af7a6b70965e59cd 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -518,8 +518,6 @@ struct SynthXilinxPass : public ScriptPass
                                techmap_args += " -map +/xilinx/arith_map.v";
                                if (vpr)
                                        techmap_args += " -D _EXPLICIT_CARRY";
-                               else
-                                       techmap_args += " -D _CLB_CARRY";
                        }
                        run("techmap " + techmap_args);
                        run("opt -fast");