default:
break;
}
+
+ if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
+ offset |= RADEON_TXO_MACRO_TILE;
+ if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
+ offset |= RADEON_TXO_MICRO_TILE_X2;
BEGIN_BATCH(18);
OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
break;
}
+ if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
+ dst_pitch |= RADEON_COLOR_TILE_ENABLE;
+
+ if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
+ dst_pitch |= RADEON_COLOR_MICROTILE_ENABLE;
+
BEGIN_BATCH_NO_AUTOSTATE(18);
OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
cbpitch = (rrb->pitch / rrb->cpp);
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
cbpitch |= R200_COLOR_TILE_ENABLE;
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
+ cbpitch |= RADEON_COLOR_MICROTILE_ENABLE;
drb = radeon_get_depthbuffer(&r100->radeon);
if (drb) {