Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf

diff --git a/passes/pmgen/ice40_wrapcarry.pmg b/passes/pmgen/ice40_wrapcarry.pmg
index 9e64c7467a4904ec56d88b616562d8fed2541d19..bb59edb0c1b031309bcb54ee92e0911ebf517881 100644 (file)
--- a/passes/pmgen/ice40_wrapcarry.pmg
+++ b/passes/pmgen/ice40_wrapcarry.pmg
@@ -9,3 +9,7 @@ match lut
        index <SigSpec> port(lut, \I1) === port(carry, \I0)
        index <SigSpec> port(lut, \I2) === port(carry, \I1)
 endmatch
+
+code
+       accept;
+endcode

diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys
new file mode 100644 (file)
index 0000000..10c029e
--- /dev/null
+++ b/tests/ice40/wrapcarry.ys
@@ -0,0 +1,22 @@
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+       SB_CARRY carry (
+               .I0(A),
+               .I1(B),
+               .CI(CI),
+               .CO(CO)
+       );
+       SB_LUT4 #(
+               .LUT_INIT(16'b 0110_1001_1001_0110)
+       ) adder (
+               .I0(1'b0),
+               .I1(A),
+               .I2(B),
+               .I3(1'b0),
+               .O(O)
+       );
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER