r600g: use pipe_resource::width0 instead pb_buffer::size
authorMarek Olšák <marek.olsak@amd.com>
Sun, 6 Sep 2015 14:40:21 +0000 (16:40 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 10 Sep 2015 15:14:15 +0000 (17:14 +0200)
pb_buffer::size was aligned by 29aaab2b5f55cc6d9a84f58ce2bb8607e76a9dde,
which broke the CMASK code I think.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91881

Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_state.c

index 6f4cb55f887757f0ab3d05032d5ec5aaa06b8dc2..0c54a3fe953b97ada17cf996ac19f4bbcee6367d 100644 (file)
@@ -1864,7 +1864,7 @@ static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
                radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
                radeon_emit(cs, (resource_offset + buffer_index) * 8);
                radeon_emit(cs, va); /* RESOURCEi_WORD0 */
-               radeon_emit(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
+               radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
                radeon_emit(cs, /* RESOURCEi_WORD2 */
                                 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
                                 S_030008_STRIDE(vb->stride) |
@@ -1934,7 +1934,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
                radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
                radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
                radeon_emit(cs, va); /* RESOURCEi_WORD0 */
-               radeon_emit(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
+               radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
                radeon_emit(cs, /* RESOURCEi_WORD2 */
                            S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
                            S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
index 93a74f7c2ca1c341f7480d434832fc567df00b35..3464c382dc6e891fc8518a1787eff6374d3bfd91 100644 (file)
@@ -1022,7 +1022,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
 
                /* CMASK. */
                if (!rctx->dummy_cmask ||
-                   rctx->dummy_cmask->buf->size < cmask.size ||
+                   rctx->dummy_cmask->b.b.width0 < cmask.size ||
                    rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
                        struct pipe_transfer *transfer;
                        void *ptr;
@@ -1040,7 +1040,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
 
                /* FMASK. */
                if (!rctx->dummy_fmask ||
-                   rctx->dummy_fmask->buf->size < fmask.size ||
+                   rctx->dummy_fmask->b.b.width0 < fmask.size ||
                    rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
                        pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
                        rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
@@ -1709,7 +1709,7 @@ static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom
                radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
                radeon_emit(cs, (320 + buffer_index) * 7);
                radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
-               radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
+               radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
                radeon_emit(cs, /* RESOURCEi_WORD2 */
                                 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
                                 S_038008_STRIDE(vb->stride));
@@ -1758,7 +1758,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
                radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
                radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
                radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
-               radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
+               radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
                radeon_emit(cs, /* RESOURCEi_WORD2 */
                            S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
                            S_038008_STRIDE(gs_ring_buffer ? 4 : 16));