Revert "Trim shiftx_width when upper bits are 1'bx"

This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb.

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index d3ba0109f6f0524309c07ff6e04e99422e56751f..3f4efebe96cbd89607992901d945e167f35a2807 100644 (file)
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -164,11 +164,6 @@ endmatch
 
 code shiftx_width
        shiftx_width = param(shiftx, \A_WIDTH).as_int();
-       while (shiftx_width > 1) {
-               if (port(shiftx, \A)[shiftx_width-1] != State::Sx)
-                       break;
-               --shiftx_width;
-       }
 endcode
 
 match first
@@ -182,7 +177,7 @@ code
        chain.push_back(first);
        subpattern(tail);
 finally
-       if (GetSize(chain) == shiftx_width)
+       if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int())
                accept;
        chain.clear();
 endcode