Merge branch 'master' of /project/eecs/parlab/git/projects/riscv

Conflicts:
	sim/riscv/insns/mtpcr.h
	sim/riscv/processor.cc

diff --cc riscv/insns/mfpcr.h
Simple merge

diff --cc riscv/insns/mtpcr.h
index d9b47f02fd8ea0b6a06c79cc38fa8464ded09691,5c7289eb7097f4366240278425ac872247d9a9aa..79e28bf4c5c44a36f6bd7a86abef0c523b844657
--- 1/riscv/insns/mtpcr.h
--- 2/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@@ -20,7 -15,8 +20,8 @@@ switch(insn.rtype.rb
      break;
  
    case 16:
 -    tohost = val;
 -    sim->set_tohost(tohost);
++    tohost = RA;
 +    sim->set_tohost(RA);
      break;
  
    case 24:

diff --cc riscv/processor.cc
index e04f4985d74ceea9633b9f0f29335ecad78e70f6,e336aa1990113b736aa0c10055dfdedc1a9e5596..271afbf0115652af627073b693c1d1858a4f3a5c
--- 1/riscv/processor.cc
--- 2/riscv/processor.cc
+++ b/riscv/processor.cc
@@@ -21,10 -21,9 +21,12 @@@ processor_t::processor_t(sim_t* _sim, c
    tid = 0;
    pcr_k0 = 0;
    pcr_k1 = 0;
 -  set_sr(SR_S | (support_64bit ? SR_KX : 0));
+   tohost = 0;
+   fromhost = 0;
 +  count = 0;
 +  compare = 0;
 +  interrupts_pending = 0;
 +  set_sr(SR_S | (support_64bit ? SR_SX : 0));
    set_fsr(0);
  
    memset(counters,0,sizeof(counters));

diff --cc riscv/processor.h
Simple merge