i965/vec4: Assert that ATTR regions are register-aligned.

It might be useful to actually handle this once copy propagation
becomes smarter about register-misaligned offsets.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 470f814f562f844526c469a7a7a53a48a7a82d5f..58c8a8a5bdbe7bce2a5b3195ac120b391304438e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1620,6 +1620,7 @@ vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map,
 
          int grf = attribute_map[inst->src[i].nr +
                                  inst->src[i].offset / REG_SIZE];
+         assert(inst->src[i].offset % REG_SIZE == 0);
 
          /* All attributes used in the shader need to have been assigned a
           * hardware register by the caller