(no commit message)

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 225542475a840bc33a8a9455add888fae455235f..f417589a05c1a2df465b9ff692df87ddf2f4f606 100644 (file)
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -8,7 +8,10 @@ Links
 
 the encoding embeds predication into the swizzle as well as constants 1/1.0 and 0/0.0
 
-As a Scalar instruction, mv.swiz and fmv.swiz operate on four 32-bit
+**As a Scalar instruction**
+
+When part of the Scalar Power ISA (not SVP64 Vectorised)
+mv.swiz and fmv.swiz operate on four 32-bit
 quantities, reducing this instruction to 2-in, 2-out pairs of 64-bit
 registers:
 
@@ -19,7 +22,20 @@ registers:
 | Z            | RA+1   | RT+1 | lo-half |
 | W            | RA+1   | RT+1 | hi-half |
 
-When RA=RT (in-place swizzle) any 
+When RA=RT (in-place swizzle) any portion of RT not covered by
+the Swizzle is unmodified.  For example a Swizzle of "..XY"
+will copy the contents RA+1 into RT but leave RT+1 unmodified.
+
+When RA!=RT any part of RT or RT+1 not set as a destination by
+the Swizzle will be set to zero.  A Swizzle of "..XY" would
+copy the contents RA+1 into RT, but set RT+1 to zero.
+
+When (RA,RA+1) overlaps with (RT,RT+1) and RA!=RT, the results
+are `UNDEFINED`.
+
+**SVP64 Vectorised**
+
+When Vectorised, TODO
 
 # Format