tests: update tests because of changes in stat names and in the stats package
authorNathan Binkert <nate@binkert.org>
Sat, 7 Mar 2009 22:30:55 +0000 (14:30 -0800)
committerNathan Binkert <nate@binkert.org>
Sat, 7 Mar 2009 22:30:55 +0000 (14:30 -0800)
26 files changed:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt

index e459fc4f1fd02757a1a3273807ca18c0e0531d02..0988daaa558adb5bf48e394ccb5669a2f69a5c70 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:15:58
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index c5506c5e0517df3fecf20591dcabc06240ecdcfa..b3f903358b495a4cf8900253536a37eaaa348b1d 100644 (file)
@@ -1,25 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                     65718859                       # Number of BTB hits
-global.BPredUnit.BTBLookups                  73181368                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                     198                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                4206850                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted               70112287                       # Number of conditional branches predicted
-global.BPredUnit.lookups                     76039018                       # Number of BP lookups
-global.BPredUnit.usedRAS                      1692219                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 244512                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204148                       # Number of bytes of host memory used
-host_seconds                                  2312.99                       # Real time elapsed on the host
-host_tick_rate                               72234766                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads           19292303                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores          14732751                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads             126977202                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores             43223597                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 309694                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206028                       # Number of bytes of host memory used
+host_seconds                                  1826.17                       # Real time elapsed on the host
+host_tick_rate                               91491135                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   565552443                       # Number of instructions simulated
 sim_seconds                                  0.167078                       # Number of seconds simulated
 sim_ticks                                167078146500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                 65718859                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              73181368                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                 198                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            4206850                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           70112287                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 76039018                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1692219                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               62547159                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events          17700250                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
@@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples    332581112                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0     92203773   2772.37%           
-                               1     67051353   2016.09%           
-                               2     80133780   2409.45%           
-                               3     36043478   1083.75%           
-                               4     30084945    904.59%           
-                               5     14579095    438.36%           
-                               6     10850493    326.25%           
-                               7      1143008     34.37%           
-                               8       491187     14.77%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples    332581112                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1     92203773     27.72%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2     67051353     20.16%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3     80133780     24.09%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4     36043478     10.84%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5     30084945      9.05%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6     14579095      4.38%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7     10850493      3.26%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8      1143008      0.34%           
+system.cpu.iq.ISSUE:issued_per_cycle::8        491187      0.15%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total    332581112                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.821264                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.674645                      
 system.cpu.iq.ISSUE:rate                     1.812679                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                  620382553                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 605718112                       # Number of instructions issued
@@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse             16333.162457                       # Cy
 system.cpu.l2cache.total_refs                  375607                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   63236                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          19292303                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         14732751                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            126977202                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            43223597                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                        334156294                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles         15214853                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      463854889                       # Number of HB maps that are committed
index 4fc3f25f84f6f1cd024a322a886685db13cae0ec..b7b45d62c04ca529e3321065f6d735ee1c5c6e5a 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:45:29
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing
+M5 compiled Mar  6 2009 18:29:06
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:38:25
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 1bd86bd33d943aca427b8a063f90294f6908670a..a8a0693180df2f843db97129f5b8aaddbe079325 100644 (file)
@@ -1,25 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                    182414509                       # Number of BTB hits
-global.BPredUnit.BTBLookups                 203429504                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                       0                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect               83681535                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted              254458067                       # Number of conditional branches predicted
-global.BPredUnit.lookups                    254458067                       # Number of BP lookups
-global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 104414                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206176                       # Number of bytes of host memory used
-host_seconds                                 13461.92                       # Real time elapsed on the host
-host_tick_rate                               81909485                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads          460341314                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores         141106006                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads             743909112                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores            301399355                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 148318                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 208044                       # Number of bytes of host memory used
+host_seconds                                  9477.08                       # Real time elapsed on the host
+host_tick_rate                              116350072                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1405618365                       # Number of instructions simulated
 sim_seconds                                  1.102659                       # Number of seconds simulated
 sim_ticks                                1102659164000                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                182414509                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             203429504                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect           83681535                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          254458067                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                254458067                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               86248929                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events           8096119                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
@@ -291,21 +287,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples   2203815119                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0   1083882017   4918.21%           
-                               1    586425796   2660.96%           
-                               2    298714416   1355.44%           
-                               3    164995052    748.68%           
-                               4     47215795    214.25%           
-                               5     14943133     67.81%           
-                               6      6716024     30.47%           
-                               7       790185      3.59%           
-                               8       132701      0.60%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples   2203815119                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1   1083882017     49.18%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2    586425796     26.61%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3    298714416     13.55%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4    164995052      7.49%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5     47215795      2.14%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6     14943133      0.68%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7      6716024      0.30%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8       790185      0.04%           
+system.cpu.iq.ISSUE:issued_per_cycle::8        132701      0.01%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total   2203815119                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.902665                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.144866                      
 system.cpu.iq.ISSUE:rate                     0.902050                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                 2506731523                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                1989307676                       # Number of instructions issued
@@ -387,6 +385,10 @@ system.cpu.l2cache.tagsinuse             16402.911294                       # Cy
 system.cpu.l2cache.total_refs                  423238                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   61945                       # number of writebacks
+system.cpu.memDep0.conflictingLoads         460341314                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        141106006                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            743909112                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           301399355                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                       2205318329                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles         17694794                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1244779250                       # Number of HB maps that are committed
index 1910760d1c1edbfd407d75aa44e407ba7524c371..a6115dc061b1b9740cac7365230b1748b13a8e6c 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:15:24
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:44:44
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
+M5 compiled Mar  6 2009 18:15:39
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:15:43
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
index dcbc52710f505a715a45cb18b0e2c06dc531f881..a35446ce714dfa34377c6630733cca0049bb25bf 100644 (file)
@@ -1,37 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                      4976196                       # Number of BTB hits
-global.BPredUnit.BTBHits                      2271370                       # Number of BTB hits
-global.BPredUnit.BTBLookups                   9270308                       # Number of BTB lookups
-global.BPredUnit.BTBLookups                   5052293                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                   24350                       # Number of incorrect RAS predictions.
-global.BPredUnit.RASInCorrect                   16405                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                 550496                       # Number of conditional branches incorrect
-global.BPredUnit.condIncorrect                 327507                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted                8475186                       # Number of conditional branches predicted
-global.BPredUnit.condPredicted                4551940                       # Number of conditional branches predicted
-global.BPredUnit.lookups                     10093436                       # Number of BP lookups
-global.BPredUnit.lookups                      5538388                       # Number of BP lookups
-global.BPredUnit.usedRAS                       690374                       # Number of times the RAS was used to get a target.
-global.BPredUnit.usedRAS                       417429                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 133092                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 294856                       # Number of bytes of host memory used
-host_seconds                                   422.19                       # Real time elapsed on the host
-host_tick_rate                             4518571306                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads            2050532                       # Number of conflicting loads.
-memdepunit.memDep.conflictingLoads             906322                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores           1832540                       # Number of conflicting stores.
-memdepunit.memDep.conflictingStores            817104                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads               7553751                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads               4247428                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores              4835994                       # Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores              2557361                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 195579                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 296668                       # Number of bytes of host memory used
+host_seconds                                   287.30                       # Real time elapsed on the host
+host_tick_rate                             6640015618                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56190549                       # Number of instructions simulated
 sim_seconds                                  1.907705                       # Number of seconds simulated
 sim_ticks                                1907705384500                       # Number of ticks simulated
+system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.BPredUnit.BTBHits                 4976196                       # Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups              9270308                       # Number of BTB lookups
+system.cpu0.BPredUnit.RASInCorrect              24350                       # Number of incorrect RAS predictions.
+system.cpu0.BPredUnit.condIncorrect            550496                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted           8475186                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups                10093436                       # Number of BP lookups
+system.cpu0.BPredUnit.usedRAS                  690374                       # Number of times the RAS was used to get a target.
 system.cpu0.commit.COM:branches               5979895                       # Number of branches committed
 system.cpu0.commit.COM:bw_lim_events           670394                       # number cycles where commit BW limit reached
 system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
@@ -334,21 +318,23 @@ system.cpu0.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full.end_dist
-system.cpu0.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle.samples     70526789                      
-system.cpu0.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0     49764698   7056.14%           
-                               1     10507711   1489.89%           
-                               2      4625293    655.82%           
-                               3      2839060    402.55%           
-                               4      1729945    245.29%           
-                               5       663621     94.09%           
-                               6       315226     44.70%           
-                               7        67152      9.52%           
-                               8        14083      2.00%           
-system.cpu0.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu0.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu0.iq.ISSUE:issued_per_cycle::samples     70526789                      
+system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu0.iq.ISSUE:issued_per_cycle::0-1     49764698     70.56%           
+system.cpu0.iq.ISSUE:issued_per_cycle::1-2     10507711     14.90%           
+system.cpu0.iq.ISSUE:issued_per_cycle::2-3      4625293      6.56%           
+system.cpu0.iq.ISSUE:issued_per_cycle::3-4      2839060      4.03%           
+system.cpu0.iq.ISSUE:issued_per_cycle::4-5      1729945      2.45%           
+system.cpu0.iq.ISSUE:issued_per_cycle::5-6       663621      0.94%           
+system.cpu0.iq.ISSUE:issued_per_cycle::6-7       315226      0.45%           
+system.cpu0.iq.ISSUE:issued_per_cycle::7-8        67152      0.10%           
+system.cpu0.iq.ISSUE:issued_per_cycle::8        14083      0.02%           
+system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu0.iq.ISSUE:issued_per_cycle::total     70526789                      
+system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.581161                      
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.133095                      
 system.cpu0.iq.ISSUE:rate                    0.406210                       # Inst issue rate
 system.cpu0.iq.iqInstsAdded                  42280485                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqInstsIssued                 40987446                       # Number of instructions issued
@@ -449,6 +435,10 @@ system.cpu0.kern.syscall_98                         2      0.90%     97.75% # nu
 system.cpu0.kern.syscall_132                        1      0.45%     98.20% # number of syscalls executed
 system.cpu0.kern.syscall_144                        2      0.90%     99.10% # number of syscalls executed
 system.cpu0.kern.syscall_147                        2      0.90%    100.00% # number of syscalls executed
+system.cpu0.memDep0.conflictingLoads          2050532                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1832540                       # Number of conflicting stores.
+system.cpu0.memDep0.insertedLoads             7553751                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            4835994                       # Number of stores inserted to the mem dependence unit.
 system.cpu0.numCycles                       100902021                       # number of cpu cycles simulated
 system.cpu0.rename.RENAME:BlockCycles        10627682                       # Number of cycles rename is blocking
 system.cpu0.rename.RENAME:CommittedMaps      27337911                       # Number of HB maps that are committed
@@ -468,6 +458,14 @@ system.cpu0.rename.RENAME:serializingInsts      1163461                       #
 system.cpu0.rename.RENAME:skidInsts           8536821                       # count of insts added to the skid buffer
 system.cpu0.rename.RENAME:tempSerializingInsts       181475                       # count of temporary serializing insts renamed
 system.cpu0.timesIdled                         904725                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.BPredUnit.BTBHits                 2271370                       # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups              5052293                       # Number of BTB lookups
+system.cpu1.BPredUnit.RASInCorrect              16405                       # Number of incorrect RAS predictions.
+system.cpu1.BPredUnit.condIncorrect            327507                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.condPredicted           4551940                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups                 5538388                       # Number of BP lookups
+system.cpu1.BPredUnit.usedRAS                  417429                       # Number of times the RAS was used to get a target.
 system.cpu1.commit.COM:branches               2947825                       # Number of branches committed
 system.cpu1.commit.COM:bw_lim_events           401526                       # number cycles where commit BW limit reached
 system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
@@ -770,21 +768,23 @@ system.cpu1.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu1.iq.ISSUE:fu_full.end_dist
-system.cpu1.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle.samples     38118977                      
-system.cpu1.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0     28405823   7451.88%           
-                               1      4664380   1223.64%           
-                               2      1989669    521.96%           
-                               3      1362790    357.51%           
-                               4       979073    256.85%           
-                               5       465618    122.15%           
-                               6       186895     49.03%           
-                               7        52286     13.72%           
-                               8        12443      3.26%           
-system.cpu1.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu1.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu1.iq.ISSUE:issued_per_cycle::samples     38118977                      
+system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu1.iq.ISSUE:issued_per_cycle::0-1     28405823     74.52%           
+system.cpu1.iq.ISSUE:issued_per_cycle::1-2      4664380     12.24%           
+system.cpu1.iq.ISSUE:issued_per_cycle::2-3      1989669      5.22%           
+system.cpu1.iq.ISSUE:issued_per_cycle::3-4      1362790      3.58%           
+system.cpu1.iq.ISSUE:issued_per_cycle::4-5       979073      2.57%           
+system.cpu1.iq.ISSUE:issued_per_cycle::5-6       465618      1.22%           
+system.cpu1.iq.ISSUE:issued_per_cycle::6-7       186895      0.49%           
+system.cpu1.iq.ISSUE:issued_per_cycle::7-8        52286      0.14%           
+system.cpu1.iq.ISSUE:issued_per_cycle::8        12443      0.03%           
+system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu1.iq.ISSUE:issued_per_cycle::total     38118977                      
+system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.539453                      
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.158806                      
 system.cpu1.iq.ISSUE:rate                    0.479953                       # Inst issue rate
 system.cpu1.iq.iqInstsAdded                  21283894                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu1.iq.iqInstsIssued                 20563386                       # Number of instructions issued
@@ -864,6 +864,10 @@ system.cpu1.kern.syscall_59                         1      0.96%     57.69% # nu
 system.cpu1.kern.syscall_71                        31     29.81%     87.50% # number of syscalls executed
 system.cpu1.kern.syscall_74                        10      9.62%     97.12% # number of syscalls executed
 system.cpu1.kern.syscall_132                        3      2.88%    100.00% # number of syscalls executed
+system.cpu1.memDep0.conflictingLoads           906322                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          817104                       # Number of conflicting stores.
+system.cpu1.memDep0.insertedLoads             4247428                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            2557361                       # Number of stores inserted to the mem dependence unit.
 system.cpu1.numCycles                        42844582                       # number of cpu cycles simulated
 system.cpu1.rename.RENAME:BlockCycles         3655834                       # Number of cycles rename is blocking
 system.cpu1.rename.RENAME:CommittedMaps      13191652                       # Number of HB maps that are committed
index c6712a23be98d45bc2f92a3bb8ab95bedbbf00fc..139f5f740c850f2e204e1aa393a90936a780a120 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:15:24
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:42:11
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
+M5 compiled Mar  6 2009 18:15:39
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:15:42
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
index 37990c73f41170e4c0b548f2f74f9d8714598fed..4534484ec163f97833b20b9b5d629cd2d1c4dffa 100644 (file)
@@ -1,25 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                      6937900                       # Number of BTB hits
-global.BPredUnit.BTBLookups                  13339861                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                   41537                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                 828629                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted               12132448                       # Number of conditional branches predicted
-global.BPredUnit.lookups                     14570242                       # Number of BP lookups
-global.BPredUnit.usedRAS                      1034900                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 209657                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 292968                       # Number of bytes of host memory used
-host_seconds                                   253.23                       # Real time elapsed on the host
-host_tick_rate                             7374290880                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads            3083644                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores           2877472                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads              11055097                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores              7027136                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 203131                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 294692                       # Number of bytes of host memory used
+host_seconds                                   261.36                       # Real time elapsed on the host
+host_tick_rate                             7144744614                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    53090630                       # Number of instructions simulated
 sim_seconds                                  1.867363                       # Number of seconds simulated
 sim_ticks                                1867363148500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                  6937900                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              13339861                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               41537                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect             828629                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           12132448                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 14570242                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1034900                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches                8461943                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events            974606                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
@@ -322,21 +318,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples    102267931                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0     73151138   7152.89%           
-                               1     14628619   1430.42%           
-                               2      6419666    627.73%           
-                               3      3934330    384.71%           
-                               4      2528894    247.28%           
-                               5      1032607    100.97%           
-                               6       444582     43.47%           
-                               7       106443     10.41%           
-                               8        21652      2.12%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples    102267931                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1     73151138     71.53%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2     14628619     14.30%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3      6419666      6.28%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4      3934330      3.85%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5      2528894      2.47%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6      1032607      1.01%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7       444582      0.43%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8       106443      0.10%           
+system.cpu.iq.ISSUE:issued_per_cycle::8         21652      0.02%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total    102267931                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.568461                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.134174                      
 system.cpu.iq.ISSUE:rate                     0.424355                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                   60200389                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                  58135361                       # Number of instructions issued
@@ -433,6 +431,10 @@ system.cpu.kern.syscall_98                          2      0.61%     97.55% # nu
 system.cpu.kern.syscall_132                         4      1.23%     98.77% # number of syscalls executed
 system.cpu.kern.syscall_144                         2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_147                         2      0.61%    100.00% # number of syscalls executed
+system.cpu.memDep0.conflictingLoads           3083644                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2877472                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             11055097                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             7027136                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                        136996939                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles         14276861                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       38259280                       # Number of HB maps that are committed
index e8a891c227fc5d0e3f018a2035eab39a9c0d13d9..d243310c61c32755816e1fe319f4c4bba10fbb59 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:25:10
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index cbcabf35c0100c992a8a9fccdd23918508d87a8b..5e076a2751460699b8d2c31ac6891233cda3a385 100644 (file)
@@ -1,25 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                     38296034                       # Number of BTB hits
-global.BPredUnit.BTBLookups                  45834466                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                    1077                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                5781170                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted               35418150                       # Number of conditional branches predicted
-global.BPredUnit.lookups                     62209737                       # Number of BP lookups
-global.BPredUnit.usedRAS                     12344504                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 183215                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211568                       # Number of bytes of host memory used
-host_seconds                                  2049.91                       # Real time elapsed on the host
-host_tick_rate                               65854919                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads           73961217                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores          54131405                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads             124841223                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores             92324076                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 243217                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213460                       # Number of bytes of host memory used
+host_seconds                                  1544.20                       # Real time elapsed on the host
+host_tick_rate                               87422028                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   375574819                       # Number of instructions simulated
 sim_seconds                                  0.134997                       # Number of seconds simulated
 sim_ticks                                134996684500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                 38296034                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              45834466                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                1077                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            5781170                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           35418150                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 62209737                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 12344504                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               44587532                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events          13163574                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
@@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples    269852647                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0     99465935   3685.94%           
-                               1     57766030   2140.65%           
-                               2     39984554   1481.72%           
-                               3     29664959   1099.30%           
-                               4     23966120    888.12%           
-                               5     10452563    387.34%           
-                               6      5712016    211.67%           
-                               7      2252970     83.49%           
-                               8       587500     21.77%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples    269852647                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1     99465935     36.86%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2     57766030     21.41%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3     39984554     14.82%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4     29664959     10.99%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5     23966120      8.88%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6     10452563      3.87%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7      5712016      2.12%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8      2252970      0.83%           
+system.cpu.iq.ISSUE:issued_per_cycle::8        587500      0.22%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total    269852647                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.591981                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.720906                      
 system.cpu.iq.ISSUE:rate                     1.591151                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                  466283095                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 429600196                       # Number of instructions issued
@@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse              3875.343408                       # Cy
 system.cpu.l2cache.total_refs                     609                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          73961217                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         54131405                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            124841223                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            92324076                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                        269993372                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles          8452992                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      259532341                       # Number of HB maps that are committed
index 8803cb82c34625e58f7e6a2512c9339150434c76..3ec2c9e61ef2bb92a872f2f08cdcd473a274b4dd 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:24:11
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 6ff850ff758e2d3c4c81397a13fca480a27edf98..655e48f3b91bdb17111eb1bb4d5c9120a27d6de1 100644 (file)
@@ -1,25 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                    240462096                       # Number of BTB hits
-global.BPredUnit.BTBLookups                 294213603                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                    3593                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect               29107758                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted              233918302                       # Number of conditional branches predicted
-global.BPredUnit.lookups                    349424731                       # Number of BP lookups
-global.BPredUnit.usedRAS                     49888256                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 217689                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211464                       # Number of bytes of host memory used
-host_seconds                                  8374.52                       # Real time elapsed on the host
-host_tick_rate                               84202937                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads          118847053                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores          21034746                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads             655954745                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores            303651290                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 233158                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213372                       # Number of bytes of host memory used
+host_seconds                                  7818.92                       # Real time elapsed on the host
+host_tick_rate                               90186298                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_seconds                                  0.705159                       # Number of seconds simulated
 sim_ticks                                705159454500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                240462096                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             294213603                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                3593                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect           29107758                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          233918302                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                349424731                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 49888256                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches              266706457                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events          68860244                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
@@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples   1410161885                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0    537278436   3810.05%           
-                               1    285217724   2022.59%           
-                               2    273546804   1939.83%           
-                               3    154810620   1097.82%           
-                               4     63341841    449.18%           
-                               5     51438515    364.77%           
-                               6     32491109    230.41%           
-                               7      9036668     64.08%           
-                               8      3000168     21.28%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples   1410161885                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1    537278436     38.10%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2    285217724     20.23%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3    273546804     19.40%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4    154810620     10.98%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5     63341841      4.49%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6     51438515      3.65%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7     32491109      2.30%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8      9036668      0.64%           
+system.cpu.iq.ISSUE:issued_per_cycle::8       3000168      0.21%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total   1410161885                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.481750                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.637343                      
 system.cpu.iq.ISSUE:rate                     1.481585                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                 2386031660                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                2089507805                       # Number of instructions issued
@@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse             31919.645552                       # Cy
 system.cpu.l2cache.total_refs                   35353                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   66899                       # number of writebacks
+system.cpu.memDep0.conflictingLoads         118847053                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         21034746                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            655954745                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           303651290                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                       1410318910                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles         20063964                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1384969070                       # Number of HB maps that are committed
index 830b96073a239012ef339d929a7db62633751119..3c4f7e5f4ea09be52296f9c1abad3430127d4b44 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:29:46
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:23:18
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index ea0c054705aefe09aa368dbfd3bb9fefd235755a..c3cb349a5a03679a2fd16875c26f26b8be4b3171 100644 (file)
@@ -1,25 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                      8039250                       # Number of BTB hits
-global.BPredUnit.BTBLookups                  14256744                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                   34579                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                 452707                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted               10551565                       # Number of conditional branches predicted
-global.BPredUnit.lookups                     16249463                       # Number of BP lookups
-global.BPredUnit.usedRAS                      1941929                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 207814                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214944                       # Number of bytes of host memory used
-host_seconds                                   382.99                       # Real time elapsed on the host
-host_tick_rate                               70849023                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads           12835812                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores          11558188                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads              23001213                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores             16328872                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 261905                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 216920                       # Number of bytes of host memory used
+host_seconds                                   303.90                       # Real time elapsed on the host
+host_tick_rate                               89289765                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_seconds                                  0.027135                       # Number of seconds simulated
 sim_ticks                                 27134794500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                  8039250                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              14256744                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               34579                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect             452707                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           10551565                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 16249463                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1941929                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               13754477                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events           3320894                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
@@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples     53041270                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0     17563410   3311.27%           
-                               1     13937999   2627.76%           
-                               2      8266125   1558.43%           
-                               3      4784809    902.09%           
-                               4      4627568    872.45%           
-                               5      2066740    389.65%           
-                               6      1112374    209.72%           
-                               7       454507     85.69%           
-                               8       227738     42.94%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples     53041270                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1     17563410     33.11%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2     13937999     26.28%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3      8266125     15.58%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4      4784809      9.02%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5      4627568      8.72%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6      2066740      3.90%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7      1112374      2.10%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8       454507      0.86%           
+system.cpu.iq.ISSUE:issued_per_cycle::8        227738      0.43%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total     53041270                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.609055                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.711333                      
 system.cpu.iq.ISSUE:rate                     1.572637                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                   89571437                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                  85346345                       # Number of instructions issued
@@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse             18483.925058                       # Cy
 system.cpu.l2cache.total_refs                  118089                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                  120647                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          12835812                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11558188                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             23001213                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16328872                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                         54269590                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles          2047052                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       52546881                       # Number of HB maps that are committed
index 75ae695aae49890c750c32696baa0386d3a84ba8..644c3eb5c1070d48693e30240587be51d773d8c0 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:32:43
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:18:05
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py long/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index d59f4f0e0ca2136e1f89885d9a16fdba1bfd0874..16f472fdfdcad103fb8d9397376dbfb99f7c9815 100644 (file)
@@ -1,25 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                    312845737                       # Number of BTB hits
-global.BPredUnit.BTBLookups                 319575559                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                     136                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect               19647325                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted              266741494                       # Number of conditional branches predicted
-global.BPredUnit.lookups                    345502589                       # Number of BP lookups
-global.BPredUnit.usedRAS                     23750300                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 166211                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203924                       # Number of bytes of host memory used
-host_seconds                                 10444.84                       # Real time elapsed on the host
-host_tick_rate                               71069469                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads          127392983                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores          67515291                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads             621608435                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores            234046222                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 226973                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 205820                       # Number of bytes of host memory used
+host_seconds                                  7648.67                       # Real time elapsed on the host
+host_tick_rate                               97050740                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_seconds                                  0.742309                       # Number of seconds simulated
 sim_ticks                                742309425500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                312845737                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             319575559                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                 136                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect           19647325                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          266741494                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                345502589                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 23750300                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches              214632552                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events          62782585                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
@@ -306,21 +302,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples   1472299541                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0    577695763   3923.77%           
-                               1    271543756   1844.35%           
-                               2    242868170   1649.58%           
-                               3    139713874    948.95%           
-                               4    122021082    828.78%           
-                               5     69652698    473.09%           
-                               6     39670196    269.44%           
-                               7      8017828     54.46%           
-                               8      1116174      7.58%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples   1472299541                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1    577695763     39.24%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2    271543756     18.44%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3    242868170     16.50%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4    139713874      9.49%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5    122021082      8.29%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6     69652698      4.73%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7     39670196      2.69%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8      8017828      0.54%           
+system.cpu.iq.ISSUE:issued_per_cycle::8       1116174      0.08%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total   1472299541                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.572944                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.737325                      
 system.cpu.iq.ISSUE:rate                     1.559892                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                 2492922509                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                2315844900                       # Number of instructions issued
@@ -406,6 +404,10 @@ system.cpu.l2cache.tagsinuse             25902.034914                       # Cy
 system.cpu.l2cache.total_refs                 6731622                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          154290039500                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                 1195718                       # number of writebacks
+system.cpu.memDep0.conflictingLoads         127392983                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         67515291                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            621608435                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           234046222                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                       1484618852                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles         68342801                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
index f827bf3c92a801e8621971d758ca25bf71ce9fc8..4f595ede79516d5f2f9057704a62fa9077a6d7da 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:37:34
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:16:08
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py long/70.twolf/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 485a8a7d7e6cc2af288e9aa445cf654829eb7dc0..21c5777d879ac10917b0603bff73931dafa658b7 100644 (file)
@@ -1,25 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                     13008791                       # Number of BTB hits
-global.BPredUnit.BTBLookups                  16964874                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                    1204                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                1946248                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted               14605230                       # Number of conditional branches predicted
-global.BPredUnit.lookups                     19468548                       # Number of BP lookups
-global.BPredUnit.usedRAS                      1719783                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 179748                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 209188                       # Number of bytes of host memory used
-host_seconds                                   468.32                       # Real time elapsed on the host
-host_tick_rate                               87159490                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads           17216078                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores           5041116                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads              33976826                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores             10628051                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 205423                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211084                       # Number of bytes of host memory used
+host_seconds                                   409.79                       # Real time elapsed on the host
+host_tick_rate                               99609545                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.040819                       # Number of seconds simulated
 sim_ticks                                 40818658500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                 13008791                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              16964874                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                1204                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            1946248                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           14605230                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 19468548                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1719783                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               10240685                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events           2855802                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
@@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples     81528343                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0     35305774   4330.49%           
-                               1     18904885   2318.81%           
-                               2     11574997   1419.75%           
-                               3      6762756    829.50%           
-                               4      5075415    622.53%           
-                               5      2394533    293.71%           
-                               6      1208963    148.29%           
-                               7       250769     30.76%           
-                               8        50251      6.16%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples     81528343                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1     35305774     43.30%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2     18904885     23.19%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3     11574997     14.20%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4      6762756      8.29%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5      5075415      6.23%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6      2394533      2.94%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7      1208963      1.48%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8       250769      0.31%           
+system.cpu.iq.ISSUE:issued_per_cycle::8         50251      0.06%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total     81528343                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.275981                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.540298                      
 system.cpu.iq.ISSUE:rate                     1.274278                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                  135454267                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 104028641                       # Number of instructions issued
@@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse              2244.769579                       # Cy
 system.cpu.l2cache.total_refs                    7171                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          17216078                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5041116                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             33976826                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10628051                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                         81637318                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles          1761024                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       68427361                       # Number of HB maps that are committed
index 0d9f81ac8f2a42993e1e30a1d6977c35b5c8b020..f448ee025734a2403864c9d39a3a3a2b42d9b532 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:22:19
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index b0c4635e4b7bc2f2f46798c33a70f5e4e0f2bf8e..21437f2a44f0a0eb9fedb617b316377e5a0daae9 100644 (file)
@@ -1,43 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                          806                       # Number of BTB hits
-global.BPredUnit.BTBLookups                      1937                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                      67                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                    440                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted                   1370                       # Number of conditional branches predicted
-global.BPredUnit.lookups                         2263                       # Number of BP lookups
-global.BPredUnit.usedRAS                          304                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  68343                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 200684                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
-host_tick_rate                              133183507                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads                 36                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores                29                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads                  2287                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores                 1266                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                  83921                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202572                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
+host_tick_rate                              163392144                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6386                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
 sim_ticks                                    12474500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                      806                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  1937                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                  67                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect                440                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted               1370                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     2263                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                      304                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches                   1051                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events               115                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples        12416                      
-system.cpu.commit.COM:committed_per_cycle.min_value            0                      
-                               0         9513   7661.89%           
-                               1         1627   1310.41%           
-                               2          488    393.04%           
-                               3          267    215.05%           
-                               4          153    123.23%           
-                               5          104     83.76%           
-                               6           96     77.32%           
-                               7           53     42.69%           
-                               8          115     92.62%           
-system.cpu.commit.COM:committed_per_cycle.max_value            8                      
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
+system.cpu.commit.COM:committed_per_cycle::samples        12416                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0-1         9513     76.62%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1-2         1627     13.10%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2-3          488      3.93%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3-4          267      2.15%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4-5          153      1.23%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5-6          104      0.84%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6-7           96      0.77%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7-8           53      0.43%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8          115      0.93%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total        12416                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.515706                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.304935                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      6403                       # Number of instructions committed
 system.cpu.commit.COM:loads                      1185                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
@@ -147,21 +145,23 @@ system.cpu.fetch.branchRate                  0.090701                       # Nu
 system.cpu.fetch.icacheStallCycles               1802                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches               1110                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.rate                        0.531102                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples               13314                      
-system.cpu.fetch.rateDist.min_value                 0                      
-                               0        10844   8144.81%           
-                               1          252    189.27%           
-                               2          238    178.76%           
-                               3          230    172.75%           
-                               4          272    204.30%           
-                               5          162    121.68%           
-                               6          232    174.25%           
-                               7          129     96.89%           
-                               8          955    717.29%           
-system.cpu.fetch.rateDist.max_value                 8                      
-system.cpu.fetch.rateDist.end_dist
-
+system.cpu.fetch.rateDist::samples              13314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0-1                  10844     81.45%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1-2                    252      1.89%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2-3                    238      1.79%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3-4                    230      1.73%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4-5                    272      2.04%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5-6                    162      1.22%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6-7                    232      1.74%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7-8                    129      0.97%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      955      7.17%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total                13314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.995268                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.362110                       # Number of instructions fetched each cycle (Total)
 system.cpu.icache.ReadReq_accesses               1802                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 35400.943396                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951                       # average ReadReq mshr miss latency
@@ -296,21 +296,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples        13314                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0         9113   6844.67%           
-                               1         1716   1288.87%           
-                               2         1071    804.42%           
-                               3          725    544.54%           
-                               4          355    266.64%           
-                               5          172    129.19%           
-                               6          115     86.38%           
-                               7           34     25.54%           
-                               8           13      9.76%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples        13314                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1         9113     68.45%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2         1716     12.89%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3         1071      8.04%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4          725      5.45%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5          355      2.67%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6          172      1.29%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7          115      0.86%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8           34      0.26%           
+system.cpu.iq.ISSUE:issued_per_cycle::8            13      0.10%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total        13314                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.701893                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.302449                      
 system.cpu.iq.ISSUE:rate                     0.374549                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                      10972                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      9345                       # Number of instructions issued
@@ -394,6 +396,10 @@ system.cpu.l2cache.tagsinuse               214.901533                       # Cy
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.memDep0.conflictingLoads                36                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               29                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads                 2287                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1266                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                            24950                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles              371                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           4583                       # Number of HB maps that are committed
index d373e353b0ed30cdfe751343b2d5b840d007ca12..038644e5f6877e65c04a7057b1f38bdcc01beaff 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:16:36
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index af633c5e87757f443748a47bbeaefbe5e8bed316..14b605eaaa4fe560762768f3fc3dc062810b014d 100644 (file)
@@ -1,43 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                          198                       # Number of BTB hits
-global.BPredUnit.BTBLookups                       684                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                      35                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                    209                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted                    447                       # Number of conditional branches predicted
-global.BPredUnit.lookups                          859                       # Number of BP lookups
-global.BPredUnit.usedRAS                          165                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  22600                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199684                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                               67889683                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads                  7                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores                 7                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads                   738                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores                  411                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                  39458                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201572                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                              118256203                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2387                       # Number of instructions simulated
 sim_seconds                                  0.000007                       # Number of seconds simulated
 sim_ticks                                     7183000                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                      198                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                   684                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                  35                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect                209                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted                447                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                      859                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                      165                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches                    396                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events                38                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples         6196                      
-system.cpu.commit.COM:committed_per_cycle.min_value            0                      
-                               0         5239   8455.46%           
-                               1          263    424.47%           
-                               2          334    539.06%           
-                               3          134    216.27%           
-                               4           73    117.82%           
-                               5           63    101.68%           
-                               6           32     51.65%           
-                               7           20     32.28%           
-                               8           38     61.33%           
-system.cpu.commit.COM:committed_per_cycle.max_value            8                      
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
+system.cpu.commit.COM:committed_per_cycle::samples         6196                      
+system.cpu.commit.COM:committed_per_cycle::min_value            0                      
+system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%           
+system.cpu.commit.COM:committed_per_cycle::0-1         5239     84.55%           
+system.cpu.commit.COM:committed_per_cycle::1-2          263      4.24%           
+system.cpu.commit.COM:committed_per_cycle::2-3          334      5.39%           
+system.cpu.commit.COM:committed_per_cycle::3-4          134      2.16%           
+system.cpu.commit.COM:committed_per_cycle::4-5           73      1.18%           
+system.cpu.commit.COM:committed_per_cycle::5-6           63      1.02%           
+system.cpu.commit.COM:committed_per_cycle::6-7           32      0.52%           
+system.cpu.commit.COM:committed_per_cycle::7-8           20      0.32%           
+system.cpu.commit.COM:committed_per_cycle::8           38      0.61%           
+system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%           
+system.cpu.commit.COM:committed_per_cycle::total         6196                      
+system.cpu.commit.COM:committed_per_cycle::max_value            8                      
+system.cpu.commit.COM:committed_per_cycle::mean     0.415752                      
+system.cpu.commit.COM:committed_per_cycle::stdev     1.208059                      
 system.cpu.commit.COM:count                      2576                       # Number of instructions committed
 system.cpu.commit.COM:loads                       415                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
@@ -147,21 +145,23 @@ system.cpu.fetch.branchRate                  0.059790                       # Nu
 system.cpu.fetch.icacheStallCycles                747                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches                363                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.rate                        0.375374                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples                6528                      
-system.cpu.fetch.rateDist.min_value                 0                      
-                               0         5595   8570.77%           
-                               1           36     55.15%           
-                               2          100    153.19%           
-                               3           69    105.70%           
-                               4          130    199.14%           
-                               5           72    110.29%           
-                               6           45     68.93%           
-                               7           48     73.53%           
-                               8          433    663.30%           
-system.cpu.fetch.rateDist.max_value                 8                      
-system.cpu.fetch.rateDist.end_dist
-
+system.cpu.fetch.rateDist::samples               6528                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0-1                   5595     85.71%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1-2                     36      0.55%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2-3                    100      1.53%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3-4                     69      1.06%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4-5                    130      1.99%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5-6                     72      1.10%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6-7                     45      0.69%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7-8                     48      0.74%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      433      6.63%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total                 6528                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.826134                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.219931                       # Number of instructions fetched each cycle (Total)
 system.cpu.icache.ReadReq_accesses                747                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 35989.361702                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541                       # average ReadReq mshr miss latency
@@ -296,21 +296,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples         6528                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0         5051   7737.44%           
-                               1          569    871.63%           
-                               2          331    507.05%           
-                               3          253    387.56%           
-                               4          172    263.48%           
-                               5           97    148.59%           
-                               6           39     59.74%           
-                               7           11     16.85%           
-                               8            5      7.66%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples         6528                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1         5051     77.37%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2          569      8.72%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3          331      5.07%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4          253      3.88%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5          172      2.63%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6           97      1.49%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7           39      0.60%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8           11      0.17%           
+system.cpu.iq.ISSUE:issued_per_cycle::8             5      0.08%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total         6528                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.538297                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.220228                      
 system.cpu.iq.ISSUE:rate                     0.244588                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                       4031                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      3514                       # Number of instructions issued
@@ -393,6 +395,10 @@ system.cpu.l2cache.tagsinuse               110.762790                       # Cy
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                7                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads                  738                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                 411                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                            14367                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles               14                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           1768                       # Number of HB maps that are committed
index 73f0d59691143a7c0c4616bf33fe1ecadca31948..7101807dffd8d7713335af43deeed642d1181f4c 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:22:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
+M5 compiled Mar  6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:23:16
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index c9242b88622d48e05fe339bbcba5aac410a70fab..7838679393d4ca16d04d23526c741b07b8340a6b 100644 (file)
@@ -1,29 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                          916                       # Number of BTB hits
-global.BPredUnit.BTBLookups                      4733                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                     175                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                   1595                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted                   3153                       # Number of conditional branches predicted
-global.BPredUnit.lookups                         5548                       # Number of BP lookups
-global.BPredUnit.usedRAS                          681                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  67823                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201212                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
-host_tick_rate                               75589135                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads                 22                       # Number of conflicting loads.
-memdepunit.memDep.conflictingLoads                 58                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores                 4                       # Number of conflicting stores.
-memdepunit.memDep.conflictingStores                32                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads                  2431                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads                  2520                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores                 1282                       # Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores                 1303                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                 106034                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203088                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
+host_tick_rate                              118060043                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       12773                       # Number of instructions simulated
 sim_seconds                                  0.000014                       # Number of seconds simulated
 sim_ticks                                    14251500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                      916                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  4733                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                 175                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect               1595                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted               3153                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     5548                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                      681                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches                   2102                       # Number of branches committed
 system.cpu.commit.COM:branches_0                 1051                       # Number of branches committed
 system.cpu.commit.COM:branches_1                 1051                       # Number of branches committed
@@ -31,21 +23,23 @@ system.cpu.commit.COM:bw_lim_events               122                       # nu
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
 system.cpu.commit.COM:bw_limited_0                  0                       # number of insts not committed due to BW limits
 system.cpu.commit.COM:bw_limited_1                  0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples        22837                      
-system.cpu.commit.COM:committed_per_cycle.min_value            0                      
-                               0        16880   7391.51%           
-                               1         3016   1320.66%           
-                               2         1386    606.91%           
-                               3          576    252.22%           
-                               4          326    142.75%           
-                               5          268    117.35%           
-                               6          170     74.44%           
-                               7           93     40.72%           
-                               8          122     53.42%           
-system.cpu.commit.COM:committed_per_cycle.max_value            8                      
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
+system.cpu.commit.COM:committed_per_cycle::samples        22837                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0-1        16880     73.92%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1-2         3016     13.21%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2-3         1386      6.07%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3-4          576      2.52%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4-5          326      1.43%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5-6          268      1.17%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6-7          170      0.74%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7-8           93      0.41%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8          122      0.53%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total        22837                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.560800                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.272250                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                     12807                       # Number of instructions committed
 system.cpu.commit.COM:count_0                    6403                       # Number of instructions committed
 system.cpu.commit.COM:count_1                    6404                       # Number of instructions committed
@@ -239,21 +233,23 @@ system.cpu.fetch.branchRate                  0.194639                       # Nu
 system.cpu.fetch.icacheStallCycles               4113                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches               1597                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.rate                        1.085777                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples               22904                      
-system.cpu.fetch.rateDist.min_value                 0                      
-                               0        17622   7693.85%           
-                               1          416    181.63%           
-                               2          353    154.12%           
-                               3          477    208.26%           
-                               4          425    185.56%           
-                               5          349    152.38%           
-                               6          442    192.98%           
-                               7          261    113.95%           
-                               8         2559   1117.27%           
-system.cpu.fetch.rateDist.max_value                 8                      
-system.cpu.fetch.rateDist.end_dist
-
+system.cpu.fetch.rateDist::samples              22904                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0-1                  17622     76.94%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1-2                    416      1.82%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2-3                    353      1.54%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3-4                    477      2.08%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4-5                    425      1.86%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5-6                    349      1.52%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6-7                    442      1.93%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7-8                    261      1.14%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2559     11.17%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total                22904                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.351249                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.742840                       # Number of instructions fetched each cycle (Total)
 system.cpu.icache.ReadReq_accesses               4113                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses_0             4113                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979                       # average ReadReq miss latency
@@ -530,21 +526,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples        22904                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0        14156   6180.58%           
-                               1         3289   1435.99%           
-                               2         2351   1026.46%           
-                               3         1373    599.46%           
-                               4          854    372.86%           
-                               5          535    233.58%           
-                               6          261    113.95%           
-                               7           57     24.89%           
-                               8           28     12.22%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples        22904                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1        14156     61.81%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2         3289     14.36%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3         2351     10.26%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4         1373      5.99%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5          854      3.73%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6          535      2.34%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7          261      1.14%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8           57      0.25%           
+system.cpu.iq.ISSUE:issued_per_cycle::8            28      0.12%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total        22904                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.890238                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.446450                      
 system.cpu.iq.ISSUE:rate                     0.715338                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                      23596                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     20390                       # Number of instructions issued
@@ -702,6 +700,14 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.writebacks_0                     0                       # number of writebacks
 system.cpu.l2cache.writebacks_1                     0                       # number of writebacks
+system.cpu.memDep0.conflictingLoads                22                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads                 2431                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1282                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads                58                       # Number of conflicting loads.
+system.cpu.memDep1.conflictingStores               32                       # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads                 2520                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1303                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                            28504                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles             2835                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           9166                       # Number of HB maps that are committed
index d0efe85b3abb3a8a35e49f413bb5561cd2a52b9a..f1994d462cda1c6c49e930c9778060cb7ad96178 100755 (executable)
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:17:34
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing
+M5 compiled Mar  6 2009 18:29:06
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar  6 2009 18:30:50
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
index 0584aa2e20cee84152aecd8ab930795023296954..67e62423ea06200867b5e32b1252b930255a7427 100644 (file)
@@ -1,43 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                         4398                       # Number of BTB hits
-global.BPredUnit.BTBLookups                      9844                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                       0                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect                   2923                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted                  11413                       # Number of conditional branches predicted
-global.BPredUnit.lookups                        11413                       # Number of BP lookups
-global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  30716                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201632                       # Number of bytes of host memory used
-host_seconds                                     0.47                       # Real time elapsed on the host
-host_tick_rate                               58973694                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads                 26                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores                 0                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads                  4960                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores                 3415                       # Number of stores inserted to the mem dependence unit.
+host_inst_rate                                  66771                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203496                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
+host_tick_rate                              128111456                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       14449                       # Number of instructions simulated
 sim_seconds                                  0.000028                       # Number of seconds simulated
 sim_ticks                                    27756500                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                     4398                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  9844                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect               2923                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted              11413                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                    11413                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches                   3359                       # Number of branches committed
 system.cpu.commit.COM:bw_lim_events               103                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples        42766                      
-system.cpu.commit.COM:committed_per_cycle.min_value            0                      
-                               0        34594   8089.14%           
-                               1         4804   1123.32%           
-                               2         1741    407.10%           
-                               3          720    168.36%           
-                               4          413     96.57%           
-                               5          144     33.67%           
-                               6          196     45.83%           
-                               7           51     11.93%           
-                               8          103     24.08%           
-system.cpu.commit.COM:committed_per_cycle.max_value            8                      
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
+system.cpu.commit.COM:committed_per_cycle::samples        42766                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0-1        34594     80.89%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1-2         4804     11.23%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2-3         1741      4.07%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3-4          720      1.68%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4-5          413      0.97%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5-6          144      0.34%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6-7          196      0.46%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7-8           51      0.12%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8          103      0.24%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%            # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total        42766                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.354838                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     0.957636                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                     15175                       # Number of instructions committed
 system.cpu.commit.COM:loads                      2226                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
@@ -134,21 +132,23 @@ system.cpu.fetch.branchRate                  0.205588                       # Nu
 system.cpu.fetch.icacheStallCycles               7356                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches               4398                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.rate                        1.049231                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples               47090                      
-system.cpu.fetch.rateDist.min_value                 0                      
-                               0        30448   6465.92%           
-                               1         7532   1599.49%           
-                               2         1217    258.44%           
-                               3         1059    224.89%           
-                               4         1060    225.10%           
-                               5         1193    253.34%           
-                               6          711    150.99%           
-                               7          327     69.44%           
-                               8         3543    752.39%           
-system.cpu.fetch.rateDist.max_value                 8                      
-system.cpu.fetch.rateDist.end_dist
-
+system.cpu.fetch.rateDist::samples              47090                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0-1                  30448     64.66%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1-2                   7532     15.99%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2-3                   1217      2.58%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3-4                   1059      2.25%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4-5                   1060      2.25%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5-6                   1193      2.53%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6-7                    711      1.51%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7-8                    327      0.69%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     3543      7.52%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%            # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total                47090                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.236929                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.372442                       # Number of instructions fetched each cycle (Total)
 system.cpu.icache.ReadReq_accesses               7356                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 33620.560748                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780                       # average ReadReq mshr miss latency
@@ -283,21 +283,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                        IprAccess            0      0.00%            # attempts to use FU when none available
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples        47090                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0        34112   7244.00%           
-                               1         5516   1171.37%           
-                               2         3070    651.94%           
-                               3         2146    455.72%           
-                               4          997    211.72%           
-                               5          653    138.67%           
-                               6          342     72.63%           
-                               7          211     44.81%           
-                               8           43      9.13%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples        47090                      
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                      
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::0-1        34112     72.44%           
+system.cpu.iq.ISSUE:issued_per_cycle::1-2         5516     11.71%           
+system.cpu.iq.ISSUE:issued_per_cycle::2-3         3070      6.52%           
+system.cpu.iq.ISSUE:issued_per_cycle::3-4         2146      4.56%           
+system.cpu.iq.ISSUE:issued_per_cycle::4-5          997      2.12%           
+system.cpu.iq.ISSUE:issued_per_cycle::5-6          653      1.39%           
+system.cpu.iq.ISSUE:issued_per_cycle::6-7          342      0.73%           
+system.cpu.iq.ISSUE:issued_per_cycle::7-8          211      0.45%           
+system.cpu.iq.ISSUE:issued_per_cycle::8            43      0.09%           
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%           
+system.cpu.iq.ISSUE:issued_per_cycle::total        47090                      
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.620514                      
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.275912                      
 system.cpu.iq.ISSUE:rate                     0.526354                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                      32302                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     29220                       # Number of instructions issued
@@ -377,6 +379,10 @@ system.cpu.l2cache.tagsinuse               251.642612                       # Cy
 system.cpu.l2cache.total_refs                       4                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.memDep0.conflictingLoads                26                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads                 4960                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                3415                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                            55514                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles               32                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps          13832                       # Number of HB maps that are committed