intel: Update alignment restrictions for HiZ surfaces.

v2 (Nanley):
* Maintain a chronological ordering for HiZ alignments. Suggested by
  Ken.

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 5fd6aded2aed34e22fef080ffb6c8d21ad3ae9c1..f1859588013bb9076cfaf045c6a6ab92cf8ea5ff 100644 (file)
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -656,11 +656,17 @@ isl_choose_image_alignment_el(const struct isl_device *dev,
       if (ISL_DEV_GEN(dev) == 6) {
          /* HiZ surfaces on Sandy Bridge are packed tightly. */
          *image_align_el = isl_extent3d(1, 1, 1);
-      } else {
+      } else if (ISL_DEV_GEN(dev) < 12) {
          /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
           * primary surface which works out to 2x2 HiZ elments.
           */
          *image_align_el = isl_extent3d(2, 2, 1);
+      } else {
+         /* On gen12+, HiZ surfaces are always aligned to 16x16 pixels in the
+          * primary surface which works out to 2x4 HiZ elments.
+          * TODO: Verify
+          */
+         *image_align_el = isl_extent3d(2, 4, 1);
       }
       return;
    }