i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE

Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE.  Only SSE register
source operand is allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_ashr<mode>3): Also allow
	TARGET_MMX_WITH_SSE.  Add SSE emulation.
	(mmx_<shift_insn><mode>3): Likewise.
	(ashr<mode>3): New.
	(<shift_insn><mode>3): Likewise.

From-SVN: r271221

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 597ba816fd40862c90c8d1fd68d229ff27a3204f..ecf9f7b98a5dbbc50fe3cf8d9f031f2c54378e53 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/89021
+       * config/i386/mmx.md (mmx_ashr<mode>3): Also allow
+       TARGET_MMX_WITH_SSE.  Add SSE emulation.
+       (mmx_<shift_insn><mode>3): Likewise.
+       (ashr<mode>3): New.
+       (<shift_insn><mode>3): Likewise.
+
 2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/89021

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 7cbca961a6089327fc6df891cb333b1aa4f31b82..73110b5e43c5d0c5eb3b3a0263145be2d6fd964a 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -984,32 +984,54 @@
    (set_attr "mode" "DI")])
 
 (define_insn "mmx_ashr<mode>3"
-  [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
+  [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv")
         (ashiftrt:MMXMODE24
-         (match_operand:MMXMODE24 1 "register_operand" "0")
-         (match_operand:DI 2 "nonmemory_operand" "yN")))]
-  "TARGET_MMX"
-  "psra<mmxvecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxshft")
+         (match_operand:MMXMODE24 1 "register_operand" "0,0,Yv")
+         (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
+  "@
+   psra<mmxvecsize>\t{%2, %0|%0, %2}
+   psra<mmxvecsize>\t{%2, %0|%0, %2}
+   vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxshft,sseishft,sseishft")
    (set (attr "length_immediate")
      (if_then_else (match_operand 2 "const_int_operand")
        (const_string "1")
        (const_string "0")))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
+
+(define_expand "ashr<mode>3"
+  [(set (match_operand:MMXMODE24 0 "register_operand")
+        (ashiftrt:MMXMODE24
+         (match_operand:MMXMODE24 1 "register_operand")
+         (match_operand:DI 2 "nonmemory_operand")))]
+  "TARGET_MMX_WITH_SSE")
 
 (define_insn "mmx_<shift_insn><mode>3"
-  [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
+  [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv")
         (any_lshift:MMXMODE248
-         (match_operand:MMXMODE248 1 "register_operand" "0")
-         (match_operand:DI 2 "nonmemory_operand" "yN")))]
-  "TARGET_MMX"
-  "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxshft")
+         (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv")
+         (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))]
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
+  "@
+   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
+   p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
+   vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxshft,sseishft,sseishft")
    (set (attr "length_immediate")
      (if_then_else (match_operand 2 "const_int_operand")
        (const_string "1")
        (const_string "0")))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
+
+(define_expand "<shift_insn><mode>3"
+  [(set (match_operand:MMXMODE248 0 "register_operand")
+        (any_lshift:MMXMODE248
+         (match_operand:MMXMODE248 1 "register_operand")
+         (match_operand:DI 2 "nonmemory_operand")))]
+  "TARGET_MMX_WITH_SSE")
 
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