Stats: Update stats for minor O3 changes below.
authorAli Saidi <Ali.Saidi@ARM.com>
Mon, 23 May 2011 15:59:13 +0000 (10:59 -0500)
committerAli Saidi <Ali.Saidi@ARM.com>
Mon, 23 May 2011 15:59:13 +0000 (10:59 -0500)
33 files changed:
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
tests/long/20.parser/ref/arm/linux/o3-timing/simout
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
tests/long/20.parser/ref/x86/linux/o3-timing/simout
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
tests/long/30.eon/ref/arm/linux/o3-timing/simout
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
tests/long/70.twolf/ref/arm/linux/o3-timing/simout
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/arm/linux/o3-timing/simout
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/x86/linux/o3-timing/simout
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt

index df78a3a5da066c71506e6250d6db916ea6748e23..7084f92e245bf24a9f8563855585ab503c4caab9 100755 (executable)
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 13:57:03
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 16:32:58
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -44,4 +44,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 189747670000 because target called exit()
+Exiting @ tick 189745250000 because target called exit()
index b2bd08a2b80ac99eeeea4aba0f4f14bf77d7f731..1e34e6b021eb49fd32a924020ba71f51b9317338 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 210962                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 262196                       # Number of bytes of host memory used
-host_seconds                                  2855.31                       # Real time elapsed on the host
-host_tick_rate                               66454392                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.189745                       # Number of seconds simulated
+sim_ticks                                189745250000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   602359850                       # Number of instructions simulated
-sim_seconds                                  0.189748                       # Number of seconds simulated
-sim_ticks                                189747670000                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 74615208                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              80130233                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                1670                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            3884107                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           80516162                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 86913734                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  1397693                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts           3943213                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                   70828611                       # Number of branches committed
-system.cpu.commit.bw_lim_events              15126616                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts      602359901                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls            6307                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        75686006                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples    366955970                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.641505                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.022822                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    118814632     32.38%     32.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    123407521     33.63%     66.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     52313499     14.26%     80.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12481991      3.40%     83.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     20938472      5.71%     89.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13691845      3.73%     93.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7616390      2.08%     95.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2565004      0.70%     95.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15126616      4.12%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    366955970                       # Number of insts commited each cycle
-system.cpu.commit.count                     602359901                       # Number of instructions committed
-system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls               997573                       # Number of function calls committed.
-system.cpu.commit.int_insts                 533522679                       # Number of committed integer instructions.
-system.cpu.commit.loads                     148952604                       # Number of loads committed
-system.cpu.commit.membars                        1328                       # Number of memory barriers committed
-system.cpu.commit.refs                      219173627                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                   602359850                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             602359850                       # Number of Instructions Simulated
-system.cpu.cpi                               0.630014                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.630014                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses         1349                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits             1334                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency       152000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.011119                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses             15                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits           15                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses          138720806                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13339.905680                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8226.668223                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              138476956                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     3252936000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.001758                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               243850                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits             46844                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1620703000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001420                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          197006                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses          1337                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits              1337                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 17857.107875                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.095668                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              67921343                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   26717590518                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.021553                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1496188                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1248875                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   2561939027                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003563                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         247313                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4385.596339                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 464.535408                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs              2185                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs      9582528                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           208138337                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 17224.064370                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  9413.601550                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               206398299                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     29970526518                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.008360                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1740038                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1295719                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   4182642027                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002135                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           444319                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4094.816119                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999711                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          208138337                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 17224.064370                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  9413.601550                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              206398299                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    29970526518                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.008360                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1740038                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1295719                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   4182642027                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002135                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          444319                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 440221                       # number of replacements
-system.cpu.dcache.sampled_refs                 444317                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.816119                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                206400979                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               88948000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   394697                       # number of writebacks
-system.cpu.decode.BlockedCycles              57854165                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                  1286                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved              5859491                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts              711052352                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                160285716                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                 140722772                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles               11629973                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                  4744                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles               8093316                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+host_inst_rate                                  57706                       # Simulator instruction rate (inst/s)
+host_tick_rate                               18177630                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255472                       # Number of bytes of host memory used
+host_seconds                                 10438.39                       # Real time elapsed on the host
+sim_insts                                   602359840                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    86913734                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  70195415                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     151344798                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                922649                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      678928974                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                   33                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 4471477                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.229025                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           70195415                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           76012901                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.789031                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          378585942                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.910009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.919514                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                        379490501                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 86928352                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           80528545                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3884028                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              80092626                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 74490175                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1400314                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1695                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           70199329                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      678993278                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86928352                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           75890489                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     151223447                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4473449                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   35                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                  70199329                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                924096                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          378585601                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.910199                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.920341                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                227241307     60.02%     60.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 25123172      6.64%     66.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 17643544      4.66%     71.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 21901113      5.78%     77.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11234102      2.97%     80.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 11763660      3.11%     83.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4451384      1.18%     84.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7295384      1.93%     86.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 51932276     13.72%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                227362317     60.06%     60.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25157685      6.65%     66.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 17486331      4.62%     71.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 21712752      5.74%     77.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 11244311      2.97%     80.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 11955687      3.16%     83.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4446495      1.17%     84.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7289466      1.93%     86.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 51930557     13.72%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            378585942                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            378585601                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.229066                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.789223                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                160153181                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              58093543                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 140600980                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8092430                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               11645467                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              5860940                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  1284                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              711110342                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  4730                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               11645467                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                169808793                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 7731895                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         102804                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 138994558                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              50302084                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              699378515                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   157                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               44454073                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4930432                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              610                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           723286205                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3254558347                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3254558219                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               128                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             627417450                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 95868750                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               6063                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           6060                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  83251971                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            172882787                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            80813690                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          15992884                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         23084405                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  678074240                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                7046                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 648954836                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            321485                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        74818706                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    185294154                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            741                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     378585601                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.714156                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.635088                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            99002495     26.15%     26.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           107489876     28.39%     54.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            72418873     19.13%     73.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            48797355     12.89%     86.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            22456398      5.93%     92.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            17049752      4.50%     97.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             6015477      1.59%     98.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3775065      1.00%     99.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1580310      0.42%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       378585601                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  164864      5.19%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2380738     74.98%     80.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                629773     19.83%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             405017368     62.41%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 6545      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            167786137     25.85%     88.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            76144783     11.73%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              648954836                       # Type of FU issued
+system.cpu.iq.rate                           1.710069                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3175375                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.004893                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1679992097                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         753424475                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    636613588                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              652130191                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         25625639                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     23930184                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       271058                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       524844                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     10592669                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads        15888                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         12323                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               11645467                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  694588                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 38667                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           678142321                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           3267373                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             172882787                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             80813690                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5710                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   7359                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3854                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         524844                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3752039                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       638545                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              4390584                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             642328929                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             165615332                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6625907                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         61035                       # number of nop insts executed
+system.cpu.iew.exec_refs                    240294143                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 74636278                       # Number of branches executed
+system.cpu.iew.exec_stores                   74678811                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.692609                       # Inst execution rate
+system.cpu.iew.wb_sent                      637663585                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     636613604                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 410591202                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 620919251                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.677548                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.661263                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      602359891                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        75781554                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls            6305                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           3943142                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    366940135                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.641575                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.021399                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    118738354     32.36%     32.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    123466865     33.65%     66.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     52180899     14.22%     80.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12560554      3.42%     83.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     20975428      5.72%     89.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     13806386      3.76%     93.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7633759      2.08%     95.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2509750      0.68%     95.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15068140      4.11%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    366940135                       # Number of insts commited each cycle
+system.cpu.commit.count                     602359891                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      219173623                       # Number of memory references committed
+system.cpu.commit.loads                     148952602                       # Number of loads committed
+system.cpu.commit.membars                        1328                       # Number of memory barriers committed
+system.cpu.commit.branches                   70828609                       # Number of branches committed
+system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 533522671                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               997573                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              15068140                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   1030012828                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1367937117                       # The number of ROB writes
+system.cpu.timesIdled                           36799                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          904900                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   602359840                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             602359840                       # Number of Instructions Simulated
+system.cpu.cpi                               0.630006                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.630006                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.587286                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.587286                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3206207435                       # number of integer regfile reads
+system.cpu.int_regfile_writes               661050575                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses           70195415                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35447.995666                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34312.158470                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               70194492                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       32718500                       # number of ReadReq miss cycles
+system.cpu.misc_regfile_reads               912573919                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                   2672                       # number of misc regfile writes
+system.cpu.icache.replacements                     41                       # number of replacements
+system.cpu.icache.tagsinuse                627.011637                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 70198409                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    729                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               96294.113855                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            627.011637                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.306158                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               70198409                       # number of ReadReq hits
+system.cpu.icache.demand_hits                70198409                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               70198409                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  920                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   920                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  920                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       32585000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        32585000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       32585000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           70199329                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            70199329                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           70199329                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000013                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  923                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               191                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     25116500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             732                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               96156.838356                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000013                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000013                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35418.478261                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35418.478261                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35418.478261                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            70195415                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35447.995666                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34312.158470                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                70194492                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        32718500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000013                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   923                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                191                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     25116500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               189                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                189                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               189                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             731                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              731                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             731                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     25045500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     25045500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     25045500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000010                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              732                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            626.402984                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.305861                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses           70195415                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35447.995666                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34312.158470                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               70194492                       # number of overall hits
-system.cpu.icache.overall_miss_latency       32718500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000013                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  923                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               191                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     25116500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000010                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             732                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                     43                       # number of replacements
-system.cpu.icache.sampled_refs                    730                       # Sample count of references to valid blocks.
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34261.969904                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34261.969904                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34261.969904                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                626.402984                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 70194492                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          909399                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts              4390377                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 74630961                       # Number of branches executed
-system.cpu.iew.exec_nop                         61033                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.692381                       # Inst execution rate
-system.cpu.iew.exec_refs                    240248450                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                   74641760                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                  692845                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             172870468                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts               5721                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           3255991                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             80793372                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           678046798                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             165606690                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           6567715                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             642250536                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                   7466                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  3846                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               11629973                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 38806                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked         12320                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads         25624582                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses       272347                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation       522665                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads        15873                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads     23917863                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores     10572349                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         522665                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       636797                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        3753580                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                 620419783                       # num instructions consuming a value
-system.cpu.iew.wb_count                     636524370                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.661688                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                 410524106                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.677292                       # insts written-back per cycle
-system.cpu.iew.wb_sent                      637578270                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads               3205843747                       # number of integer regfile reads
-system.cpu.int_regfile_writes               660980878                       # number of integer regfile writes
-system.cpu.ipc                               1.587265                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.587265                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             404976250     62.42%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 6544      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            167780307     25.86%     88.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            76055147     11.72%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              648818251                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     3420971                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.005273                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  164650      4.81%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2528736     73.92%     78.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                727585     21.27%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses              652239202                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         1679971887                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    636524354                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         753225503                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  677978706                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 648818251                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                7059                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        74717328                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            328508                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved            752                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    185330852                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples     378585942                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.713794                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.641678                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            99098284     26.18%     26.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           107923682     28.51%     54.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            72401438     19.12%     73.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            48461841     12.80%     86.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            21953161      5.80%     92.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            16842853      4.45%     96.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             6368110      1.68%     98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3821983      1.01%     99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1714590      0.45%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       378585942                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.709687                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          247312                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.062545                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.030776                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              188954                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   2003142000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.235969                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             58358                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1822989000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235969                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        58358                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            197735                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34360.710576                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.859290                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                165001                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1124763500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.165545                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               32734                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits                7                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1018296000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165509                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          32727                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses              2                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 440236                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.816019                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                206409236                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 444332                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 464.538309                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               88952000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.816019                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999711                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              138485254                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              67921309                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             1329                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              1335                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               206406563                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              206406563                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               243961                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1496222                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses             15                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               1740183                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1740183                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     3253587000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   26715936018                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       152000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     29969523018                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    29969523018                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          138729215                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         1344                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          1335                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           208146746                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          208146746                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001759                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.021554                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.011161                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.008360                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.008360                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 13336.504605                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 17855.596307                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 17222.052519                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 17222.052519                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      9582528                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2185                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4385.596339                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   394716                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             46944                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1248905                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits           15                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1295849                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1295849                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          197017                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         247317                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           444334                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          444334                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1620169000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2562065527                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4182234527                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4182234527                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001420                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003563                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002135                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002135                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8223.498480                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.439614                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  9412.366659                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  9412.366659                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 72895                       # number of replacements
+system.cpu.l2cache.tagsinuse             17837.050931                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  420745                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 88410                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.759020                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1909.078024                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15927.972907                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.058260                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.486083                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                165017                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              394716                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits                  1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_rate      0.500000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_hits              188953                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 353970                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                353970                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32728                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          394697                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              394697                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5845.170455                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  4.758732                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs              352                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_misses             58363                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                91091                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               91091                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1124545500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2003459500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3128005000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3128005000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            197745                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          394716                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses              2                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          247316                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             445061                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            445061                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.165506                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.500000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.235986                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.204671                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.204671                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34360.348937                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34327.561983                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34339.341977                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34339.341977                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs      2057500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              352                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5845.170455                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             445047                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34337.872700                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31193.775045                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 353955                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     3127905500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.204680                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                91092                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                 7                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   2841285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.204664                       # mshr miss rate for demand accesses
+system.cpu.l2cache.writebacks                   58107                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits                6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                 6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                6                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          32722                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58363                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses           91085                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          1908.878881                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15928.587231                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.058254                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.486102                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses            445047                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34337.872700                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31193.775045                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                353955                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    3127905500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.204680                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               91092                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                7                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   2841285000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.204664                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses          91085                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 72893                       # number of replacements
-system.cpu.l2cache.sampled_refs                 88408                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1018131500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        32000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1823239000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2841370500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2841370500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165476                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.500000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235986                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.204657                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.204657                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.586517                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        32000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31239.638127                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.713729                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.713729                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             17837.466112                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  420710                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   58103                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          15581715                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         22335111                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            172870468                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            80793372                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               912454826                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                   2676                       # number of misc regfile writes
-system.cpu.numCycles                        379495341                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                 7724801                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps             627417466                       # Number of HB maps that are committed
-system.cpu.rename.FullRegisterEvents              610                       # Number of times there has been no free registers
-system.cpu.rename.IQFullEvents               44461884                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                169816321                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents               4814649                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                   165                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups            3254253647                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts              699315987                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands           723227895                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                 139243664                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles               11629973                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles              50068276                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                 95810424                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups               128                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups       3254253519                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles         102907                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts               6090                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  82758432                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts           6087                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   1029874649                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1367730511                       # The number of ROB writes
-system.cpu.timesIdled                           36653                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 75039630927a0fcc8f20816ac4bead9d07af711f..e576e666c12f65574f37a42b7f4f0d99f9716ae7 100755 (executable)
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2011 13:27:10
-M5 started Apr 21 2011 13:30:00
-M5 executing on maize
+M5 compiled May 17 2011 09:24:34
+M5 started May 18 2011 08:03:10
+M5 executing on nadc-0214
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -42,4 +44,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 582418059000 because target called exit()
+Exiting @ tick 582418265000 because target called exit()
index 9d595253b5eecb2b15c49602476a6190d963fed2..15c38b8eb652798e04ebe1965b9e1bc508995aaa 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 154343                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 212152                       # Number of bytes of host memory used
-host_seconds                                  9107.03                       # Real time elapsed on the host
-host_tick_rate                               63952564                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.582418                       # Number of seconds simulated
+sim_ticks                                582418265000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 199078                       # Simulator instruction rate (inst/s)
+host_tick_rate                               82488656                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245404                       # Number of bytes of host memory used
+host_seconds                                  7060.59                       # Real time elapsed on the host
 sim_insts                                  1405604152                       # Number of instructions simulated
-sim_seconds                                  0.582418                       # Number of seconds simulated
-sim_ticks                                582418059000                       # Number of ticks simulated
+system.cpu.workload.num_syscalls                   49                       # Number of system calls
+system.cpu.numCycles                       1164836531                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                103713430                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          103713430                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            5339068                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              99018529                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 97659626                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 97659749                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              99018650                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            5339067                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          103713551                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                103713551                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts           5339067                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                   86248929                       # Number of branches committed
-system.cpu.commit.bw_lim_events              26710610                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts     1489523295                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       199490556                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples   1136580592                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.310530                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.747403                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    402922453     35.45%     35.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    477569543     42.02%     77.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     55697713      4.90%     82.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     97088718      8.54%     90.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     32658945      2.87%     93.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      8438570      0.74%     94.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     25679618      2.26%     96.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      9814422      0.86%     97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     26710610      2.35%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1136580592                       # Number of insts commited each cycle
-system.cpu.commit.count                    1489523295                       # Number of instructions committed
-system.cpu.commit.fp_insts                    8452036                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.int_insts                1319476388                       # Number of committed integer instructions.
-system.cpu.commit.loads                     402512844                       # Number of loads committed
-system.cpu.commit.membars                       51356                       # Number of memory barriers committed
-system.cpu.commit.refs                      569360986                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                  1405604152                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1405604152                       # Number of Instructions Simulated
-system.cpu.cpi                               0.828709                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.828709                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          291461478                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14664.632652                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7474.067095                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              290645276                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    11969302500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.002800                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               816202                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            602863                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1594510000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000732                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          213339                       # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency         267500                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency       246500                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 15381.021476                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13048.542893                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             165025455                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   28014392657                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.010916                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1821361                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1553325                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   3497479243                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.001606                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         268036                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets         5000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 946.591376                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         5000                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           458308294                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 15159.332747                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 10578.009334                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               455670731                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     39983695157                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.005755                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2637563                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            2156188                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   5091989243                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.001050                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           481375                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4095.405595                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999855                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          458308294                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 15159.332747                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 10578.009334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              455670731                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    39983695157                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.005755                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2637563                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           2156188                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   5091989243                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.001050                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          481375                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 477286                       # number of replacements
-system.cpu.dcache.sampled_refs                 481382                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.405595                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                455672050                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              132278000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   428224                       # number of writebacks
-system.cpu.decode.BlockedCycles             373408138                       # Number of cycles decode is blocked
-system.cpu.decode.DecodedInsts             1727466392                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                394807577                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                 348667632                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles               27885594                       # Number of cycles decode is squashing
-system.cpu.decode.UnblockCycles              19696634                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                   103713551                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 170870865                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     370648133                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               1257771                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     1732289789                       # Number of instructions fetch has processed
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          170870341                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1732290571                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   103713430                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           97659626                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     370649677                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5787764                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   47                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 5787763                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.089037                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          170870865                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           97659749                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.487153                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         1164465575                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.491538                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                 170870341                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1258030                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1164465958                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.491542                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::stdev             2.715145                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                793817442     68.17%     68.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 81924135      7.04%     75.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 44978693      3.86%     79.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 22977276      1.97%     81.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                793816281     68.17%     68.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 81924128      7.04%     75.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 44979241      3.86%     79.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 22976761      1.97%     81.04% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::4                 33360505      2.86%     83.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 33148842      2.85%     86.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 14858388      1.28%     88.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7508131      0.64%     88.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                131892163     11.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 33149354      2.85%     86.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 14860425      1.28%     88.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7508136      0.64%     88.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                131891127     11.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1164465575                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                  16956220                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 10464632                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses          170870865                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35272.495756                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35056.283732                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              170869098                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       62326500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 1767                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               470                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     45468000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            1297                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               131843.439815                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           170870865                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35272.495756                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35056.283732                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               170869098                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        62326500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000010                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  1767                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                470                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     45468000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000008                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             1297                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1047.623620                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.511535                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          170870865                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35272.495756                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35056.283732                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              170869098                       # number of overall hits
-system.cpu.icache.overall_miss_latency       62326500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000010                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 1767                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               470                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     45468000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000008                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            1297                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                    159                       # number of replacements
-system.cpu.icache.sampled_refs                   1296                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1047.623620                       # Cycle average of tags in use
-system.cpu.icache.total_refs                170869098                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          370544                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts              5675287                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 89603944                       # Number of branches executed
-system.cpu.iew.exec_nop                     100373819                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.267070                       # Inst execution rate
-system.cpu.iew.exec_refs                    591399205                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                  170154785                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                 2507924                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             461157302                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            2999936                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           4553877                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            187022162                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          1689106884                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             421244420                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           6318503                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            1475928628                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  66196                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  8462                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               27885594                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                128708                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked         40205                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads        129748862                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses        35905                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation       460365                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads          237                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads     58644458                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores     20174020                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         460365                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       670427                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        5004860                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                1209973999                       # num instructions consuming a value
-system.cpu.iew.wb_count                    1473173854                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.961076                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                1162877329                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.264705                       # insts written-back per cycle
-system.cpu.iew.wb_sent                     1474297623                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads               1997794756                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1296594839                       # number of integer regfile writes
-system.cpu.ipc                               1.206697                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.206697                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             883945189     59.64%     59.64% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     59.64% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     59.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2631981      0.18%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            424001958     28.61%     88.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           171668003     11.58%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1482247131                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                 9142959                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads            17762219                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses      8523024                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes            9165283                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     3391020                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002288                       # FU busy rate (busy events/executed inst)
+system.cpu.fetch.rateDist::total           1164465958                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.089037                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.487153                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                394807963                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             373406946                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 348668673                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              19696602                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               27885774                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             1727469213                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               27885774                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                433132489                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               115497751                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       53046647                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 325738473                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             209164824                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1709743087                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents              128337088                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              40459305                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents         28107626                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1426817560                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2887436309                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2853766100                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          33670209                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1244770452                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                182047108                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            3085415                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        3085429                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 378978234                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            461157304                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           187023629                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         386274628                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        159918062                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1585635160                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3099558                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1482248202                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            280896                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       182707220                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    240691130                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         855887                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1164465958                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.272900                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.148645                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           309299023     26.56%     26.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           465738912     40.00%     66.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           229120955     19.68%     86.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           104114644      8.94%     95.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            41468820      3.56%     98.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8912789      0.77%     99.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5349021      0.46%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              304255      0.03%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              157539      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1164465958                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                  214212      6.32%      6.32% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      6.32% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                187778      5.54%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                187446      5.53%     11.85% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.85% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.85% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.85% # attempts to use FU when none available
@@ -339,139 +131,347 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.85% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.85% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.85% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2748667     81.06%     92.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                240363      7.09%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2748470     81.06%     92.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                240369      7.09%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses             1476495192                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         4114870575                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses   1464650830                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        1762732094                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                 1585633508                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                1482247131                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             3099557                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       182705519                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            281937                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved         855886                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    240684944                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples    1164465575                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.272899                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.148641                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           309298241     26.56%     26.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           465738905     40.00%     66.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           229121985     19.68%     86.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           104115000      8.94%     95.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            41467759      3.56%     98.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             8912842      0.77%     99.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5349281      0.46%     99.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              304172      0.03%     99.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              157390      0.01%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1164465575                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.272494                       # Inst issue rate
-system.cpu.l2cache.ReadExReq_accesses          268051                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.834444                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.706026                       # average ReadExReq mshr miss latency
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             883945192     59.64%     59.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     59.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     59.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2632003      0.18%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            424002994     28.61%     88.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           171668013     11.58%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1482248202                       # Type of FU issued
+system.cpu.iq.rate                           1.272495                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3390497                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002287                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4114870963                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1762732436                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1464650831                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            17762792                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9168295                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      8523374                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1476495195                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 9143504                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        129748862                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     58644460                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        35905                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       460365                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     20175487                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads          237                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         40205                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               27885774                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2507670                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                128778                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1689108521                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           4553883                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             461157304                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            187023629                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2999936                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  66282                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  8454                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         460365                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5004860                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       670428                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              5675288                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1475929151                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             421244589                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6319051                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                     100373803                       # number of nop insts executed
+system.cpu.iew.exec_refs                    591399372                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 89603944                       # Number of branches executed
+system.cpu.iew.exec_stores                  170154783                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.267070                       # Inst execution rate
+system.cpu.iew.wb_sent                     1474297977                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1473174205                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1162879989                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1209979019                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.264705                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.961075                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1489523295                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       199492196                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           5339068                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1136580795                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.310530                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.747402                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    402923295     35.45%     35.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    477569254     42.02%     77.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     55696756      4.90%     82.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     97088676      8.54%     90.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     32659153      2.87%     93.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8439015      0.74%     94.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     25679683      2.26%     96.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      9814988      0.86%     97.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     26709975      2.35%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1136580795                       # Number of insts commited each cycle
+system.cpu.commit.count                    1489523295                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      569360986                       # Number of memory references committed
+system.cpu.commit.loads                     402512844                       # Number of loads committed
+system.cpu.commit.membars                       51356                       # Number of memory barriers committed
+system.cpu.commit.branches                   86248929                       # Number of branches committed
+system.cpu.commit.fp_insts                    8452036                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1319476388                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              26709975                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   2798821441                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3405949800                       # The number of ROB writes
+system.cpu.timesIdled                           11505                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          370573                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1405604152                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1405604152                       # Number of Instructions Simulated
+system.cpu.cpi                               0.828709                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.828709                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.206696                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.206696                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1997795279                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1296594841                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  16957636                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 10465342                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               597198734                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                2258933                       # number of misc regfile writes
+system.cpu.icache.replacements                    159                       # number of replacements
+system.cpu.icache.tagsinuse               1046.779418                       # Cycle average of tags in use
+system.cpu.icache.total_refs                170868575                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1295                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               131944.845560                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1046.779418                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.511123                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              170868575                       # number of ReadReq hits
+system.cpu.icache.demand_hits               170868575                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              170868575                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1766                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1766                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1766                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       62279500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        62279500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       62279500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          170870341                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           170870341                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          170870341                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000010                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000010                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35265.855040                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35265.855040                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35265.855040                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               470                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                470                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               470                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            1296                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             1296                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            1296                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     45432500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     45432500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     45432500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000008                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000008                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35055.941358                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35055.941358                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35055.941358                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 477286                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.405832                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                455671846                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 481382                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 946.590953                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              132241000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.405832                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999855                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              290645446                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             165025081                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
+system.cpu.dcache.demand_hits               455670527                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              455670527                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               816201                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1821735                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
+system.cpu.dcache.demand_misses               2637936                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2637936                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    11969600500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   28019650157                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency         267500                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency     39989250657                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    39989250657                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          291461647                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           458308463                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          458308463                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002800                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.010919                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate           0.005756                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.005756                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14665.015725                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 15380.749756                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 15159.295243                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 15159.295243                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         5000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets         5000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   428224                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            602862                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1553699                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            2156561                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           2156561                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          213339                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         268036                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           481375                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          481375                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1594439500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3497902243                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency       246500                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   5092341743                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   5092341743                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000732                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001606                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.001050                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001050                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7473.736635                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13050.121040                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 10578.741611                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 10578.741611                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 75915                       # number of replacements
+system.cpu.l2cache.tagsinuse             17662.572587                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  467082                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 91426                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.108853                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1959.264776                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15703.307811                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.059792                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.479227                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                180932                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              428224                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits              207600                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   2079988000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.225521                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                 388532                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                388532                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               33695                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses             60451                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1893368000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.225521                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        60451                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            214628                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34037.437678                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.970916                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                180932                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1146925500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.156997                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               33696                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1044743500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.156997                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          33696                       # number of ReadReq MSHR misses
+system.cpu.l2cache.demand_misses                94146                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               94146                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1146858500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2079993500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3226852000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3226852000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            214627                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses          428224                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              428224                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  5.108819                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses          268051                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             482678                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            482678                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.156993                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.225521                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.195049                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.195049                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34036.459415                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.925427                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34274.977163                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34274.977163                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             482679                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34275.266339                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.701786                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 388532                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     3226913500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.195051                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                94147                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                   59282                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   2938111500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.195051                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           94147                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          1959.521413                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15703.307498                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.059800                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.479227                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses            482679                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34275.266339                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.701786                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                388532                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    3226913500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.195051                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               94147                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   2938111500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.195051                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          94147                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses          33695                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        60451                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           94146                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          94146                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 75916                       # number of replacements
-system.cpu.l2cache.sampled_refs                 91427                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1044714500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1893375500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2938090000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2938090000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.156993                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.225521                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.195049                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.195049                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.030420                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.830094                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.804899                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.804899                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             17662.828910                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  467084                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   59282                       # number of writebacks
-system.cpu.memDep0.conflictingLoads         386274637                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        159916794                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            461157302                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           187022162                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               597198570                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                2258933                       # number of misc regfile writes
-system.cpu.numCycles                       1164836119                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles               115497905                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps            1244770452                       # Number of HB maps that are committed
-system.cpu.rename.FullRegisterEvents         28107626                       # Number of times there has been no free registers
-system.cpu.rename.IQFullEvents              128337052                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                433132347                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents              40459205                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenameLookups            2887426636                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts             1709740875                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands          1426816340                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                 325737783                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles               27885594                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles             209164686                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                182045888                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups          33660518                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups       2853766118                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles       53047260                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts            3085415                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                 378977297                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts        3085429                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   2798818963                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3405946340                       # The number of ROB writes
-system.cpu.timesIdled                           11499                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                   49                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index fc45f8a25a34bd1850e797d32570d6f389b41441..a5d2218bed848b5fbb1ce46365a75e1269055d78 100755 (executable)
@@ -1,3 +1,5 @@
+Redirecting stdout to build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2011 13:30:37
-M5 started Apr 21 2011 13:30:43
-M5 executing on maize
+M5 compiled May 17 2011 12:22:59
+M5 started May 18 2011 08:01:14
+M5 executing on nadc-0105
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1066,4 +1068,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 751079230500 because target called exit()
+Exiting @ tick 750278436000 because target called exit()
index a21571816b78ed779cbe76e199249df41bf4b895..64628a88b2628134661bddb7f3e58cf511e159fe 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 131052                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215332                       # Number of bytes of host memory used
-host_seconds                                 12372.92                       # Real time elapsed on the host
-host_tick_rate                               60703496                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.750278                       # Number of seconds simulated
+sim_ticks                                750278436000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 180615                       # Simulator instruction rate (inst/s)
+host_tick_rate                               83571906                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250232                       # Number of bytes of host memory used
+host_seconds                                  8977.64                       # Real time elapsed on the host
 sim_insts                                  1621493982                       # Number of instructions simulated
-sim_seconds                                  0.751079                       # Number of seconds simulated
-sim_ticks                                751079230500                       # Number of ticks simulated
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.numCycles                       1500556873                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                179206646                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          179206646                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            8463551                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             169776881                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                168588435                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                168460210                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             169652659                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            8971423                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          179993455                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                179993455                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts           8971450                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                  107161579                       # Number of branches committed
-system.cpu.commit.bw_lim_events              11445860                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts     1621493982                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       721713449                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples   1402522347                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.156127                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.381739                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    522037324     37.22%     37.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    531767209     37.92%     75.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    125147036      8.92%     84.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    139348503      9.94%     93.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     42559094      3.03%     97.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     23457685      1.67%     98.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5021941      0.36%     99.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1737695      0.12%     99.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11445860      0.82%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1402522347                       # Number of insts commited each cycle
-system.cpu.commit.count                    1621493982                       # Number of instructions committed
-system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
-system.cpu.commit.loads                     419042125                       # Number of loads committed
-system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.refs                      607228182                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                  1621493982                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1621493982                       # Number of Instructions Simulated
-system.cpu.cpi                               0.926404                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.926404                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          325401931                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 10107.251018                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7152.951878                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              325183672                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     2205998500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000671                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               218259                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits              3345                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1537269500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000660                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          214914                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 19574.534314                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10012.304968                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             186952974                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   24137025496                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.006552                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1233083                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           982981                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   2504097497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.001329                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         250102                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2357.476636                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 15974.978853                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                1101.331236                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs               214                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           29555                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs       504500                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets    472140500                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           513587988                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18150.803874                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  8690.812783                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               512136646                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     26343023996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002826                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1451342                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits             986326                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   4041366997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000905                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           465016                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4095.146726                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999792                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          513587988                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18150.803874                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  8690.812783                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              512136646                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    26343023996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002826                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1451342                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits            986326                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   4041366997                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000905                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          465016                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 460920                       # number of replacements
-system.cpu.dcache.sampled_refs                 465016                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.146726                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                512136646                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              317706000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   411408                       # number of writebacks
-system.cpu.decode.BlockedCycles             587921420                       # Number of cycles decode is blocked
-system.cpu.decode.DecodedInsts             2472731706                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                429893143                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                 331529130                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles               99378480                       # Number of cycles decode is squashing
-system.cpu.decode.UnblockCycles              53178654                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                   179993455                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 170058043                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     400227143                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                625222                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     1408639601                       # Number of instructions fetch has processed
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          168643185                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1398775423                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   179206646                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          168588435                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     401459368                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14868125                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   42                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                15384200                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.119823                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          170058043                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          168460210                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.937744                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         1501900827                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.699260                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.059388                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                 168643185                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                821564                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1500265844                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.692515                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.050179                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1104715792     73.55%     73.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 26107791      1.74%     75.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14369087      0.96%     76.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 13756932      0.92%     77.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 30207594      2.01%     79.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 20132707      1.34%     80.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 34410865      2.29%     82.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 37556252      2.50%     85.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                220643807     14.69%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1101846908     73.44%     73.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25629201      1.71%     75.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 17503252      1.17%     76.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 17259352      1.15%     77.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 30203070      2.01%     79.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 16882652      1.13%     80.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 34105222      2.27%     82.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 37737433      2.52%     85.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                219098754     14.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1501900827                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        12                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses          170058043                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35240.756303                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.058688                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              170056853                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       41936500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000007                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 1190                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               321                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     30694000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             869                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               195692.581128                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           170058043                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35240.756303                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35321.058688                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               170056853                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        41936500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000007                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  1190                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                321                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     30694000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              869                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            793.670730                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.387535                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          170058043                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35240.756303                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              170056853                       # number of overall hits
-system.cpu.icache.overall_miss_latency       41936500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000007                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 1190                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               321                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     30694000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             869                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                     11                       # number of replacements
-system.cpu.icache.sampled_refs                    869                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                793.670730                       # Cycle average of tags in use
-system.cpu.icache.total_refs                170056853                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          257635                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts              9107858                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                111429178                       # Number of branches executed
-system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.227514                       # Inst execution rate
-system.cpu.iew.exec_refs                    636597814                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                  191695864                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                 1395305                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             615851374                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                 81                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            312936                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            250798855                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          2343198083                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             444901950                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          13067063                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            1843921293                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  56293                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                     6                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               99378480                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                111986                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked         30239                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads        119484333                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses        15966                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation      6399400                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads           47                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads    196809249                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores     62612798                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents        6399400                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      4677718                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        4430140                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                2082700302                       # num instructions consuming a value
-system.cpu.iew.wb_count                    1838995466                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.683970                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                1424504384                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.224235                       # insts written-back per cycle
-system.cpu.iew.wb_sent                     1842743630                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads               3236941415                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1831971139                       # number of integer regfile writes
-system.cpu.ipc                               1.079443                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.079443                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass          28079218      1.51%      1.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1185434411     63.84%     65.35% # Type of FU issued
+system.cpu.fetch.rateDist::total           1500265844                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.119427                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.932171                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                426619882                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             588582259                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 331774062                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              54890410                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               98399231                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2463603655                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               98399231                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                490140995                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               167797271                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           3037                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 309381141                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             434544169                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2390094348                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    68                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              298397694                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             109374277                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2388910462                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5790943512                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       5790943448                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups                64                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1617994650                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                770915812                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 87                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             87                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 713558954                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            613723437                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           250366407                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         539421468                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        206415389                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2337617045                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  78                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1854722734                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            196953                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       715983422                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1505792788                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             28                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1500265844                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.236263                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.216770                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           461494018     30.76%     30.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           582014055     38.79%     69.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           214930558     14.33%     83.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           153972669     10.26%     94.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            64799231      4.32%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            17691341      1.18%     99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             4397619      0.29%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              840611      0.06%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              125742      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1500265844                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  159647      3.75%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3486871     81.91%     85.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                610438     14.34%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass          27575645      1.49%      1.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1184540758     63.87%     65.35% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.35% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.35% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     65.35% # Type of FU issued
@@ -287,179 +165,301 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.35% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.35% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.35% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            451340139     24.30%     89.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           192134588     10.35%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            450487645     24.29%     89.64% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192118686     10.36%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1856988356                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                      19                       # Number of floating point alu accesses
+system.cpu.iq.FU_type_0::total             1854722734                       # Type of FU issued
+system.cpu.iq.rate                           1.236023                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4256956                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002295                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5214165186                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3059990828                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1837811582                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  35                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           12                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 32                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     4273878                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002302                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  161807      3.79%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                3493887     81.75%     85.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                618184     14.46%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses             1833182997                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         5220358647                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses   1838995454                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        3071160852                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                 2343198002                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                1856988356                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                  81                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       721564206                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            207265                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             31                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined   1518322063                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples    1501900827                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.236425                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.221094                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           463034659     30.83%     30.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           580779168     38.67%     69.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           218589752     14.55%     84.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           151066938     10.06%     94.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            63504112      4.23%     98.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            18859628      1.26%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5092601      0.34%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              833076      0.06%     99.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              140893      0.01%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1501900827                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.236213                       # Inst issue rate
-system.cpu.l2cache.ReadExReq_accesses          250113                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              191287                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   2024064500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.235198                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             58826                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1832767000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235198                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        58826                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            215772                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34136.783762                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.222249                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                182665                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1130166500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.153435                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               33107                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1026523000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.153435                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          33107                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          411408                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              411408                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          500                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  5.099879                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs               12                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.iq.fp_inst_queue_wakeup_accesses           12                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1831404026                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      19                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        117971084                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    194681312                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        16091                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      6391116                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     62180350                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads           42                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         30252                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               98399231                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1363305                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                110880                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2337617123                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            338195                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             613723437                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            250366407                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 78                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  56702                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     4                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        6391116                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4450206                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4153743                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8603949                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1842187665                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             444314021                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          12535069                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                    636013673                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                111427506                       # Number of branches executed
+system.cpu.iew.exec_stores                  191699652                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.227669                       # Inst execution rate
+system.cpu.iew.wb_sent                     1840965230                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1837811594                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1424401809                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2083960582                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.224753                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.683507                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1621493982                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       716132515                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8463578                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1401866613                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.156668                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.378442                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    520031376     37.10%     37.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    533018726     38.02%     75.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    125308330      8.94%     84.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    139235246      9.93%     93.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     43288203      3.09%     97.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     23453801      1.67%     98.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4331063      0.31%     99.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1854281      0.13%     99.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11345587      0.81%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1401866613                       # Number of insts commited each cycle
+system.cpu.commit.count                    1621493982                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      607228182                       # Number of memory references committed
+system.cpu.commit.loads                     419042125                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                  107161579                       # Number of branches committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              11345587                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   3728147523                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4773653528                       # The number of ROB writes
+system.cpu.timesIdled                           43666                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          291029                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1621493982                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1621493982                       # Number of Instructions Simulated
+system.cpu.cpi                               0.925416                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.925416                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.080595                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.080595                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3235784294                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1830729236                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        12                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               930213220                       # number of misc regfile reads
+system.cpu.icache.replacements                     17                       # number of replacements
+system.cpu.icache.tagsinuse                793.330591                       # Cycle average of tags in use
+system.cpu.icache.total_refs                168641986                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    875                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               192733.698286                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            793.330591                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.387368                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              168641986                       # number of ReadReq hits
+system.cpu.icache.demand_hits               168641986                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              168641986                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1199                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1199                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1199                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       42201000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        42201000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       42201000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          168643185                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           168643185                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          168643185                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000007                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000007                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000007                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35196.830692                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35196.830692                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35196.830692                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               324                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                324                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               324                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             875                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              875                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             875                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     30921000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     30921000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     30921000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35338.285714                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35338.285714                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35338.285714                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 460957                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.145869                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                513034277                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 465053                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                1103.173782                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              317696000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.145869                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999791                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              326108931                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             186925346                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               513034277                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              513034277                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               218266                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1260711                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1478977                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1478977                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     2205272500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   24390827496                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     26596099996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    26596099996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          326327197                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           514513254                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          514513254                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000669                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.006699                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.002875                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002875                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 10103.600652                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 19346.882431                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 17982.767816                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 17982.767816                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       504500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets    474736000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               214                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           29560                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2357.476636                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16060.081191                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   411400                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              3331                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1010593                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1013924                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1013924                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          214935                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         250118                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           465053                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          465053                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1536673000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2518183497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4054856497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4054856497                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000659                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001329                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000904                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000904                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7149.477749                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10067.981901                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  8719.127706                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  8719.127706                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 73679                       # number of replacements
+system.cpu.l2cache.tagsinuse             18021.980204                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  455469                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89282                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.101465                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1918.737195                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16103.243009                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.058555                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.491432                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                182682                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              411400                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              191297                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 373979                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                373979                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               33118                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             58831                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                91949                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               91949                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1130130500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2026415500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3156546000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3156546000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            215800                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          411400                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          250128                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             465928                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            465928                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.153466                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.235204                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.197346                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.197346                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34124.358355                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34444.689024                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34329.312989                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34329.312989                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs         6000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               12                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          500                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             465885                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34310.106273                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.889419                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 373952                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     3154231000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.197330                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                91933                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                   58539                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   2859290000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.197330                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           91933                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          1916.626475                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16094.448281                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.058491                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.491164                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses            465885                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34310.106273                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                373952                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    3154231000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.197330                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               91933                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   2859290000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.197330                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          91933                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses          33118                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58831                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           91949                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          91949                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 73660                       # number of replacements
-system.cpu.l2cache.sampled_refs                 89268                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1026873000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1832918500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2859791500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2859791500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.153466                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235204                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.197346                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.197346                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.491938                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.657731                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.931506                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.931506                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18011.074755                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  455256                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   58532                       # number of writebacks
-system.cpu.memDep0.conflictingLoads         528261825                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        206728085                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            615851374                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           250798855                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               931071836                       # number of misc regfile reads
-system.cpu.numCycles                       1502158462                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles               169288978                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps            1617994650                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents              298516669                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                493321936                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents             107168100                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                    70                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups            5808956116                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts             2397077126                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands          2395694665                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                 310095488                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles               99378480                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles             429812969                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                777700015                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups                64                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups       5808956052                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles           2976                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts                 89                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                 706930007                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts             89                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   3734283918                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4785794667                       # The number of ROB writes
-system.cpu.timesIdled                           45615                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                   48                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 36f52242294b60ff4f23b99e6a01c867dca5fd5c..a758a5804fe86f50664eda44c51d5a8bf0352522 100755 (executable)
@@ -22,8 +22,6 @@ warn:         instruction 'mcr icimvau' unimplemented
 For more information see: http://www.m5sim.org/warn/21b09adb
 warn:  instruction 'mcr bpiall' unimplemented
 For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-For more information see: http://www.m5sim.org/warn/7998f2ea
 warn:  instruction 'mcr bpiall' unimplemented
 For more information see: http://www.m5sim.org/warn/21b09adb
 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
index c9bf50a5d60bde50d31f90d717f8d5f1e8638dfb..8fc1c35c1c2f743853516d64a77827bb408114af 100755 (executable)
@@ -7,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 15:43:04
-M5 started May  4 2011 15:43:52
-M5 executing on nadc-0364
+M5 compiled May 16 2011 21:41:16
+M5 started May 16 2011 21:43:01
+M5 executing on nadc-0271
 command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /arm/scratch/alisai01/dist/binaries/vmlinux.arm
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 82034111500 because m5_exit instruction encountered
+Exiting @ tick 81956970500 because m5_exit instruction encountered
index 48678b994b28f02290fda7056dc445c5616fdb17..147873eb29d03c9a04762757cab602820cfabfbc 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 134958                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 390376                       # Number of bytes of host memory used
-host_seconds                                   384.42                       # Real time elapsed on the host
-host_tick_rate                              213396272                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.081957                       # Number of seconds simulated
+sim_ticks                                 81956970500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    51880909                       # Number of instructions simulated
-sim_seconds                                  0.082034                       # Number of seconds simulated
-sim_ticks                                 82034111500                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                  9102571                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              11540733                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect              156710                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect             673757                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           10989170                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 12912764                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                   784193                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts            650030                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                    8429925                       # Number of branches committed
-system.cpu.commit.bw_lim_events               1000240                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts       52004139                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls         2962847                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        14909049                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples     92471034                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.562383                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.400559                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     71745851     77.59%     77.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     10051673     10.87%     88.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3131233      3.39%     91.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1338201      1.45%     93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3541768      3.83%     97.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       776921      0.84%     97.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       574229      0.62%     98.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       310918      0.34%     98.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1000240      1.08%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     92471034                       # Number of insts commited each cycle
-system.cpu.commit.count                      52004139                       # Number of instructions committed
-system.cpu.commit.fp_insts                       6017                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls               530212                       # Number of function calls committed.
-system.cpu.commit.int_insts                  42426831                       # Number of committed integer instructions.
-system.cpu.commit.loads                       9179406                       # Number of loads committed
-system.cpu.commit.membars                           3                       # Number of memory barriers committed
-system.cpu.commit.refs                       16257275                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                    51880909                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              51880909                       # Number of Instructions Simulated
-system.cpu.cpi                               3.162401                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.162401                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses::0       111119                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       111119                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14959.662577                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11867.723914                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0        104599                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       104599                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency     97537000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.058676                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0         6520                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         6520                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits          971                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency     65854000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.049937                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses         5549                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0         9452855                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9452855                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 14680.380096                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13336.103253                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0             8917516                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         8917516                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     7858980000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0       0.056633                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0            535339                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        535339                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            286475                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   3318876000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.026327                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          248864                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency  38199227500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0       105008                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       105008                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0         105008                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       105008                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0        6663158                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6663158                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 39939.228652                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38506.801730                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0            4619008                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4619008                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   81641774250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0      0.306784                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0          2044150                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2044150                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1873534                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   6569876484                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.025606                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         170616                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency    944300187                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  7573.849650                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 26206.896552                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  32.474872                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs              1144                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              29                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs      8664484                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       760000                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::0         16116013                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     16116013                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 34697.087001                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23573.835425                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             13536524                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13536524                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     89500754250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.160058                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0            2579489                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2579489                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            2160009                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   9888752484                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0     0.026029                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           419480                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0            511.748800                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999509                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses::0        16116013                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     16116013                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 34697.087001                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23573.835425                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            13536524                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13536524                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    89500754250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.160058                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0           2579489                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2579489                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           2160009                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   9888752484                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0     0.026029                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          419480                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency  39143527687                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 422827                       # number of replacements
-system.cpu.dcache.sampled_refs                 423339                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.748800                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 13747880                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               48233000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   391156                       # number of writebacks
-system.cpu.decode.BlockedCycles              53430670                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                 71225                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved              1206438                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts               75318678                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                 23535399                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                  14503134                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles                2432206                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                234974                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles               1001803                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                      35326890                       # DTB accesses
-system.cpu.dtb.align_faults                      1798                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                     2918                       # Number of entries that have been flushed from TLB
+host_inst_rate                                  32873                       # Simulator instruction rate (inst/s)
+host_tick_rate                               51935468                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 384040                       # Number of bytes of host memory used
+host_seconds                                  1578.05                       # Real time elapsed on the host
+sim_insts                                    51876153                       # Number of instructions simulated
+system.l2c.replacements                         94702                       # number of replacements
+system.l2c.tagsinuse                     38059.464310                       # Cycle average of tags in use
+system.l2c.total_refs                         1031447                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        126964                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          8.123933                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                  6535.540690                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 31523.923619                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.099724                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.481017                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                     732124                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     105939                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 838063                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   432446                       # number of Writeback hits
+system.l2c.Writeback_hits::total               432446                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                      20                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  20                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0                    60973                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                60973                       # number of ReadExReq hits
+system.l2c.demand_hits::0                      793097                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      105939                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  899036                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                     793097                       # number of overall hits
+system.l2c.overall_hits::1                     105939                       # number of overall hits
+system.l2c.overall_hits::total                 899036                       # number of overall hits
+system.l2c.ReadReq_misses::0                    20401                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                      101                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20502                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  1673                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1673                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                 107993                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             107993                       # number of ReadExReq misses
+system.l2c.demand_misses::0                    128394                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                       101                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                128495                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   128394                       # number of overall misses
+system.l2c.overall_misses::1                      101                       # number of overall misses
+system.l2c.overall_misses::total               128495                       # number of overall misses
+system.l2c.ReadReq_miss_latency            1071402500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency             728500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          5664440500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency             6735843000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency            6735843000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                 752525                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 106040                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             858565                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               432446                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           432446                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                1693                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1693                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               168966                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           168966                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                  921491                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  106040                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1027531                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                 921491                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 106040                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1027531                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.027110                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.000952                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.028063                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.988187                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.639140                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.139333                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.000952                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.140285                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.139333                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.000952                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.140285                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   52517.156022                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   10607945.544554                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 10660462.700576                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0   435.445308                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52451.922810                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    52462.287957                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    66691514.851485                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 66743977.139443                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   52462.287957                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   66691514.851485                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 66743977.139443                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                           87773                       # number of writebacks
+system.l2c.ReadReq_mshr_hits                       47                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits                        47                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                       47                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                  20455                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                1673                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               107993                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  128448                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 128448                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency        819077500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency      66920000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     4321060500                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency        5140138000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency       5140138000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency  28946041000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency    748279439                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency  29694320439                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.027182                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.192899                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.220081                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.988187                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.639140                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0          0.139391                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.211316                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      1.350708                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         0.139391                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.211316                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     1.350708                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40042.899047                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40012.412842                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40017.267688                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40017.267688                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                     27773403                       # DTB read hits
+system.cpu.dtb.read_misses                      62999                       # DTB read misses
+system.cpu.dtb.write_hits                     7478070                       # DTB write hits
+system.cpu.dtb.write_misses                     11819                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                          35252902                       # DTB hits
+system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                     2909                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      3199                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1081                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                      1182                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 27836402                       # DTB read accesses
+system.cpu.dtb.write_accesses                 7489889                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                           73988                       # DTB misses
-system.cpu.dtb.perms_faults                      1167                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                   1080                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                 27838344                       # DTB read accesses
-system.cpu.dtb.read_hits                     27775801                       # DTB read hits
-system.cpu.dtb.read_misses                      62543                       # DTB read misses
-system.cpu.dtb.write_accesses                 7488546                       # DTB write accesses
-system.cpu.dtb.write_hits                     7477101                       # DTB write hits
-system.cpu.dtb.write_misses                     11445                       # DTB write misses
-system.cpu.fetch.Branches                    12912764                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                   6451359                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      15867747                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                266743                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                       62809765                       # Number of instructions fetch has processed
-system.cpu.fetch.ItlbSquashes                    3974                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.MiscStallCycles                15287                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 1056460                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                       7130                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.branchRate                  0.078704                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles            6449881                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches            9886764                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.382827                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples           94903212                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.817121                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.069432                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.hits                          35251473                       # DTB hits
+system.cpu.dtb.misses                           74818                       # DTB misses
+system.cpu.dtb.accesses                      35326291                       # DTB accesses
+system.cpu.itb.inst_hits                      6378307                       # ITB inst hits
+system.cpu.itb.inst_misses                       7071                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                     1627                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                      5145                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                  6385378                       # ITB inst accesses
+system.cpu.itb.hits                           6378307                       # DTB hits
+system.cpu.itb.misses                            7071                       # DTB misses
+system.cpu.itb.accesses                       6385378                       # DTB accesses
+system.cpu.numCycles                        163913942                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 12907993                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           10988942                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             671137                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              11440578                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8975415                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                   783446                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              155600                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles            6371114                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       62781923                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    12907993                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9758861                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      15757873                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1054135                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       7071                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                17008                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                   6372584                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                264714                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    3927                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples           94752246                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.818183                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.071967                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 79052742     83.30%     83.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1297873      1.37%     84.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1713716      1.81%     86.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1275370      1.34%     87.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4689358      4.94%     92.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   820409      0.86%     93.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   791742      0.83%     94.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   709911      0.75%     95.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4552091      4.80%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 79011674     83.39%     83.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1184236      1.25%     84.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1729223      1.82%     86.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1152880      1.22%     87.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4802064      5.07%     92.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   820808      0.87%     93.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   792852      0.84%     94.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   714149      0.75%     95.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4544360      4.80%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             94903212                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                      5507                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     1900                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses::0         6451264                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      6451264                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14776.807600                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12031.141929                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_hits::0             5903994                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         5903994                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency     8086903495                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0       0.084831                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0            547270                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        547270                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits             44668                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency   6046875996                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.077908                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          502602                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable_latency      5118000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.avg_blocked_cycles::no_mshrs  9184.960000                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  11.746927                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs               100                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs       918496                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::0          6451264                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      6451264                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14776.807600                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12031.141929                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::0              5903994                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          5903994                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency      8086903495                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0        0.084831                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::0             547270                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         547270                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits              44668                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency   6046875996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0     0.077908                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           502602                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            496.931894                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.970570                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0         6451264                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      6451264                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14776.807600                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12031.141929                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0             5903994                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         5903994                       # number of overall hits
-system.cpu.icache.overall_miss_latency     8086903495                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0       0.084831                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::0            547270                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total        547270                       # number of overall misses
-system.cpu.icache.overall_mshr_hits             44668                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency   6046875996                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0     0.077908                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          502602                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency      5118000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                 502087                       # number of replacements
-system.cpu.icache.sampled_refs                 502599                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                496.931894                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  5903994                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle             6080140000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                    41635                       # number of writebacks
-system.cpu.idleCycles                        69165012                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts               732544                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 10340571                       # Number of branches executed
-system.cpu.iew.exec_nop                        166091                       # number of nop insts executed
-system.cpu.iew.exec_rate                     0.481516                       # Inst execution rate
-system.cpu.iew.exec_refs                     36056816                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                    7788477                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                21357228                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              12530635                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            3998139                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            368991                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts              8665122                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts            69169972                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              28268339                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1213523                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts              79001525                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  20798                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 45676                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                2432206                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                253616                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked          9528                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads           361126                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses        20031                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation       319619                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads     17031579                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads      3351229                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores      1587253                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         319619                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       190941                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect         541603                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                  56089369                       # num instructions consuming a value
-system.cpu.iew.wb_count                      61177944                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.565288                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                  31706672                       # num instructions producing a value
-system.cpu.iew.wb_rate                       0.372881                       # insts written-back per cycle
-system.cpu.iew.wb_sent                       78478869                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads                348371686                       # number of integer regfile reads
-system.cpu.int_regfile_writes                63138434                       # number of integer regfile writes
-system.cpu.ipc                               0.316215                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.316215                       # IPC: Total IPC of All Threads
+system.cpu.fetch.rateDist::total             94752246                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.078749                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.383018                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 23351217                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              53571370                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  14396920                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1001314                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2431425                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1204609                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 71112                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               75302047                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                237029                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2431425                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 24915043                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                33439496                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       16240153                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  12813964                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4912165                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               72500713                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                458049                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 112730                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2517697                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              125                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands            74405789                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             315201303                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        315135556                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             65747                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              51886765                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 22519023                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             806998                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         658881                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13649364                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             12530731                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8670127                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads              2363                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores             8454                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   64971047                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             4028155                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  80215912                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            157537                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        16406339                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     29306942                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1065284                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      94752246                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.846586                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.419375                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            59642752     62.95%     62.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            15646635     16.51%     79.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             6436241      6.79%     86.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4342320      4.58%     90.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6236918      6.58%     97.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1389324      1.47%     98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              710831      0.75%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              267243      0.28%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               79982      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        94752246                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   27052      0.56%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      1      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                4512476     93.02%     93.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                311301      6.42%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass           2393223      2.98%      2.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              41072292     51.20%     54.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                70482      0.09%     54.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              41066468     51.19%     54.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                70508      0.09%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     54.27% # Type of FU issued
@@ -393,355 +330,418 @@ system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     54.27% # Ty
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    1      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  10      0.00%     54.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  14      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     54.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               7      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            884      0.00%     54.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     54.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             28695689     35.77%     90.05% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7982456      9.95%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            885      0.00%     54.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     54.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             28697043     35.77%     90.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7987756      9.96%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               80215048                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                    8599                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads               16423                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses         6406                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes               9332                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     4845478                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.060406                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   27460      0.57%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      1      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                4510772     93.09%     93.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                307245      6.34%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses               82658704                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          260393825                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses     61171538                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes          85667061                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                   64975740                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                  80215048                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             4028141                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        16400358                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            157721                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved        1065294                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     29302343                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples      94903212                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.845230                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.416160                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            59674120     62.88%     62.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            15813070     16.66%     79.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6357188      6.70%     86.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4447704      4.69%     90.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6195201      6.53%     97.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1359588      1.43%     98.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              707137      0.75%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              270708      0.29%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               78496      0.08%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        94903212                       # Number of insts issued each cycle
-system.cpu.iq.rate                           0.488913                       # Inst issue rate
-system.cpu.itb.accesses                       6464349                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                     1626                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                           6457219                       # DTB hits
-system.cpu.itb.inst_accesses                  6464349                       # ITB inst accesses
-system.cpu.itb.inst_hits                      6457219                       # ITB inst hits
-system.cpu.itb.inst_misses                       7130                       # ITB inst misses
-system.cpu.itb.misses                            7130                       # DTB misses
-system.cpu.itb.perms_faults                      5291                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.memDep0.conflictingLoads              2897                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores             8478                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             12530635                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8665122                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                83057686                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 512562                       # number of misc regfile writes
-system.cpu.numCycles                        164068224                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                33437707                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps              51892623                       # Number of HB maps that are committed
-system.cpu.rename.FullRegisterEvents               80                       # Number of times there has been no free registers
-system.cpu.rename.IQFullEvents                 112778                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                 25099116                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents               2516814                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                458049                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups             315223829                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts               72505198                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands            74411101                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                  12919645                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles                2432206                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles               4910329                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                 22518477                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups             65605                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups        315158224                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles       16104209                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts             806801                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  13643103                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts         658966                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    157442889                       # The number of ROB reads
-system.cpu.rob.rob_writes                   136308798                       # The number of ROB writes
-system.cpu.timesIdled                         1088030                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.iq.FU_type_0::total               80215912                       # Type of FU issued
+system.cpu.iq.rate                           0.489378                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4850830                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.060472                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          260250560                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          85669706                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     61171405                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               16469                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               9406                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         6426                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               82664896                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    8623                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           366873                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      3351745                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        17637                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       321029                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1592843                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads     17031974                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          9614                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                2431425                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                21357875                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                254886                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            69165110                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            377919                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              12530731                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8670127                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            3998128                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  20657                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 45624                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         321029                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         537696                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       192380                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               730076                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              79002177                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              28266423                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1213735                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                        165908                       # number of nop insts executed
+system.cpu.iew.exec_refs                     36059018                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 10339734                       # Number of branches executed
+system.cpu.iew.exec_stores                    7792595                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.481974                       # Inst execution rate
+system.cpu.iew.wb_sent                       78480189                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      61177831                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  31697588                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  56147470                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       0.373231                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.564542                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       51999383                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        14908448                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         2962871                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            647540                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     92320849                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.563246                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.403184                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     71715015     77.68%     77.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      9932500     10.76%     88.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3015414      3.27%     91.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1450347      1.57%     93.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3545032      3.84%     97.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       778946      0.84%     97.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       574470      0.62%     98.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       309664      0.34%     98.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8       999461      1.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     92320849                       # Number of insts commited each cycle
+system.cpu.commit.count                      51999383                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       16256270                       # Number of memory references committed
+system.cpu.commit.loads                       9178986                       # Number of loads committed
+system.cpu.commit.membars                           3                       # Number of memory barriers committed
+system.cpu.commit.branches                    8429045                       # Number of branches committed
+system.cpu.commit.fp_insts                       6017                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  42422970                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               530172                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events                999461                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    157288126                       # The number of ROB reads
+system.cpu.rob.rob_writes                   136297259                       # The number of ROB writes
+system.cpu.timesIdled                         1087126                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        69161696                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    51876153                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              51876153                       # Number of Instructions Simulated
+system.cpu.cpi                               3.159717                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.159717                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.316484                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.316484                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                348377421                       # number of integer regfile reads
+system.cpu.int_regfile_writes                63134850                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      5557                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     1914                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                83038352                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 512623                       # number of misc regfile writes
+system.cpu.icache.replacements                 500212                       # number of replacements
+system.cpu.icache.tagsinuse                496.830420                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  5827483                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 500724                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  11.638114                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             6079257000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            496.830420                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.970372                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0             5827483                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         5827483                       # number of ReadReq hits
+system.cpu.icache.demand_hits::0              5827483                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          5827483                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0             5827483                       # number of overall hits
+system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::total         5827483                       # number of overall hits
+system.cpu.icache.ReadReq_misses::0            545006                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        545006                       # number of ReadReq misses
+system.cpu.icache.demand_misses::0             545006                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         545006                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0            545006                       # number of overall misses
+system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::total        545006                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     8053875993                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      8053875993                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     8053875993                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0         6372489                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      6372489                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0          6372489                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      6372489                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0         6372489                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      6372489                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0       0.085525                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0        0.085525                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::0       0.085525                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::0 14777.591427                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::0 14777.591427                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 14777.591427                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       923494                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               110                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  8395.400000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                    41542                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits             44276                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits              44276                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits             44276                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          500730                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           500730                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          500730                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency   6024482994                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   6024482994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   6024482994                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency      5116500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency      5116500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.078577                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.078577                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.078577                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12031.400144                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12031.400144                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12031.400144                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 422669                       # number of replacements
+system.cpu.dcache.tagsinuse                511.748488                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 13739336                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 423181                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  32.466807                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               48245000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0            511.748488                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999509                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0             8909058                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         8909058                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0            4618812                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4618812                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0        104652                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       104652                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0         105045                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       105045                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0             13527870                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13527870                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0            13527870                       # number of overall hits
+system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13527870                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::0            535094                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        535094                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0          2043981                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2043981                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0         6519                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         6519                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::0            2579075                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2579075                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0           2579075                       # number of overall misses
+system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2579075                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     7852770500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   81637630250                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency     97499500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     89490400750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    89490400750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0         9444152                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9444152                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0        6662793                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6662793                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0       111171                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       111171                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0       105045                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       105045                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0         16106945                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     16106945                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0        16106945                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     16106945                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0       0.056659                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0      0.306775                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.058639                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::0        0.160122                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::0       0.160122                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::0 14675.497202                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 39940.503483                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14956.204939                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 34698.642246                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 34698.642246                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      8797482                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       743000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1156                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              28                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  7610.278547                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 26535.714286                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   390904                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            286385                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1873352                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits          983                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            2159737                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           2159737                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          248709                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         170629                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses         5536                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           419338                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          419338                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3317944000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   6570142982                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency     65837500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   9888086982                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   9888086982                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency  38198704500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency    944337693                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency  39143042193                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.026335                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.025609                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.049797                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.026035                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.026035                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13340.667205                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38505.429804                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11892.611994                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23580.231179                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23580.231179                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
 system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
 system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
 system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                    0                       # number of overall misses
+system.iocache.overall_misses::total                0                       # number of overall misses
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                    0                       # number of overall misses
-system.iocache.overall_misses::total                0                       # number of overall misses
+system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks                           0                       # number of writebacks
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.replacements                         0                       # number of replacements
-system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.writebacks                           0                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               168958                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           168958                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52452.169082                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40012.241307                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                    60963                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                60963                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          5664572000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.639183                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 107995                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             107995                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     4321122000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.639183                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               107995                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                 754554                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 104775                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             859329                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52478.338642                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   12451401.162791                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 12503879.501433                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40044.278096                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                     734149                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     104689                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 838838                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency            1070820500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.027042                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.000821                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.027863                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                    20405                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       86                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20491                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits                       52                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency        818465000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.027088                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.195075                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.222163                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                  20439                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency  28946123000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0                1690                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1690                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0   404.548175                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                      19                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  19                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency             676000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.988757                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                  1671                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1671                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency      66840000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.988757                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses                1671                       # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency    748306939                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               432791                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           432791                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   432791                       # number of Writeback hits
-system.l2c.Writeback_hits::total               432791                       # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          8.132274                       # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                  923512                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  104775                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1028287                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    52456.327882                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    78318517.441860                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 78370973.769742                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40017.339645                       # average overall mshr miss latency
-system.l2c.demand_hits::0                      795112                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      104689                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  899801                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency             6735392500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.139034                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.000821                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.139855                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    128400                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        86                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                128486                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                        52                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency        5139587000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.139071                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.225808                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      1.364879                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  128434                       # number of demand (read+write) MSHR misses
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_blocks::0                  6549.473309                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 31510.112837                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.099937                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.480806                       # Average percentage of cache occupancy
-system.l2c.overall_accesses::0                 923512                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 104775                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1028287                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   52456.327882                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   78318517.441860                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 78370973.769742                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40017.339645                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                     795112                       # number of overall hits
-system.l2c.overall_hits::1                     104689                       # number of overall hits
-system.l2c.overall_hits::total                 899801                       # number of overall hits
-system.l2c.overall_miss_latency            6735392500                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.139034                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.000821                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.139855                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   128400                       # number of overall misses
-system.l2c.overall_misses::1                       86                       # number of overall misses
-system.l2c.overall_misses::total               128486                       # number of overall misses
-system.l2c.overall_mshr_hits                       52                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency       5139587000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.139071                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.225808                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     1.364879                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 128434                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency  29694429939                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                         94693                       # number of replacements
-system.l2c.sampled_refs                        126949                       # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     38059.586146                       # Cycle average of tags in use
-system.l2c.total_refs                         1032384                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                           87781                       # number of writebacks
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
index 127859fda32af6014d0c361558c65f11252b2bb2..33d2d38b3a620c60bb72e5de048aaa732d49b63a 100755 (executable)
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 15:10:15
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 18:02:55
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -29,4 +29,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 38285728000 because target called exit()
+Exiting @ tick 38330782000 because target called exit()
index 49f882c534f20c4cab6c669c0414aa369ab40a6b..e7c27e9ae94d9b4bca04d1024cdd3b76a653b66c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 204577                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 394692                       # Number of bytes of host memory used
-host_seconds                                   446.04                       # Real time elapsed on the host
-host_tick_rate                               85834347                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.038331                       # Number of seconds simulated
+sim_ticks                                 38330782000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  50765                       # Simulator instruction rate (inst/s)
+host_tick_rate                               21324746                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 388132                       # Number of bytes of host memory used
+host_seconds                                  1797.48                       # Real time elapsed on the host
 sim_insts                                    91249905                       # Number of instructions simulated
-sim_seconds                                  0.038286                       # Number of seconds simulated
-sim_ticks                                 38285728000                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 23530821                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              24877982                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect               12905                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            1726717                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           22205827                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 27600817                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                   100979                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts           1707487                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                   18722470                       # Number of branches committed
-system.cpu.commit.bw_lim_events               3914130                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts       91262514                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          554406                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        27309497                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples     72214525                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.263769                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.025482                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     36127600     50.03%     50.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18090116     25.05%     75.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      6155866      8.52%     83.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4484410      6.21%     89.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2045917      2.83%     92.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       550531      0.76%     93.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       763612      1.06%     94.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7        82343      0.11%     94.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3914130      5.42%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     72214525                       # Number of insts commited each cycle
-system.cpu.commit.count                      91262514                       # Number of instructions committed
-system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls                56148                       # Number of function calls committed.
-system.cpu.commit.int_insts                  72533318                       # Number of committed integer instructions.
-system.cpu.commit.loads                      22575876                       # Number of loads committed
-system.cpu.commit.membars                        3888                       # Number of memory barriers committed
-system.cpu.commit.refs                       27322629                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                    91249905                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              91249905                       # Number of Instructions Simulated
-system.cpu.cpi                               0.839140                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.839140                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses         6778                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits             6771                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency       124000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.001033                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses              7                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits            7                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses           25525235                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  5595.134205                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2527.282218                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               24493235                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     5774178500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.040431                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1032000                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            119171                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   2306976500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.035762                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          912829                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses          5796                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits              5796                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27661.201792                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30532.344047                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               4581531                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    4244611415                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.032408                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              153450                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           118821                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   1057304542                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.007313                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          34629                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2864.324268                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  30.700427                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs              8126                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs     23275499                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            30260216                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  8451.465616                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3550.849792                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                29074766                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     10018789915                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.039175                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1185450                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits             237992                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   3364281042                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.031310                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           947458                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           3486.280912                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.851143                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses           30260216                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  8451.465616                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3550.849792                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               29074766                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    10018789915                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.039175                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1185450                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits            237992                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   3364281042                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.031310                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          947458                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 943361                       # number of replacements
-system.cpu.dcache.sampled_refs                 947457                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3486.280912                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 29087334                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            16275855000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   942852                       # number of writebacks
-system.cpu.decode.BlockedCycles              10213263                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                 32161                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved              4330029                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts              129908076                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                 30506430                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                  31240805                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles                4327396                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                 33218                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles                254026                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    27600817                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  14528959                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      32560436                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                362446                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      132910862                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                    6                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 1860393                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.360458                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           14528959                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           23631800                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.735776                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples           76541920                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.751769                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.650338                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.numCycles                         76661565                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 27657644                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           22240511                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1744604                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              24744282                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 23393916                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                   124718                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               12906                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           14552899                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      133105183                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    27657644                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           23518634                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      32520380                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1878354                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                    7                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                  14552899                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                370142                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           76631921                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.753228                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.654795                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 44039302     57.54%     57.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  6026139      7.87%     65.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  6234278      8.14%     73.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4503549      5.88%     79.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3291793      4.30%     83.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1400372      1.83%     85.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1662749      2.17%     87.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3136974      4.10%     91.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  6246764      8.16%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 44169594     57.64%     57.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  6017071      7.85%     65.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6194245      8.08%     73.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4415007      5.76%     79.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3274566      4.27%     83.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1452193      1.90%     85.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1693941      2.21%     87.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3142647      4.10%     91.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  6272657      8.19%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             76541920                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        60                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       46                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           14528959                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36006.674757                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34472.834068                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               14528135                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       29669500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000057                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  824                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               143                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     23476000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000047                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             681                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               21364.904412                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            14528959                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36006.674757                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34472.834068                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                14528135                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        29669500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000057                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   824                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                143                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     23476000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000047                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              681                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            570.381562                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.278507                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses           14528959                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36006.674757                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34472.834068                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               14528135                       # number of overall hits
-system.cpu.icache.overall_miss_latency       29669500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000057                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  824                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               143                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     23476000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000047                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             681                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.sampled_refs                    680                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                570.381562                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 14528135                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           29537                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts              1811010                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 21021161                       # Number of branches executed
-system.cpu.iew.exec_nop                         38671                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.370820                       # Inst execution rate
-system.cpu.iew.exec_refs                     31258880                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                    5296884                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                   92844                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              29388831                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts             647702                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            633555                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts              6085547                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           118572043                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              25961996                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2334217                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             104965675                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  21340                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                   243                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                4327396                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 27063                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked         30520                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads           260518                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses         7496                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation       117715                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads      6812954                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores      1338794                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         117715                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       241876                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        1569134                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                  95054189                       # num instructions consuming a value
-system.cpu.iew.wb_count                     102978657                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.626333                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                  59535555                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.344870                       # insts written-back per cycle
-system.cpu.iew.wb_sent                      103397813                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads                499543161                       # number of integer regfile reads
-system.cpu.int_regfile_writes               121465311                       # number of integer regfile writes
-system.cpu.ipc                               1.191696                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.191696                       # IPC: Total IPC of All Threads
+system.cpu.fetch.rateDist::total             76631921                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.360776                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.736270                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 30588008                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              10266300                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  31174404                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                260454                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4342755                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4341355                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 41083                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              130094148                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 33304                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4342755                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 31960440                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  537193                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        8162537                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  30023248                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               1605748                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              125609145                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    19                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  50871                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                833181                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               20                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           146281053                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             547382815                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        547382254                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               561                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             107429471                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 38851577                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             673626                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         677053                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   5163872                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29426504                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6065519                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            977286                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           410445                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  117966564                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              652219                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 107299468                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             25775                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        24675448                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     62409285                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          97813                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      76631921                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.400193                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.609861                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            31086016     40.57%     40.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            16895448     22.05%     62.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            11625629     15.17%     77.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7628942      9.96%     87.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5191089      6.77%     94.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2275199      2.97%     97.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1510567      1.97%     99.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              290065      0.38%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              128966      0.17%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        76631921                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  155894     31.11%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     27      0.01%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     31.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                  83070     16.58%     47.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                262134     52.31%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              75293930     70.17%     70.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10513      0.01%     70.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              75289326     70.17%     70.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10516      0.01%     70.18% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.18% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.18% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.18% # Type of FU issued
@@ -321,210 +211,320 @@ system.cpu.iq.FU_type_0::SimdFloatMisc             24      0.00%     70.18% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.18% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.18% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26527925     24.72%     94.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5467485      5.10%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26536591     24.73%     94.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5462996      5.09%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              107299892                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                      69                       # Number of floating point alu accesses
+system.cpu.iq.FU_type_0::total              107299468                       # Type of FU issued
+system.cpu.iq.rate                           1.399651                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      501125                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.004670                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          291757623                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         143406422                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    102963471                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 134                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           61                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 92                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                      522807                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.004872                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  178340     34.11%     34.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     27      0.01%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                  83834     16.04%     50.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                260606     49.85%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses              107822630                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          291690830                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    102978596                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         143196091                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  117880817                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 107299892                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded              652555                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        24550577                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued             26453                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved          98149                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     62032164                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples      76541920                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.401845                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.609057                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            30986860     40.48%     40.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            16938663     22.13%     62.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            11541566     15.08%     77.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7661333     10.01%     87.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5199199      6.79%     94.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2314331      3.02%     97.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1500377      1.96%     99.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              273343      0.36%     99.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              126248      0.16%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        76541920                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.401304                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses           34664                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.196506                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31055.712222                       # average ReadExReq mshr miss latency
+system.cpu.iq.fp_inst_queue_wakeup_accesses           61                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              107800524                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      69                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           260883                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      6850627                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7190                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       117769                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1318766                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         30512                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                4342755                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   92075                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 26289                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           118657452                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            642589                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29426504                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6065519                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             647367                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  20754                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   246                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         117769                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1576147                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       244055                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1820202                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             104961161                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25966774                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2338307                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         38669                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31256963                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 21029204                       # Number of branches executed
+system.cpu.iew.exec_stores                    5290189                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.369150                       # Inst execution rate
+system.cpu.iew.wb_sent                      103386173                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     102963532                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  59509513                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95068105                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.343092                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.625967                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts       91262514                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        27394736                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          554406                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1716455                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     72289167                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.262465                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.025163                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     36212335     50.09%     50.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18072720     25.00%     75.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      6165923      8.53%     83.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4479757      6.20%     89.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2050310      2.84%     92.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       555022      0.77%     93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       748999      1.04%     94.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7        84475      0.12%     94.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3919626      5.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     72289167                       # Number of insts commited each cycle
+system.cpu.commit.count                      91262514                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       27322629                       # Number of memory references committed
+system.cpu.commit.loads                      22575876                       # Number of loads committed
+system.cpu.commit.membars                        3888                       # Number of memory barriers committed
+system.cpu.commit.branches                   18722470                       # Number of branches committed
+system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  72533318                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                56148                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               3919626                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    187021057                       # The number of ROB reads
+system.cpu.rob.rob_writes                   241665246                       # The number of ROB writes
+system.cpu.timesIdled                            1537                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           29644                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    91249905                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              91249905                       # Number of Instructions Simulated
+system.cpu.cpi                               0.840128                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.840128                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.190295                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.190295                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                499502252                       # number of integer regfile reads
+system.cpu.int_regfile_writes               121448309                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        60                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       46                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               187007485                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  11602                       # number of misc regfile writes
+system.cpu.icache.replacements                      2                       # number of replacements
+system.cpu.icache.tagsinuse                569.362196                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 14552080                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    678                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               21463.244838                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            569.362196                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.278009                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               14552080                       # number of ReadReq hits
+system.cpu.icache.demand_hits                14552080                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               14552080                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  819                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   819                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  819                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       29501500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        29501500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       29501500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           14552899                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            14552899                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           14552899                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000056                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000056                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000056                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36021.367521                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36021.367521                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36021.367521                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               140                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                140                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               140                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             679                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              679                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             679                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     23405500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     23405500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     23405500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000047                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000047                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000047                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34470.544919                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34470.544919                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34470.544919                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 943332                       # number of replacements
+system.cpu.dcache.tagsinuse               3485.983944                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 29091101                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 947428                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  30.705342                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            16303802000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3485.983944                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.851070                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               24496946                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               4581580                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             6778                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              5796                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                29078526                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               29078526                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1032002                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              153401                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              7                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               1185403                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1185403                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     5774861500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    4244831902                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       124000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     10019693402                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    10019693402                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           25528948                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses         6785                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          5796                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            30263929                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           30263929                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.040425                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.032397                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.001032                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.039169                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.039169                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency  5595.785183                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27671.474775                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency  8452.562885                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency  8452.562885                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     23297488                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              8138                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2862.802654                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   942849                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            119201                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           118773                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            7                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             237974                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            237974                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          912801                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          34628                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           947429                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          947429                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   2307886000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1057417534                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   3365303534                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   3365303534                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.035756                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.007313                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.031306                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.031306                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2528.356126                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30536.488795                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3552.037708                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3552.037708                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                   702                       # number of replacements
+system.cpu.l2cache.tagsinuse              8532.679465                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1625371                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15516                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                104.754511                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           402.391901                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8130.287564                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.012280                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.248117                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                912439                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              942849                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits               20125                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency    499228500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.419426                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                 932564                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                932564                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                1003                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses             14539                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    451519000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.419426                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        14539                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            913473                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34317.365269                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31113.911290                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                912471                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      34386000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.001097                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                1002                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001086                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            992                       # number of ReadReq MSHR misses
+system.cpu.l2cache.demand_misses                15542                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               15542                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      34422500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    499217500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      533640000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     533640000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            913442                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          942849                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_accesses           34664                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             948106                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            948106                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.001098                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          942852                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              942852                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                104.767129                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate       0.419426                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.016393                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.016393                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34319.541376                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.439920                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34335.349376                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34335.349376                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             948137                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34335.917895                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.429528                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 932596                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      533614500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.016391                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                15541                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                      32                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    482384000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.016381                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           15531                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0           401.000485                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8133.618465                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.012238                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.248218                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses            948137                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34335.917895                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.429528                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                932596                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     533614500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.016391                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               15541                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits               10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    482384000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.016381                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          15531                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses            993                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        14539                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           15532                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          15532                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                   703                       # number of replacements
-system.cpu.l2cache.sampled_refs                 15515                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency     30896000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    451520000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    482416000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    482416000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001087                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.419426                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.016382                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.016382                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31113.796576                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31055.781003                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.490085                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.490085                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              8534.618949                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1625462                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                      32                       # number of writebacks
-system.cpu.memDep0.conflictingLoads            929079                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           406185                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             29388831                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6085547                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               186806187                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                  11602                       # number of misc regfile writes
-system.cpu.numCycles                         76571457                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                  527053                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps             107429471                       # Number of HB maps that are committed
-system.cpu.rename.FullRegisterEvents               10                       # Number of times there has been no free registers
-system.cpu.rename.IQFullEvents                  52081                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                 31875440                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents                790758                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                    19                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups             546541782                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts              125415140                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands           146085442                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                  30085876                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles                4327396                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles               1561693                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                 38655966                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups               561                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups        546541221                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles        8164462                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts             673678                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                   5091742                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts         677127                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    186866672                       # The number of ROB reads
-system.cpu.rob.rob_writes                   241479537                       # The number of ROB writes
-system.cpu.timesIdled                            1545                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                  442                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index b2a54aa3484a60354435eca3895437fb41023755..e9e668346879b8e4da6735bdcf2e5df53a2e052f 100755 (executable)
@@ -1,3 +1,5 @@
+Redirecting stdout to build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2011 13:30:37
-M5 started Apr 21 2011 13:35:14
-M5 executing on maize
+M5 compiled May 17 2011 12:22:59
+M5 started May 17 2011 13:00:50
+M5 executing on nadc-0309
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -27,4 +29,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 81396224000 because target called exit()
+Exiting @ tick 81353358500 because target called exit()
index 516464ff96203e8fb5d9e4e283e3a17514650fbd..f27bf782582d568b148486268f5016f487312252 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 154675                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 349680                       # Number of bytes of host memory used
-host_seconds                                  1798.56                       # Real time elapsed on the host
-host_tick_rate                               45256270                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.081353                       # Number of seconds simulated
+sim_ticks                                 81353358500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 230671                       # Simulator instruction rate (inst/s)
+host_tick_rate                               67456393                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 384688                       # Number of bytes of host memory used
+host_seconds                                  1206.01                       # Real time elapsed on the host
 sim_insts                                   278192519                       # Number of instructions simulated
-sim_seconds                                  0.081396                       # Number of seconds simulated
-sim_ticks                                 81396224000                       # Number of ticks simulated
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
+system.cpu.numCycles                        162706718                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 43478033                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           43478033                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2457578                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              38773202                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 38222212                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 38238795                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              38788801                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            2465320                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           43504790                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 43504790                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts           2465329                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                   29309710                       # Number of branches committed
-system.cpu.commit.bw_lim_events              13548841                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        88842299                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples    149131695                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.865415                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.481905                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     63516016     42.59%     42.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     27005826     18.11%     60.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     19486009     13.07%     73.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13132636      8.81%     82.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4245933      2.85%     85.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      3434891      2.30%     87.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3062949      2.05%     89.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1698594      1.14%     90.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     13548841      9.09%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    149131695                       # Number of insts commited each cycle
-system.cpu.commit.count                     278192519                       # Number of instructions committed
-system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
-system.cpu.commit.loads                      90779388                       # Number of loads committed
-system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.refs                      122219139                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                   278192519                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             278192519                       # Number of Instructions Simulated
-system.cpu.cpi                               0.585179                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.585179                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses           63345837                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  6389.837562                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2805.424936                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               61126773                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    14179458500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.035031                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              2219064                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            247059                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   5532312000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.031131                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1972005                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 17790.751735                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17644.271587                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              31202641                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    4218365144                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.007542                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              237110                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           131111                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   1870275144                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003371                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         105999                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  3445.783133                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  44.431869                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                83                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs       286000                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            94785588                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  7490.439865                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3562.354617                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                92329414                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     18397823644                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.025913                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2456174                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits             378170                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   7402587144                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.021923                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          2078004                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4075.274681                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.994940                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses           94785588                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  7490.439865                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3562.354617                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               92329414                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    18397823644                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.025913                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2456174                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits            378170                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   7402587144                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.021923                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         2078004                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                2073904                       # number of replacements
-system.cpu.dcache.sampled_refs                2078000                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4075.274681                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 92329423                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            30396735000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  1448011                       # number of writebacks
-system.cpu.decode.BlockedCycles              13645155                       # Number of cycles decode is blocked
-system.cpu.decode.DecodedInsts              390459172                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                 68124952                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                  66154578                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles               12492114                       # Number of cycles decode is squashing
-system.cpu.decode.UnblockCycles               1207010                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                    43504790                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  30855910                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      71218247                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                310077                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      225429246                       # Number of instructions fetch has processed
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           30836194                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      225319865                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    43478033                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           38222212                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      71185004                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2631314                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   21                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 2638813                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.267241                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           30855910                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           38238795                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.384765                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          161623809                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.462324                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.240695                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  30836194                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                310702                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          161537602                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.462501                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.241161                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 92912734     57.49%     57.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4821587      2.98%     60.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3003433      1.86%     62.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6267047      3.88%     66.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7344013      4.54%     70.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5575474      3.45%     74.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  8028911      4.97%     79.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  6451248      3.99%     83.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 27219362     16.84%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 92871454     57.49%     57.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4826864      2.99%     60.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3003358      1.86%     62.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6248204      3.87%     66.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7317457      4.53%     70.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5554189      3.44%     74.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  8050336      4.98%     79.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  6460332      4.00%     83.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 27205408     16.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            161623809                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        75                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       41                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           30855910                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36182.458888                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35209.772952                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               30854633                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       46205000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000041                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 1277                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               264                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     35667500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000033                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            1013                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               30488.767787                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            30855910                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36182.458888                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35209.772952                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                30854633                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        46205000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000041                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  1277                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                264                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     35667500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000033                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             1013                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            812.031019                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.396500                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses           30855910                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36182.458888                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35209.772952                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               30854633                       # number of overall hits
-system.cpu.icache.overall_miss_latency       46205000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000041                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 1277                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               264                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     35667500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000033                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            1013                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                     63                       # number of replacements
-system.cpu.icache.sampled_refs                   1012                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                812.031019                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 30854633                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         1168640                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts              2866285                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 32808514                       # Number of branches executed
-system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_rate                     2.009454                       # Inst execution rate
-system.cpu.iew.exec_refs                    141715314                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                   34352421                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                  739357                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             121527888                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            440749                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             39643183                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           367028456                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             107362893                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           4685170                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             327123971                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                   4283                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 66782                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               12492114                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                101572                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked         14164                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads         43812375                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses        37185                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation       237293                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads         3275                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads     30748500                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores      8203432                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         237293                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       582972                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        2283313                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                 330470543                       # num instructions consuming a value
-system.cpu.iew.wb_count                     324204287                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.735351                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                 243011799                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.991519                       # insts written-back per cycle
-system.cpu.iew.wb_sent                      325408414                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads                572686347                       # number of integer regfile reads
-system.cpu.int_regfile_writes               291536884                       # number of integer regfile writes
-system.cpu.ipc                               1.708879                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.708879                       # IPC: Total IPC of All Threads
+system.cpu.fetch.rateDist::total            161537602                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.267217                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.384822                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 68100522                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              13645785                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  66107585                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1213656                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               12470054                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              390299110                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               12470054                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 72027635                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 3012057                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           6445                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  63003531                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              11017880                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              382954672                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 129804                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               9724945                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           343637650                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             940851472                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        940850893                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               579                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 95293458                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                468                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            462                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  25876088                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            121481389                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            39633547                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          49140895                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         10609784                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  366915906                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 465                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 331723490                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            173771                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        88480197                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    124853434                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             19                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     161537602                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.053537                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.792236                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            44403783     27.49%     27.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            26523335     16.42%     43.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            27554043     17.06%     60.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            26723041     16.54%     77.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19519323     12.08%     89.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            11121820      6.88%     96.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3849891      2.38%     98.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1601720      0.99%     99.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              240646      0.15%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       161537602                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   20533      1.17%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1580289     90.40%     91.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                147351      8.43%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             16703      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             188329198     56.76%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             188283718     56.76%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  16      0.00%     56.76% # Type of FU issued
@@ -288,186 +165,309 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.76% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            108641887     32.74%     89.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34821337     10.49%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            108609030     32.74%     89.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34814023     10.49%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              331809141                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                     101                       # Number of floating point alu accesses
+system.cpu.iq.FU_type_0::total              331723490                       # Type of FU issued
+system.cpu.iq.rate                           2.038782                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1748173                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005270                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          826906318                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         455618768                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    324136676                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 208                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                234                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           80                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                238                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     1744992                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.005259                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   20475      1.17%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1576903     90.37%     91.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                147614      8.46%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses              333537329                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          827162429                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    324204207                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         455842500                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  367027991                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 331809141                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                 465                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        88592670                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            175554                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             19                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    124945161                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples     161623809                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.052972                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.792191                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            44438080     27.49%     27.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            26560474     16.43%     43.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            27560184     17.05%     60.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            26726118     16.54%     77.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            19530475     12.08%     89.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            11104171      6.87%     96.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             3863575      2.39%     98.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1600116      0.99%     99.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              240616      0.15%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       161623809                       # Number of insts issued each cycle
-system.cpu.iq.rate                           2.038234                       # Inst issue rate
-system.cpu.l2cache.ReadExReq_accesses          106011                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.017786                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31115.893095                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               63955                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   1437979500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.396714                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             42056                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1308610000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.396714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        42056                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1973004                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34215.506485                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.372893                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               1938541                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1179169000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.017467                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               34463                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1069158500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017467                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          34463                       # number of ReadReq MSHR misses
+system.cpu.iq.int_alu_accesses              333454859                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     101                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         43811715                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     30702001                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        37170                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       238201                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      8193796                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         3292                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         14215                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               12470054                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  739461                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                101351                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           366916371                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            440258                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             121481389                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             39633547                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   4278                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 66728                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         238201                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2276962                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       580211                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              2857173                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             327058428                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             107336037                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           4665062                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                    141682074                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32801587                       # Number of branches executed
+system.cpu.iew.exec_stores                   34346037                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.010110                       # Inst execution rate
+system.cpu.iew.wb_sent                      325338572                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     324136756                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 242967422                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 330454967                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.992153                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.735251                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        88730028                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           2457587                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    149067548                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.866218                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.482505                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     63468061     42.58%     42.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     26994600     18.11%     60.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     19490262     13.07%     73.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13117480      8.80%     82.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4245570      2.85%     85.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3438248      2.31%     87.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3061065      2.05%     89.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1693051      1.14%     90.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13559211      9.10%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    149067548                       # Number of insts commited each cycle
+system.cpu.commit.count                     278192519                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      122219139                       # Number of memory references committed
+system.cpu.commit.loads                      90779388                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                   29309710                       # Number of branches committed
+system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              13559211                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    502430884                       # The number of ROB reads
+system.cpu.rob.rob_writes                   746329282                       # The number of ROB writes
+system.cpu.timesIdled                           40054                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1169116                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   278192519                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             278192519                       # Number of Instructions Simulated
+system.cpu.cpi                               0.584871                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.584871                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.709779                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.709779                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                572578713                       # number of integer regfile reads
+system.cpu.int_regfile_writes               291474353                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        75                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       41                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               211120280                       # number of misc regfile reads
+system.cpu.icache.replacements                     60                       # number of replacements
+system.cpu.icache.tagsinuse                811.599985                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 30834919                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1009                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               30559.880079                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            811.599985                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.396289                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               30834919                       # number of ReadReq hits
+system.cpu.icache.demand_hits                30834919                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               30834919                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1275                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1275                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1275                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       46105500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        46105500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       46105500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           30836194                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            30836194                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           30836194                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000041                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000041                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000041                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36161.176471                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36161.176471                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36161.176471                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               265                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                265                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               265                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            1010                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             1010                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            1010                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     35558500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     35558500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     35558500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000033                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000033                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000033                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35206.435644                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35206.435644                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35206.435644                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2073960                       # number of replacements
+system.cpu.dcache.tagsinuse               4075.298640                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 92303486                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2078056                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  44.418190                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            30307591000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4075.298640                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994946                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               61101027                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              31202450                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                92303477                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               92303477                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              2219212                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              237301                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               2456513                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2456513                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    14180205500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    4209484208                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     18389689708                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    18389689708                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           63320239                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            94759990                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           94759990                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.035047                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.007548                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.025924                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.025924                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency  6389.748028                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 17739.007455                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency  7486.095009                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency  7486.095009                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       290000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                85                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3411.764706                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  1448049                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            247154                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           131299                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             378453                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            378453                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1972058                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         106002                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2078060                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2078060                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   5532610500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1870145708                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   7402756208                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   7402756208                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.031144                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003372                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.021930                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.021930                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2805.500903                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17642.551159                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3562.339975                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3562.339975                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                 49058                       # number of replacements
+system.cpu.l2cache.tagsinuse             18069.203236                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3319340                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 77063                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 43.073070                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          6443.195976                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11626.007260                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.196631                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.354798                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1938598                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1448049                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               63959                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                2002557                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               2002557                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               34456                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses             42055                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                76511                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               76511                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1178964000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   1437688500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     2616652500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    2616652500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1973054                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1448049                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_accesses          106014                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2079068                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2079068                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.017463                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         1448011                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             1448011                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs         2500                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                 43.067418                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs               14                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate       0.396693                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.036801                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.036801                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34216.508010                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34185.911307                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34199.690241                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34199.690241                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs        35000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               14                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs         2500                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            2079015                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34202.596741                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31074.223395                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                2002496                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     2617148500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.036805                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                76519                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                   29183                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   2377768500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.036805                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           76519                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          6434.571377                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         11614.477696                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.196368                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.354446                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses           2079015                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34202.596741                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.223395                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               2002496                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    2617148500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.036805                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               76519                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   2377768500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.036805                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          76519                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses          34456                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        42055                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           76511                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          76511                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 49066                       # number of replacements
-system.cpu.l2cache.sampled_refs                 77071                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1068941000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1308447000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2377388000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2377388000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017463                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.396693                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.036801                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.036801                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.363130                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31112.757104                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.499379                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.499379                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18049.049074                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3319249                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   29185                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          49162785                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         10611644                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            121527888                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            39643183                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               211169577                       # number of misc regfile reads
-system.cpu.numCycles                        162792449                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                 3023364                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents                 130274                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                 72054036                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents               9710787                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups             941229334                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts              383108308                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands           343773743                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                  63044913                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles               12492114                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles              11002939                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                 95429551                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups               586                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups        941228748                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles           6443                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts                468                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  25868384                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts            462                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    502617672                       # The number of ROB reads
-system.cpu.rob.rob_writes                   746575877                       # The number of ROB writes
-system.cpu.timesIdled                           40062                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                  444                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index fa8986d95e885a31b7c6b41d7bb75721fd1bcc43..5a0807465baccd6ad0cc2bb73f2be65a7e02872b 100755 (executable)
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 14:22:00
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 15:29:17
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -73,4 +73,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 321578293500 because target called exit()
+Exiting @ tick 320953109000 because target called exit()
index 8213121ceba9d764a90b44e0b5d710af045b7a66..b11250106afc64e2a9782790a6822f874447d874 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 152812                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 267644                       # Number of bytes of host memory used
-host_seconds                                  3751.94                       # Real time elapsed on the host
-host_tick_rate                               85709842                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.320953                       # Number of seconds simulated
+sim_ticks                                320953109000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   573342347                       # Number of instructions simulated
-sim_seconds                                  0.321578                       # Number of seconds simulated
-sim_ticks                                321578293500                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                148133449                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             184155292                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect             2540432                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           19178163                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          179128665                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                224215048                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                 11903329                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts          21282283                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                  120192352                       # Number of branches committed
-system.cpu.commit.bw_lim_events              10124607                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts      574686231                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls         3877883                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       335224652                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples    586025394                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.980651                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.590909                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    312132657     53.26%     53.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    152008237     25.94%     79.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     54725010      9.34%     88.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     24718239      4.22%     92.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     15770136      2.69%     95.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      6564583      1.12%     96.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7700533      1.31%     97.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2281392      0.39%     98.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10124607      1.73%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    586025394                       # Number of insts commited each cycle
-system.cpu.commit.count                     574686231                       # Number of instructions committed
-system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
-system.cpu.commit.int_insts                 473702145                       # Number of committed integer instructions.
-system.cpu.commit.loads                     126773167                       # Number of loads committed
-system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
-system.cpu.commit.refs                      184377255                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                   573342347                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             573342347                       # Number of Instructions Simulated
-system.cpu.cpi                               1.121767                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.121767                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses      2604413                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency  8882.352941                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits          2604379                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency       302000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000013                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses             34                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits           34                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses          143465196                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 10833.810170                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7175.241150                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              142365589                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    11912933500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.007665                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1099607                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            241635                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   6156156000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.005980                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          857972                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses       2232152                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits           2232152                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 15161.234737                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12563.932747                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              52868553                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   20782308000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.025272                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1370753                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1034947                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   4219044000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006191                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         335806                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets  5390.625000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 167.641865                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              32                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       172500                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           197704502                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13235.010889                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  8691.063162                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               195234142                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     32695241500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.012495                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2470360                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1276582                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  10375200000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.006038                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1193778                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4060.874839                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.991425                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          197704502                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13235.010889                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  8691.063162                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              195234142                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    32695241500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.012495                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2470360                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1276582                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  10375200000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.006038                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1193778                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1189349                       # number of replacements
-system.cpu.dcache.sampled_refs                1193445                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4060.874839                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                200071346                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             6159353000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  1065214                       # number of writebacks
-system.cpu.decode.BlockedCycles              81401294                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                 76616                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved             32098392                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts             1089624407                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                274509377                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                 227139147                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles               53022157                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                216379                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles               2975575                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+host_inst_rate                                  40042                       # Simulator instruction rate (inst/s)
+host_tick_rate                               22415184                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260460                       # Number of bytes of host memory used
+host_seconds                                 14318.56                       # Real time elapsed on the host
+sim_insts                                   573342262                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                   224215048                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 130463264                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     241171413                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               4019936                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      971569879                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                 3446                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                21817115                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.348617                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          130463264                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          160036778                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.510627                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          639047550                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.784644                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.739665                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.numCycles                        641906219                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                223949599                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          179054613                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           19156129                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             184229626                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                147971030                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 11972868                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect             2532941                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          130565917                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      973113322                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   223949599                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          159943898                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     241546376                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                21862580                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2406                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                 130565917                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               3998860                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          637850640                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.791502                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.743865                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                397887895     62.26%     62.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 20346317      3.18%     65.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 35545553      5.56%     71.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 35836074      5.61%     76.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 37423623      5.86%     82.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 17678726      2.77%     85.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 18470353      2.89%     88.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 14255263      2.23%     90.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 61603746      9.64%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                396316059     62.13%     62.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 20357816      3.19%     65.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 35705192      5.60%     70.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 35959525      5.64%     76.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 37219035      5.84%     82.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 17602838      2.76%     85.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 18536216      2.91%     88.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 14275483      2.24%     90.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 61878476      9.70%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            639047550                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            637850640                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.348882                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.515974                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                274650627                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              79437827                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 227463937                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2944119                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               53354130                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             31952595                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 76091                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1091620209                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                217331                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               53354130                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                289506174                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 9893108                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       49317817                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 215240896                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              20538515                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1036732054                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   236                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                6072390                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               9974912                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               19                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1156982067                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4582431546                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4582430193                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              1353                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             672201056                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                484781006                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2811540                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2811485                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  54423240                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            192516932                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           113728531                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          52019514                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         56045106                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  898220409                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             4649392                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 742085900                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4028217                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       325034737                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    902951971                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         771526                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     637850640                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.163416                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.451606                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           296239264     46.44%     46.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           133409185     20.92%     67.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           102098632     16.01%     83.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            53722534      8.42%     91.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            32322089      5.07%     96.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            11168911      1.75%     98.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5441714      0.85%     99.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2057834      0.32%     99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1390477      0.22%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       637850640                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   95830      1.04%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5443662     59.10%     60.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3670689     39.85%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             503818075     67.89%     67.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               366199      0.05%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  82      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            163695097     22.06%     90.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            74206444     10.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              742085900                       # Type of FU issued
+system.cpu.iq.rate                           1.156066                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     9210181                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012411                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2135260638                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1228450518                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    694522935                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 200                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                304                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              751295979                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     102                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5771553                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     65743781                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        15629                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       596063                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     56124460                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads        24980                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           144                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               53354130                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2618576                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                142825                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           912051296                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          21556193                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             192516932                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            113728531                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2788498                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  84227                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  8711                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         596063                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       17931306                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6522754                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             24454060                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             711877956                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             154430876                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          30207944                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                       9181495                       # number of nop insts executed
+system.cpu.iew.exec_refs                    222561224                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                143781551                       # Number of branches executed
+system.cpu.iew.exec_stores                   68130348                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.109006                       # Inst execution rate
+system.cpu.iew.wb_sent                      704134955                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     694522951                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 388125156                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 688020690                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.081970                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.564118                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      574686146                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       337368429                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         3877866                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          21251956                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    584496511                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.983216                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.594536                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    311654164     53.32%     53.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    150316632     25.72%     79.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     55227209      9.45%     88.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     24753339      4.23%     92.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     15848741      2.71%     95.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      6546524      1.12%     96.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7691194      1.32%     97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2289333      0.39%     98.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10169375      1.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    584496511                       # Number of insts commited each cycle
+system.cpu.commit.count                     574686146                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      184377221                       # Number of memory references committed
+system.cpu.commit.loads                     126773150                       # Number of loads committed
+system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
+system.cpu.commit.branches                  120192335                       # Number of branches committed
+system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 473702077                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              10169375                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   1486374573                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1877592139                       # The number of ROB writes
+system.cpu.timesIdled                           93100                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         4055579                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   573342262                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             573342262                       # Number of Instructions Simulated
+system.cpu.cpi                               1.119586                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.119586                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.893187                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.893187                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3288876394                       # number of integer regfile reads
+system.cpu.int_regfile_writes               807633235                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses          130463264                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14395.336442                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 10664.161477                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              130448254                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      216074000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000115                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                15010                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits              1039                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    148989000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000107                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           13971                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                9587.553212                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.misc_regfile_reads              1209708694                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                4464272                       # number of misc regfile writes
+system.cpu.icache.replacements                  11767                       # number of replacements
+system.cpu.icache.tagsinuse               1053.166926                       # Cycle average of tags in use
+system.cpu.icache.total_refs                130550979                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  13545                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                9638.315172                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1053.166926                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.514242                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              130550990                       # number of ReadReq hits
+system.cpu.icache.demand_hits               130550990                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              130550990                       # number of overall hits
+system.cpu.icache.ReadReq_misses                14927                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 14927                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                14927                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      215353500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       215353500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      215353500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          130565917                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           130565917                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          130565917                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000114                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000114                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000114                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 14427.111945                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 14427.111945                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 14427.111945                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           130463264                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14395.336442                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 10664.161477                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               130448254                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       216074000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000115                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 15010                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits               1039                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    148989000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000107                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            13971                       # number of demand (read+write) MSHR misses
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1050.734375                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.513054                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          130463264                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14395.336442                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 10664.161477                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              130448254                       # number of overall hits
-system.cpu.icache.overall_miss_latency      216074000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000115                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                15010                       # number of overall misses
-system.cpu.icache.overall_mshr_hits              1039                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    148989000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000107                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           13971                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        2                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1072                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1072                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1072                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           13855                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            13855                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           13855                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  11828                       # number of replacements
-system.cpu.icache.sampled_refs                  13606                       # Sample count of references to valid blocks.
+system.cpu.icache.ReadReq_mshr_miss_latency    147833000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    147833000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    147833000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000106                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000106                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000106                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 10670.010826                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 10670.010826                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 10670.010826                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1050.734375                       # Cycle average of tags in use
-system.cpu.icache.total_refs                130448249                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        4                       # number of writebacks
-system.cpu.idleCycles                         4109038                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts             24488226                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                144045420                       # Number of branches executed
-system.cpu.iew.exec_nop                       9196797                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.104746                       # Inst execution rate
-system.cpu.iew.exec_refs                    221540830                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                   67586566                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                 2832645                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             191530512                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            2788377                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts          21562901                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            112754072                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           909908771                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             153954264                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29546426                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             710524922                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  84675                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  9984                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               53022157                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                156338                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked           138                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads          5449723                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses         9231                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation       514201                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads        24892                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads     64757344                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores     55149984                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         514201                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      6539139                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       17949087                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                 689691426                       # num instructions consuming a value
-system.cpu.iew.wb_count                     693409732                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.562543                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                 387981236                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.078135                       # insts written-back per cycle
-system.cpu.iew.wb_sent                      702871979                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads               3281708105                       # number of integer regfile reads
-system.cpu.int_regfile_writes               806654983                       # number of integer regfile writes
-system.cpu.ipc                               0.891451                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.891451                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             503382481     68.02%     68.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               366130      0.05%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 100      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            163172266     22.05%     90.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            73150368      9.88%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              740071348                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                     120                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                 236                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                322                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     9396552                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012697                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  121750      1.30%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5531349     58.87%     60.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3743453     39.84%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses              749467780                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         2132627874                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    693409716                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        1224006325                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  896062746                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 740071348                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             4649228                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       322821915                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued           4041312                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved         771345                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    897570862                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples     639047550                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.158085                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.444316                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           296540027     46.40%     46.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           135125235     21.14%     67.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           102276930     16.00%     83.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            53053702      8.30%     91.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            32312745      5.06%     96.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            10946068      1.71%     98.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5715024      0.89%     99.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1662869      0.26%     99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1414950      0.22%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       639047550                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.150686                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          335811                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.016328                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31006.007098                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              231268                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   3580704000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.311315                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            104543                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   3241461000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.311315                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       104543                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            871234                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34198.783276                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31027.526740                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                742199                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    4412840000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.148106                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              129035                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4003171500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.148089                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         129020                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses            323                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency  4157.258065                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_hits                199                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_latency       515500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate      0.383901                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses              124                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency      3844000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.383901                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses          124                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         1065218                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             1065218                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  6.556248                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1189612                       # number of replacements
+system.cpu.dcache.tagsinuse               4060.806862                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                200134121                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1193708                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 167.657518                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             6159317000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4060.806862                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.991408                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              142442366                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              52854608                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits          2604415                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits           2232135                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               195296974                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              195296974                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1102250                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1384698                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses             36                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               2486948                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2486948                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    11846428500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   20406027500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       313000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     32252456000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    32252456000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          143544616                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses      2604451                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses       2232135                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           197783922                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          197783922                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.007679                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.025529                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000014                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.012574                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.012574                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 10747.496938                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 14736.807232                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency  8694.444444                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 12968.689333                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 12968.689333                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       172500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              32                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets  5390.625000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  1065401                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            244002                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1048961                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits           36                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1292963                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1292963                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          858248                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         335737                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1193985                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1193985                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   6157877500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   4228090500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  10385968000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  10385968000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.005979                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006190                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.006037                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.006037                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7174.939528                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12593.460060                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  8698.574940                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  8698.574940                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                214616                       # number of replacements
+system.cpu.l2cache.tagsinuse             21258.843371                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1538764                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                234845                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.552254                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          231195370000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          7817.837138                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13441.006233                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.238581                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.410187                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                742273                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1065403                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits                160                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits              231247                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 973520                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                973520                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              129152                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses              112                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            104568                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               233720                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              233720                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    4416243000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency       547000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3581590000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     7997833000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    7997833000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            871425                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1065403                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses            272                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          335815                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1207240                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1207240                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.148208                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.411765                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.311386                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.193599                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.193599                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34194.151078                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency  4883.928571                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.300589                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34219.720178                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34219.720178                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1207045                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34222.161334                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31017.894530                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 973467                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     7993544000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.193512                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               233578                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                  169760                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               15                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   7244632500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.193500                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          233563                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          7806.839670                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13448.206347                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.238246                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.410407                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses           1207045                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34222.161334                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31017.894530                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                973467                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    7993544000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.193512                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              233578                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits               15                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   7244632500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.193500                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         233563                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses         129137                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses          112                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       104568                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          233705                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         233705                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                214457                       # number of replacements
-system.cpu.l2cache.sampled_refs                234692                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4006675000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency      3473000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   3242222500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   7248897500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   7248897500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.148191                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.411765                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.311386                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.193586                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.193586                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.545452                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31008.928571                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.876559                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31017.297448                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31017.297448                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             21255.046017                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1538699                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          231483982000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  169715                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          55352891                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         57957539                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            191530512                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           112754072                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads              1207319291                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                4464306                       # number of misc regfile writes
-system.cpu.numCycles                        643156588                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                10882615                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps             672201192                       # Number of HB maps that are committed
-system.cpu.rename.FullRegisterEvents               19                       # Number of times there has been no free registers
-system.cpu.rename.IQFullEvents                6788504                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                289521526                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents              10125485                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                   314                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups            4573163834                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts             1035060764                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands          1156158819                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                 214798032                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles               53022157                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles              21471386                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                483957622                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups              1478                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups       4573162356                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles       49351834                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts            2811446                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  56327662                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts        2811371                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   1485804532                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1872966430                       # The number of ROB writes
-system.cpu.timesIdled                           97371                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                  548                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 10516f0f0eabb95df5d3be035872602659ef7fb3..4df0253e79b3df1a6ac550b6e3390bc258121e19 100755 (executable)
@@ -1,3 +1,5 @@
+Redirecting stdout to build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 23 2011 16:56:34
-M5 started Apr 23 2011 17:38:09
-M5 executing on victors
+M5 compiled May 17 2011 12:22:59
+M5 started May 17 2011 13:21:24
+M5 executing on nadc-0309
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -29,6 +31,14 @@ Echoing of input sentence turned on.
 * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 * how fast the program is it 
 * I am wondering whether to invite to the party 
 * I gave him for his birthday it 
@@ -73,4 +83,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 584102039000 because target called exit()
+Exiting @ tick 584023415000 because target called exit()
index cf0c34300abda2e2ad70934956689a8ace72fe11..59fe69eba7e4262974a5488b0be0fac961b9eac3 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  88955                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 246024                       # Number of bytes of host memory used
-host_seconds                                 17188.43                       # Real time elapsed on the host
-host_tick_rate                               33982273                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.584023                       # Number of seconds simulated
+sim_ticks                                584023415000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 204231                       # Simulator instruction rate (inst/s)
+host_tick_rate                               78009509                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293660                       # Number of bytes of host memory used
+host_seconds                                  7486.57                       # Real time elapsed on the host
 sim_insts                                  1528988756                       # Number of instructions simulated
-sim_seconds                                  0.584102                       # Number of seconds simulated
-sim_ticks                                584102039000                       # Number of ticks simulated
+system.cpu.workload.num_syscalls                  551                       # Number of system calls
+system.cpu.numCycles                       1168046831                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                253390632                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          253390632                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           16658352                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             238513057                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                219596279                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                218742072                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             237579384                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           16731555                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          252612908                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                252612908                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts          16763223                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                  149758588                       # Number of branches committed
-system.cpu.commit.bw_lim_events              41097639                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          188480819                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1362450524                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   253390632                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          219596279                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     442052723                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                19279680                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                77230                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                 188480819                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               3788271                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1143904596                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.224031                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.207932                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                706004786     61.72%     61.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 32751719      2.86%     64.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 38229862      3.34%     67.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34570255      3.02%     70.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 20874859      1.82%     72.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 39604957      3.46%     76.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 44518737      3.89%     80.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 36275151      3.17%     83.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                191074270     16.70%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total           1143904596                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.216935                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.166435                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                421330270                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             186446419                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 405934175                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              21628969                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              108564763                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2493904791                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles              108564763                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                460258453                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                50662056                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          15556                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 387000173                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             137403595                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2428714828                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  8220                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               53929654                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              70829494                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2267135297                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5702873531                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       5702857140                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             16391                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                839836270                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2552                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2513                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 298757683                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            586893998                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           222778511                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         352697963                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        138822292                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2327078199                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                9768                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1903699453                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            749156                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       795322101                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1354689551                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           9215                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1143904596                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.664212                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.649949                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           364118171     31.83%     31.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           266012583     23.25%     55.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           191391841     16.73%     71.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           151042401     13.20%     85.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            94875410      8.29%     93.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            46737983      4.09%     97.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            20365340      1.78%     99.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             8494546      0.74%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              866321      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1143904596                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1290623     11.43%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7282650     64.51%     75.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2716745     24.06%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass           2276794      0.12%      0.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1273262556     66.88%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            457990895     24.06%     91.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170169208      8.94%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1903699453                       # Type of FU issued
+system.cpu.iq.rate                           1.629814                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    11290018                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005931                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4963342528                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3124994935                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1860002555                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 148                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               6470                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           35                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1912712604                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      73                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        121974892                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    202791838                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       144755                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      2595349                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     73620402                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads         1258                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles              108564763                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 9612649                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1584002                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2327087967                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2265532                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             586893998                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            222780587                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               9768                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1061349                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 44764                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        2595349                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15395124                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2700605                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18095729                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1873365131                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             447946174                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          30334322                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                    613940816                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                173514694                       # Number of branches executed
+system.cpu.iew.exec_stores                  165994642                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.603844                       # Inst execution rate
+system.cpu.iew.wb_sent                     1866291041                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1860002590                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1434917653                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2113204026                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.592404                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.679025                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1528988756                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       798102573                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       795955462                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples   1035309655                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.476842                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.993609                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          16689612                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1035339833                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.476799                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.996303                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    433213212     41.84%     41.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    271303976     26.21%     68.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    102660477      9.92%     77.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    102477093      9.90%     87.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     38291141      3.70%     91.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     25044351      2.42%     93.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10787246      1.04%     95.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     10434520      1.01%     96.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     41097639      3.97%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    433023044     41.82%     41.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    272005097     26.27%     68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    102852786      9.93%     78.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    102343925      9.89%     87.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     37875553      3.66%     91.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24412247      2.36%     93.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10662009      1.03%     94.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10610565      1.02%     95.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     41554607      4.01%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1035309655                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1035339833                       # Number of insts commited each cycle
 system.cpu.commit.count                    1528988756                       # Number of instructions committed
-system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      533262345                       # Number of memory references committed
 system.cpu.commit.loads                     384102160                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.refs                      533262345                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.branches                  149758588                       # Number of branches committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              41554607                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   3320876555                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4762809697                       # The number of ROB writes
+system.cpu.timesIdled                          612261                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        24142235                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1528988756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1528988756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.764037                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.764037                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          323639192                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15916.826695                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8444.942006                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              320628262                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    47924451000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.009303                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              3010930                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits           1248670                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  14882183500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.005445                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1762260                       # number of ReadReq MSHR misses
+system.cpu.cpi                               0.763934                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.763934                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.309013                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.309013                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3113980511                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1735312737                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        35                       # number of floating regfile reads
+system.cpu.misc_regfile_reads              1026187894                       # number of misc regfile reads
+system.cpu.icache.replacements                   9719                       # number of replacements
+system.cpu.icache.tagsinuse                962.212052                       # Cycle average of tags in use
+system.cpu.icache.total_refs                188218304                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  11170                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               16850.340555                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            962.212052                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.469830                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              188225426                       # number of ReadReq hits
+system.cpu.icache.demand_hits               188225426                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              188225426                       # number of overall hits
+system.cpu.icache.ReadReq_misses               255393                       # number of ReadReq misses
+system.cpu.icache.demand_misses                255393                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses               255393                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     1672074500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      1672074500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     1672074500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          188480819                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           188480819                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          188480819                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.001355                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.001355                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.001355                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  6547.064720                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  6547.064720                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  6547.064720                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        6                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1431                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1431                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1431                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          253962                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           253962                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          253962                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    874487000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    874487000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    874487000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.001347                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.001347                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.001347                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  3443.377356                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  3443.377356                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  3443.377356                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2526689                       # number of replacements
+system.cpu.dcache.tagsinuse               4088.695138                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                470723878                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2530785                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 185.999158                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             2167120000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4088.695138                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.998217                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              321863634                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             147543808                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               469407442                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              469407442                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              3006802                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1616393                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               4623195                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              4623195                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    47968938500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   38293464500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     86262403000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    86262403000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          324870436                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 23726.182533                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18050.899847                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             147539972                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   38441849000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.010862                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1620229                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           607112                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency  18287673500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006792                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1013117                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 185.317160                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses           474030637                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          474030637                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.009255                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.010837                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.009753                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.009753                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 15953.474323                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23690.689393                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 18658.612280                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 18658.612280                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           472799393                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18648.960228                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11951.477943                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               468168234                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     86366300000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.009795                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               4631159                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1855782                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  33169857000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.005870                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          2775377                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4088.515779                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.998173                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          472799393                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18648.960228                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              468168234                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    86366300000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.009795                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              4631159                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1855782                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  33169857000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.005870                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         2775377                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  2229828                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           1247246                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           605486                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1852732                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1852732                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1759556                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1010907                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2770463                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2770463                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                2529347                       # number of replacements
-system.cpu.dcache.sampled_refs                2533443                       # Sample count of references to valid blocks.
+system.cpu.dcache.ReadReq_mshr_miss_latency  14841103500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  18213023500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  33054127000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  33054127000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.005416                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006777                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005844                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005844                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8434.572983                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18016.517345                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11930.903607                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11930.903607                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4088.515779                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                469490463                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             2268948000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  2231104                       # number of writebacks
-system.cpu.decode.BlockedCycles             187291575                       # Number of cycles decode is blocked
-system.cpu.decode.DecodedInsts             2489806075                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                422005844                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                 404270583                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles              108207267                       # Number of cycles decode is squashing
-system.cpu.decode.UnblockCycles              21741653                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                   252612908                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 188594062                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     440470513                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               3788635                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     1360923559                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                78504                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                19199509                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.216240                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          188594062                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          218742072                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.164971                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         1143516922                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.221243                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.208291                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                707206433     61.84%     61.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 32665502      2.86%     64.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 37223305      3.26%     67.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 33654778      2.94%     70.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 21116720      1.85%     72.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 40194771      3.52%     76.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 44517058      3.89%     80.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 36097891      3.16%     83.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                190840464     16.69%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1143516922                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        40                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses          188594062                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  6510.591789                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  3406.338578                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              188336504                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency     1676855000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.001366                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses               257558                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits              1428                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    872465500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.001358                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          256130                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               16890.533363                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           188594062                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  6510.591789                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  3406.338578                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               188336504                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency      1676855000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.001366                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                257558                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits               1428                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    872465500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.001358                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           256130                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            960.715295                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.469099                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          188594062                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  6510.591789                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  3406.338578                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              188336504                       # number of overall hits
-system.cpu.icache.overall_miss_latency     1676855000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.001366                       # miss rate for overall accesses
-system.cpu.icache.overall_misses               257558                       # number of overall misses
-system.cpu.icache.overall_mshr_hits              1428                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    872465500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.001358                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          256130                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   9707                       # number of replacements
-system.cpu.icache.sampled_refs                  11150                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                960.715295                       # Cycle average of tags in use
-system.cpu.icache.total_refs                188329447                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        6                       # number of writebacks
-system.cpu.idleCycles                        24687157                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts             18167511                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                173444431                       # Number of branches executed
-system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.602205                       # Inst execution rate
-system.cpu.iew.exec_refs                    612750445                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                  165978925                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                 9685611                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             586119276                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts               9659                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           2269927                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            223085364                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          2324941378                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             446771520                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          30325762                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            1871702722                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                1004270                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 42321                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles              108207267                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles               1500742                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads        122021898                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses       146459                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation      2443893                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads         1254                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads    202017116                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores     73925179                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents        2443893                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      2771097                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       15396414                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                2110704618                       # num instructions consuming a value
-system.cpu.iew.wb_count                    1858331416                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.678632                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                1432391344                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.590759                       # insts written-back per cycle
-system.cpu.iew.wb_sent                     1864643959                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads               3111234049                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1733847214                       # number of integer regfile writes
-system.cpu.ipc                               1.308837                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.308837                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass           2348064      0.12%      0.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1272739342     66.91%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            456676516     24.01%     91.05% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170264562      8.95%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1902028484                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                      77                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                 156                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           40                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes               7351                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                    11137895                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.005856                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1120921     10.06%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7318318     65.71%     75.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2698656     24.23%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses             1910818238                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         4959453857                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses   1858331376                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        3120531509                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                 2324931719                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                1902028484                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                9659                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       793159883                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            742228                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved           9106                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined   1353359987                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples    1143516922                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.663315                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.649679                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           363234856     31.76%     31.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           268152711     23.45%     55.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           190268701     16.64%     71.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           150184864     13.13%     84.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            96042571      8.40%     93.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            45507451      3.98%     97.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            20662852      1.81%     99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             8604200      0.75%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              858716      0.08%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1143516922                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.628165                       # Inst issue rate
-system.cpu.l2cache.ReadExReq_accesses          775816                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34258.394889                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.535640                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              528344                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   8477993500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.318983                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            247472                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   7672259500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.318983                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       247472                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1768657                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34159.791245                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.301453                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               1429599                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   11582150500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.191704                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              339058                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  10512595500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191704                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         339058                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         244851                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency    42.349749                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.844007                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_hits               1225                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_latency     10317500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate      0.994997                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           243626                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   7553342500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994997                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       243626                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         2231110                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             2231110                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  5.363240                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                574908                       # number of replacements
+system.cpu.l2cache.tagsinuse             21475.483997                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3187378                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                594034                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.365649                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          306954721000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          7759.424179                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13716.059817                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.236799                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.418581                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1427745                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             2229834                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits               1220                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits              528395                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                1956140                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               1956140                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              338148                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses           241457                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            247534                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               585682                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              585682                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   11551208500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency     10591500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   8481401000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    20032609500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   20032609500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1765893                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         2229834                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses         242677                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          775929                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2541822                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2541822                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.191488                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.994973                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.319016                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.230418                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.230418                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34160.215349                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency    43.864953                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.579953                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34203.901605                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34203.901605                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            2544473                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34201.394643                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.134486                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                1957943                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    20060144000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.230511                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               586530                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                  412029                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  18184855000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.230511                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          586530                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          7751.549385                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13703.522900                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.236559                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.418198                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses           2544473                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34201.394643                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.134486                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               1957943                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   20060144000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.230511                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              586530                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  18184855000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.230511                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         586530                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses         338148                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses       241457                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       247534                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          585682                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         585682                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                575744                       # number of replacements
-system.cpu.l2cache.sampled_refs                594863                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency  10484352000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency   7486160000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   7674186000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  18158538000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  18158538000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191488                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994973                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.319016                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.230418                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.230418                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.216651                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31004.112533                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.553185                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.090957                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.090957                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             21455.072285                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3190393                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          306991433000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  412280                       # number of writebacks
-system.cpu.memDep0.conflictingLoads         354716110                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        139191834                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            586119276                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           223082546                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads              1024751398                       # number of misc regfile reads
-system.cpu.numCycles                       1168204079                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                50725953                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents               53866080                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                461056510                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents              71664979                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                  8215                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups            5693696762                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts             2424853504                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands          2263021553                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                 385257729                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles              108207267                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles             138255029                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                835722526                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups             18042                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups       5693678720                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles          14434                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts               2322                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                 301380597                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts           2286                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   3319156234                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4758159890                       # The number of ROB writes
-system.cpu.timesIdled                          639156                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                  551                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index c56e8acb0fa1c2699424b91e347dfd3c7ba9b670..62ab94a46e0954055b4f3e97602f0a2f33af6a0d 100755 (executable)
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 14:39:34
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 19:29:23
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -19,4 +19,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.110000
-Exiting @ tick 117809491500 because target called exit()
+Exiting @ tick 117852123500 because target called exit()
index 520b82c48b16b8fec25e7a45361f237430f4a603..48dd388403b26ea2fd2f1ee9056dfa2e34b800f4 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 211489                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 270680                       # Number of bytes of host memory used
-host_seconds                                  1650.52                       # Real time elapsed on the host
-host_tick_rate                               71377158                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.117852                       # Number of seconds simulated
+sim_ticks                                117852123500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   349066263                       # Number of instructions simulated
-sim_seconds                                  0.117809                       # Number of seconds simulated
-sim_ticks                                117809491500                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 21062889                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              27322695                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect               72292                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            3475103                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           20805254                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 37744082                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  7419277                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts           3443737                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                   30521923                       # Number of branches committed
-system.cpu.commit.bw_lim_events              10435258                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts      349066875                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls         3555485                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        39704049                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples    228514950                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.527545                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.133009                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    102801955     44.99%     44.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     53028094     23.21%     68.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     21141032      9.25%     77.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     16471755      7.21%     84.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11485651      5.03%     89.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      6931925      3.03%     92.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3277801      1.43%     94.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2941479      1.29%     95.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10435258      4.57%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    228514950                       # Number of insts commited each cycle
-system.cpu.commit.count                     349066875                       # Number of instructions committed
-system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls              6225114                       # Number of function calls committed.
-system.cpu.commit.int_insts                 279586113                       # Number of committed integer instructions.
-system.cpu.commit.loads                      94649044                       # Number of loads committed
-system.cpu.commit.membars                       11033                       # Number of memory barriers committed
-system.cpu.commit.refs                      177024913                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                   349066263                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             349066263                       # Number of Instructions Simulated
-system.cpu.cpi                               0.674998                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.674998                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses        11411                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits            11409                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency        76000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000175                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses           96380397                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 33471.948212                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30902.675014                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               96377153                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency      108583000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000034                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                 3244                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits              1487                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency     54296000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000018                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses            1757                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses         11147                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits             11147                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          82052699                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32597.187038                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35454.657728                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              82033751                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     617651500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000231                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               18948                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits            16114                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency    100478500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           2834                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               38865.924635                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       288500                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           178433096                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32725.058580                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33712.589850                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               178410904                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       726234500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000124                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                 22192                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits              17601                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    154774500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000026                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4591                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           3098.465756                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.756461                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          178433096                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32725.058580                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33712.589850                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              178410904                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      726234500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000124                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                22192                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits             17601                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    154774500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4591                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                   1403                       # number of replacements
-system.cpu.dcache.sampled_refs                   4591                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3098.465756                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                178433460                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                     1024                       # number of writebacks
-system.cpu.decode.BlockedCycles              69331294                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                 73618                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved              7489475                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts              420268511                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                 84393046                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                  73199019                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles                6976526                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                216081                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles               1591590                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+host_inst_rate                                  49475                       # Simulator instruction rate (inst/s)
+host_tick_rate                               16703679                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264264                       # Number of bytes of host memory used
+host_seconds                                  7055.46                       # Real time elapsed on the host
+sim_insts                                   349066258                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    37744082                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  40002335                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      76861965                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                627285                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      328341754                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 3612258                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.160191                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           40002335                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           28482166                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.393528                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          235491475                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.819242                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.041438                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.numCycles                        235704248                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 37732885                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           20795463                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3471100                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              27302215                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 21001151                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  7420100                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               72463                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           39991725                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      328152707                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37732885                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           28421251                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      76800425                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3608252                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   12                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                  39991725                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                624732                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          235576888                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.817631                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.040837                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                159219706     67.61%     67.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  9262838      3.93%     71.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  5962224      2.53%     74.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6640011      2.82%     76.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  5459111      2.32%     79.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4841931      2.06%     81.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3740667      1.59%     82.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4101328      1.74%     84.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 36263659     15.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                159366483     67.65%     67.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  9270231      3.94%     71.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5914286      2.51%     74.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6643493      2.82%     76.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  5462624      2.32%     79.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4799627      2.04%     81.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3754754      1.59%     82.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4137731      1.76%     84.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 36227659     15.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            235491475                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                 189753142                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                134299135                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           40002335                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 11799.645611                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  8377.979424                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               39986251                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      189785500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000402                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                16084                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               435                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    131107000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000391                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           15649                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                2555.195284                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            40002335                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 11799.645611                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  8377.979424                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                39986251                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       189785500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000402                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 16084                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                435                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    131107000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000391                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            15649                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1826.046295                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.891624                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses           40002335                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 11799.645611                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  8377.979424                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               39986251                       # number of overall hits
-system.cpu.icache.overall_miss_latency      189785500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000402                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                16084                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               435                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    131107000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000391                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           15649                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  13784                       # number of replacements
-system.cpu.icache.sampled_refs                  15649                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1826.046295                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 39986251                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          127509                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts              3670203                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 31934668                       # Number of branches executed
-system.cpu.iew.exec_nop                         47192                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.564151                       # Inst execution rate
-system.cpu.iew.exec_refs                    185570349                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                   84541959                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                   10926                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             106791761                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            3802356                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           6858543                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             90029129                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           388774140                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             101028390                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           4246307                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             368543664                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                     71                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                   337                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                6976526                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                   499                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked           168                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads          4560961                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses        25223                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation       199743                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads          301                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads     12142716                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores      7653260                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         199743                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       359811                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        3310392                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                 317090964                       # num instructions consuming a value
-system.cpu.iew.wb_count                     365218926                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.522267                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                 165606023                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.550040                       # insts written-back per cycle
-system.cpu.iew.wb_sent                      366001659                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads               1759246608                       # number of integer regfile reads
-system.cpu.int_regfile_writes               232102222                       # number of integer regfile writes
-system.cpu.ipc                               1.481486                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.481486                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             126463418     33.92%     33.92% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2147037      0.58%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6836747      1.83%     36.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8624018      2.31%     38.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3527986      0.95%     39.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1580654      0.42%     40.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       21035747      5.64%     45.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7283008      1.95%     47.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7262175      1.95%     49.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            102247784     27.43%     77.04% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            85606108     22.96%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              372789971                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses               127821933                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads           249342196                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses    118185962                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes          133232335                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                    13475549                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.036148                       # FU busy rate (busy events/executed inst)
+system.cpu.fetch.rateDist::total            235576888                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.160086                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.392222                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 84492760                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              69387883                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  73181829                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1548924                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6965492                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              7488186                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 73175                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              420043685                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                215754                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6965492                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 90152933                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  976284                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       57875196                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  69216447                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10390536                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              409431138                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                  10006                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               5114847                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               42                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           449313195                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2409887049                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1322854173                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups        1087032876                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             384568949                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 64744241                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            3898927                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        3897858                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  35694607                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            106772052                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            90018438                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          11281294                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         21363407                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  384862513                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3813526                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 372770888                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1408906                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        37984896                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    125485450                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         258042                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     235576888                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.582375                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.822791                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            95699423     40.62%     40.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            48065676     20.40%     61.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            27569248     11.70%     72.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20762200      8.81%     81.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            21955543      9.32%     90.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12942689      5.49%     96.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5977724      2.54%     98.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1956925      0.83%     99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              647460      0.27%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       235576888                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                    2445      0.02%      0.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    2414      0.02%      0.02% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                   5043      0.04%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.06% # attempts to use FU when none available
@@ -353,170 +167,363 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.06% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd             11285      0.08%      0.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd             11301      0.09%      0.14% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp               187      0.00%      0.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt              1509      0.01%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp               197      0.00%      0.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt              1510      0.01%      0.15% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      0.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           142639      1.06%      1.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult             1245      0.01%      1.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        303363      2.25%      3.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7221179     53.59%     57.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               5786651     42.94%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           142649      1.07%      1.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult             1224      0.01%      1.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        303363      2.28%      3.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7115466     53.58%     57.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               5697057     42.90%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses              258443587                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          746613752                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    247032964                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         293633638                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  384913340                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 372789971                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             3813608                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        38043864                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued           1408982                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved         258123                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    125676657                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples     235491475                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.583030                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.821450                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            95677321     40.63%     40.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            47888075     20.34%     60.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            27520727     11.69%     72.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20838545      8.85%     81.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            22281426      9.46%     90.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12633898      5.36%     96.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             6146913      2.61%     98.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1868425      0.79%     99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              636145      0.27%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       235491475                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.582173                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses            2834                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34401.668442                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31268.903088                       # average ReadExReq mshr miss latency
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             126467737     33.93%     33.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2147032      0.58%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    2      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6836061      1.83%     36.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8620472      2.31%     38.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3526603      0.95%     39.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1580695      0.42%     40.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       21030277      5.64%     45.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7283358      1.95%     47.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7262499      1.95%     49.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            102234129     27.43%     77.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            85606734     22.96%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              372770888                       # Type of FU issued
+system.cpu.iq.rate                           1.581520                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    13280227                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.035626                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          746488455                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         293551634                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    247041034                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           249319342                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          133204458                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    118172579                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              258240891                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               127810224                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4605348                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     12123008                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        25231                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       199737                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7642570                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads          301                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           168                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                6965492                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   10869                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   480                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           388723243                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6854795                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             106772052                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             90018438                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            3802280                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     54                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   341                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         199737                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3305937                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       361135                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3667072                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             368528754                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             101011008                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           4242134                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         47204                       # number of nop insts executed
+system.cpu.iew.exec_refs                    185554303                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31933479                       # Number of branches executed
+system.cpu.iew.exec_stores                   84543295                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.563522                       # Inst execution rate
+system.cpu.iew.wb_sent                      365991200                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     365213613                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 165367337                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 317313225                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.549457                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.521149                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      349066870                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        39653224                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         3555484                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           3440231                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    228611397                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.526901                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.127678                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    102653839     44.90%     44.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     52967573     23.17%     68.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     21494828      9.40%     77.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     16426131      7.19%     84.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11610822      5.08%     89.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      6946497      3.04%     92.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3261718      1.43%     94.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2914745      1.27%     95.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10335244      4.52%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    228611397                       # Number of insts commited each cycle
+system.cpu.commit.count                     349066870                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      177024911                       # Number of memory references committed
+system.cpu.commit.loads                      94649043                       # Number of loads committed
+system.cpu.commit.membars                       11033                       # Number of memory barriers committed
+system.cpu.commit.branches                   30521922                       # Number of branches committed
+system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 279586109                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              6225114                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              10335244                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    606993724                       # The number of ROB reads
+system.cpu.rob.rob_writes                   784416922                       # The number of ROB writes
+system.cpu.timesIdled                            2785                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          127360                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   349066258                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             349066258                       # Number of Instructions Simulated
+system.cpu.cpi                               0.675242                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.675242                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.480950                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.480950                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1759160975                       # number of integer regfile reads
+system.cpu.int_regfile_writes               232094825                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 189729002                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                134274190                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               986066945                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               34422257                       # number of misc regfile writes
+system.cpu.icache.replacements                  13781                       # number of replacements
+system.cpu.icache.tagsinuse               1824.800983                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 39975644                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  15643                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                2555.497283                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1824.800983                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.891016                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               39975644                       # number of ReadReq hits
+system.cpu.icache.demand_hits                39975644                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               39975644                       # number of overall hits
+system.cpu.icache.ReadReq_misses                16081                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 16081                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                16081                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      189840000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       189840000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      189840000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           39991725                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            39991725                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           39991725                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000402                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000402                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000402                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 11805.235993                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 11805.235993                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 11805.235993                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               435                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                435                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               435                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           15646                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            15646                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           15646                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    131146500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    131146500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    131146500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000391                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000391                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000391                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  8382.110444                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  8382.110444                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  8382.110444                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                   1396                       # number of replacements
+system.cpu.dcache.tagsinuse               3097.520126                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                178371323                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4582                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               38928.704278                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3097.520126                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.756230                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               96315033                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              82033723                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            11410                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             11146                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               178348756                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              178348756                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 3256                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               18976                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses                 22232                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                22232                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency      108888000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     618616000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        76000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency       727504000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      727504000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           96318289                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          82052699                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        11412                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         11146                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           178370988                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          178370988                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000034                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000231                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000175                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.000125                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000125                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 33442.260442                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 32599.915683                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 32723.281756                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 32723.281756                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       288500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                     1019                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              1507                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits            16140                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits              17647                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits             17647                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses            1749                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           2836                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4585                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4585                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     54106000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    100544000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    154650000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    154650000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000018                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000026                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000026                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30935.391652                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35452.750353                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33729.552890                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33729.552890                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                    54                       # number of replacements
+system.cpu.l2cache.tagsinuse              3793.062863                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13102                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  5236                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.502292                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          3424.878969                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           368.183894                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.104519                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011236                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 13017                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                1019                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                  17                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency     96909500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.994001                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              2817                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     88084500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994001                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         2817                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             17406                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34339.881224                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31154.877485                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 13028                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     150340000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.251522                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                4378                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               52                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency    134776000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.248535                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           4326                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses            1024                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                1024                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.500763                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.demand_hits                  13034                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 13034                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4374                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                3                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses              2816                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 7190                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                7190                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     150210000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     96886500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      247096500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     247096500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             17391                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses            1019                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses              3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            2833                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              20224                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             20224                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.251509                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.993999                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.355518                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.355518                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34341.563786                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.717330                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34366.689847                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34366.689847                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses              20240                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34364.072272                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31199.846003                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  13045                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      247249500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.355484                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 7195                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                52                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    222860500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.352915                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            7143                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          3426.953059                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           371.809740                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.104582                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.011347                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses             20240                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34364.072272                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31199.846003                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 13045                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     247249500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.355484                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                7195                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               52                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    222860500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.352915                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           7143                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               51                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                51                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               51                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           4323                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            3                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         2816                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            7139                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           7139                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                    53                       # number of replacements
-system.cpu.l2cache.sampled_refs                  5244                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency    134686000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        93000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     88056000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    222742000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    222742000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.248577                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.993999                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.352996                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.352996                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31155.678927                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.886364                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31200.728393                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31200.728393                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3798.762799                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   13114                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          11716702                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         21387957                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            106791761                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            90029129                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               986366370                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               34422259                       # number of misc regfile writes
-system.cpu.numCycles                        235618984                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                 1027175                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps             384568957                       # Number of HB maps that are committed
-system.cpu.rename.FullRegisterEvents               42                       # Number of times there has been no free registers
-system.cpu.rename.IQFullEvents                  10287                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                 90102617                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents               5005619                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenameLookups            2410888164                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts              409625398                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands           449508319                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                  69271276                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles                6976526                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles              10236681                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                 64939357                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups        1087176407                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups       1323711757                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles       57877200                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts            3899205                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  35615164                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts        3898099                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    606848093                       # The number of ROB reads
-system.cpu.rob.rob_writes                   784529626                       # The number of ROB writes
-system.cpu.timesIdled                            2791                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                  191                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 40b1b56a093eb7b6fa2aea0552ea5847f9bf73de..bf375000bfb8f2af97c4c73ce95d180695c48b9e 100755 (executable)
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 14:08:54
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 15:11:57
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1391,4 +1391,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 796501458500 because target called exit()
+Exiting @ tick 795626752000 because target called exit()
index 1bd5ced795208891d3e12819422e1937ee60ff4b..ce16cf8d2700af8b720e7fb3e02053f9ac73e529 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 152621                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 267940                       # Number of bytes of host memory used
-host_seconds                                 12353.14                       # Real time elapsed on the host
-host_tick_rate                               64477641                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.795627                       # Number of seconds simulated
+sim_ticks                                795626752000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1885343121                       # Number of instructions simulated
-sim_seconds                                  0.796501                       # Number of seconds simulated
-sim_ticks                                796501458500                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                295401459                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             412226769                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect             2841374                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           40219938                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          399767362                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                521351365                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                 53524846                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts          45744525                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                  291352099                       # Number of branches committed
-system.cpu.commit.bw_lim_events              67684151                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts     1885354137                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          211786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts      1014250107                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples   1409452320                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.337650                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.030019                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    650998601     46.19%     46.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    389487426     27.63%     73.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    134882374      9.57%     83.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     70608044      5.01%     88.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     45598376      3.24%     91.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     18595515      1.32%     92.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     23751287      1.69%     94.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      7846546      0.56%     95.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     67684151      4.80%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1409452320                       # Number of insts commited each cycle
-system.cpu.commit.count                    1885354137                       # Number of instructions committed
-system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
-system.cpu.commit.int_insts                1653713091                       # Number of committed integer instructions.
-system.cpu.commit.loads                     631390736                       # Number of loads committed
-system.cpu.commit.membars                        9986                       # Number of memory barriers committed
-system.cpu.commit.refs                      908389587                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                  1885343121                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1885343121                       # Number of Instructions Simulated
-system.cpu.cpi                               0.844941                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.844941                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses        16769                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits            16766                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency       108500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000179                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses          708570219                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34295.515999                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34092.262926                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              706637503                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    66283492500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.002728                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1932716                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            469902                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  49870639500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002064                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1462814                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses         13539                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits             13539                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35038.454246                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32465.652371                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             276128758                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   28273229500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.002914                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              806920                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           734193                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   2361129500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          72727                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        15250                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 640.035711                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        61000                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           985505897                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34514.337671                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34015.222648                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               982766261                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     94556722000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002780                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2739636                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1204095                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  52231769000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.001558                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1535541                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4094.850284                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999719                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          985505897                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34514.337671                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34015.222648                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              982766261                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    94556722000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002780                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2739636                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1204095                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  52231769000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.001558                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1535541                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1531438                       # number of replacements
-system.cpu.dcache.sampled_refs                1535534                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.850284                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                982796595                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              325357000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   107000                       # number of writebacks
-system.cpu.decode.BlockedCycles              41214762                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                 11076                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved             76817010                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts             3347910149                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                727407671                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                 639439291                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles              146381913                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                 20384                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles               1390594                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+host_inst_rate                                  37469                       # Simulator instruction rate (inst/s)
+host_tick_rate                               15812352                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261444                       # Number of bytes of host memory used
+host_seconds                                 50316.79                       # Real time elapsed on the host
+sim_insts                                  1885343131                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                   521351365                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 363393229                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     657902932                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes              20866192                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     2539704301                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                  165                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                47134046                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.327276                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          363393229                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          348926305                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.594287                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         1555834231                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.199016                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.044014                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
+system.cpu.numCycles                       1591253505                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                519677239                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          398144928                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           40174420                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             410482703                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                293585496                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 53540823                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect             2841317                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          361951635                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2537428028                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   519677239                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          347126319                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     659124412                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                47088491                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  166                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                 361951635                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              20842559                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1554259692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.199934                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.044955                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                897966873     57.72%     57.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 37681413      2.42%     60.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                106074065      6.82%     66.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 61536348      3.96%     70.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 89725743      5.77%     76.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 53094530      3.41%     80.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 35033115      2.25%     82.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 45486191      2.92%     85.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                229235953     14.73%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                895170810     57.59%     57.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 41935957      2.70%     60.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                103275417      6.64%     66.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 61539532      3.96%     70.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 89553793      5.76%     76.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 52982183      3.41%     80.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 34961510      2.25%     82.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 45455804      2.92%     85.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                229384686     14.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1555834231                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                  69468816                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 51556158                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses          363393229                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  9064.622402                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  5743.022314                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              363365607                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      250383000                       # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total           1554259692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.326584                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.594610                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                723197107                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              41283634                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 642007597                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1402750                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              146368604                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             76799900                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11033                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3347346347                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 20349                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              146368604                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                756568519                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                25444222                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        3271742                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 608636712                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13969893                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3194137589                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    23                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                3931047                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               7404635                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          3358259430                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           15045243779                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      14391074287                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         654169492                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1993168551                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps               1365090874                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             254462                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         254764                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  34849726                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            925173948                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           465395627                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          97302082                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        144361448                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2889677990                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              244825                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2448298992                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          12457526                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       987757973                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   2669097969                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          33037                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1554259692                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.575219                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.653577                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           571543598     36.77%     36.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           302403348     19.46%     56.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           272921305     17.56%     73.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           170079995     10.94%     84.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           141872535      9.13%     93.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            62133878      4.00%     97.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            24302902      1.56%     99.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6180941      0.40%     99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2821190      0.18%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1554259692                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    5100      0.01%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  23970      0.03%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               52395536     69.00%     69.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              23506568     30.96%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1194651657     48.80%     48.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult             11220052      0.46%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                 8628      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     49.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     49.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     49.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         6876474      0.28%     49.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         6176938      0.25%     49.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     49.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       25435651      1.04%     50.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     50.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     50.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            792339955     32.36%     83.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           410214348     16.76%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             2448298992                       # Type of FU issued
+system.cpu.iq.rate                           1.538598                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    75931174                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.031014                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6412694569                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3775928903                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2259827011                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           126551807                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          103128995                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     57766877                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2458203699                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                66026467                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         38019387                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    293783209                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses      1377644                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      2672008                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    188396774                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads           94                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            24                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles              146368604                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                17402025                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3966817                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2889988302                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           9053008                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             925173948                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            465395627                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             232022                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                2656731                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   304                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        2672008                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       37424548                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     12425696                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             49850244                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2354181989                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             757207603                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          94117003                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         65487                       # number of nop insts executed
+system.cpu.iew.exec_refs                   1128829223                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                348669519                       # Number of branches executed
+system.cpu.iew.exec_stores                  371621620                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.479451                       # Inst execution rate
+system.cpu.iew.wb_sent                     2328619665                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2317593888                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1309821619                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2336262105                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.456458                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.560648                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1885354147                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts      1004600706                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          211788                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          45699022                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1407891090                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.339134                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.034210                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    652274208     46.33%     46.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    388083214     27.56%     73.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    132034153      9.38%     83.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     69283607      4.92%     88.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     48326626      3.43%     91.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     18528976      1.32%     92.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     23779079      1.69%     94.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      7923868      0.56%     95.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     67657359      4.81%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1407891090                       # Number of insts commited each cycle
+system.cpu.commit.count                    1885354147                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      908389591                       # Number of memory references committed
+system.cpu.commit.loads                     631390738                       # Number of loads committed
+system.cpu.commit.membars                        9986                       # Number of memory barriers committed
+system.cpu.commit.branches                  291352101                       # Number of branches committed
+system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1653713099                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              67657359                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   4230170239                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5926292122                       # The number of ROB writes
+system.cpu.timesIdled                         1344848                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        36993813                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1885343131                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1885343131                       # Number of Instructions Simulated
+system.cpu.cpi                               0.844013                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.844013                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.184816                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.184816                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads              11587728749                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2306495167                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  69468418                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 51554923                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              3827336094                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               13780014                       # number of misc regfile writes
+system.cpu.icache.replacements                  25559                       # number of replacements
+system.cpu.icache.tagsinuse               1546.566470                       # Cycle average of tags in use
+system.cpu.icache.total_refs                361924025                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  27145                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               13332.990422                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1546.566470                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.755159                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              361924028                       # number of ReadReq hits
+system.cpu.icache.demand_hits               361924028                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              361924028                       # number of overall hits
+system.cpu.icache.ReadReq_misses                27607                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 27607                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                27607                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      250013500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       250013500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      250013500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          361951635                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           361951635                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          361951635                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000076                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                27622                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               464                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    155969000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000075                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           27158                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               13383.138890                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate           0.000076                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000076                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  9056.163292                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  9056.163292                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  9056.163292                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           363393229                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  9064.622402                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  5743.022314                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               363365607                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       250383000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000076                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 27622                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                464                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    155969000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               455                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                455                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               455                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           27152                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            27152                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           27152                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    155884000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    155884000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    155884000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000075                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000075                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            27158                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1549.568849                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.756625                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          363393229                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  9064.622402                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  5743.022314                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              363365607                       # number of overall hits
-system.cpu.icache.overall_miss_latency      250383000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000076                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                27622                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               464                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    155969000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000075                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           27158                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  25561                       # number of replacements
-system.cpu.icache.sampled_refs                  27151                       # Sample count of references to valid blocks.
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  5741.160872                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  5741.160872                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  5741.160872                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1549.568849                       # Cycle average of tags in use
-system.cpu.icache.total_refs                363365604                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                        37168687                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts             49895765                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                348756775                       # Number of branches executed
-system.cpu.iew.exec_nop                         65493                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.479521                       # Inst execution rate
-system.cpu.iew.exec_refs                   1131335426                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                  371509885                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                17394060                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             927609743                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts             231433                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           9066267                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            465231191                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          2899637757                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             759825541                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          94064084                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            2356880983                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                2638032                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                   300                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles              146381913                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles               3942741                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads         37882384                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses      1377639                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation      2658197                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads           94                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads    296219006                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores    188232340                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents        2658197                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect     12410188                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       37485577                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                2331728093                       # num instructions consuming a value
-system.cpu.iew.wb_count                    2317489911                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.562854                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                1312422376                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.454793                       # insts written-back per cycle
-system.cpu.iew.wb_sent                     2328575568                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads              11595279326                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2306970978                       # number of integer regfile writes
-system.cpu.ipc                               1.183515                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.183515                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1196267709     48.81%     48.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult             11218358      0.46%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                 8628      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     49.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     49.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     49.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         6876474      0.28%     49.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         6177350      0.25%     49.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     49.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       25435994      1.04%     50.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     50.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     50.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            793496500     32.38%     83.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           410088765     16.73%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2450945067                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                66027207                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads           126553287                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses     57767686                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes          103061655                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                    75909773                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.030972                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   12391      0.02%      0.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  23967      0.03%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               52380943     69.00%     69.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              23492472     30.95%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses             2460827633                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         6419542643                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses   2259722225                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        3795271933                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                 2899328074                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                2450945067                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded              244190                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       997384206                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued          12461792                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved          32404                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined   2708929658                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples    1555834231                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.575325                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.655347                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           573245192     36.84%     36.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           302098178     19.42%     56.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           270294423     17.37%     73.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           171510640     11.02%     84.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           147471533      9.48%     94.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            56656397      3.64%     97.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            24168420      1.55%     99.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             7568098      0.49%     99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2821350      0.18%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1555834231                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.538569                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses           72720                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.683474                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.187900                       # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1531405                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.850466                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                980041629                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1535501                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 638.255285                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              325046000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.850466                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999719                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              703882480                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             276128743                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            16835                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             13541                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               980011223                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              980011223                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1932681                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              806935                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               2739616                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2739616                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    66544329000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   28306423000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       108500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     94850752000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    94850752000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          705815161                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        16838                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         13541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           982750839                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          982750839                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002738                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.002914                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000178                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.002788                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002788                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 34431.098045                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 35078.938204                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 34621.914896                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 34621.914896                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        59500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        14875                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   107019                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            469901                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           734207                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1204108                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1204108                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1462780                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          72728                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1535508                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1535508                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  49902321500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2361229000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  52263550500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  52263550500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002072                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.001562                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001562                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34114.714106                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32466.574084                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34036.651388                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34036.651388                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               1479610                       # number of replacements
+system.cpu.l2cache.tagsinuse             31966.303160                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   83557                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1512330                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.055251                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         28970.488218                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          2995.814942                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.884109                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.091425                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 75230                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              107019                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits                  2                       # number of UpgradeReq hits
 system.cpu.l2cache.ReadExReq_hits                6637                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   2279776500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.908732                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             66083                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048651500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908732                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        66083                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1489965                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34238.898726                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.364741                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 75240                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   48438626000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.949502                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1414725                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               21                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency  43856340000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.949488                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1414704                       # number of ReadReq MSHR misses
+system.cpu.l2cache.demand_hits                  81867                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 81867                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1414695                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                5                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses             66084                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              1480779                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             1480779                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   48470185000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2279814000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    50749999000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   50749999000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1489925                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          107019                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses              7                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_hits                  2                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_accesses           72721                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1562646                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1562646                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.949508                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate      0.714286                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses                5                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       155000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.714286                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          107000                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              107000                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.055254                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate       0.908733                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.947610                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.947610                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34261.932784                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.728891                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34272.500488                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34272.500488                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1562685                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34250.491961                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.401476                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  81877                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    50718402500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.947605                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1480808                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  45904991500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.947591                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1480787                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0         28973.685280                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          2993.152409                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.884207                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.091344                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses           1562685                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34250.491961                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.401476                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 81877                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   50718402500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.947605                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1480808                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  45904991500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.947591                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1480787                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   66099                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               23                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                23                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               23                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1414672                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            5                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        66084                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1480756                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        1480756                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               1479625                       # number of replacements
-system.cpu.l2cache.sampled_refs               1512345                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency  43855333500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       155000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048687000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  45904020500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  45904020500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.949492                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.714286                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908733                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.947595                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.947595                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.354499                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.255977                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.394731                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.394731                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             31966.837689                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   83563                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   66099                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          97040035                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        144361648                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            927609743                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           465231191                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads              3829379582                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               13780010                       # number of misc regfile writes
-system.cpu.numCycles                       1593002918                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                25386531                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps            1993168535                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents                3907408                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                760805018                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents               7406697                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                    22                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups           15047193383                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts             3194680592                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands          3359704809                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                 606032208                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles              146381913                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles              13958692                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps               1366536269                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups         653924872                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups      14393268511                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles        3269869                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts             253997                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  34813344                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts         254310                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   4241354068                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5945603467                       # The number of ROB writes
-system.cpu.timesIdled                         1344843                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                 1411                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index f10c82a79b33cc56f433858e4611ae2a21885137..8322d7ab6d239e46d10b1f556b6a9981ec76dcf6 100755 (executable)
@@ -7,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 15:24:46
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 15:12:09
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 36353754500 because target called exit()
+Exiting @ tick 36348210000 because target called exit()
index cef2ea6daf9cd93d62bf6b023b2c4344d03ac77b..d8be316308e36d6a80e158a9589282a7324a6bf0 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 214709                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 270620                       # Number of bytes of host memory used
-host_seconds                                   468.69                       # Real time elapsed on the host
-host_tick_rate                               77563856                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.036348                       # Number of seconds simulated
+sim_ticks                                 36348210000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   100633040                       # Number of instructions simulated
-sim_seconds                                  0.036354                       # Number of seconds simulated
-sim_ticks                                 36353754500                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                  9550734                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              14928040                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect              176432                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect             851746                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           11455775                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 17580538                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  1841093                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts            821012                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                   13669859                       # Number of branches committed
-system.cpu.commit.bw_lim_events               3808519                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts      100638592                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          700861                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        11103325                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples     69924626                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.439244                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.122917                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     31252926     44.70%     44.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     20119479     28.77%     73.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4663386      6.67%     80.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4133493      5.91%     86.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3064979      4.38%     90.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1713503      2.45%     92.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       682108      0.98%     93.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       486233      0.70%     94.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3808519      5.45%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     69924626                       # Number of insts commited each cycle
-system.cpu.commit.count                     100638592                       # Number of instructions committed
-system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
-system.cpu.commit.int_insts                  91477711                       # Number of committed integer instructions.
-system.cpu.commit.loads                      27308340                       # Number of loads committed
-system.cpu.commit.membars                       15920                       # Number of memory barriers committed
-system.cpu.commit.refs                       47865309                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                   100633040                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             100633040                       # Number of Instructions Simulated
-system.cpu.cpi                               0.722501                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.722501                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses        18710                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 13233.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits            18680                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency       397000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.001603                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses             30                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits           30                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses           26887551                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 22428.849743                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18951.207188                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               26783609                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     2331299500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.003866                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               103942                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits             49518                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1031400500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses           54424                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses         17150                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits             17150                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32635.826769                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34153.814138                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              18303641                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   50463473500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.077898                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1546260                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1439342                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   3651657500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005386                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         106918                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        18500                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 279.697951                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               9                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       166500                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            46737452                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 31992.915413                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 29025.659779                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                45087250                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     52794773000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.035308                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1650202                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            1488860                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   4683058000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.003452                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           161342                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4074.742226                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.994810                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses           46737452                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 31992.915413                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 29025.659779                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               45087250                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    52794773000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.035308                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1650202                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           1488860                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   4683058000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.003452                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          161342                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 157232                       # number of replacements
-system.cpu.dcache.sampled_refs                 161328                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4074.742226                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 45123111                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              314584000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   123248                       # number of writebacks
-system.cpu.decode.BlockedCycles              22792287                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                 94517                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved              3532335                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts              118494504                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                 25168271                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                  21456388                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles                1835527                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                324840                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles                507679                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+host_inst_rate                                  54516                       # Simulator instruction rate (inst/s)
+host_tick_rate                               19691005                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264076                       # Number of bytes of host memory used
+host_seconds                                  1845.93                       # Real time elapsed on the host
+sim_insts                                   100633035                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    17580538                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  11694526                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      22441550                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                172369                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                       87382256                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                   56                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                  923972                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.241798                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           11694526                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           11391827                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.201833                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples           71760152                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.691303                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.918883                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.numCycles                         72696421                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 17573172                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           11453458                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             851549                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              14915035                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  9554942                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  1842823                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              176515                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           11675232                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       87296891                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17573172                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11397765                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22503406                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  923751                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   51                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                  11675232                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                177839                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           71670018                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.692121                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.915842                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 49333953     68.75%     68.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2332887      3.25%     72.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2565274      3.57%     75.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2261875      3.15%     78.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1646575      2.29%     81.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1680171      2.34%     83.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   992700      1.38%     84.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1397961      1.95%     86.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9548756     13.31%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 49181996     68.62%     68.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2373056      3.31%     71.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2569214      3.58%     75.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2298620      3.21%     78.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1644656      2.29%     81.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1723119      2.40%     83.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   990721      1.38%     84.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1380652      1.93%     86.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9507984     13.27%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             71760152                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                       101                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       77                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           11694526                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 12656.148341                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  9158.013544                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               11668397                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      330692500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.002234                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                26129                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               878                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    231249000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.002159                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           25251                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                 462.334456                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.fetch.rateDist::total             71670018                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.241734                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.200842                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 25114154                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              22709447                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  21527142                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                497633                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1821642                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3527413                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 94287                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              118399354                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                324192                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1821642                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 26632137                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2439992                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       16812666                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20410601                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3552980                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              115899857                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                  27143                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2453549                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           118034319                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             532748209                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        532647632                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            100577                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              99142525                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 18891789                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             756618                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         756606                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  10359843                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29552116                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            22027852                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          13146932                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         13132796                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  110916590                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              749122                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 106735970                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            111004                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        10702418                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     27336640                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          48262                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      71670018                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.489269                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.647816                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            26697633     37.25%     37.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17182939     23.98%     61.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10552290     14.72%     75.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7611894     10.62%     86.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5202284      7.26%     93.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2658918      3.71%     97.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1053563      1.47%     99.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              496311      0.69%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              214186      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        71670018                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   81861      4.61%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1408075     79.27%     83.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                286311     16.12%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              56941286     53.35%     53.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                86568      0.08%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  21      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    2      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     53.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             28575402     26.77%     80.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21132684     19.80%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              106735970                       # Type of FU issued
+system.cpu.iq.rate                           1.468242                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1776247                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016642                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          287029038                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         122376660                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    105058655                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 171                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                178                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           74                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              108512130                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      87                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1096048                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads      2243776                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2146                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         9239                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1470884                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads           41                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            45                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                1821642                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  971169                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 52846                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           111742721                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            886869                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29552116                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             22027852                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             732058                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3681                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  5880                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           9239                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         680356                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       238968                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               919324                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             105624762                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              28223458                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1111208                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         77009                       # number of nop insts executed
+system.cpu.iew.exec_refs                     49234670                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14652571                       # Number of branches executed
+system.cpu.iew.exec_stores                   21011212                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.452957                       # Inst execution rate
+system.cpu.iew.wb_sent                      105223313                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     105058729                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  51964381                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  99748825                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.445171                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.520952                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      100638587                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        11026953                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          700860                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            821298                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     69848377                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.440815                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.128695                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     31252601     44.74%     44.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     20067748     28.73%     73.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4700774      6.73%     80.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4062261      5.82%     86.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3060219      4.38%     90.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1682719      2.41%     92.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       680213      0.97%     93.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       487977      0.70%     94.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3853865      5.52%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     69848377                       # Number of insts commited each cycle
+system.cpu.commit.count                     100638587                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       47865307                       # Number of memory references committed
+system.cpu.commit.loads                      27308339                       # Number of loads committed
+system.cpu.commit.membars                       15920                       # Number of memory barriers committed
+system.cpu.commit.branches                   13669858                       # Number of branches committed
+system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  91477707                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               3853865                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    177634753                       # The number of ROB reads
+system.cpu.rob.rob_writes                   225156428                       # The number of ROB writes
+system.cpu.timesIdled                           61363                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1026403                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   100633035                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             100633035                       # Number of Instructions Simulated
+system.cpu.cpi                               0.722391                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.722391                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.384291                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.384291                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                508078422                       # number of integer regfile reads
+system.cpu.int_regfile_writes               103555080                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       153                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      125                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               144338885                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  34300                       # number of misc regfile writes
+system.cpu.icache.replacements                  23105                       # number of replacements
+system.cpu.icache.tagsinuse               1790.585512                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 11649212                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  25136                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 463.447327                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1790.585512                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.874309                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               11649212                       # number of ReadReq hits
+system.cpu.icache.demand_hits                11649212                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               11649212                       # number of overall hits
+system.cpu.icache.ReadReq_misses                26020                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 26020                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                26020                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      329928500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       329928500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      329928500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           11675232                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            11675232                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           11675232                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.002229                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.002229                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.002229                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 12679.803997                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 12679.803997                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 12679.803997                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            11694526                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 12656.148341                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  9158.013544                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                11668397                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       330692500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.002234                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 26129                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                878                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    231249000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.002159                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            25251                       # number of demand (read+write) MSHR misses
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1791.221082                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.874620                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses           11694526                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 12656.148341                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  9158.013544                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               11668397                       # number of overall hits
-system.cpu.icache.overall_miss_latency      330692500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.002234                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                26129                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               878                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    231249000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.002159                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           25251                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               875                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                875                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               875                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           25145                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            25145                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           25145                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  23207                       # number of replacements
-system.cpu.icache.sampled_refs                  25238                       # Sample count of references to valid blocks.
+system.cpu.icache.ReadReq_mshr_miss_latency    230769000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    230769000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    230769000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.002154                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.002154                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.002154                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  9177.530324                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  9177.530324                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  9177.530324                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1791.221082                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 11668397                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          947358                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts               921550                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 14656801                       # Number of branches executed
-system.cpu.iew.exec_nop                         77012                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.452788                       # Inst execution rate
-system.cpu.iew.exec_refs                     49215024                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                   21014437                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                 1008310                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              29564246                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts             729945                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            860230                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             22056705                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           111818970                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              28200587                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1136003                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             105628608                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                   3950                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  5079                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                1835527                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 47240                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked            45                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads          1083799                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses         2228                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation         9171                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads           42                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads      2255905                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores      1499736                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents           9171                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       239261                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect         682289                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                  99911986                       # num instructions consuming a value
-system.cpu.iew.wb_count                     105081633                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.522057                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                  52159787                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.445265                       # insts written-back per cycle
-system.cpu.iew.wb_sent                      105241173                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads                508070420                       # number of integer regfile reads
-system.cpu.int_regfile_writes               103566970                       # number of integer regfile writes
-system.cpu.ipc                               1.384080                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.384080                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              56975144     53.37%     53.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                86496      0.08%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  11      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    3      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     53.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             28559455     26.75%     80.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21143495     19.80%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              106764611                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                      78                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                 153                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           67                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                132                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     1795216                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.016815                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   87233      4.86%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1425196     79.39%     84.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                282787     15.75%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses              108559749                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          287203483                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    105081566                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         122521154                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  110994950                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 106764611                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded              747008                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        10770592                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            119046                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved          46147                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     27581574                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples      71760152                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.487798                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.647275                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            26733734     37.25%     37.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17263615     24.06%     61.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10576325     14.74%     76.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7516482     10.47%     86.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5241170      7.30%     93.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2631549      3.67%     97.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1101075      1.53%     99.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              499591      0.70%     99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              196611      0.27%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        71760152                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.468412                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          106906                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34397.046928                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31243.735685                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                4301                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   3529309000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.959768                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            102605                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   3205763500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.959768                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       102605                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             79657                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34365.671873                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.753936                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 47389                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1108911500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.405087                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               32268                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               65                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1001763000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.404271                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          32203                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             13                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 157197                       # number of replacements
+system.cpu.dcache.tagsinuse               4074.737833                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 45133660                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 161293                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 279.824047                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              314597000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4074.737833                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994809                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               26793039                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              18304159                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            19298                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             17149                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                45097198                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               45097198                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               104208                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1545742                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses             31                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               1649950                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1649950                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     2387617500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   50445288500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       403500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     52832906000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    52832906000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           26897247                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        19329                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         17149                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            46747148                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           46747148                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.003874                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.077872                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.001604                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.035295                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.035295                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 22912.036504                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 32634.998920                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 13016.129032                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 32020.913361                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 32020.913361                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       170000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               9                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 18888.888889                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                   123219                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             49816                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1438831                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits           31                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1488647                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1488647                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           54392                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         106911                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           161303                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          161303                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   1030956000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3651524500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4682480500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4682480500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002022                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005386                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.003451                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.003451                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18954.184439                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34154.806334                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 29029.097413                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 29029.097413                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                114546                       # number of replacements
+system.cpu.l2cache.tagsinuse             18280.291791                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   68908                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                133392                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.516583                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2302.452210                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15977.839581                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.070265                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.487605                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 47261                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              123219                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits                  5                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_rate      0.615385                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses                8                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       248000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.615385                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            8                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          123248                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              123248                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.517741                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_hits                4298                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  51559                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 51559                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32262                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                4                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            102605                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               134867                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              134867                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1107753000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency        34000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3528908000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4636661000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4636661000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             79523                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          123219                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses              9                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          106903                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             186426                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            186426                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.405694                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.444444                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.959795                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.723434                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.723434                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34336.153989                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency         8500                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34393.138736                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34379.507218                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34379.507218                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             186563                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34389.540531                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.252300                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  51690                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     4638220500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.722935                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               134873                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                65                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   4207526500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.722587                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          134808                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          2299.680524                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15982.000784                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.070181                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.487732                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses            186563                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34389.540531                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.252300                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 51690                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    4638220500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.722935                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              134873                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits               65                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   4207526500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.722587                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         134808                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                   88455                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               63                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                63                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               63                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses          32199                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       102605                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          134804                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         134804                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                114549                       # number of replacements
-system.cpu.l2cache.sampled_refs                133395                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1001736500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       124000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   3205255000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   4206991500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   4206991500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.404902                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.444444                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.959795                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.723097                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.723097                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31110.795366                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.779787                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.209697                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.209697                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18281.681308                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   69064                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   88456                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          13566871                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         13247079                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             29564246                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            22056705                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               144417750                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                  34302                       # number of misc regfile writes
-system.cpu.numCycles                         72707510                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                 2506668                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps              99142533                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents                  23088                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                 26680183                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents               2442887                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups             533141286                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts              115984519                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands           118104117                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                  20356223                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles                1835527                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles               3532279                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                 18961579                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups            100234                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups        533041052                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles       16849272                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts             756028                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  10368336                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts         756038                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    177832725                       # The number of ROB reads
-system.cpu.rob.rob_writes                   225323365                       # The number of ROB writes
-system.cpu.timesIdled                           61505                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index c62a2de391e85b64fddb29de896a99040ebdc8fc..2decff9a64609bc03b6699d81584e7d99319d83f 100755 (executable)
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 15:15:49
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 19:27:10
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +30,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 567799725500 because target called exit()
+Exiting @ tick 566011920000 because target called exit()
index 2e13b2c1d421829d171945c7a1ac010751c9f84f..974fb936f7598b9d46a5682057600a80b65e9480 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 218238                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 262044                       # Number of bytes of host memory used
-host_seconds                                  7895.40                       # Real time elapsed on the host
-host_tick_rate                               71915281                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.566012                       # Number of seconds simulated
+sim_ticks                                566011920000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1723073864                       # Number of instructions simulated
-sim_seconds                                  0.567800                       # Number of seconds simulated
-sim_ticks                                567799725500                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                215471079                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             251238209                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                 391                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           18325747                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          236131073                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                286913964                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                 18098794                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts          18325219                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                  213462368                       # Number of branches committed
-system.cpu.commit.bw_lim_events              71826225                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts     1723073882                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls             460                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       387631176                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples   1070469701                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.609643                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.327352                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    480995228     44.93%     44.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    256180333     23.93%     68.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    110567341     10.33%     79.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     54815725      5.12%     84.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28914668      2.70%     87.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     29042780      2.71%     89.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     21062487      1.97%     91.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     17064914      1.59%     93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     71826225      6.71%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1070469701                       # Number of insts commited each cycle
-system.cpu.commit.count                    1723073882                       # Number of instructions committed
-system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
-system.cpu.commit.int_insts                1536941865                       # Number of committed integer instructions.
-system.cpu.commit.loads                     485926774                       # Number of loads committed
-system.cpu.commit.membars                          62                       # Number of memory barriers committed
-system.cpu.commit.refs                      660773823                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                  1723073864                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1723073864                       # Number of Instructions Simulated
-system.cpu.cpi                               0.659054                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.659054                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses           70                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits               67                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency       113500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.042857                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses          520005687                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 17036.313346                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11712.292709                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              509774132                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   174307977000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.019676                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses             10231555                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits           2567467                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  89764042000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.014738                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         7664088                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses            65                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits                65                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 24384.889096                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22421.774164                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             167960973                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency  112781916549                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.026799                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             4625074                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          2732851                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency  42426996773                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010964                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1892223                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4138.422705                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20785.714286                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  70.920174                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs             35824                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs    148254855                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       145500                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           692591734                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 19324.026571                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13832.852319                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               677735105                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    287089893549                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.021451                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses              14856629                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            5300318                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 132191038773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.013798                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9556311                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           4083.025990                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.996833                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses          692591734                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 19324.026571                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13832.852319                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              677735105                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   287089893549                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.021451                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses             14856629                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           5300318                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 132191038773                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.013798                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9556311                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                9552215                       # number of replacements
-system.cpu.dcache.sampled_refs                9556311                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4083.025990                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                677735237                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             6495250000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  3126399                       # number of writebacks
-system.cpu.decode.BlockedCycles              74308472                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                   637                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved             43193928                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts             2255287801                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                552391486                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                 436619657                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles               60139906                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                  2271                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles               7150085                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+host_inst_rate                                  52057                       # Simulator instruction rate (inst/s)
+host_tick_rate                               17100212                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255500                       # Number of bytes of host memory used
+host_seconds                                 33099.70                       # Real time elapsed on the host
+sim_insts                                  1723073884                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                   286913964                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 267974440                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     453847586                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               5761362                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     2078528457                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                   26                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                20230062                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.252654                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          267974440                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          233569873                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.830336                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         1130609606                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.039152                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.930908                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.numCycles                       1132023841                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                287218932                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          236434259                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           18348095                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             250920104                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                213740165                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                 18278609                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 393                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          265451297                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2081730004                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   287218932                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          232018774                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     452716467                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                20281434                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                 265451297                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               5801201                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1120688032                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.061143                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.942664                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                676762075     59.86%     59.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 34315412      3.04%     62.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 55733130      4.93%     67.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 58083869      5.14%     72.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 45528699      4.03%     76.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 55300610      4.89%     81.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 46771165      4.14%     86.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 18710110      1.65%     87.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                139404536     12.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                667971623     59.60%     59.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 32961041      2.94%     62.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 55903718      4.99%     67.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 56895013      5.08%     72.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 45557119      4.07%     76.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 54242890      4.84%     81.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 48750643      4.35%     85.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 18749981      1.67%     87.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                139656004     12.46%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1130609606                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        48                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       48                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses          267974440                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35169.574700                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34452.712100                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              267973523                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       32250500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  917                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               198                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     24771500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             719                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               372703.091794                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           267974440                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35169.574700                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34452.712100                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               267973523                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        32250500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   917                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                198                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     24771500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              719                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            573.603161                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.280080                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses          267974440                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35169.574700                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34452.712100                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              267973523                       # number of overall hits
-system.cpu.icache.overall_miss_latency       32250500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  917                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               198                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     24771500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             719                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                     10                       # number of replacements
-system.cpu.icache.sampled_refs                    719                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                573.603161                       # Cycle average of tags in use
-system.cpu.icache.total_refs                267973523                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         4989846                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts             20125806                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                235514393                       # Number of branches executed
-system.cpu.iew.exec_nop                           296                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.713630                       # Inst execution rate
-system.cpu.iew.exec_refs                    742460046                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                  185795418                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                18248815                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             598179019                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                540                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           6117477                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            212168948                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          2110540592                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             556664628                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          28602946                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            1945996752                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                 245772                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 55469                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               60139906                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles               1077846                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked        273714                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads         32169435                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses       459248                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation      1853009                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads    112252244                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores     37321899                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents        1853009                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      3267376                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       16858430                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                1884646665                       # num instructions consuming a value
-system.cpu.iew.wb_count                    1921636859                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.642567                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                1211011051                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.692178                       # insts written-back per cycle
-system.cpu.iew.wb_sent                     1926273504                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads               9735130843                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1902150318                       # number of integer regfile writes
-system.cpu.ipc                               1.517325                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.517325                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1219271237     61.75%     61.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              1051701      0.05%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              12      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc             12      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            566539676     28.69%     90.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           187737057      9.51%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1974599698                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                      74                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                 142                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           62                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                168                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                    24432078                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012373                       # FU busy rate (busy events/executed inst)
+system.cpu.fetch.rateDist::total           1120688032                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.253722                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.838945                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                546126816                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              71463989                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 435974123                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6702645                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               60420459                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             43189829                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   635                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2259641783                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2302                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               60420459                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                563998095                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                40175582                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          14256                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 424146965                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              31932675                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2194117520                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 11722                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                3482918                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              25684334                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2171048745                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           10125608138                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      10125607580                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               558                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1706320007                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                464728733                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                633                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            629                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  66642282                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            598549667                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           212535274                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          87730642                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         84698913                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2112468775                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 616                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1975042527                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            852567                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       380766314                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    858455180                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            152                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1120688032                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.762348                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.680120                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           337912961     30.15%     30.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           234234895     20.90%     51.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           220010483     19.63%     70.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           141420525     12.62%     83.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           101836492      9.09%     92.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            53894209      4.81%     97.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            20983167      1.87%     99.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             9353324      0.83%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1041976      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1120688032                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  518261      2.12%      2.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      2      0.00%      2.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  517494      2.12%      2.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      1      0.00%      2.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.12% # attempts to use FU when none available
@@ -362,161 +176,347 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.12% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               23578927     96.51%     98.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                334888      1.37%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               23433886     96.11%     98.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                430313      1.76%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses             1999031702                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads         5105133398                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses   1921636797                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes        2491239828                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                 2110539690                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                1974599698                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                 606                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       378853333                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            892460                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved            146                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    851689687                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples    1130609606                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.746491                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.678752                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           343530730     30.38%     30.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           241793067     21.39%     51.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           218551738     19.33%     71.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           140017220     12.38%     83.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           100970740      8.93%     92.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            54673459      4.84%     97.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            20221073      1.79%     99.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             9737830      0.86%     99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1113749      0.10%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1130609606                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.738817                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses         1892225                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34668.138336                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31525.497909                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              980562                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  31605659000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.481794                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            911663                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  28740630000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.481794                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       911663                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           7664805                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34326.590029                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31154.423829                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5643096                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   69398376000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.263765                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             2021709                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency  62984867500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.263764                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        2021699                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         3126399                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             3126399                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8610.632689                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.658362                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs             5690                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs     48994500                       # number of cycles access was blocked
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1219473147     61.74%     61.74% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              1083372      0.05%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               6      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            566098039     28.66%     90.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           188387953      9.54%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1975042527                       # Type of FU issued
+system.cpu.iq.rate                           1.744700                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    24381694                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012345                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5096007233                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2495143403                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1922135162                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 114                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                 98                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           48                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1999424161                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      60                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         34829517                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads    112622888                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       463072                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      1914554                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     37688221                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        273360                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               60420459                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                18632955                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1195402                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2112469674                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6157143                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             598549667                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            212535274                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                546                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 334650                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 56652                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        1914554                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       16889121                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3256921                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             20146042                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1946822051                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             556717785                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          28220476                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                           283                       # number of nop insts executed
+system.cpu.iew.exec_refs                    742905406                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                235411550                       # Number of branches executed
+system.cpu.iew.exec_stores                  186187621                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.719771                       # Inst execution rate
+system.cpu.iew.wb_sent                     1926889510                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1922135210                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1211916900                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1896005064                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.697964                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.639195                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts     1723073902                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       389560093                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             464                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          18347567                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1060267574                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.625131                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.338631                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    472290035     44.54%     44.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    255203775     24.07%     68.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    110318720     10.40%     79.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     55061761      5.19%     84.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28404469      2.68%     86.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27943387      2.64%     89.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     20897685      1.97%     91.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     17855453      1.68%     93.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     72292289      6.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1060267574                       # Number of insts commited each cycle
+system.cpu.commit.count                    1723073902                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                      660773831                       # Number of memory references committed
+system.cpu.commit.loads                     485926778                       # Number of loads committed
+system.cpu.commit.membars                          62                       # Number of memory barriers committed
+system.cpu.commit.branches                  213462372                       # Number of branches committed
+system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1536941881                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              72292289                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                   3100608681                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4285815110                       # The number of ROB writes
+system.cpu.timesIdled                          696063                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        11335809                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1723073884                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1723073884                       # Number of Instructions Simulated
+system.cpu.cpi                               0.656979                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.656979                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.522118                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.522118                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               9738255749                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1902471542                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       31                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              2800450937                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    140                       # number of misc regfile writes
+system.cpu.icache.replacements                      9                       # number of replacements
+system.cpu.icache.tagsinuse                573.017722                       # Cycle average of tags in use
+system.cpu.icache.total_refs                265450383                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    717                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               370223.686192                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            573.017722                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.279794                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              265450383                       # number of ReadReq hits
+system.cpu.icache.demand_hits               265450383                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              265450383                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  914                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   914                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  914                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       32210500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        32210500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       32210500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          265451297                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           265451297                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          265451297                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35241.247265                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35241.247265                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35241.247265                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               197                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                197                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               197                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             717                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              717                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             717                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     24697500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     24697500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     24697500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34445.606695                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34445.606695                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34445.606695                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                9552367                       # number of replacements
+system.cpu.dcache.tagsinuse               4082.984998                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                675087648                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9556463                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  70.641999                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             6495236000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4082.984998                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.996823                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              507131941                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             167955564                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               74                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits                69                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               675087505                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              675087505                       # number of overall hits
+system.cpu.dcache.ReadReq_misses             10254687                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             4630483                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses              14885170                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses             14885170                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   173914872000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency  112892331168                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       113500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency    286807203168                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   286807203168                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          517386628                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses           77                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses            69                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           689972675                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          689972675                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.019820                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.026830                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.038961                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.021574                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.021574                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 16959.549521                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 24380.249570                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 19267.983044                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 19267.983044                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    148361910                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       159500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             35813                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4142.683104                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                  3126452                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           2590385                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          2738322                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            5328707                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           5328707                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7664302                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1892161                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9556463                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9556463                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  89320855000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  42428124877                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 131748979877                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 131748979877                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.014813                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.010964                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.013850                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.013850                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11654.140847                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22423.105051                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13786.374716                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 13786.374716                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements               2920822                       # number of replacements
+system.cpu.l2cache.tagsinuse             26404.864855                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7838163                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2948145                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.658676                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          129803245500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15746.128543                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10658.736312                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.480534                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.325279                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5643332                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3126452                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              980638                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6623970                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6623970                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             2021685                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            911525                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2933210                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2933210                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   69338469500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  31601923000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency   100940392500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency  100940392500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7665017                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3126452                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1892163                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9557180                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9557180                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.263755                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.481737                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.306912                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.306912                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34297.365564                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34669.288281                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34412.944351                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34412.944351                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs     48964500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs             5689                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8606.872913                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            9557030                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34432.739864                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31269.750375                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                6623658                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   101004035000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.306933                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              2933372                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                 1216359                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  91725497500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.306932                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         2933362                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0         15787.476515                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10639.481396                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.481796                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.324691                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses           9557030                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34432.739864                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31269.750375                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               6623658                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  101004035000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.306933                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             2933372                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits               10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  91725497500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.306932                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        2933362                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses        2021675                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       911525                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2933200                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2933200                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2921001                       # number of replacements
-system.cpu.l2cache.sampled_refs               2948324                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency  62968532000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  28735558500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  91704090500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  91704090500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.263753                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.481737                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.306911                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.306911                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.713493                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31524.706947                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.179224                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.179224                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             26426.957911                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 7837713                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          129803259500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1216468                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          87202635                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         84882545                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            598179019                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           212168948                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads              2797025769                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                    132                       # number of misc regfile writes
-system.cpu.numCycles                       1135599452                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                43624609                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps            1706319975                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents                3032404                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                568994598                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents              25723615                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                 11682                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups           10112299112                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts             2191283557                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands          2168556618                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                 426283235                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles               60139906                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles              31553217                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                462236638                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups              1010                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups      10112298102                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles          14041                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts                629                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  61919422                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts            626                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                   3109347935                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4281671298                       # The number of ROB writes
-system.cpu.timesIdled                          552036                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                   46                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 19caace726d6b00244b088440732a0e04a0d6ede..5262b166251040e3ae7da339d9f1f72a8e98152c 100755 (executable)
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 14:48:18
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 16:39:45
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -27,4 +27,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 114589481500 because target called exit()
+122 123 124 Exiting @ tick 114583980000 because target called exit()
index debcad22a7128db07a75b9cb09f98c1c124f16a8..5a112fdddd213699464a2faf2b3bb7b6ba83d41d 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 145628                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 265820                       # Number of bytes of host memory used
-host_seconds                                  1295.56                       # Real time elapsed on the host
-host_tick_rate                               88448039                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.114584                       # Number of seconds simulated
+sim_ticks                                114583980000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                   188668737                       # Number of instructions simulated
-sim_seconds                                  0.114589                       # Number of seconds simulated
-sim_ticks                                114589481500                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 74760196                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              79995618                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect              111816                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           10349538                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           77060035                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 98242064                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  4425750                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts          10211892                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                   40284128                       # Number of branches committed
-system.cpu.commit.bw_lim_events               3189966                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts      188683125                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls         1635840                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       132289806                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples    207214501                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.910569                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.539108                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    117707920     56.80%     56.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     47326882     22.84%     79.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20304092      9.80%     89.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8456473      4.08%     93.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      5239140      2.53%     96.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1942567      0.94%     96.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2142710      1.03%     98.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       904751      0.44%     98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3189966      1.54%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    207214501                       # Number of insts commited each cycle
-system.cpu.commit.count                     188683125                       # Number of instructions committed
-system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
-system.cpu.commit.int_insts                 150116005                       # Number of committed integer instructions.
-system.cpu.commit.loads                      29851930                       # Number of loads committed
-system.cpu.commit.membars                       22408                       # Number of memory barriers committed
-system.cpu.commit.refs                       42499009                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                   188668737                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             188668737                       # Number of Instructions Simulated
-system.cpu.cpi                               1.214716                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.214716                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses        26526                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        32000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits            26524                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency        64000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000075                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses           36836691                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 32644.833427                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32223.719677                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               36834920                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       57814000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000048                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                 1771                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits              1029                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency     23910000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000020                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             742                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses         24852                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits             24852                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 31348.093725                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35116.758242                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              12356733                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     236803500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000611                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                7554                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits             6462                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency     38347500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1092                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               26864.722313                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            49200978                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 31594.369973                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33946.292257                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                49191653                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       294617500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000190                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  9325                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits               7491                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     62257500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000037                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             1834                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           1395.552568                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.340711                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses           49200978                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 31594.369973                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33946.292257                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               49191653                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      294617500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000190                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 9325                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits              7491                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     62257500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000037                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            1834                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                     49                       # number of replacements
-system.cpu.dcache.sampled_refs                   1833                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1395.552568                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 49243036                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                       17                       # number of writebacks
-system.cpu.decode.BlockedCycles              32329175                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                166208                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved             14317214                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts              406876360                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                 79350559                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                  94851777                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles               21897649                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                708566                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles                682989                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+host_inst_rate                                  37904                       # Simulator instruction rate (inst/s)
+host_tick_rate                               23020273                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259288                       # Number of bytes of host memory used
+host_seconds                                  4977.52                       # Real time elapsed on the host
+sim_insts                                   188668727                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                    98242064                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  37011796                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     102039448                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               2084661                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      401290022                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                   47                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                10742446                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.428670                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           37011796                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           79185946                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.750990                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          229112149                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.894065                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.602797                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        229167961                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 98244922                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           77066129                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           10346796                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              79994397                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 74750808                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  4424088                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              111792                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           36996487                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      401246546                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    98244922                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79174896                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     102059455                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                10739700                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   48                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                  36996487                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2084614                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          229101172                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.893988                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.602493                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                127250145     55.54%     55.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4018044      1.75%     57.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 29090462     12.70%     69.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 15702504      6.85%     76.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  9815384      4.28%     81.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 13327940      5.82%     86.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  7882856      3.44%     90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4750026      2.07%     92.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 17274788      7.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                127219261     55.53%     55.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4017584      1.75%     57.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 29118578     12.71%     69.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 15726187      6.86%     76.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  9819635      4.29%     81.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 13296507      5.80%     86.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  7877710      3.44%     90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4751479      2.07%     92.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 17274231      7.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            229112149                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                   2915845                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2459384                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           37011796                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 23764.120428                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20374.787294                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               37007777                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       95508000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000109                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 4019                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               493                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     71841500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000095                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            3526                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               10498.660142                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            37011796                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 23764.120428                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20374.787294                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                37007777                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        95508000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000109                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  4019                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                493                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     71841500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000095                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             3526                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1276.804996                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.623440                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses           37011796                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 23764.120428                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20374.787294                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               37007777                       # number of overall hits
-system.cpu.icache.overall_miss_latency       95508000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000109                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 4019                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               493                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     71841500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000095                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            3526                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   1866                       # number of replacements
-system.cpu.icache.sampled_refs                   3525                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1276.804996                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 37007777                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           66815                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts             11832778                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 51965807                       # Number of branches executed
-system.cpu.iew.exec_nop                         52722                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.079834                       # Inst execution rate
-system.cpu.iew.exec_refs                     51989932                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                   13440828                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                   16073                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              47405288                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            2181665                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           8564193                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             16540037                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           320981934                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              38549104                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          13994480                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             247475158                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                    251                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  3185                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               21897649                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                  3565                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads           982919                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses          850                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation       453121                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads     17553357                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores      3892958                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         453121                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      2166634                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        9666144                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                 237697826                       # num instructions consuming a value
-system.cpu.iew.wb_count                     243310186                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.616543                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                 146551038                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.061660                       # insts written-back per cycle
-system.cpu.iew.wb_sent                      244563892                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads               1105271362                       # number of integer regfile reads
-system.cpu.int_regfile_writes               405517163                       # number of integer regfile writes
-system.cpu.ipc                               0.823238                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.823238                       # IPC: Total IPC of All Threads
+system.cpu.fetch.rateDist::total            229101172                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.428703                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.750884                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 79313906                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              32327887                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  94878595                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                682758                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               21898026                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             14316236                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                166090                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              406876598                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                708405                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               21898026                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 88099979                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  621468                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       27861388                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  86740372                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3879939                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              372161493                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                  76195                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1579800                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           635133998                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1589359787                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1572376571                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          16983216                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             298063696                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                337070297                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2567300                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2531045                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  20595382                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             47397575                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16557205                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           6544934                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          4003679                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  318729231                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2207616                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 261466746                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            554929                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       126483137                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    283584721                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         571778                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     229101172                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.141272                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.407939                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           108324411     47.28%     47.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            46627729     20.35%     67.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34182087     14.92%     82.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            22115521      9.65%     92.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            11617915      5.07%     97.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4157757      1.81%     99.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1774100      0.77%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              189981      0.08%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              111671      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       229101172                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  110643      6.25%      6.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5520      0.31%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                24      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1295953     73.23%     79.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                357680     20.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             205122709     78.45%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               918079      0.35%     78.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             205127791     78.45%     78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               918034      0.35%     78.80% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.80% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.80% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.80% # Type of FU issued
@@ -301,228 +189,340 @@ system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.80% # Ty
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.80% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.80% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                10109      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                10104      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.81% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAdd           32866      0.01%     78.82% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          166325      0.06%     78.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          251418      0.10%     78.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          166342      0.06%     78.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          251406      0.10%     78.98% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv           76052      0.03%     79.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         462207      0.18%     79.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         207191      0.08%     79.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         462257      0.18%     79.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         207196      0.08%     79.27% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc        71628      0.03%     79.29% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt            324      0.00%     79.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             40432924     15.46%     94.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13717806      5.25%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             40426138     15.46%     94.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13716608      5.25%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              261469638                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                 1855088                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads             3701583                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1822597                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes            2110861                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     1743440                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006668                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  109941      6.31%      6.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   5520      0.32%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                12      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1271011     72.90%     79.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                356956     20.47%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses              261357990                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          750654117                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    241487589                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         445672842                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  318723473                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 261469638                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             2205739                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       126475271                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            560835                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved         569899                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    283578220                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples     229112149                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.141230                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.407706                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           108319489     47.28%     47.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            46636134     20.36%     67.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            34199454     14.93%     82.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            22104068      9.65%     92.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            11622825      5.07%     97.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4159052      1.82%     99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1773728      0.77%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              185728      0.08%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              111671      0.05%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       229112149                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.140897                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses            1091                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34343.345656                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31041.127542                       # average ReadExReq mshr miss latency
+system.cpu.iq.FU_type_0::total              261466746                       # Type of FU issued
+system.cpu.iq.rate                           1.140939                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1769820                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006769                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          750657753                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         445688656                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    241497013                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3701660                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2110445                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1822638                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              261381402                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1855164                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           983049                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     17545646                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          834                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       453061                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3910128                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads            3                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               21898026                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   16044                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                  3524                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           320989557                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           8588110                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              47397575                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16557205                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2183565                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    259                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3132                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         453061                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        9663378                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2166474                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11829852                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             247483110                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              38551878                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          13983636                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         52710                       # number of nop insts executed
+system.cpu.iew.exec_refs                     51991708                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 51968856                       # Number of branches executed
+system.cpu.iew.exec_stores                   13439830                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.079920                       # Inst execution rate
+system.cpu.iew.wb_sent                      244574618                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     243319651                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 146548425                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 237755963                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.061752                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.616382                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      188683115                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       132297419                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1635838                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          10209212                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    207203147                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.910619                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.539035                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    117680182     56.79%     56.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     47355200     22.85%     79.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     20289931      9.79%     89.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8457444      4.08%     93.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5251466      2.53%     96.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1928686      0.93%     96.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2144986      1.04%     98.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       905505      0.44%     98.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3189747      1.54%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    207203147                       # Number of insts commited each cycle
+system.cpu.commit.count                     188683115                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       42499005                       # Number of memory references committed
+system.cpu.commit.loads                      29851928                       # Number of loads committed
+system.cpu.commit.membars                       22408                       # Number of memory barriers committed
+system.cpu.commit.branches                   40284126                       # Number of branches committed
+system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 150115997                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               3189747                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    524988733                       # The number of ROB reads
+system.cpu.rob.rob_writes                   663890510                       # The number of ROB writes
+system.cpu.timesIdled                            1538                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           66789                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   188668727                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             188668727                       # Number of Instructions Simulated
+system.cpu.cpi                               1.214658                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.214658                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.823277                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.823277                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1105306330                       # number of integer regfile reads
+system.cpu.int_regfile_writes               405513282                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2915970                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2459492                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               485972392                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 824922                       # number of misc regfile writes
+system.cpu.icache.replacements                   1867                       # number of replacements
+system.cpu.icache.tagsinuse               1275.783892                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 36992467                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3528                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               10485.393141                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1275.783892                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.622941                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               36992467                       # number of ReadReq hits
+system.cpu.icache.demand_hits                36992467                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               36992467                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 4020                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  4020                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 4020                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       95473000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        95473000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       95473000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           36996487                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            36996487                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           36996487                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000109                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000109                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000109                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 23749.502488                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 23749.502488                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 23749.502488                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               491                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                491                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               491                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3529                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3529                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3529                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     71843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     71843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     71843000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000095                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000095                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000095                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 20357.891754                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 20357.891754                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 20357.891754                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     49                       # number of replacements
+system.cpu.dcache.tagsinuse               1395.560229                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 49245913                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1834                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               26851.642857                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1395.560229                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.340713                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               36836047                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              12356734                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            28275                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             24850                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                49192781                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               49192781                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1779                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                7553                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses                  9332                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 9332                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       57926000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     236821500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        64000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency       294747500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      294747500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           36837826                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        28277                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         24850                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            49202113                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           49202113                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000048                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000611                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000071                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.000190                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000190                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 32560.989320                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 31354.627300                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        32000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 31584.601372                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 31584.601372                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                       17                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              1036                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             6461                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               7497                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              7497                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             743                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1092                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1835                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1835                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     23910500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     38348500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     62259000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     62259000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000020                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000037                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000037                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32181.022880                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35117.673993                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33928.610354                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33928.610354                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              1850.961242                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1671                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2592                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.644676                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1847.906973                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             3.054268                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.056394                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  1671                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                  17                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                   9                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency     37159500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.991751                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              1082                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     33586500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.991751                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1082                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              4267                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34290.769231                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31075.270898                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                  1667                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      89156000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.609327                       # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_hits                   1680                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  1680                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses                2600                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits               16                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency     80298500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.605578                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           2584                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_misses              1082                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 3682                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                3682                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      89152000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     37162000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      126314000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     126314000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              4271                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses              17                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                  17                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.643133                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1091                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               5362                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              5362                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.608757                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.991751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.686684                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.686684                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34289.230769                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34345.656192                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34305.812059                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34305.812059                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               5358                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34306.219446                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.193672                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   1676                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      126315500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.687197                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 3682                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               16                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                16                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    113885000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.684211                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            3666                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          1849.891639                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             3.054324                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.056454                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses              5358                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34306.219446                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.193672                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  1676                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     126315500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.687197                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                3682                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits               16                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    113885000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.684211                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_mshr_misses           2584                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            3666                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses           3666                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  2592                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency     80301000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     33586500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    113887500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    113887500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.605011                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.991751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.683700                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.683700                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31076.238390                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31041.127542                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.875614                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.875614                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              1852.945963                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    1667                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads           6544677                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          3988120                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             47405288                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16540037                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               486015075                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 824926                       # number of misc regfile writes
-system.cpu.numCycles                        229178964                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                  628152                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps             298063712                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents                  76310                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                 88142663                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents               1597239                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenameLookups            1589178031                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts              372125350                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands           635131206                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                  86698420                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles               21897649                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles               3896290                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                337067489                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups          16987486                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups       1572190545                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles       27848975                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts            2565042                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  20623537                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts        2528667                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    524992265                       # The number of ROB reads
-system.cpu.rob.rob_writes                   663874910                       # The number of ROB writes
-system.cpu.timesIdled                            1540                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 1b4fcdc8a6c8d4610a6e6fc41abddeb53734fbb5..4239fb14e9138772ce312671edb8074052300b87 100755 (executable)
@@ -1,3 +1,5 @@
+Redirecting stdout to build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  1 2011 16:48:51
-M5 started May  1 2011 16:48:54
-M5 executing on u200439-lin.austin.arm.com
+M5 compiled May 17 2011 12:22:59
+M5 started May 17 2011 12:44:44
+M5 executing on nadc-0309
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
 Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2
@@ -28,4 +30,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 106659390000 because target called exit()
+122 123 124 Exiting @ tick 106734154000 because target called exit()
index 176877f025c9ce612204b417ef27dfe9dd0b525e..3cac44fa8550a30310bd8bdef8099ee9711387d7 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  88999                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 265284                       # Number of bytes of host memory used
-host_seconds                                  2487.25                       # Real time elapsed on the host
-host_tick_rate                               42882469                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.106734                       # Number of seconds simulated
+sim_ticks                                106734154000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 173636                       # Simulator instruction rate (inst/s)
+host_tick_rate                               83720146                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258788                       # Number of bytes of host memory used
+host_seconds                                  1274.89                       # Real time elapsed on the host
 sim_insts                                   221363017                       # Number of instructions simulated
-sim_seconds                                  0.106659                       # Number of seconds simulated
-sim_ticks                                106659390000                       # Number of ticks simulated
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        213468309                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                 25050494                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           25050494                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3072725                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              22404993                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 19578906                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 19559071                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              22388883                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            3071862                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           25034838                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 25034838                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts           3071894                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                   12326943                       # Number of branches committed
-system.cpu.commit.bw_lim_events               2350531                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           27480404                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      261552197                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    25050494                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           19578906                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      69713468                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3100277                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   57                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                  27480404                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                444252                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          213378820                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.014955                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.225944                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                145514774     68.20%     68.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3945621      1.85%     70.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3133148      1.47%     71.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4337653      2.03%     73.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4594142      2.15%     75.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4407004      2.07%     77.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5010346      2.35%     80.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3238927      1.52%     81.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 39197205     18.37%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            213378820                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.117350                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.225251                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 66958522                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              57001085                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  60412397                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5858231                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               23148585                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              419968775                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               23148585                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 74832356                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                18068346                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          22426                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  57435303                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              39871804                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              409779934                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents               21501033                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              16352489                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           430797249                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1054244251                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1043122686                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          11121565                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                196433840                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1440                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1310                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  83098345                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            104980766                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37095594                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          90430171                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         30425406                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  395507958                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1424                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 281831488                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             66022                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       173816816                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    357685429                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            178                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     213378820                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.320803                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.372846                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            72508340     33.98%     33.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            65572290     30.73%     64.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            36644917     17.17%     81.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20570479      9.64%     91.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12013956      5.63%     97.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3959522      1.86%     99.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1478424      0.69%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              513187      0.24%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              117705      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       213378820                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   68507      2.43%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2380396     84.55%     86.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                366520     13.02%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass           1200241      0.43%      0.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             187039498     66.37%     66.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1589434      0.56%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             68498295     24.30%     91.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            23504020      8.34%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              281831488                       # Type of FU issued
+system.cpu.iq.rate                           1.320250                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2815423                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009990                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          774688380                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         563666165                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    273461056                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             5234861                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            5690969                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2532279                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              280809032                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2637638                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         16340043                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     48331176                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        20419                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        34133                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     16579878                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads        45973                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               23148585                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  533368                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                548562                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           395509382                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            255580                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             104980766                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37095594                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1424                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 479390                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 13059                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          34133                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2541200                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       744980                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3286180                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             278314164                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              67081099                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3517324                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                     90254153                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15873858                       # Number of branches executed
+system.cpu.iew.exec_stores                   23173054                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.303773                       # Inst execution rate
+system.cpu.iew.wb_sent                      277023863                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     275993335                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 222941305                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 371922764                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.292901                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.599429                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      221363017                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       174164321                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       173965235                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples    190108496                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.164404                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.519902                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           3072754                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    190230235                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.163658                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.518986                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     74006380     38.93%     38.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     71095556     37.40%     76.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     18250817      9.60%     85.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12666090      6.66%     92.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      5885570      3.10%     95.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2802504      1.47%     97.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1948827      1.03%     98.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1102221      0.58%     98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2350531      1.24%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     74059520     38.93%     38.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     71187215     37.42%     76.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     18215863      9.58%     85.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12685132      6.67%     92.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5921003      3.11%     95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2781558      1.46%     97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1922219      1.01%     98.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1098236      0.58%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2359489      1.24%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    190108496                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    190230235                       # Number of insts commited each cycle
 system.cpu.commit.count                     221363017                       # Number of instructions committed
-system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       77165306                       # Number of memory references committed
 system.cpu.commit.loads                      56649590                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.refs                       77165306                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.branches                   12326943                       # Number of branches committed
+system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2359489                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    583398084                       # The number of ROB reads
+system.cpu.rob.rob_writes                   814214437                       # The number of ROB writes
+system.cpu.timesIdled                            1914                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           89489                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   221363017                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             221363017                       # Number of Instructions Simulated
-system.cpu.cpi                               0.963660                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.963660                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses           50560876                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 33172.166428                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34228.682171                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               50560179                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       23121000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  697                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits               310                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency     13246500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             387                       # number of ReadReq MSHR misses
+system.cpu.cpi                               0.964336                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.964336                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.036983                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.036983                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                516528082                       # number of integer regfile reads
+system.cpu.int_regfile_writes               284024941                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3512884                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2186553                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               145160346                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
+system.cpu.icache.replacements                   3419                       # number of replacements
+system.cpu.icache.tagsinuse               1603.937064                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 27474068                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   5377                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                5109.553282                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1603.937064                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.783172                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               27474068                       # number of ReadReq hits
+system.cpu.icache.demand_hits                27474068                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               27474068                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 6336                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  6336                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 6336                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      161881500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       161881500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      161881500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           27480404                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            27480404                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           27480404                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000231                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000231                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000231                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 25549.479167                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 25549.479167                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 25549.479167                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               957                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                957                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               957                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            5379                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             5379                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            5379                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    120710000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    120710000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    120710000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000196                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000196                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000196                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22440.974159                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22440.974159                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22440.974159                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     48                       # number of replacements
+system.cpu.dcache.tagsinuse               1400.553684                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 71038551                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1955                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               36336.854731                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1400.553684                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.341932                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               50529918                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              20508631                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                71038549                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               71038549                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  700                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                7099                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  7799                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 7799                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       23034500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     187834000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       210868500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      210868500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           50530618                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 26488.657179                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35473.248408                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              20508633                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     187990000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_accesses            71046348                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           71046348                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.000346                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                7097                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits             5527                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency     55693000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000077                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1570                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               36352.334527                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate           0.000110                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000110                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 32906.428571                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 26459.219608                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 27037.889473                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 27037.889473                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            71076606                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27086.348473                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35227.133367                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                71068812                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       211111000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000110                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  7794                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits               5837                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     68939500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000028                       # mshr miss rate for demand accesses
+system.cpu.dcache.writebacks                       10                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits               312                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             5530                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               5842                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              5842                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             388                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1569                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses             1957                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0           1400.398145                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.341894                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses           71076606                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27086.348473                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35227.133367                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               71068812                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      211111000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000110                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 7794                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits              5837                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     68939500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000028                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses            1957                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                     48                       # number of replacements
-system.cpu.dcache.sampled_refs                   1955                       # Sample count of references to valid blocks.
+system.cpu.dcache.ReadReq_mshr_miss_latency     13276000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     55641500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     68917500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     68917500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000076                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000028                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000028                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34216.494845                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35463.033779                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35215.891671                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35215.891671                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1400.398145                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 71068814                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                       10                       # number of writebacks
-system.cpu.decode.BlockedCycles              57002752                       # Number of cycles decode is blocked
-system.cpu.decode.DecodedInsts              419872535                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                 66995296                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                  60323444                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles               23120513                       # Number of cycles decode is squashing
-system.cpu.decode.UnblockCycles               5787004                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                    25034838                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  27511716                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      69512577                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                449654                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      261443886                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                   62                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                 3099669                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.117359                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           27511716                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           19559071                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.225602                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          213229009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.015146                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.226933                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                145563800     68.27%     68.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3763912      1.77%     70.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3143749      1.47%     71.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4274487      2.00%     73.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4655568      2.18%     75.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4407393      2.07%     77.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4998818      2.34%     80.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3209647      1.51%     81.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 39211635     18.39%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            213229009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                   3514377                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2187528                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses           27511716                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 25569.940006                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.790041                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               27505382                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      161960000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000230                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 6334                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               952                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    120905500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000196                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            5382                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                5112.524535                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            27511716                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 25569.940006                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 22464.790041                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                27505382                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       161960000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000230                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  6334                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                952                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    120905500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000196                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             5382                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0           1605.599338                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.783984                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses           27511716                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 25569.940006                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 22464.790041                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               27505382                       # number of overall hits
-system.cpu.icache.overall_miss_latency      161960000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000230                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 6334                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               952                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    120905500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000196                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            5382                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   3421                       # number of replacements
-system.cpu.icache.sampled_refs                   5380                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1605.599338                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 27505382                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           89772                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts              3285583                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                 15876599                       # Number of branches executed
-system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_rate                     1.304758                       # Inst execution rate
-system.cpu.iew.exec_refs                     90277406                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                   23169669                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                  535171                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             104943598                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts               1424                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            227523                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             37082263                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           395310289                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              67107737                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3518032                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             278329468                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                 451527                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 13065                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               23120513                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                520097                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads         16336525                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses        15761                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation        34193                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads        46033                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads     48294008                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores     16566547                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          34193                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       745041                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        2540542                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                 371832293                       # num instructions consuming a value
-system.cpu.iew.wb_count                     275994943                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.599268                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                 222827233                       # num instructions producing a value
-system.cpu.iew.wb_rate                       1.293815                       # insts written-back per cycle
-system.cpu.iew.wb_sent                      277038754                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads                516581259                       # number of integer regfile reads
-system.cpu.int_regfile_writes               284038520                       # number of integer regfile writes
-system.cpu.ipc                               1.037710                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.037710                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass           1197054      0.42%      0.42% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             187021337     66.36%     66.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1590291      0.56%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             68531630     24.32%     91.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            23507188      8.34%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              281847500                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                 2638444                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads             5236518                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2534154                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes            5693561                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                     2791850                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009906                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   67290      2.41%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2359047     84.50%     86.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                365513     13.09%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses              280803852                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          774570053                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses    273460789                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes         563268520                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                  395308865                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 281847500                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                1424                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       173620640                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued             90712                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved            178                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    357064626                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples     213229009                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.321807                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.374231                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            72462076     33.98%     33.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            65441995     30.69%     64.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            36667606     17.20%     81.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20567003      9.65%     91.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            11965683      5.61%     97.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3990809      1.87%     99.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1502036      0.70%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              514117      0.24%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              117684      0.06%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       213229009                       # Number of insts issued each cycle
-system.cpu.iq.rate                           1.321250                       # Inst issue rate
-system.cpu.l2cache.ReadExReq_accesses            1568                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.695262                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.472471                       # average ReadExReq mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              2429.026594                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    2107                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3661                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.575526                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          2428.011682                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             1.014912                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.074097                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000031                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  2107                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                  10                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                   6                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency     53963500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.996173                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits                   2113                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  2113                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3657                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                2                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses              1562                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     48971000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.996173                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1562                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              5767                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34290.551611                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.326597                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                  2105                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     125572000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.634992                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                3662                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    113677000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.634992                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           3662                       # number of ReadReq MSHR misses
+system.cpu.l2cache.demand_misses                 5219                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                5219                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     125400000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     53945500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      179345500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     179345500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              5764                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses              10                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses              2                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_accesses            1568                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               7332                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              7332                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.634455                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses                2                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        62000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses              10                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                  10                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.574195                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate       0.996173                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.711811                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.711811                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34290.401969                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.171575                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34363.958613                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34363.958613                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               7335                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34367.438744                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.762634                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   2111                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      179535500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.712202                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 5224                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    162648000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.712202                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            5224                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0          2429.722700                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             1.014710                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.074149                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000031                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses              7335                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34367.438744                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.762634                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  2111                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     179535500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.712202                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                5224                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    162648000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.712202                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           5224                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses           3657                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            2                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1562                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            5219                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           5219                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  3666                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency    113519000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        62000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     48964500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    162483500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    162483500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.634455                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.996173                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.711811                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.711811                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.564124                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.311140                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31133.071470                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31133.071470                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2430.737411                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    2105                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          90595235                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         30370608                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            104943598                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            37082263                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads               145181965                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
-system.cpu.numCycles                        213318781                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                18031749                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents               21548402                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                 74813235                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents              16345466                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups            1053910938                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts              409668647                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands           430592677                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                  57355298                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles               23120513                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles              39885814                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                196229268                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups          11151271                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups       1042759667                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles          22400                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts               1440                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                  83004304                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts           1309                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    583086217                       # The number of ROB reads
-system.cpu.rob.rob_writes                   813789002                       # The number of ROB writes
-system.cpu.timesIdled                            1930                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 811dc859b0df06ab927723adabe3a80abcfe52bf..7a48bdd9d4156ed9cdac1ba0ca92a90b6de276e3 100755 (executable)
@@ -7,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled May  4 2011 13:56:47
-M5 started May  4 2011 14:21:49
-M5 executing on nadc-0364
+M5 compiled May 16 2011 15:11:25
+M5 started May 16 2011 15:11:56
+M5 executing on nadc-0271
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 10782500 because target called exit()
+Exiting @ tick 10758500 because target called exit()
index 7db13d16a433b5a1ced51938f1bd50f250eb3372..b6528098799b37083b4d2c8c6886c1f71110f5e0 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  97592                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 257968                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              182664453                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.000011                       # Number of seconds simulated
+sim_ticks                                    10758500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  88454                       # Simulator instruction rate (inst/s)
+host_tick_rate                              165780634                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251164                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5739                       # Number of instructions simulated
-sim_seconds                                  0.000011                       # Number of seconds simulated
-sim_ticks                                    10782500                       # Number of ticks simulated
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.numCycles                            21518                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                     2191                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1669                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                423                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  1853                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      732                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                      725                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups                  1851                       # Number of BTB lookups
+system.cpu.BPredUnit.usedRAS                      242                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  63                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect                423                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted               1665                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                     2185                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                      238                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts               332                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                        945                       # Number of branches committed
-system.cpu.commit.bw_lim_events                    74                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.fetch.icacheStallCycles               1618                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          11168                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2191                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                974                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2422                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     514                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      1618                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   231                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              11665                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.190999                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.598414                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9243     79.24%     79.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      226      1.94%     81.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      153      1.31%     82.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      215      1.84%     84.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      195      1.67%     86.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      261      2.24%     88.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      124      1.06%     89.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       97      0.83%     90.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1151      9.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total                11665                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.101822                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.519007                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7384                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1181                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2267                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    47                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    786                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  350                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   158                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  12143                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   552                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    786                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7644                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     280                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            712                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2054                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   189                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11385                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     38                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   124                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               11181                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 51901                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            51381                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               520                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps                  5684                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                     5492                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 15                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             13                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       493                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2353                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1452                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      10217                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  24                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      8487                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                21                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            3978                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        11076                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples         11665                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.727561                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.389080                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8112     69.54%     69.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1403     12.03%     81.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 820      7.03%     88.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 520      4.46%     93.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 393      3.37%     96.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 236      2.02%     98.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 143      1.23%     99.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  30      0.26%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   8      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           11665                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      11      6.01%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    116     63.39%     69.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    56     30.60%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5246     61.81%     61.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    6      0.07%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     61.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.92% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2078     24.48%     86.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1154     13.60%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                   8487                       # Type of FU issued
+system.cpu.iq.rate                           0.394414                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         183                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021562                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              28807                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             14215                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7753                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses                   8650                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads               50                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads         1152                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          514                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                    786                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     166                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    27                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10244                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               136                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2353                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1452                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 12                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     19                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             14                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            128                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          243                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  371                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8154                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1932                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               333                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             3                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3053                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1361                       # Number of branches executed
+system.cpu.iew.exec_stores                       1121                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.378939                       # Inst execution rate
+system.cpu.iew.wb_sent                           7896                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7769                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3570                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7022                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       0.361047                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.508402                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5739                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts            4400                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              24                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts            4364                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples        10921                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.525501                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.286416                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               334                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        10880                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.527482                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.289859                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8444     77.32%     77.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1188     10.88%     88.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          479      4.39%     92.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          318      2.91%     95.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          171      1.57%     97.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          152      1.39%     98.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           62      0.57%     99.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           33      0.30%     99.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8406     77.26%     77.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1187     10.91%     88.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          477      4.38%     92.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          317      2.91%     95.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          170      1.56%     97.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          153      1.41%     98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           62      0.57%     99.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           34      0.31%     99.32% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8           74      0.68%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        10921                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        10880                       # Number of insts commited each cycle
 system.cpu.commit.count                          5739                       # Number of instructions committed
-system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls                   82                       # Number of function calls committed.
-system.cpu.commit.int_insts                      4985                       # Number of committed integer instructions.
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                           2139                       # Number of memory references committed
 system.cpu.commit.loads                          1201                       # Number of loads committed
 system.cpu.commit.membars                          12                       # Number of memory barriers committed
-system.cpu.commit.refs                           2139                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.branches                        945                       # Number of branches committed
+system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                      4985                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                   82                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events                    74                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                        20788                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21080                       # The number of ROB writes
+system.cpu.timesIdled                             199                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            9853                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5739                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  5739                       # Number of Instructions Simulated
-system.cpu.cpi                               3.757798                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.757798                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        38250                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency        76500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses               1795                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 32493.670886                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29240.566038                       # average ReadReq mshr miss latency
+system.cpu.cpi                               3.749434                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.749434                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.266707                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.266707                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    37248                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7653                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
+system.cpu.misc_regfile_reads                   13970                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
+system.cpu.icache.replacements                      2                       # number of replacements
+system.cpu.icache.tagsinuse                146.709916                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1288                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    285                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   4.519298                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            146.709916                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.071636                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   1288                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    1288                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   1288                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  330                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   330                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  330                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       11562500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        11562500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       11562500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               1618                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                1618                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               1618                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.203956                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.203956                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.203956                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35037.878788                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35037.878788                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35037.878788                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits                45                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                 45                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                45                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             285                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              285                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             285                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency      9568500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      9568500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      9568500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.176143                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.176143                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.176143                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 33573.684211                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 33573.684211                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 33573.684211                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                      0                       # number of replacements
+system.cpu.dcache.tagsinuse                 89.574063                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2279                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    149                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  15.295302                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0             89.574063                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.021869                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits                   1637                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        5134000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.088022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  158                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits                52                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency      3099500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.059053                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses             106                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits                   622                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits                11                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                    2259                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   2259                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  159                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                 291                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses                   450                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  450                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        5132500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      10420500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        76500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency        15553000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       15553000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1796                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses               913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35800.687285                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35880.952381                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   622                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      10418000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses                2709                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2709                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.088530                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.318729                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                 291                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits              249                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency      1507000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses             42                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  15.398649                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_miss_rate     0.181818                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.166113                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.166113                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 32279.874214                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 35809.278351                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        38250                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 34562.222222                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 34562.222222                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                2708                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34636.971047                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        31125                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    2259                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        15552000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.165805                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   449                       # number of demand (read+write) misses
+system.cpu.dcache.writebacks                        0                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits                52                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits              249                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.demand_mshr_hits                301                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      4606500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.054653                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0             89.451060                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.021839                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses               2708                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34636.971047                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        31125                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   2259                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       15552000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.165805                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  449                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits               301                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      4606500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.054653                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             148                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_misses             107                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses             42                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses              149                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses             149                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                    148                       # Sample count of references to valid blocks.
+system.cpu.dcache.ReadReq_mshr_miss_latency      3099500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      1507500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      4607000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      4607000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.059577                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.046002                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.055002                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.055002                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28967.289720                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35892.857143                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 30919.463087                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 30919.463087                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 89.451060                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2279                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.BlockedCycles                  1179                       # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred                   161                       # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved                  352                       # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts                  12101                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                     7437                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                      2257                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles                    777                       # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts                   565                       # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles                    47                       # Number of cycles decode is unblocking
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
-system.cpu.dtb.read_hits                            0                       # DTB read hits
-system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
-system.cpu.dtb.write_hits                           0                       # DTB write hits
-system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.fetch.Branches                        2185                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                      1628                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                          2410                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                   234                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                          11189                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                     514                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.101317                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles               1628                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches                963                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.518826                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples              11697                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.186202                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.597096                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9287     79.40%     79.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      223      1.91%     81.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      149      1.27%     82.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      211      1.80%     84.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      194      1.66%     86.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      259      2.21%     88.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      122      1.04%     89.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                       98      0.84%     90.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1154      9.87%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11697                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses               1628                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35051.051051                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 33594.076655                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                   1295                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       11672000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.204545                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  333                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits                46                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency      9641500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.176290                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             287                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                   4.512195                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                1628                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35051.051051                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 33594.076655                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    1295                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        11672000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.204545                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   333                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                 46                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      9641500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.176290                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              287                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            147.191898                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.071871                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses               1628                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35051.051051                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 33594.076655                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   1295                       # number of overall hits
-system.cpu.icache.overall_miss_latency       11672000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.204545                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  333                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                46                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      9641500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.176290                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             287                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.sampled_refs                    287                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                147.191898                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1295                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                            9869                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts                  371                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                     1360                       # Number of branches executed
-system.cpu.iew.exec_nop                             3                       # number of nop insts executed
-system.cpu.iew.exec_rate                     0.377446                       # Inst execution rate
-system.cpu.iew.exec_refs                         3052                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                       1120                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                     166                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts                  2335                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                 12                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts               127                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts                 1452                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts               10208                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts                  1932                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               326                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts                  8140                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                     19                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                    777                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                    27                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads               50                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads         1134                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores          514                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents             14                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect          243                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect            128                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                      6995                       # num instructions consuming a value
-system.cpu.iew.wb_count                          7761                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.509078                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                      3561                       # num instructions producing a value
-system.cpu.iew.wb_rate                       0.359872                       # insts written-back per cycle
-system.cpu.iew.wb_sent                           7887                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads                    37201                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7643                       # number of integer regfile writes
-system.cpu.ipc                               0.266113                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.266113                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5232     61.80%     61.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    6      0.07%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     61.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2072     24.47%     86.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1153     13.62%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8466                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                         182                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.021498                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      11      6.04%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    115     63.19%     69.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    56     30.77%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses                   8628                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              28796                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses         7745                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             14142                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                      10181                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                      8466                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                  24                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined            3941                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued                21                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedOperandsExamined        10938                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples         11697                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.723775                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.386140                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8148     69.66%     69.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1408     12.04%     81.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 816      6.98%     88.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 516      4.41%     93.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 394      3.37%     96.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 234      2.00%     98.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 143      1.22%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  30      0.26%     99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                   8      0.07%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11697                       # Number of insts issued each cycle
-system.cpu.iq.rate                           0.392562                       # Inst issue rate
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse               185.420659                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                      39                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   347                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.112392                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           185.420659                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005659                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                    39                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits                     39                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                    39                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                 353                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses                42                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                  395                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                 395                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      12138500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      1447000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency       13585500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      13585500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses               392                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses              42                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34440.476190                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      1446500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_accesses                434                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses               434                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.900510                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses                42                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1315000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses           42                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses               393                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34391.549296                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31237.822350                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                    38                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      12209000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.903308                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 355                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits                6                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency     10902000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.888041                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            349                       # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.108883                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.demand_miss_rate          0.910138                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.910138                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34386.685552                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34452.380952                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34393.670886                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34393.670886                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                435                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34396.725441                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.524297                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                     38                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       13655500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.912644                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                  397                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits                6                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                 6                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency     12217000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.898851                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses             391                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0           185.920349                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005674                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses               435                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34396.725441                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.524297                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                    38                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      13655500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.912644                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                 397                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                6                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency     12217000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.898851                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses            391                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_misses            347                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses           42                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses             389                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses            389                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   349                       # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency     10837500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency      1315000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency     12152500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     12152500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.885204                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.896313                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.896313                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31231.988473                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31240.359897                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31240.359897                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               185.920349                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                      38                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads                 2335                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1452                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                   13994                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.numCycles                            21566                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                     280                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps                  5684                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents                     38                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                     7695                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents                   122                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenameLookups                 51738                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts                  11352                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands               11162                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                      2047                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles                    777                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles                   186                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                     5473                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups               520                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups            51218                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles            712                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts                 15                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                       482                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts             13                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        20793                       # The number of ROB reads
-system.cpu.rob.rob_writes                       20998                       # The number of ROB writes
-system.cpu.timesIdled                             201                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index f23e1efe674cb34d35c99f7e90c8c697b18c41ed..a4e55b227eb7dccfe9a0cf397d48e4c66bd8014e 100755 (executable)
@@ -1,3 +1,5 @@
+Redirecting stdout to build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,12 +7,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2011 13:30:37
-M5 started Apr 21 2011 14:05:23
-M5 executing on maize
+M5 compiled May 17 2011 12:22:59
+M5 started May 17 2011 13:06:27
+M5 executing on nadc-0309
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 11371000 because target called exit()
+Exiting @ tick 11369000 because target called exit()
index 71886c36a7597d0b4fc89fe894a5e308e858c680..fb3f0ce4de43d84b6237fad02c57502adf59558d 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  99680                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 212240                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-host_tick_rate                              115331857                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.000011                       # Number of seconds simulated
+sim_ticks                                    11369000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 133340                       # Simulator instruction rate (inst/s)
+host_tick_rate                              154514196                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245132                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        9809                       # Number of instructions simulated
-sim_seconds                                  0.000011                       # Number of seconds simulated
-sim_ticks                                    11371000                       # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                      931                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups                  2531                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.workload.num_syscalls                   11                       # Number of system calls
+system.cpu.numCycles                            22739                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                     2757                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               2757                       # Number of conditional branches predicted
 system.cpu.BPredUnit.condIncorrect                485                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted               2758                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                     2758                       # Number of BP lookups
+system.cpu.BPredUnit.BTBLookups                  2530                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      929                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts               485                       # The number of times a branch was mispredicted
-system.cpu.commit.branches                       1214                       # Number of branches committed
-system.cpu.commit.bw_lim_events                   141                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts            9222                       # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples        11809                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.830638                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.597584                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8189     69.35%     69.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1225     10.37%     79.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          582      4.93%     84.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          958      8.11%     92.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          396      3.35%     96.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          132      1.12%     97.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          128      1.08%     98.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           58      0.49%     98.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          141      1.19%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11809                       # Number of insts commited each cycle
-system.cpu.commit.count                          9809                       # Number of instructions committed
-system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
-system.cpu.commit.loads                          1056                       # Number of loads committed
-system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.refs                           1990                       # Number of memory references committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.committedInsts                        9809                       # Number of Instructions Simulated
-system.cpu.committedInsts_total                  9809                       # Number of Instructions Simulated
-system.cpu.cpi                               2.318585                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.318585                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses               1531                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                   1418                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency        3899000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.073808                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  113                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits                46                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency      2354500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.043762                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses              67                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        36000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits                   621                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      10668500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.335118                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                 313                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits              236                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency      2772000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.082441                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses             77                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  14.258741                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                2465                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34196.009390                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    2039                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        14567500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.172819                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                   426                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                282                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      5126500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.058418                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses              144                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0             85.873455                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.020965                       # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses               2465                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34196.009390                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   2039                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       14567500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.172819                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                  426                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits               282                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      5126500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.058418                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses             144                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.sampled_refs                    143                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 85.873455                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2039                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.BlockedCycles                  1369                       # Number of cycles decode is blocked
-system.cpu.decode.DecodedInsts                  22088                       # Number of instructions handled by decode
-system.cpu.decode.IdleCycles                     7085                       # Number of cycles decode is idle
-system.cpu.decode.RunCycles                      3278                       # Number of cycles decode is running
-system.cpu.decode.SquashCycles                   1477                       # Number of cycles decode is squashing
-system.cpu.decode.UnblockCycles                    77                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                        2758                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                      1703                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                          3590                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                   238                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                          12847                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               1700                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12836                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2757                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                929                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3597                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                     497                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.121268                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles               1703                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches                931                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.564877                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples              13286                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.734834                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.110520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      1700                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   237                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13282                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.734377                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.109101                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9786     73.66%     73.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      161      1.21%     74.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      122      0.92%     75.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      227      1.71%     77.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      192      1.45%     78.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      168      1.26%     80.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      257      1.93%     82.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      171      1.29%     83.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2202     16.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9775     73.60%     73.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      168      1.26%     74.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      126      0.95%     75.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      226      1.70%     77.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      192      1.45%     78.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      168      1.26%     80.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      259      1.95%     82.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      168      1.26%     83.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2200     16.56%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13286                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses               1703                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36577.562327                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        35100                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                   1342                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       13204500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.211979                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  361                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits                66                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     10354500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.173224                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             295                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                   4.549153                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses                1703                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36577.562327                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        35100                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                    1342                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        13204500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.211979                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   361                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                 66                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     10354500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.173224                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              295                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0            144.881554                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.070743                       # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses               1703                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36577.562327                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        35100                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                   1342                       # number of overall hits
-system.cpu.icache.overall_miss_latency       13204500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.211979                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  361                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                66                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     10354500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.173224                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             295                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.sampled_refs                    295                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                144.881554                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1342                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                            9457                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts                  566                       # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches                     1545                       # Number of branches executed
-system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_rate                     0.675461                       # Inst execution rate
-system.cpu.iew.exec_refs                         2952                       # number of memory reference insts executed
-system.cpu.iew.exec_stores                       1295                       # Number of stores executed
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.iewBlockCycles                     187                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts                  2082                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                 33                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts               207                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts                 1617                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts               19032                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts                  1657                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               693                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts                 15362                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                     12                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                   1477                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                    20                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads               69                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses           12                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads         1026                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores          683                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents             14                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect          497                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect             69                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers                     14668                       # num instructions consuming a value
-system.cpu.iew.wb_count                         15056                       # cumulative count of insts written-back
-system.cpu.iew.wb_fanout                     0.677734                       # average fanout of values written-back
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers                      9941                       # num instructions producing a value
-system.cpu.iew.wb_rate                       0.662006                       # insts written-back per cycle
-system.cpu.iew.wb_sent                          15179                       # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads                    22959                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   13993                       # number of integer regfile writes
-system.cpu.ipc                               0.431298                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.431298                       # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 12893     80.31%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1771     11.03%     91.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1387      8.64%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  16055                       # Type of FU issued
-system.cpu.iq.fp_alu_accesses                       5                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                   9                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009156                       # FU busy rate (busy events/executed inst)
+system.cpu.fetch.rateDist::total                13282                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.121245                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.564493                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7076                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1369                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3285                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    77                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1475                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  22079                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1475                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7317                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     565                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            440                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3105                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   380                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  21002                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                     52                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   248                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               19737                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 44285                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            44269                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps                  9368                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                    10369                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             31                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      1483                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2081                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1618                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                14                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      18991                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  33                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     16049                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            8597                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        10847                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             20                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         13282                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.208327                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.917321                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8198     61.72%     61.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1295      9.75%     71.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 980      7.38%     78.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 727      5.47%     84.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 779      5.87%     90.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 582      4.38%     94.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 507      3.82%     98.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 167      1.26%     99.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  47      0.35%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13282                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                     101     68.71%     68.71% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     68.71% # attempts to use FU when none available
@@ -332,129 +135,326 @@ system.cpu.iq.fu_full::MemRead                     27     18.37%     87.07% # at
 system.cpu.iq.fu_full::MemWrite                    19     12.93%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses                  16193                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              45588                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses        15052                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             27650                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                      18999                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                     16055                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                  33                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined            8610                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             20                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined        10851                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples         13286                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.208415                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.917020                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8201     61.73%     61.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1290      9.71%     71.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 986      7.42%     78.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 726      5.46%     84.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 782      5.89%     90.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 580      4.37%     94.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 507      3.82%     98.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 167      1.26%     99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  47      0.35%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13286                       # Number of insts issued each cycle
-system.cpu.iq.rate                           0.705931                       # Inst issue rate
-system.cpu.l2cache.ReadExReq_accesses              77                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34603.896104                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency      2664500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 12887     80.30%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1771     11.03%     91.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1387      8.64%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                  16049                       # Type of FU issued
+system.cpu.iq.rate                           0.705792                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009159                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              45572                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             27629                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        15050                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                   9                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses                  16187                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                       5                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads               69                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads         1025                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses           12                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          684                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles                   1475                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     187                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    20                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               19024                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               215                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2081                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1618                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 33                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     12                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             14                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect             69                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          498                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  567                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 15360                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1657                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               689                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_refs                         2952                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1546                       # Number of branches executed
+system.cpu.iew.exec_stores                       1295                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.675491                       # Inst execution rate
+system.cpu.iew.wb_sent                          15177                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         15054                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      9950                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     14675                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       0.662034                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.678024                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts            9214                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts               485                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        11807                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.830778                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.597683                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8187     69.34%     69.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1225     10.38%     79.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          582      4.93%     84.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          958      8.11%     92.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          396      3.35%     96.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          132      1.12%     97.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          128      1.08%     98.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           58      0.49%     98.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          141      1.19%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11807                       # Number of insts commited each cycle
+system.cpu.commit.count                          9809                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                           1990                       # Number of memory references committed
+system.cpu.commit.loads                          1056                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.branches                       1214                       # Number of branches committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events                   141                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                        30689                       # The number of ROB reads
+system.cpu.rob.rob_writes                       39546                       # The number of ROB writes
+system.cpu.timesIdled                             184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            9457                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                        9809                       # Number of Instructions Simulated
+system.cpu.committedInsts_total                  9809                       # Number of Instructions Simulated
+system.cpu.cpi                               2.318177                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.318177                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.431373                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.431373                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    22959                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   13989                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
+system.cpu.misc_regfile_reads                    6812                       # number of misc regfile reads
+system.cpu.icache.replacements                      0                       # number of replacements
+system.cpu.icache.tagsinuse                144.881621                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1339                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    295                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   4.538983                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            144.881621                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.070743                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   1339                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    1339                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   1339                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  361                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   361                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  361                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       13205500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        13205500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       13205500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               1700                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                1700                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               1700                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.212353                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.212353                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.212353                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36580.332410                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36580.332410                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36580.332410                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits                66                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                 66                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                66                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             295                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              295                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             295                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     10355500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     10355500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     10355500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.173529                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.173529                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.173529                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35103.389831                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35103.389831                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35103.389831                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                      0                       # number of replacements
+system.cpu.dcache.tagsinuse                 85.872025                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2039                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    143                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  14.258741                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0             85.872025                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.020965                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                   1418                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits                   621                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                    2039                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   2039                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  113                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                 313                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                   426                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  426                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        3899000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      10668500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency        14567500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       14567500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1531                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses                2465                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2465                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.073808                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.335118                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.172819                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.172819                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 34196.009390                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 34196.009390                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                        0                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits                46                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits              236                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits                282                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits               282                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses              67                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses             77                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses              144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses             144                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency      2354500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      2772000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      5126500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      5126500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.043762                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.082441                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.058418                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.058418                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        36000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse               178.189347                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   359                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.005571                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0           178.189347                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005438                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                     2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                 360                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses                77                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2417500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses           77                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_misses                  437                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                 437                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      12329000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      2664000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency       14993000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      14993000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses               362                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34244.444444                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      12328000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses              77                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses                439                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses               439                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate         0.994475                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 360                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11174500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994475                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            360                       # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.005571                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.995444                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.995444                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34247.222222                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34597.402597                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34308.924485                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34308.924485                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses                439                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34307.780320                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency       14992500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.995444                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                  437                       # number of demand (read+write) misses
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses            360                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses           77                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses             437                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses            437                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     11174500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency      2417500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency     13592000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     13592000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994475                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.995444                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses             437                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0           178.188786                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005438                       # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses               439                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34307.780320                       # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate     0.995444                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency      14992500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.995444                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                 437                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency     13592000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.995444                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses            437                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                   359                       # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               178.188786                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads                14                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads                 2082                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1617                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                    6812                       # number of misc regfile reads
-system.cpu.numCycles                            22743                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.BlockCycles                     565                       # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps                  9368                       # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents                     52                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles                     7327                       # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents                   248                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups                 44292                       # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts                  21008                       # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands               19746                       # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles                      3097                       # Number of cycles rename is running
-system.cpu.rename.SquashCycles                   1477                       # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles                   380                       # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps                    10378                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups            44276                       # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles            440                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
-system.cpu.rename.skidInsts                      1483                       # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts             31                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        30699                       # The number of ROB reads
-system.cpu.rob.rob_writes                       39564                       # The number of ROB writes
-system.cpu.timesIdled                             184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls                   11                       # Number of system calls
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------